From nobody Fri Oct 2 04:27:23 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 003203A1685; Wed, 5 Aug 2026 10:33:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785926007; cv=none; b=Em5N69CVj8M4WDwGF4bGZboIVLdmQ2sXXZgVAuHczqN0bZRidJ5S1jUpaysTV70XUJKsQgph+GZLgKSa5BDIkWReb6zVDKnobkHa/ls0LHSEFif7C3TICNG+I/NJf6EGw6TV+1v7gbOqvfBs8vgy2lZT9vz/2SZC7hbz//sH6rE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785926007; c=relaxed/simple; bh=oEa1rZ7jhjgKUm5sxpeN55GPhpoxQuvfkNNHnl/9FHQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=FzFIOKrbhdYZ9VP6M7qMI2tpd10+okuzXFG6nt5AGRjAKYa0+/avwk+jiUAasj3NbYfykNJE2SpkOgPSScTlwxEB8tnF6xBlzX44IihtEnK2ckXDNJiwQDcGEf9NtY18fJg5Kry89XqsUCMaXDsjA96DMcBchcoBuJm+qf52ifs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GUurDotb; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GUurDotb" Received: by smtp.kernel.org (Postfix) with ESMTPS id A1E06C2BCFA; Wed, 5 Aug 2026 10:33:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1785926006; bh=oEa1rZ7jhjgKUm5sxpeN55GPhpoxQuvfkNNHnl/9FHQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=GUurDotb9o5mdyq+uDPdiBdZWVl0OIQ29crG0XeTIxsrEEPNHuT1Xb408Xtm5necD zXbFIA9iuYIG9CVZURR+ybIAZkarGtO+h2XPprSubwml+cuRutJB8YD2oJz4+KIWyY m7L2A4pgpc33levjBgJJJmNqURLhaR5lAxvSvvVjjTvWqxdxfoMt6xXNokTWWeBJc3 qKjSbrqb0dJTdEaPV19o4FO4tTL0/NUqruW/fTWMZTm7uejkHQvFXd52FMLCMWK8jB QHaWiffeqGS0zAo1LHN2w0r4xOkeL4ucHnar6/gL7Xc1Cr+07/kzbw4QKnpgO7lT6P TbZLr38AY4VZA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 822F5C55ABA; Wed, 5 Aug 2026 10:33:26 +0000 (UTC) From: Sarath Ganapathiraju via B4 Relay Date: Wed, 05 Aug 2026 16:03:19 +0530 Subject: [PATCH v4 1/2] dt-bindings: clock: qcom: Add LPASS VA CSR HeartBeat pulse clock Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260805-master-20260805-sync-v4-1-dfbcbf427c2c@oss.qualcomm.com> References: <20260805-master-20260805-sync-v4-0-dfbcbf427c2c@oss.qualcomm.com> In-Reply-To: <20260805-master-20260805-sync-v4-0-dfbcbf427c2c@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, prasad.kumpatla@oss.qualcomm.com, Sarath Ganapathiraju , Krzysztof Kozlowski X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1785926004; l=2278; i=sarath.ganapathiraju@oss.qualcomm.com; s=default; h=from:subject:message-id; bh=qxVOLK3Yva6vAmZ6Xln4mzA/Miy1La7zeDTze4nIz90=; b=TlbwGrbaX0lNE/YcP63xEeG312pM2XUHFr9Gn7sx83abvUcHdK043J0ICZtKhjV+46AbVKLht MLSGIwWUs5jAX2VtpUBw74PBCNDxyejpyxRiE6G5310q1IPT2CKU1YP X-Developer-Key: i=sarath.ganapathiraju@oss.qualcomm.com; a=ed25519; pk=4p2FWGXM+F2sir13Lu5stw5aKX5trUymK/ttESvgxQg= X-Endpoint-Received: by B4 Relay for sarath.ganapathiraju@oss.qualcomm.com/default with auth_id=870 X-Original-From: Sarath Ganapathiraju Reply-To: sarath.ganapathiraju@oss.qualcomm.com From: Sarath Ganapathiraju Add a binding for the Qualcomm LPASS VA CSR rate generator node that exposes the lpass_heartbeat_pulse clock on hawi. The HeartBeat Pulse (also known as RateGen Pulse) synchronizes the start of the DMAs and Codec Interfaces for the audio usecase and can serve as a periodic wakeup source for the DSP. Signed-off-by: Sarath Ganapathiraju Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/qcom,hawi-lpass-va-csr.yaml | 51 ++++++++++++++++++= ++++ 1 file changed, 51 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,hawi-lpass-va-csr= .yaml b/Documentation/devicetree/bindings/clock/qcom,hawi-lpass-va-csr.yaml new file mode 100644 index 000000000000..9935173d8bee --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,hawi-lpass-va-csr.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,hawi-lpass-va-csr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm LPASS VA CSR heartbeat pulse clock provider + +maintainers: + - Srinivas Kandagatla + - Sarath Ganapathiraju + +description: + The LPASS (Low Power Audio Subsystem) VA CSR block contains a rate + generator that produces a periodic HeartBeat Pulse, also known as + the RateGen Pulse. This pulse synchronizes the start of DMAs and + Codec Interfaces for audio usecases and can serve as a periodic + wakeup source for the DSP. + +properties: + compatible: + enum: + - qcom,hawi-lpass-va-csr + + reg: + maxItems: 1 + description: Address and size of the rate generator registers within + the VA CSR block. + + "#clock-cells": + const: 0 + +required: + - compatible + - reg + - "#clock-cells" + +additionalProperties: false + +examples: + - | + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + clock-controller@7eed000 { + compatible =3D "qcom,hawi-lpass-va-csr"; + reg =3D <0x0 0x07eed000 0x0 0x14>; + #clock-cells =3D <0>; + }; + }; --=20 2.34.1 From nobody Fri Oct 2 04:27:23 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 003CA400983; Wed, 5 Aug 2026 10:33:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785926007; cv=none; b=g7bbyRsiU8O+ddwn9nyo3Ftty6cv05F0JoNeCOj4rrVxUe33uG6R76pf1t9GD/6iP1ffsdB874sWE7Fj6ih/fAgNXZrOiygdmmhwDb6/LnkMNnDrU8VcoEUGxk5NJqkMTOSqOdstKwoKpea2/0ivF7j6LcDMJUjUUaxm1adwIxw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785926007; c=relaxed/simple; bh=lOmGNFcBI8N/6uHMSF2A/5RwgzKqOPUPDi2PSs4PVUk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Dt93ucMI/FMaqb8K4YEIfI+YyEdDy7cf23VD8lrI/XqSnMUIIHNDbUd+dQMpbLG2nOvNdAJH1JlzwnDJIsNyue+qdAdsjQXKtkKr2Gag2jHEGmgD8bB230zjSvjTa7Tyhp5oyx/wawnvxY7zo5s1zQKkYpOH/9Aj7fYys4ggi0w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Q3GzjmxU; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Q3GzjmxU" Received: by smtp.kernel.org (Postfix) with ESMTPS id B247BC2BCF6; Wed, 5 Aug 2026 10:33:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1785926006; bh=lOmGNFcBI8N/6uHMSF2A/5RwgzKqOPUPDi2PSs4PVUk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Q3GzjmxUh9c2O49xyjNAsg7H1M/oR8V15BFtouSoox1jdSVzWzTiFylqs20rb2fYQ 0qGAmSm91hHtfLD0bxXDRFojpCCK7tzcHPfSE26o+jM7n0stM+pJTvJQlcRHaxdjtV cylgmPHYIkwoD4o8Lj9MFk3NfIm2O77Hkw0ym43kHoyt+1y09LVHOBgTWpaaeYuAqj UyBP7micU6/kD9zii/fSTuHXmqv5q9amKm3fYhkipeU7FX2Vg7h34dP6YCQlZdN96w 2+bTxZakgHqfP4CyV7iCGuLqZ59ayH/sylSCNYyDq3IE07kN+ixEyqwqiKXmkxLAEM iBlkcE5YNmt7Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 933F2C56203; Wed, 5 Aug 2026 10:33:26 +0000 (UTC) From: Sarath Ganapathiraju via B4 Relay Date: Wed, 05 Aug 2026 16:03:20 +0530 Subject: [PATCH v4 2/2] clk: qcom: Add LPASS VA CSR heartbeat pulse clock Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260805-master-20260805-sync-v4-2-dfbcbf427c2c@oss.qualcomm.com> References: <20260805-master-20260805-sync-v4-0-dfbcbf427c2c@oss.qualcomm.com> In-Reply-To: <20260805-master-20260805-sync-v4-0-dfbcbf427c2c@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, prasad.kumpatla@oss.qualcomm.com, Sarath Ganapathiraju X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1785926004; l=6599; i=sarath.ganapathiraju@oss.qualcomm.com; s=default; h=from:subject:message-id; bh=DjFlc29XwWELcwQ1H8nX8cjMRr4Pyj2h1iQ9wIHJM7c=; b=sf1cUeEa13Qoh+BIbBavTBVvVeHlvWCElBY1OtoJ1qkybf/MakgedRSmUeivhJ+SnxEHPWvcT fv3sRoAvhdqBsx9G50RiNZBqxbQVFkTlv/6xONDlj+i6jijIDmTjZI5 X-Developer-Key: i=sarath.ganapathiraju@oss.qualcomm.com; a=ed25519; pk=4p2FWGXM+F2sir13Lu5stw5aKX5trUymK/ttESvgxQg= X-Endpoint-Received: by B4 Relay for sarath.ganapathiraju@oss.qualcomm.com/default with auth_id=870 X-Original-From: Sarath Ganapathiraju Reply-To: sarath.ganapathiraju@oss.qualcomm.com From: Sarath Ganapathiraju The HeartBeat Pulse (also known as RateGen Pulse) synchronizes the start of the DMAs and Codec Interfaces for the audio usecases and can serve as a periodic wakeup source for the DSP. Add the LPASS VA CSR driver that models the rate generator as a clock provider so it is enabled and disabled automatically alongside the other clocks during runtime PM resume and suspend. Signed-off-by: Sarath Ganapathiraju --- drivers/clk/qcom/Kconfig | 12 ++++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/lpass-va-csr.c | 148 ++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 161 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index d1fc9bf87126..d9a4ceb1d3a0 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -2040,6 +2040,18 @@ config CLK_GFM_LPASS_SM8250 Support for the Glitch Free Mux (GFM) Low power audio subsystem (LPASS) clocks found on SM8250 SoCs. =20 +config QCOM_CLK_LPASS_HEARTBEAT_PULSE + tristate "Qualcomm LPASS VA CSR heartbeat pulse clock provider" + depends on COMMON_CLK + select REGMAP_MMIO + help + Qualcomm LPASS VA CSR block contains the rate generator hardware + that produces the HeartBeat Pulse (also known as RateGen Pulse). + This driver models the rate generator as a clock provider so + that consumers can enable or disable it via the common clock + framework, and it can be used to synchronize the start of DMAs + and Codec Interfaces or as a periodic wakeup source for the DSP. + config SM_VIDEOCC_8450 tristate "SM8450 Video Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index daf25d583be2..8d3e3381bc29 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_CLK_ELIZA_DISPCC) +=3D dispcc-eliza.o obj-$(CONFIG_CLK_ELIZA_GCC) +=3D gcc-eliza.o obj-$(CONFIG_CLK_ELIZA_TCSRCC) +=3D tcsrcc-eliza.o obj-$(CONFIG_CLK_GFM_LPASS_SM8250) +=3D lpass-gfm-sm8250.o +obj-$(CONFIG_QCOM_CLK_LPASS_HEARTBEAT_PULSE) +=3D lpass-va-csr.o obj-$(CONFIG_CLK_GLYMUR_CAMCC) +=3D camcc-glymur.o obj-$(CONFIG_CLK_GLYMUR_DISPCC) +=3D dispcc-glymur.o obj-$(CONFIG_CLK_GLYMUR_EVACC) +=3D evacc-glymur.o diff --git a/drivers/clk/qcom/lpass-va-csr.c b/drivers/clk/qcom/lpass-va-cs= r.c new file mode 100644 index 000000000000..2e692407a966 --- /dev/null +++ b/drivers/clk/qcom/lpass-va-csr.c @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define LPASS_RATE_GEN_CTRL 0xd000 +#define LPASS_RATE_GEN_COUNTER_0 0xd004 +#define LPASS_RATE_GEN_DELAY 0xd010 + +#define LPASS_RATE_GEN_MAX_REG LPASS_RATE_GEN_DELAY + +#define LPASS_RG_CTRL_EN BIT(0) + +struct lpass_va_csr_data { + u32 counter_0; + u32 delay; +}; + +static const struct lpass_va_csr_data hawi_csr_data =3D { + .counter_0 =3D 0x960, + .delay =3D 0x16, +}; + +static const struct regmap_config lpass_rate_gen_regmap_config =3D { + .name =3D "lpass_rate_gen", + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .max_register =3D LPASS_RATE_GEN_MAX_REG, + .cache_type =3D REGCACHE_MAPLE, +}; + +struct lpass_va_csr { + struct regmap *regmap; + const struct lpass_va_csr_data *data; + struct clk_hw hb_hw; +}; + +#define to_lpass_va_csr(_hw) container_of(_hw, struct lpass_va_csr, hb_hw) + +static int heartbeat_pulse_prepare(struct clk_hw *hw) +{ + struct lpass_va_csr *csr =3D to_lpass_va_csr(hw); + int ret; + + ret =3D regmap_write(csr->regmap, LPASS_RATE_GEN_COUNTER_0, csr->data->co= unter_0); + if (ret) + return ret; + + ret =3D regmap_write(csr->regmap, LPASS_RATE_GEN_DELAY, csr->data->delay); + if (ret) + return ret; + + return regmap_set_bits(csr->regmap, LPASS_RATE_GEN_CTRL, LPASS_RG_CTRL_EN= ); +} + +static void heartbeat_pulse_unprepare(struct clk_hw *hw) +{ + struct lpass_va_csr *csr =3D to_lpass_va_csr(hw); + + regmap_clear_bits(csr->regmap, LPASS_RATE_GEN_CTRL, LPASS_RG_CTRL_EN); +} + +static int heartbeat_pulse_is_prepared(struct clk_hw *hw) +{ + struct lpass_va_csr *csr =3D to_lpass_va_csr(hw); + + return regmap_test_bits(csr->regmap, LPASS_RATE_GEN_CTRL, LPASS_RG_CTRL_E= N); +} + +static const struct clk_ops heartbeat_pulse_ops =3D { + .prepare =3D heartbeat_pulse_prepare, + .unprepare =3D heartbeat_pulse_unprepare, + .is_prepared =3D heartbeat_pulse_is_prepared, +}; + +static int lpass_va_csr_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct lpass_va_csr *csr; + struct clk_init_data init =3D { + .name =3D "lpass_heartbeat_pulse", + .ops =3D &heartbeat_pulse_ops, + }; + void __iomem *base; + int ret; + + csr =3D devm_kzalloc(dev, sizeof(*csr), GFP_KERNEL); + if (!csr) + return -ENOMEM; + + csr->data =3D of_device_get_match_data(dev); + if (!csr->data) + return dev_err_probe(dev, -EINVAL, "no variant data for compatible\n"); + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + csr->regmap =3D devm_regmap_init_mmio(dev, base, + &lpass_rate_gen_regmap_config); + if (IS_ERR(csr->regmap)) + return dev_err_probe(dev, PTR_ERR(csr->regmap), + "failed to init regmap\n"); + + csr->hb_hw.init =3D &init; + + ret =3D devm_pm_runtime_enable(dev); + if (ret) + return dev_err_probe(dev, ret, "failed to enable PM runtime\n"); + + ret =3D devm_clk_hw_register(dev, &csr->hb_hw); + if (ret) + return dev_err_probe(dev, ret, "failed to register heartbeat clock\n"); + + ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &csr->hb_h= w); + if (ret) + return dev_err_probe(dev, ret, "failed to add clock provider\n"); + + return 0; +} + +static const struct of_device_id lpass_va_csr_dt_match[] =3D { + { .compatible =3D "qcom,hawi-lpass-va-csr", .data =3D &hawi_csr_data }, + {} +}; +MODULE_DEVICE_TABLE(of, lpass_va_csr_dt_match); + +static struct platform_driver lpass_va_csr_driver =3D { + .driver =3D { + .name =3D "qcom-lpass-va-csr", + .of_match_table =3D lpass_va_csr_dt_match, + }, + .probe =3D lpass_va_csr_probe, +}; + +module_platform_driver(lpass_va_csr_driver); + +MODULE_DESCRIPTION("Qualcomm LPASS VA CSR heartbeat pulse clock provider"); +MODULE_LICENSE("GPL"); --=20 2.34.1