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Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/falcon.rs | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon= .rs index a91cbdd5d636..cd05985f5ee6 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -9,8 +9,7 @@ dma::{ Coherent, CoherentBox, - DmaAddress, - DmaMask, // + DmaAddress, // }, io::{ poll::read_poll_timeout, @@ -534,12 +533,6 @@ fn dma_wr( return Err(EINVAL); } =20 - // The DMATRFBASE/1 register pair only supports a 49-bit address. - if dma_start > DmaMask::new::<49>().value() { - dev_err!(self.dev, "DMA address {:#x} exceeds 49 bits\n", dma_= start); - return Err(ERANGE); - } - // DMA transfers can only be done in units of 256 bytes. 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everything named `dma_handle` is actually a `dma_addr_t`. This naming introduces some confusion on the Rust API side, as handles are supposed to be opaque tokens, yet we were doing address computation on values returned by `dma_handle`. Rename `dma_handle` to `dma_address` while nova-core is still its only user. Suggested-by: John Hubbard Suggested-by: Danilo Krummrich Link: https://lore.kernel.org/all/DK75LUA4NLGI.3P29AIZQE20V2@kernel.org/ Signed-off-by: Alexandre Courbot Reviewed-by: Robin Murphy --- drivers/gpu/nova-core/falcon.rs | 8 +-- drivers/gpu/nova-core/fb.rs | 4 +- drivers/gpu/nova-core/firmware/booter.rs | 8 ++- drivers/gpu/nova-core/firmware/fwsec/bootloader.rs | 4 +- drivers/gpu/nova-core/firmware/gsp.rs | 6 +- drivers/gpu/nova-core/fsp.rs | 6 +- drivers/gpu/nova-core/gsp.rs | 2 +- drivers/gpu/nova-core/gsp/cmdq.rs | 8 +-- drivers/gpu/nova-core/gsp/fw.rs | 10 ++-- drivers/gpu/nova-core/gsp/hal/gh100.rs | 2 +- drivers/gpu/nova-core/gsp/hal/tu102.rs | 8 ++- drivers/gpu/nova-core/gsp/sequencer.rs | 8 +-- rust/kernel/dma.rs | 70 +++++++++++-------= ---- 13 files changed, 74 insertions(+), 70 deletions(-) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon= .rs index cd05985f5ee6..a281d316ebfd 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -499,7 +499,7 @@ pub(crate) fn pio_load = + FalconPioLoadable>( Ok(()) } =20 - /// Perform a DMA write according to `load_offsets` from `dma_handle` = into the falcon's + /// Perform a DMA write according to `load_offsets` from `dma_obj` int= o the falcon's /// `target_mem`. /// /// `sec` is set if the loaded firmware is expected to run in secure m= ode. @@ -514,14 +514,14 @@ fn dma_wr( // For IMEM, we want to use the start offset as a virtual address = tag for each page, since // code addresses in the firmware (and the boot vector) are virtua= l. // - // For DMEM we can fold the start offset into the DMA handle. + // For DMEM we can fold the start offset into the DMA address. let (src_start, dma_start) =3D match target_mem { FalconMem::ImemSecure | FalconMem::ImemNonSecure =3D> { - (load_offsets.src_start, dma_obj.dma_handle()) + (load_offsets.src_start, dma_obj.dma_address()) } FalconMem::Dmem =3D> ( 0, - dma_obj.dma_handle() + DmaAddress::from(load_offsets.src_s= tart), + dma_obj.dma_address() + DmaAddress::from(load_offsets.src_= start), ), }; if dma_start % DmaAddress::from(DMA_LEN) > 0 { diff --git a/drivers/gpu/nova-core/fb.rs b/drivers/gpu/nova-core/fb.rs index 9e475efb1150..e7ed19a61c1a 100644 --- a/drivers/gpu/nova-core/fb.rs +++ b/drivers/gpu/nova-core/fb.rs @@ -61,7 +61,7 @@ pub(crate) fn register( ) -> Result { let page =3D CoherentHandle::alloc(dev, kernel::page::PAGE_SIZE, G= FP_KERNEL)?; =20 - hal::fb_hal(chipset).write_sysmem_flush_page(bar, page.dma_handle(= ))?; + hal::fb_hal(chipset).write_sysmem_flush_page(bar, page.dma_address= ())?; =20 Ok(Self { chipset, @@ -76,7 +76,7 @@ impl Drop for SysmemFlush<'_> { fn drop(&mut self) { let hal =3D hal::fb_hal(self.chipset); =20 - if hal.read_sysmem_flush_page(self.bar) =3D=3D self.page.dma_handl= e() { + if hal.read_sysmem_flush_page(self.bar) =3D=3D self.page.dma_addre= ss() { let _ =3D hal.write_sysmem_flush_page(self.bar, 0).inspect_err= (|e| { dev_warn!( &self.device, diff --git a/drivers/gpu/nova-core/firmware/booter.rs b/drivers/gpu/nova-co= re/firmware/booter.rs index acb7f4d8a532..972618e5eafe 100644 --- a/drivers/gpu/nova-core/firmware/booter.rs +++ b/drivers/gpu/nova-core/firmware/booter.rs @@ -405,9 +405,11 @@ pub(crate) fn run( ) -> Result { sec2_falcon.reset()?; sec2_falcon.load(self)?; - let wpr_handle =3D wpr_meta.dma_handle(); - let (mbox0, mbox1) =3D - sec2_falcon.boot(Some(wpr_handle as u32), Some((wpr_handle >> = 32) as u32))?; + let wpr_dma_address =3D wpr_meta.dma_address(); + let (mbox0, mbox1) =3D sec2_falcon.boot( + Some(wpr_dma_address as u32), + Some((wpr_dma_address >> 32) as u32), + )?; dev_dbg!(dev, "SEC2 MBOX0: {:#x}, MBOX1: {:#x}\n", mbox0, mbox1); =20 if mbox0 !=3D 0 { diff --git a/drivers/gpu/nova-core/firmware/fwsec/bootloader.rs b/drivers/g= pu/nova-core/firmware/fwsec/bootloader.rs index d9fafd2eea5b..c4a327af9ac7 100644 --- a/drivers/gpu/nova-core/firmware/fwsec/bootloader.rs +++ b/drivers/gpu/nova-core/firmware/fwsec/bootloader.rs @@ -230,7 +230,7 @@ pub(crate) fn new( reserved: [0; 4], signature: [0; 4], ctx_dma: FALCON_DMAIDX_PHYS_SYS_NCOH, - code_dma_base: firmware_dma.dma_handle(), + code_dma_base: firmware_dma.dma_address(), // `dst_start` is also valid as the source offset since th= e firmware DMA object is // a mirror image of the target IMEM layout. non_sec_code_off: imem_ns.dst_start, @@ -242,7 +242,7 @@ pub(crate) fn new( code_entry_point: 0, // Start of data section is the added padding + the DMEM `= src_start` field. data_dma_base: firmware_dma - .dma_handle() + .dma_address() .checked_add(u64::from_safe_cast(align_padding)) .and_then(|offset| offset.checked_add(dmem.src_start.i= nto())) .ok_or(EOVERFLOW)?, diff --git a/drivers/gpu/nova-core/firmware/gsp.rs b/drivers/gpu/nova-core/= firmware/gsp.rs index 99a302bae567..97977f27d74b 100644 --- a/drivers/gpu/nova-core/firmware/gsp.rs +++ b/drivers/gpu/nova-core/firmware/gsp.rs @@ -161,9 +161,9 @@ pub(crate) fn new<'a>( }) } =20 - /// Returns the DMA handle of the radix3 level 0 page table. - pub(crate) fn radix3_dma_handle(&self) -> DmaAddress { - self.level0.dma_handle() + /// Returns the DMA address of the radix3 level 0 page table. + pub(crate) fn radix3_dma_address(&self) -> DmaAddress { + self.level0.dma_address() } } =20 diff --git a/drivers/gpu/nova-core/fsp.rs b/drivers/gpu/nova-core/fsp.rs index ba4544210e40..1721a8387636 100644 --- a/drivers/gpu/nova-core/fsp.rs +++ b/drivers/gpu/nova-core/fsp.rs @@ -287,12 +287,12 @@ fn new<'a>( .chain(move |msg| { msg.cot.version =3D version; msg.cot.size =3D size; - msg.cot.gsp_fmc_sysmem_offset =3D fsp_fw.fmc_image.dma_handle(= ); + msg.cot.gsp_fmc_sysmem_offset =3D fsp_fw.fmc_image.dma_address= (); msg.cot.frts_vidmem_offset =3D frts_vidmem_offset; msg.cot.frts_vidmem_size =3D frts_size; // frts_sysmem_* are left at zero because this path places FRT= S in vidmem. The sysmem // fields point to an FRTS buffer in sysmem instead, for syste= ms without VRAM. - msg.cot.gsp_boot_args_sysmem_offset =3D args.fmc_boot_params.d= ma_handle(); + msg.cot.gsp_boot_args_sysmem_offset =3D args.fmc_boot_params.d= ma_address(); msg.cot.sigs =3D *fsp_fw.fmc_sigs; =20 Ok(()) @@ -353,7 +353,7 @@ pub(crate) fn new( libos: &'a Coherent<[LibosMemoryRegionInitArgument]>, resume: bool, ) -> Result { - let init =3D GspFmcBootParams::new(wpr_meta.dma_handle(), libos.dm= a_handle()); + let init =3D GspFmcBootParams::new(wpr_meta.dma_address(), libos.d= ma_address()); =20 Ok(Self { chipset, diff --git a/drivers/gpu/nova-core/gsp.rs b/drivers/gpu/nova-core/gsp.rs index b403dc3515a5..13f361406a6c 100644 --- a/drivers/gpu/nova-core/gsp.rs +++ b/drivers/gpu/nova-core/gsp.rs @@ -122,7 +122,7 @@ impl LogBuffer { fn new(dev: &device::Device) -> Result { let obj =3D Self(Coherent::zeroed(dev, GFP_KERNEL)?); =20 - let start_addr =3D obj.0.dma_handle(); + let start_addr =3D obj.0.dma_address(); =20 let pte_view =3D io_project!( obj.0, diff --git a/drivers/gpu/nova-core/gsp/cmdq.rs b/drivers/gpu/nova-core/gsp/= cmdq.rs index cd844fe48f05..f0f28b6ded7a 100644 --- a/drivers/gpu/nova-core/gsp/cmdq.rs +++ b/drivers/gpu/nova-core/gsp/cmdq.rs @@ -243,7 +243,7 @@ fn new(dev: &device::Device) -> Result { gsp_mem.cpuq.rx =3D MsgqRxHeader::new(); =20 let gsp_mem: Coherent<_> =3D gsp_mem.into(); - PteArray::init(io_project!(gsp_mem, .ptes), gsp_mem.dma_handle())?; + PteArray::init(io_project!(gsp_mem, .ptes), gsp_mem.dma_address())= ?; =20 Ok(Self(gsp_mem)) } @@ -487,8 +487,8 @@ pub(crate) struct Cmdq { /// Inner mutex-protected state. #[pin] inner: Mutex, - /// DMA handle of the command queue's shared memory region. - pub(super) dma_handle: DmaAddress, + /// DMA address of the command queue's shared memory region. + pub(super) dma_addr: DmaAddress, } =20 impl Cmdq { @@ -517,7 +517,7 @@ pub(crate) fn new(dev: &device::Device) = -> impl PinInit( // CAST: we want to store the bits of `GSP_FW_WPR_META_MAGIC` = unmodified. magic: bindings::GSP_FW_WPR_META_MAGIC as u64, revision: u64::from(bindings::GSP_FW_WPR_META_REVISION), - sysmemAddrOfRadix3Elf: gsp_firmware.radix3_dma_handle(), + sysmemAddrOfRadix3Elf: gsp_firmware.radix3_dma_address(), sizeOfRadix3Elf: u64::from_safe_cast(gsp_firmware.size), - sysmemAddrOfBootloader: gsp_firmware.bootloader.ucode.dma_hand= le(), + sysmemAddrOfBootloader: gsp_firmware.bootloader.ucode.dma_addr= ess(), sizeOfBootloader: u64::from_safe_cast(gsp_firmware.bootloader.= ucode.size()), bootloaderCodeOffset: u64::from(gsp_firmware.bootloader.code_o= ffset), bootloaderDataOffset: u64::from(gsp_firmware.bootloader.data_o= ffset), bootloaderManifestOffset: u64::from(gsp_firmware.bootloader.ma= nifest_offset), __bindgen_anon_1: GspFwWprMetaBootResumeInfo { __bindgen_anon_1: GspFwWprMetaBootInfo { - sysmemAddrOfSignature: gsp_firmware.signatures.dma_han= dle(), + sysmemAddrOfSignature: gsp_firmware.signatures.dma_add= ress(), sizeOfSignature: u64::from_safe_cast(gsp_firmware.sign= atures.size()), }, }, @@ -635,7 +635,7 @@ fn id8(name: &str) -> u64 { =20 let init_inner =3D init!(bindings::LibosMemoryRegionInitArgument { id8: id8(name), - pa: obj.dma_handle(), + pa: obj.dma_address(), size: num::usize_as_u64(obj.size()), kind: num::u32_into_u8::< { bindings::LibosMemoryRegionKind_LIBOS_MEMORY_REGION_CONT= IGUOUS }, @@ -901,7 +901,7 @@ impl MessageQueueInitArguments { /// Creates a new init arguments structure for `cmdq`. fn new(cmdq: &Cmdq) -> impl Init + '_ { init!(MessageQueueInitArguments { - sharedMemPhysAddr: cmdq.dma_handle, + sharedMemPhysAddr: cmdq.dma_addr, pageTableEntryCount: num::usize_into_u32::<{ Cmdq::NUM_PTES }>= (), cmdQueueOffset: num::usize_as_u64(Cmdq::CMDQ_OFFSET), statQueueOffset: num::usize_as_u64(Cmdq::STATQ_OFFSET), diff --git a/drivers/gpu/nova-core/gsp/hal/gh100.rs b/drivers/gpu/nova-core= /gsp/hal/gh100.rs index 22b60f9233de..8e219a0cb164 100644 --- a/drivers/gpu/nova-core/gsp/hal/gh100.rs +++ b/drivers/gpu/nova-core/gsp/hal/gh100.rs @@ -63,7 +63,7 @@ fn lockdown_released_or_error( // boot. If the address is still there, keep polling rather than t= reating it as an error. // Any other non-zero mailbox0 value is a GSP-FMC error code. if self.mbox0 !=3D 0 { - return self.combined_addr() !=3D fmc_boot_params.dma_handle(); + return self.combined_addr() !=3D fmc_boot_params.dma_address(); } =20 !gsp_falcon.riscv_branch_privilege_lockdown() diff --git a/drivers/gpu/nova-core/gsp/hal/tu102.rs b/drivers/gpu/nova-core= /gsp/hal/tu102.rs index 03133f723faf..26ac1adba1bf 100644 --- a/drivers/gpu/nova-core/gsp/hal/tu102.rs +++ b/drivers/gpu/nova-core/gsp/hal/tu102.rs @@ -286,9 +286,11 @@ fn boot( } =20 gsp_falcon.reset()?; - let libos_handle =3D gsp.libos.dma_handle(); - let (mbox0, mbox1) =3D - gsp_falcon.boot(Some(libos_handle as u32), Some((libos_handle = >> 32) as u32))?; + let libos_dma_address =3D gsp.libos.dma_address(); + let (mbox0, mbox1) =3D gsp_falcon.boot( + Some(libos_dma_address as u32), + Some((libos_dma_address >> 32) as u32), + )?; dev_dbg!(dev, "GSP MBOX0: {:#x}, MBOX1: {:#x}\n", mbox0, mbox1); =20 dev_dbg!( diff --git a/drivers/gpu/nova-core/gsp/sequencer.rs b/drivers/gpu/nova-core= /gsp/sequencer.rs index 5e1ec7e59ab0..bcad1421953a 100644 --- a/drivers/gpu/nova-core/gsp/sequencer.rs +++ b/drivers/gpu/nova-core/gsp/sequencer.rs @@ -234,12 +234,12 @@ fn run(&self, seq: &GspSequencer<'_>) -> Result { // Reset the GSP to prepare it for resuming. seq.gsp_falcon.reset()?; =20 - let libos_dma_handle =3D seq.libos.dma_handle(); + let libos_dma_address =3D seq.libos.dma_address(); =20 - // Write the libOS DMA handle to GSP mailboxes. + // Write the libOS DMA address to GSP mailboxes. seq.gsp_falcon.write_mailboxes( - Some(libos_dma_handle as u32), - Some((libos_dma_handle >> 32) as u32), + Some(libos_dma_address as u32), + Some((libos_dma_address >> 32) as u32), ); =20 // Start the SEC2 falcon which will trigger GSP-RM to resu= me on the GSP. diff --git a/rust/kernel/dma.rs b/rust/kernel/dma.rs index e275f2562a5b..4258ff7ff525 100644 --- a/rust/kernel/dma.rs +++ b/rust/kernel/dma.rs @@ -585,7 +585,7 @@ fn from(value: CoherentBox) -> Self { /// # Invariants /// /// - For the lifetime of an instance of [`Coherent`], the `cpu_addr` is a= valid pointer -/// to an allocated region of coherent memory and `dma_handle` is the DM= A address base of the +/// to an allocated region of coherent memory and `dma_addr` is the DMA = address base of the /// region. /// - The size in bytes of the allocation is equal to size information via= pointer. // TODO @@ -602,7 +602,7 @@ fn from(value: CoherentBox) -> Self { // entire `Coherent` including the allocated memory itself. pub struct Coherent { dev: ARef, - dma_handle: DmaAddress, + dma_addr: DmaAddress, cpu_addr: NonNull, dma_attrs: Attrs, } @@ -627,11 +627,10 @@ pub fn as_mut_ptr(&self) -> *mut T { self.cpu_addr.as_ptr() } =20 - /// Returns a DMA handle which may be given to the device as the DMA a= ddress base of - /// the region. + /// Returns a DMA address which may be given to the device as the base= of the region. #[inline] - pub fn dma_handle(&self) -> DmaAddress { - self.dma_handle + pub fn dma_address(&self) -> DmaAddress { + self.dma_addr } =20 /// Returns a reference to the data in the region. @@ -678,13 +677,13 @@ fn alloc_with_attrs( ); } =20 - let mut dma_handle =3D 0; + let mut dma_addr =3D 0; // SAFETY: Device pointer is guaranteed as valid by the type invar= iant on `Device`. let addr =3D unsafe { bindings::dma_alloc_attrs( dev.as_raw(), core::mem::size_of::(), - &mut dma_handle, + &mut dma_addr, gfp_flags.as_raw(), dma_attrs.as_raw(), ) @@ -696,7 +695,7 @@ fn alloc_with_attrs( // - We also hold a refcounted reference to the device. Ok(Self { dev: dev.into(), - dma_handle, + dma_addr, cpu_addr, dma_attrs, }) @@ -795,13 +794,13 @@ fn alloc_slice_with_attrs( } =20 let size =3D core::mem::size_of::().checked_mul(len).ok_or(ENOM= EM)?; - let mut dma_handle =3D 0; + let mut dma_addr =3D 0; // SAFETY: Device pointer is guaranteed as valid by the type invar= iant on `Device`. let addr =3D unsafe { bindings::dma_alloc_attrs( dev.as_raw(), size, - &mut dma_handle, + &mut dma_addr, gfp_flags.as_raw(), dma_attrs.as_raw(), ) @@ -813,7 +812,7 @@ fn alloc_slice_with_attrs( // - We also hold a refcounted reference to the device. Ok(Coherent { dev: dev.into(), - dma_handle, + dma_addr, cpu_addr, dma_attrs, }) @@ -927,14 +926,14 @@ impl Drop for Coherent { fn drop(&mut self) { let size =3D T::size(self.cpu_addr.as_ptr()); // SAFETY: Device pointer is guaranteed as valid by the type invar= iant on `Device`. - // The cpu address, and the dma handle are valid due to the type i= nvariants on + // The cpu address, and the dma address are valid due to the type = invariants on // `Coherent`. unsafe { bindings::dma_free_attrs( self.dev.as_raw(), size, self.cpu_addr.as_ptr().cast(), - self.dma_handle, + self.dma_addr, self.dma_attrs.as_raw(), ) } @@ -989,13 +988,13 @@ fn write_to_slice( /// /// - `cpu_handle` holds the opaque handle returned by `dma_alloc_attrs` w= ith /// `DMA_ATTR_NO_KERNEL_MAPPING` set, and is only valid for passing back= to `dma_free_attrs`. -/// - `dma_handle` is the corresponding bus address for device DMA. +/// - `dma_addr` is the corresponding bus address for device DMA. /// - `size` is the allocation size in bytes as passed to `dma_alloc_attrs= `. /// - `dma_attrs` contains the attributes used for the allocation, always = including /// `DMA_ATTR_NO_KERNEL_MAPPING`. pub struct CoherentHandle { dev: ARef, - dma_handle: DmaAddress, + dma_addr: DmaAddress, cpu_handle: NonNull, size: usize, dma_attrs: Attrs, @@ -1019,13 +1018,13 @@ pub fn alloc_with_attrs( } =20 let dma_attrs =3D dma_attrs | Attrs(bindings::DMA_ATTR_NO_KERNEL_M= APPING); - let mut dma_handle =3D 0; + let mut dma_addr =3D 0; // SAFETY: `dev.as_raw()` is valid by the type invariant on `devic= e::Device`. let cpu_handle =3D unsafe { bindings::dma_alloc_attrs( dev.as_raw(), size, - &mut dma_handle, + &mut dma_addr, gfp_flags.as_raw(), dma_attrs.as_raw(), ) @@ -1034,11 +1033,11 @@ pub fn alloc_with_attrs( let cpu_handle =3D NonNull::new(cpu_handle).ok_or(ENOMEM)?; =20 // INVARIANT: `cpu_handle` is the opaque handle from a successful = `dma_alloc_attrs` call - // with `DMA_ATTR_NO_KERNEL_MAPPING`, `dma_handle` is the correspo= nding DMA address, + // with `DMA_ATTR_NO_KERNEL_MAPPING`, `dma_addr` is the correspond= ing DMA address, // and we hold a refcounted reference to the device. Ok(Self { dev: dev.into(), - dma_handle, + dma_addr, cpu_handle, size, dma_attrs, @@ -1055,12 +1054,12 @@ pub fn alloc( Self::alloc_with_attrs(dev, size, gfp_flags, Attrs(0)) } =20 - /// Returns the DMA handle for this allocation. + /// Returns the DMA address for this allocation. /// /// This address can be programmed into device hardware for DMA access. #[inline] - pub fn dma_handle(&self) -> DmaAddress { - self.dma_handle + pub fn dma_address(&self) -> DmaAddress { + self.dma_addr } =20 /// Returns the size in bytes of this allocation. @@ -1079,28 +1078,29 @@ fn drop(&mut self) { self.dev.as_raw(), self.size, self.cpu_handle.as_ptr(), - self.dma_handle, + self.dma_addr, self.dma_attrs.as_raw(), ) } } } =20 -// SAFETY: `CoherentHandle` only holds a device reference, a DMA handle, a= n opaque CPU handle, +// SAFETY: `CoherentHandle` only holds a device reference, a DMA address, = an opaque CPU handle, // and a size. None of these are tied to a specific thread. unsafe impl Send for CoherentHandle {} =20 // SAFETY: `CoherentHandle` provides no CPU access to the underlying alloc= ation. The only -// operations on `&CoherentHandle` are reading the DMA handle and size, bo= th of which are +// operations on `&CoherentHandle` are reading the DMA address and size, b= oth of which are // plain `Copy` values. unsafe impl Sync for CoherentHandle {} =20 /// View type for `Coherent`. /// -/// This is same as [`SysMem`] but with additional information that allows= handing out a DMA handle. +/// This is same as [`SysMem`] but with additional information that allows= handing out a DMA +/// address. pub struct CoherentView<'a, T: ?Sized> { cpu_addr: SysMem<'a, T>, - dma_handle: DmaAddress, + dma_addr: DmaAddress, } =20 impl Copy for CoherentView<'_, T> {} @@ -1112,16 +1112,16 @@ fn clone(&self) -> Self { } =20 impl<'a, T: ?Sized> CoherentView<'a, T> { - /// Erase the DMA handle information and obtain a [`SysMem`] view of t= he same memory region. + /// Erase the DMA address information and obtain a [`SysMem`] view of = the same memory region. #[inline] pub fn as_sys_mem(self) -> SysMem<'a, T> { self.cpu_addr } =20 - /// Returns a DMA handle which may be given to the device as the DMA a= ddress base of the region. + /// Returns the DMA address which may be given to the device as base o= f the region. #[inline] - pub fn dma_handle(self) -> DmaAddress { - self.dma_handle + pub fn dma_address(self) -> DmaAddress { + self.dma_addr } =20 /// Returns a reference to the data in the region. @@ -1174,9 +1174,9 @@ unsafe fn project_view<'a, T: ?Sized + KnownSize, U: = ?Sized + KnownSize>( ) -> Self::View<'a, U> { let offset =3D ptr.addr() - view.cpu_addr.as_ptr().addr(); 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It then checked manually that the upper bound was valid. Convert this to an I/O projection of the same region, which returns `ERANGE` if the passed range does not fit within the coherent allocation. This removes the need to perform arithmetic on DMA addresses and to explicitly check for the bounds' validity. Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/falcon.rs | 55 +++++++++++++++++--------------------= ---- 1 file changed, 23 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon= .rs index a281d316ebfd..65cb12d26e2b 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -12,6 +12,7 @@ DmaAddress, // }, io::{ + io_project, poll::read_poll_timeout, register::{ RegisterBase, @@ -511,20 +512,31 @@ fn dma_wr( ) -> Result { const DMA_LEN: u32 =3D num::usize_into_u32::<{ MEM_BLOCK_ALIGNMENT= }>(); =20 + // DMA transfers can only be done in units of 256 bytes. Compute h= ow many such transfers we + // need to perform. + let num_transfers =3D load_offsets.len.div_ceil(DMA_LEN); + // For IMEM, we want to use the start offset as a virtual address = tag for each page, since // code addresses in the firmware (and the boot vector) are virtua= l. // - // For DMEM we can fold the start offset into the DMA address. + // For DMEM, the start offset is folded into the DMA address. let (src_start, dma_start) =3D match target_mem { - FalconMem::ImemSecure | FalconMem::ImemNonSecure =3D> { - (load_offsets.src_start, dma_obj.dma_address()) - } - FalconMem::Dmem =3D> ( - 0, - dma_obj.dma_address() + DmaAddress::from(load_offsets.src_= start), - ), + FalconMem::ImemSecure | FalconMem::ImemNonSecure =3D> (load_of= fsets.src_start, 0), + FalconMem::Dmem =3D> (0, usize::from_safe_cast(load_offsets.sr= c_start)), }; - if dma_start % DmaAddress::from(DMA_LEN) > 0 { + + let dma_address =3D { + // Upper limit of transfer is `(num_transfers * DMA_LEN) + loa= d_offsets.src_start`. + let dma_end =3D num_transfers + .checked_mul(DMA_LEN) + .and_then(|size| size.checked_add(load_offsets.src_start)) + .map(usize::from_safe_cast) + .ok_or(EOVERFLOW)?; + + io_project!(dma_obj, [try: dma_start..dma_end]).dma_address() + }; + + if dma_address % DmaAddress::from(DMA_LEN) > 0 { dev_err!( self.dev, "DMA transfer start addresses must be a multiple of {}\n", @@ -533,27 +545,6 @@ fn dma_wr( return Err(EINVAL); } =20 - // DMA transfers can only be done in units of 256 bytes. Compute h= ow many such transfers we - // need to perform. - let num_transfers =3D load_offsets.len.div_ceil(DMA_LEN); - - // Check that the area we are about to transfer is within the boun= ds of the DMA object. - // Upper limit of transfer is `(num_transfers * DMA_LEN) + load_of= fsets.src_start`. - match num_transfers - .checked_mul(DMA_LEN) - .and_then(|size| size.checked_add(load_offsets.src_start)) - { - None =3D> { - dev_err!(self.dev, "DMA transfer length overflow\n"); - return Err(EOVERFLOW); - } - Some(upper_bound) if usize::from_safe_cast(upper_bound) > dma_= obj.size() =3D> { - dev_err!(self.dev, "DMA transfer goes beyond range of DMA = object\n"); - return Err(EINVAL); - } - Some(_) =3D> (), - }; - // Set up the base source DMA address. =20 self.bar.write( @@ -561,12 +552,12 @@ fn dma_wr( regs::NV_PFALCON_FALCON_DMATRFBASE::zeroed().with_base( // CAST: `as u32` is used on purpose since we do want to s= trip the upper bits, // which will be written to `NV_PFALCON_FALCON_DMATRFBASE1= `. - (dma_start >> 8) as u32, + (dma_address >> 8) as u32, ), ); self.bar.write( WithBase::of::(), - regs::NV_PFALCON_FALCON_DMATRFBASE1::zeroed().try_with_base(dm= a_start >> 40)?, + regs::NV_PFALCON_FALCON_DMATRFBASE1::zeroed().try_with_base(dm= a_address >> 40)?, ); =20 let cmd =3D regs::NV_PFALCON_FALCON_DMATRFCMD::zeroed() --=20 2.55.0