From nobody Sat Oct 3 04:32:05 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C80A545041C; Wed, 5 Aug 2026 13:03:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785934989; cv=none; b=AgmX3rcGyKf2blufvEEd0NB9XrGhotDRrOAKaoW6FKrw10b/SI2wCwL9pzL119vG6oI6woLI/d7/PiRfuT3od14ab4/dS3aPSimIJ33uMSVW+Z0c0VSscdj+5cttL4UY4F+mLc/QpcOFsnzHlAyWYKj7G6EkJ71rP9B+Fkqjhok= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785934989; c=relaxed/simple; bh=hi9+GeaO3bLXI76yLDOrNGxGs+Avu1qw0k4soBp8eiI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=M6rxdAI5xNgkkBmIFZLavdQgyi9p42kznL26uimJizcDh1hWxUShooVEq6rIg4ZOlqcF3lg31truhs8gcbGyp3SGP6LOiNQwX5pxUC+Tt/cVPCoJMjKpvnMAgzdPHbrd46+0/gn7UJRY8cXHU4u/CwbYnJJVdYvndWFr60JDcmw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qm4SYNsc; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qm4SYNsc" Received: by smtp.kernel.org (Postfix) with ESMTPS id D247EC2BCFA; Wed, 5 Aug 2026 13:03:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1785934988; bh=hi9+GeaO3bLXI76yLDOrNGxGs+Avu1qw0k4soBp8eiI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=qm4SYNscAty2fhpjlJog1/Rn4io74dZUykcajbdY1oUKhrFeHIDi1fSS0lFP2BCaF zPTdiihSkw3LQ/8OVmeioC9hXKxt1EEsYa7SG7kVBorCDj9TCYV4OMl8ck+burVuCJ 8Ve0ccQA8F07FIDOCNDuFInLoUKSMPUvy6p64GtiDtUz+ncBNgNbR4o6HE1az16KFn UQm0jPLG29dROXECE+FZsqo72t+qGwtgulqDv9CqMHYpimW7x2txFvxQIDmJGTdZ09 K1yaSVZsZyEIXScj0tLR1ItsEJLDjfX+u54NqN6SpYYsKlKRaMI/uqQi/fJt04F8Gr VWp61Mbwyxyug== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B27B5C55ABF; Wed, 5 Aug 2026 13:03:08 +0000 (UTC) From: Colin Huang via B4 Relay Date: Wed, 05 Aug 2026 21:02:29 +0800 Subject: [PATCH v4 01/12] dt-bindings: arm: aspeed: Add Anacapa EVT1 EVT2 DVT board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260805-anacapa-devlop-phase-devicetree-v4-1-5d67e0efa6c5@gmail.com> References: <20260805-anacapa-devlop-phase-devicetree-v4-0-5d67e0efa6c5@gmail.com> In-Reply-To: <20260805-anacapa-devlop-phase-devicetree-v4-0-5d67e0efa6c5@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, colin.huang2@amd.com, Colin Huang X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1785934963; l=932; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=ilMNo/yT6oeGDuaZTkvgyuXcAOciPuXW9RaEwTNseF4=; b=IjmR4C9MhRHgPVRJbUmaRVvWK6Fm9xWsXUIsegB8uCkYjFtnjuak1hlTKO26h394Pf3l8/3Dt ZCm+QUb4/VaCz8vSOW/ih6xrZseYTI/ZqmcQWprg/DvN/cXhCw+rH60 X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 X-Original-From: Colin Huang Reply-To: u8813345@gmail.com From: Colin Huang Document Anacapa BMC EVT1, EVT2, and DVT compatibles. Signed-off-by: Colin Huang --- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Doc= umentation/devicetree/bindings/arm/aspeed/aspeed.yaml index dd7996960de3..1c2656d99807 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -84,6 +84,9 @@ properties: - asus,ast2600-kommando-ipmi-card - asus,x4tf-bmc - facebook,anacapa-bmc + - facebook,anacapa-bmc-evt1 + - facebook,anacapa-bmc-evt2 + - facebook,anacapa-bmc-dvt - facebook,bletchley-bmc - facebook,catalina-bmc - facebook,clemente-bmc --=20 2.34.1 From nobody Sat Oct 3 04:32:05 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8A4546F488; Wed, 5 Aug 2026 13:03:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785934989; cv=none; b=J3I1gjrP0KwRiSB6YbpDVXmGx7+2pD1RtDs5LwRP9pgVWEv4z2zk/t9pSX5jdR1Dxm64dTkA1XwSwgCSOtdDjK6CVjeOHy1Kul6PKhIVKsHpISW/ZKEYBD3dTIVq7EK7nKLD37SZ496wjDnLnPrAwoomZ7mY7yKCUCfVWaE5fgs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785934989; c=relaxed/simple; bh=l5P6aBAuWFE4QLII7CZeHdNvd3BnLqH9TEDuTgQPNWk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=OMmBpEwTqFQaQTBUDzncbLr6bPOdCp0Y1lsJs7Z2znCP415ol77HHSaDK6FhzKRh3qBsdXurs/euczzdR8eAmXgASdXMWXzvlbOQLxYJQbAafeZvcRDXw8hykpBfdlLVE4ngL640UlpkRuz/Duie8/Nu9gC2r8CyhaIpZkf/oOg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=c5Zxg7un; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="c5Zxg7un" Received: by smtp.kernel.org (Postfix) with ESMTPS id E447FC2BCB9; Wed, 5 Aug 2026 13:03:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1785934989; bh=l5P6aBAuWFE4QLII7CZeHdNvd3BnLqH9TEDuTgQPNWk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=c5Zxg7unQoErvz+e2hECy7lwt85w6KnLB6d4vgIVJG8L+fnFUHkQX6BPCWuEC2bvi 1n6+Nn1l+ncfFpHb/U27rVlKttoIZDJrZrqYXQMwkvAY9DpeSTPrLKePVpbqSBGeoT PgvaEvaohwOuQsof46YgbofbvmPP0c+eQCHNTY4wuW8yYLiyexfzw4noxVEG+qkzvV 51Ui6THXjTVESpCdDvrAM1VJLQSwLYqkNiYpLmQ2GGmb6X8/Q43JoujDZB1CR+9Ksn IORHHJufnvIN+JSY1MhL90sC++/2oIdjEwa5grgzKsYXYf1Xx/ocvmOxNHVjREB5TY sL7eeJ8gSojRQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9167C56205; Wed, 5 Aug 2026 13:03:08 +0000 (UTC) From: Colin Huang via B4 Relay Date: Wed, 05 Aug 2026 21:02:30 +0800 Subject: [PATCH v4 02/12] ARM: dts: aspeed: anacapa: Add EVT1 devicetree and point wrapper to it Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260805-anacapa-devlop-phase-devicetree-v4-2-5d67e0efa6c5@gmail.com> References: <20260805-anacapa-devlop-phase-devicetree-v4-0-5d67e0efa6c5@gmail.com> In-Reply-To: <20260805-anacapa-devlop-phase-devicetree-v4-0-5d67e0efa6c5@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, colin.huang2@amd.com, Colin Huang X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1785934963; l=47015; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=EIkYAn0CSXMJ+VNzVnKAvLzUiz34bj9V+R4z011eNJ0=; b=CQJvMxfCpE4Fv686jwAgYzJ4/+Fa70Hc95XFNR72x3HCoDIx8nu9wwi08A1zqlVi5EihIZWLF AEznjaf9n2CBDejf36vyDHeUUjBmiQha2P6MMjbQmhGxyKu86l+Ja19 X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 X-Original-From: Colin Huang Reply-To: u8813345@gmail.com From: Colin Huang This change introduces a development-phase devicetree for the Facebook Anacapa BMC EVT1 hardware revision and updates the Anacapa wrapper DTS to reference it. A dedicated EVT1 DTS is added for revision-specific hardware while keeping a single, Anacapa entrypoint used by the build and deployment flow. The top-level aspeed-bmc-facebook-anacapa.dts Signed-off-by: Colin Huang --- .../aspeed/aspeed-bmc-facebook-anacapa-evt1.dts | 1079 ++++++++++++++++= ++++ .../dts/aspeed/aspeed-bmc-facebook-anacapa.dts | 1077 +---------------= --- 2 files changed, 1080 insertions(+), 1076 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dts = b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dts new file mode 100644 index 000000000000..a095be48a3fe --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dts @@ -0,0 +1,1079 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/dts-v1/; +#include "aspeed-g6.dtsi" +#include +#include + +/ { + model =3D "Facebook Anacapa BMC"; + compatible =3D "facebook,anacapa-bmc-evt1", "aspeed,ast2600"; + + aliases { + serial0 =3D &uart1; + serial1 =3D &uart2; + serial2 =3D &uart3; + serial3 =3D &uart4; + serial4 =3D &uart5; + i2c16 =3D &i2c0mux0ch0; + i2c17 =3D &i2c0mux0ch1; + i2c18 =3D &i2c0mux0ch2; + i2c19 =3D &i2c0mux0ch3; + i2c20 =3D &i2c1mux0ch0; + i2c21 =3D &i2c1mux0ch1; + i2c22 =3D &i2c1mux0ch2; + i2c23 =3D &i2c1mux0ch3; + i2c24 =3D &i2c4mux0ch0; + i2c25 =3D &i2c4mux0ch1; + i2c26 =3D &i2c4mux0ch2; + i2c27 =3D &i2c4mux0ch3; + i2c28 =3D &i2c4mux0ch4; + i2c29 =3D &i2c4mux0ch5; + i2c30 =3D &i2c4mux0ch6; + i2c31 =3D &i2c4mux0ch7; + i2c32 =3D &i2c8mux0ch0; + i2c33 =3D &i2c8mux0ch1; + i2c34 =3D &i2c8mux0ch2; + i2c35 =3D &i2c8mux0ch3; + i2c36 =3D &i2c10mux0ch0; + i2c37 =3D &i2c10mux0ch1; + i2c38 =3D &i2c10mux0ch2; + i2c39 =3D &i2c10mux0ch3; + i2c40 =3D &i2c10mux0ch4; + i2c41 =3D &i2c10mux0ch5; + i2c42 =3D &i2c10mux0ch6; + i2c43 =3D &i2c10mux0ch7; + i2c44 =3D &i2c11mux0ch0; + i2c45 =3D &i2c11mux0ch1; + i2c46 =3D &i2c11mux0ch2; + i2c47 =3D &i2c11mux0ch3; + i2c48 =3D &i2c11mux0ch4; + i2c49 =3D &i2c11mux0ch5; + i2c50 =3D &i2c11mux0ch6; + i2c51 =3D &i2c11mux0ch7; + i2c52 =3D &i2c13mux0ch0; + i2c53 =3D &i2c13mux0ch1; + i2c54 =3D &i2c13mux0ch2; + i2c55 =3D &i2c13mux0ch3; + i2c56 =3D &i2c13mux0ch4; + i2c57 =3D &i2c13mux0ch5; + i2c58 =3D &i2c13mux0ch6; + i2c59 =3D &i2c13mux0ch7; + }; + + chosen { + stdout-path =3D "serial4:57600n8"; + }; + + iio-hwmon { + compatible =3D "iio-hwmon"; + io-channels =3D <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, + <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, + <&adc1 2>; + }; + + leds { + compatible =3D "gpio-leds"; + + led-0 { + label =3D "bmc_heartbeat_amber"; + gpios =3D <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>; + linux,default-trigger =3D "heartbeat"; + }; + + led-1 { + label =3D "fp_id_amber"; + default-state =3D "off"; + gpios =3D <&gpio0 ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>; + }; + }; + + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x80000000 0x80000000>; + }; + + reserved-memory { + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + video_engine_memory: video { + size =3D <0x02c00000>; + alignment =3D <0x00100000>; + compatible =3D "shared-dma-pool"; + reusable; + }; + + gfx_memory: framebuffer { + size =3D <0x01000000>; + alignment =3D <0x01000000>; + compatible =3D "shared-dma-pool"; + reusable; + }; + }; + + p3v3_bmc_aux: regulator-p3v3-bmc-aux { + compatible =3D "regulator-fixed"; + regulator-name =3D "p3v3_bmc_aux"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + }; + + spi_gpio: spi { + compatible =3D "spi-gpio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + sck-gpios =3D <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; + mosi-gpios =3D <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; + miso-gpios =3D <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>; + cs-gpios =3D <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; + num-chipselects =3D <1>; + status =3D "okay"; + + tpm@0 { + compatible =3D "infineon,slb9670", "tcg,tpm_tis-spi"; + spi-max-frequency =3D <33000000>; + reg =3D <0>; + }; + }; +}; + +&adc0 { + aspeed,int-vref-microvolt =3D <2500000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_adc0_default &pinctrl_adc1_default + &pinctrl_adc2_default &pinctrl_adc3_default + &pinctrl_adc4_default &pinctrl_adc5_default + &pinctrl_adc6_default &pinctrl_adc7_default>; + status =3D "okay"; +}; + +&adc1 { + aspeed,int-vref-microvolt =3D <2500000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_adc10_default>; + status =3D "okay"; +}; + +&ehci1 { + status =3D "okay"; +}; + +&fmc { + status =3D "okay"; + + flash@0 { + status =3D "okay"; + m25p,fast-read; + label =3D "bmc"; + spi-max-frequency =3D <50000000>; +#include "openbmc-flash-layout-128.dtsi" + }; + + flash@1 { + status =3D "okay"; + m25p,fast-read; + label =3D "alt-bmc"; + spi-max-frequency =3D <50000000>; + }; +}; + +&gfx { + status =3D "okay"; + memory-region =3D <&gfx_memory>; +}; + +&gpio0 { + gpio-line-names =3D + + /*A0-A7*/ + "","","","","","","","", + + /*B0-B7*/ + "BATTERY_DETECT", "", "", "BMC_READY", + "", "FM_ID_LED", "", "", + + /*C0-C7*/ + "","","","","","","","", + + /*D0-D7*/ + "","","","","","","","", + + /*E0-E7*/ + "","","","","","","","", + + /*F0-F7*/ + "","","","","","","","", + + /*G0-G7*/ + "FM_MUX1_SEL", "", "", "", + "", "", "FM_DEBUG_PORT_PRSNT_N", "FM_BMC_DBP_PRESENT_N", + + /*H0-H7*/ + "","","","","","","","", + + /*I0-I7*/ + "", "", "", "", + "", "FLASH_WP_STATUS", "BMC_JTAG_MUX_SEL", "", + + /*J0-J7*/ + "","","","","","","","", + + /*K0-K7*/ + "","","","","","","","", + + /*L0-L7*/ + "","","","","","","","", + + /*M0-M7*/ + "", "BMC_FRU_WP", "", "", + "", "", "", "", + + /*N0-N7*/ + "LED_POSTCODE_0", "LED_POSTCODE_1", "LED_POSTCODE_2", "LED_POSTCODE_3", + "LED_POSTCODE_4", "LED_POSTCODE_5", "LED_POSTCODE_6", "LED_POSTCODE_7", + + /*O0-O7*/ + "","","","","","","","", + + /*P0-P7*/ + "PWR_BTN_BMC_BUF_N", "", "ID_RST_BTN_BMC_N", "", + "PWR_LED", "", "", "BMC_HEARTBEAT_N", + + /*Q0-Q7*/ + "","","","","","","","", + + /*R0-R7*/ + "","","","","","","","", + + /*S0-S7*/ + "", "", "SYS_BMC_PWRBTN_N", "", + "", "", "", "RUN_POWER_FAULT", + + /*T0-T7*/ + "","","","","","","","", + + /*U0-U7*/ + "","","","","","","","", + + /*V0-V7*/ + "","","","","","","","", + + /*W0-W7*/ + "","","","","","","","", + + /*X0-X7*/ + "","","","","","","","", + + /*Y0-Y7*/ + "","","","","","","","", + + /*Z0-Z7*/ + "SPI_BMC_TPM_CS2_N", "", "", "SPI_BMC_TPM_CLK", + "SPI_BMC_TPM_MOSI", "SPI_BMC_TPM_MISO", "", ""; +}; + +&gpio1 { + gpio-line-names =3D + /*18A0-18A7*/ + "","","","","","","","", + + /*18B0-18B7*/ + "","","","", + "FM_BOARD_BMC_REV_ID0", "FM_BOARD_BMC_REV_ID1", + "FM_BOARD_BMC_REV_ID2", "", + + /*18C0-18C7*/ + "","","","","","","","", + + /*18D0-18D7*/ + "","","","","","","","", + + /*18E0-18E3*/ + "FM_BMC_PROT_LS_EN", "AC_PWR_BMC_BTN_N", "", ""; +}; + +// L Bridge Board +&i2c0 { + status =3D "okay"; + + eeprom@50 { + compatible =3D "atmel,24c2048"; + reg =3D <0x50>; + pagesize =3D <128>; + }; + + i2c-mux@70 { + compatible =3D "nxp,pca9546"; + reg =3D <0x70>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + + i2c0mux0ch0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c0mux0ch1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c0mux0ch2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c0mux0ch3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +// R Bridge Board +&i2c1 { + status =3D "okay"; + + eeprom@50 { + compatible =3D "atmel,24c2048"; + reg =3D <0x50>; + pagesize =3D <128>; + }; + + i2c-mux@70 { + compatible =3D "nxp,pca9546"; + reg =3D <0x70>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + + i2c1mux0ch0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c1mux0ch1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c1mux0ch2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c1mux0ch3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +// MB - E1.S +&i2c4 { + status =3D "okay"; + + i2c-mux@70 { + compatible =3D "nxp,pca9548"; + reg =3D <0x70>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + + i2c4mux0ch0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c4mux0ch1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c4mux0ch2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c4mux0ch3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c4mux0ch4: i2c@4 { + reg =3D <4>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c4mux0ch5: i2c@5 { + reg =3D <5>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c4mux0ch6: i2c@6 { + reg =3D <6>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c4mux0ch7: i2c@7 { + reg =3D <7>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +// AMC +&i2c5 { + status =3D "okay"; +}; + +// MB +&i2c6 { + status =3D "okay"; + + // HPM FRU + eeprom@50 { + compatible =3D "atmel,24c256"; + reg =3D <0x50>; + }; +}; + +// SCM +&i2c7 { + status =3D "okay"; + + +}; + +// MB - PDB +&i2c8 { + status =3D "okay"; + + i2c-mux@72 { + compatible =3D "nxp,pca9546"; + reg =3D <0x72>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + + i2c8mux0ch0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@1f { + compatible =3D "ti,adc128d818"; + reg =3D <0x1f>; + ti,mode =3D /bits/ 8 <1>; + }; + + gpio@22 { + compatible =3D "nxp,pca9555"; + reg =3D <0x22>; + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-parent =3D <&sgpiom0>; + interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names =3D + "RPDB_FAN_FULL_SPEED_R_N", "RPDB_I2C_TEMP75_U8_ALERT_R_N", + "RPDB_I2C_TMP432_U29_ALERT_R_N", "RPDB_GLOBAL_WP", + "RPDB_FAN_CT_FAN_FAIL_R_N", "", + "", "", + "RPDB_ALERT_P50V_HSC2_R_N", "RPDB_ALERT_P50V_HSC3_R_N", + "RPDB_ALERT_P50V_HSC4_R_N", "RPDB_ALERT_P50V_STBY_R_N", + "RPDB_I2C_P12V_MB_VRM_ALERT_R_N", + "RPDB_I2C_P12V_STBY_VRM_ALERT_R_N", + "RPDB_PGD_P3V3_STBY_PWRGD_R", + "RPDB_P12V_STBY_VRM_PWRGD_BUF_R"; + }; + + gpio@24 { + compatible =3D "nxp,pca9555"; + reg =3D <0x24>; + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-parent =3D <&sgpiom0>; + interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names =3D + "RPDB_EAM2_PRSNT_MOS_N_R", "RPDB_EAM3_PRSNT_MOS_N_R", + "RPDB_PWRGD_P50V_HSC4_SYS_R", + "RPDB_PWRGD_P50V_STBY_SYS_BUF_R", + "RPDB_P50V_FAN1_R2_PG", "RPDB_P50V_FAN2_R2_PG", + "RPDB_P50V_FAN3_R2_PG", "RPDB_P50V_FAN4_R2_PG", + "", "RPDB_FAN1_PRSNT_N_R", + "", "RPDB_FAN2_PRSNT_N_R", + "RPDB_FAN3_PRSNT_N_R", "RPDB_FAN4_PRSNT_N_R", + "", ""; + }; + + // R-PDB FRU + eeprom@50 { + compatible =3D "atmel,24c128"; + reg =3D <0x50>; + }; + }; + i2c8mux0ch1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + gpio@22 { + compatible =3D "nxp,pca9555"; + reg =3D <0x22>; + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-parent =3D <&sgpiom0>; + interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names =3D + "LPDB_FAN_FULL_SPEED_R_N","LPDB_I2C_TEMP75_U8_ALERT_R_N", + "LPDB_I2C_TMP432_U29_ALERT_R_N","LPDB_GLOBAL_WP", + "LPDB_FAN_CT_FAN_FAIL_R_N","", + "","", + "LPDB_ALERT_P50V_HSC0_R_N","LPDB_ALERT_P50V_HSC1_R_N", + "LPDB_ALERT_P50V_HSC5_R_N","LPDB_I2C_P12V_SW_VRM_ALERT_R_N", + "LPDB_EAM0_PRSNT_MOS_N_R","LPDB_EAM1_PRSNT_MOS_N_R", + "LPDB_PWRGD_P50V_HSC5_SYS_R",""; + }; + + gpio@24 { + compatible =3D "nxp,pca9555"; + reg =3D <0x24>; + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-parent =3D <&sgpiom0>; + interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names =3D + "LPDB_P50V_FAN1_R2_PG","LPDB_P50V_FAN2_R2_PG", + "LPDB_P50V_FAN3_R2_PG","LPDB_P50V_FAN4_R2_PG", + "LPDB_P50V_FAN5_R2_PG","LPDB_FAN1_PRSNT_N_R", + "LPDB_FAN2_PRSNT_N_R","LPDB_FAN3_PRSNT_N_R", + "LPDB_FAN4_PRSNT_N_R","LPDB_FAN5_PRSNT_N_R", + "","", + "","", + "",""; + }; + + // L-PDB FRU + eeprom@50 { + compatible =3D "atmel,24c128"; + reg =3D <0x50>; + }; + }; + i2c8mux0ch2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c8mux0ch3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +// SCM +&i2c9 { + status =3D "okay"; + + // SCM FRU + eeprom@50 { + compatible =3D "atmel,24c128"; + reg =3D <0x50>; + }; + + // BSM FRU + eeprom@56 { + compatible =3D "atmel,24c64"; + reg =3D <0x56>; + }; +}; + +// R Bridge Board +&i2c10 { + status =3D "okay"; + + i2c-mux@71 { + compatible =3D "nxp,pca9548"; + reg =3D <0x71>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + + i2c10mux0ch0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c10mux0ch1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c10mux0ch2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c10mux0ch3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c10mux0ch4: i2c@4 { + reg =3D <4>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c10mux0ch5: i2c@5 { + reg =3D <5>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + gpio@22 { + compatible =3D "nxp,pca9555"; + reg =3D <0x22>; + gpio-controller; + #gpio-cells =3D <2>; + + gpio-line-names =3D + "","", + "","RBB_CPLD_REFRESH_IN_PRGRS_R_L", + "RBB_EAM0_NIC_CBL_PRSNT_R_L","RBB_EAM1_NIC_CBL_PRSNT_R_L", + "RBB_AINIC_JTAG_MUX_R2_SEL","RBB_SPI_MUX0_R2_SEL", + "RBB_AINIC_PRSNT_R_L","RBB_AINIC_OE_R_N", + "RBB_AINIC_BOARD_R2_ID","RBB_RST_USB2_HUB_R_N", + "RBB_RST_FT4222_R_N","RBB_RST_MCP2210_R_N", + "",""; + }; + + // R Bridge Board FRU + eeprom@52 { + compatible =3D "atmel,24c256"; + reg =3D <0x52>; + }; + }; + i2c10mux0ch6: i2c@6 { + reg =3D <6>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c10mux0ch7: i2c@7 { + reg =3D <7>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +// L Bridge Board +&i2c11 { + status =3D "okay"; + + i2c-mux@71 { + compatible =3D "nxp,pca9548"; + reg =3D <0x71>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + + i2c11mux0ch0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c11mux0ch1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c11mux0ch2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c11mux0ch3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c11mux0ch4: i2c@4 { + reg =3D <4>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c11mux0ch5: i2c@5 { + reg =3D <5>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + gpio@22 { + compatible =3D "nxp,pca9555"; + reg =3D <0x22>; + gpio-controller; + #gpio-cells =3D <2>; + + gpio-line-names =3D + "","", + "","LBB_CPLD_REFRESH_IN_PRGRS_R_L", + "LBB_EAM0_NIC_CBL_PRSNT_R_L","LBB_EAM1_NIC_CBL_PRSNT_R_L", + "LBB_AINIC_JTAG_MUX_R2_SEL","LBB_SPI_MUX0_R2_SEL", + "LBB_AINIC_PRSNT_R_L","LBB_AINIC_OE_R_N", + "LBB_AINIC_BOARD_R2_ID","LBB_RST_USB2_HUB_R_N", + "LBB_RST_FT4222_R_N","LBB_RST_MCP2210_R_N", + "",""; + }; + + // L Bridge Board FRU + eeprom@52 { + compatible =3D "atmel,24c256"; + reg =3D <0x52>; + }; + }; + i2c11mux0ch6: i2c@6 { + reg =3D <6>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c11mux0ch7: i2c@7 { + reg =3D <7>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +// Debug Card +&i2c12 { + status =3D "okay"; +}; + +// MB +&i2c13 { + status =3D "okay"; + + i2c-mux@70 { + compatible =3D "nxp,pca9548"; + reg =3D <0x70>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + + i2c13mux0ch0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c13mux0ch1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c13mux0ch2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c13mux0ch3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@1f { + compatible =3D "ti,adc128d818"; + reg =3D <0x1f>; + ti,mode =3D /bits/ 8 <1>; + }; + }; + i2c13mux0ch4: i2c@4 { + reg =3D <4>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + // HPM BRD ID FRU + eeprom@51 { + compatible =3D "atmel,24c256"; + reg =3D <0x51>; + }; + }; + i2c13mux0ch5: i2c@5 { + reg =3D <5>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c13mux0ch6: i2c@6 { + reg =3D <6>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + i2c13mux0ch7: i2c@7 { + reg =3D <7>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + nfc@28 { + compatible =3D "nxp,nxp-nci-i2c"; + reg =3D <0x28>; + + interrupt-parent =3D <&sgpiom0>; + interrupts =3D <156 IRQ_TYPE_LEVEL_HIGH>; + + enable-gpios =3D <&sgpiom0 241 GPIO_ACTIVE_HIGH>; + }; + }; + }; +}; + +// SCM +&i2c14 { + status =3D "okay"; +}; + +&i2c15 { + status =3D "okay"; +}; + +&kcs2 { + aspeed,lpc-io-reg =3D <0xca8>; + status =3D "okay"; +}; + +&kcs3 { + aspeed,lpc-io-reg =3D <0xca2>; + status =3D "okay"; +}; + +&lpc_ctrl { + status =3D "okay"; +}; + +&mac2 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_ncsi3_default>; + use-ncsi; +}; + +&sgpiom0 { + ngpios =3D <128>; + bus-frequency =3D <2000000>; + gpio-line-names =3D + /*in - out - in - out */ + /* A0-A7 line 0-15 */ + "", "FM_CPU0_SYS_RESET_N", "", "CPU0_KBRST_N", + "", "FM_CPU0_PROCHOT_trigger_N", "", "FM_CLR_CMOS_R_P0", + "", "Force_I3C_SEL", "", "SYSTEM_Force_Run_AC_Cycle", + "", "", "", "", + + /* B0-B7 line 16-31 */ + "Channel0_leakage_EAM3", "FM_CPU_FPGA_JTAG_MUX_SEL", + "Channel1_leakage_EAM0", "FM_SCM_JTAG_MUX_SEL", + "Channel2_leakage_Manifold1", "FM_BRIDGE_JTAG_MUX_SEL", + "Channel3_leakage", "FM_CPU0_NMI_SYNC_FLOOD_N", + "Channel4_leakage_Manifold2", "", + "Channel5_leakage_EAM1", "", + "Channel6_leakage_CPU_DIMM", "", + "Channel7_leakage_EAM2", "", + + /* C0-C7 line 32-47 */ + "RSVD_RMC_GPIO3", "", "", "", + "", "", "", "", + "LEAK_DETECT_RMC_N", "JTAG_CPLD_TRST_R_N", "", "", + "", "", "", "", + + /* D0-D7 line 48-63 */ + "PWRGD_PDB_EAMHSC0_CPLD_PG_R", "", + "PWRGD_PDB_EAMHSC1_CPLD_PG_R", "", + "PWRGD_PDB_EAMHSC2_CPLD_PG_R", "", + "PWRGD_PDB_EAMHSC3_CPLD_PG_R", "", + "AMC_BRD_PRSNT_CPLD_L", "", "", "", + "", "", "", "", + + /* E0-E7 line 64-79 */ + "AMC_PDB_EAMHSC0_CPLD_EN_R", "", + "AMC_PDB_EAMHSC1_CPLD_EN_R", "", + "AMC_PDB_EAMHSC2_CPLD_EN_R", "", + "AMC_PDB_EAMHSC3_CPLD_EN_R", "", + "", "", "", "", + "", "", "", "", + + /* F0-F7 line 80-95 */ + "PWRGD_PVDDCR_CPU1_P0", "SGPIO_READY", + "PWRGD_PVDDCR_CPU0_P0", "", + "", "", "", "", + "", "", "", "", + + /* G0-G7 line 96-111 */ + "L_PRSNT_EDSFF0_N", "", + "L_PRSNT_EDSFF1_N", "", + "R_PRSNT_EDSFF2_N", "", + "R_PRSNT_EDSFF3_N", "", + "HPM_EDSFF_PG", "", + "PWRGD_CHEH_CPU0_FPGA", "", + "PWRGD_CHAD_CPU0_FPGA", "FM_BMC_READY_PLD", + "", "", + + /* H0-H7 line 112-127 */ + "PWRGD_P3V3", "", + "P12V_DDR_IP_PWRGD_R", "", + "P12V_DDR_AH_PWRGD_R", "", + "PWRGD_P12V_VRM1_CPLD_PG_R", "", + "PWRGD_P12V_VRM0_CPLD_PG_R", "", + "PWRGD_PDB_HSC4_CPLD_PG_R", "", + "PWRGD_PVDD18_S5_P0_PG", "", + "PWRGD_PVDD33_S5_P0_PG", "", + + /* I0-I7 line 128-143 */ + "EAM0_BRD_PRSNT_R_L", "", + "EAM1_BRD_PRSNT_R_L", "", + "EAM2_BRD_PRSNT_R_L", "", + "EAM3_BRD_PRSNT_R_L", "", + "EAM0_CPU_MOD_PWR_GD_R", "", + "EAM1_CPU_MOD_PWR_GD_R", "", + "PRSNT_EDSFF_BOOT_N", "", + "EAM3_CPU_MOD_PWR_GD_R", "", + + /* J0-J7 line 144-159 */ + "PRSNT_L_BIRDGE_R", "", + "PRSNT_R_BIRDGE_R", "", + "BRIDGE_L_MAIN_PG_R", "", + "BRIDGE_R_MAIN_PG_R", "", + "BRIDGE_L_STBY_PG_R", "", + "BRIDGE_R_STBY_PG_R", "", + "", "", "", "", + + /* K0-K7 line 160-175 */ + "ADC_I2C_ALERT_N", "", + "TEMP_I2C_ALERT_R_L", "", + "CPU0_VR_SMB_ALERT_CPLD_N", "", + "COVER_INTRUDER_R_N", "", + "HANDLE_INTRUDER_CPLD_N", "", + "IRQ_MCIO_CPLD_WAKE_R_N", "", + "APML_CPU0_ALERT_R_N", "", + "PDB_ALERT_R_N", "", + + /* L0-L7 line 176-191 */ + "L_EDSFF0_PG", "", "L_EDSFF1_PG", "", + "R_EDSFF2_PG", "", "R_EDSFF3_PG", "", + "CPU0_CORETYPE0", "", "CPU0_CORETYPE1", "", + "CPU0_CORETYPE2", "", "FM_BIOS_POST_CMPLT_R_N", "", + + /* M0-M7 line 192-207 */ + "EAM0_SMERR_CPLD_R_L", "", + "EAM1_SMERR_CPLD_R_L", "", + "EAM2_SMERR_CPLD_R_L", "", + "EAM3_SMERR_CPLD_R_L", "", + "CPU0_SMERR_N_R", "", + "CPU0_NV_SAVE_N_R", "", + "PDB_PWR_LOSS_CPLD_N", "", + "IRQ_BMC_SMI_ACTIVE_R_N", "", + + /* N0-N7 line 208-223 */ + "AMCROT_BMC_S5_RDY_R", "", + "AMC_RDY_R", "", + "AMC_STBY_PGOOD_R", "", + "CPU_AMC_SLP_S5_R_L", "", + "AMC_CPU_EAMPG_R", "", + "", "", "", "", + + /* O0-O7 line 224-239 */ + "HPM_PWR_FAIL", "Port80_b0", + "FM_DIMM_IP_FAIL", "Port80_b1", + "FM_DIMM_AH_FAIL", "Port80_b2", + "AMC_THERMTRIP_ASSERT", "Port80_b3", + "CPU_THERMTRIP_ASSERT", "Port80_b4", + "PVDDCR_SOC_P0_OCP_L", "Port80_b5", + "CPLD_SGPIO_RDY", "Port80_b6", + "", "Port80_b7", + + /* P0-P7 line 240-255 */ + "CPU0_SLP_S5_N_R", "NFC_VEN", + "CPU0_SLP_S3_N_R", "", + "FM_CPU0_PWRGD", "", + "PWRGD_RMC", "", + "FM_RST_CPU0_RESET_N", "", + "FM_PWRGD_CPU0_PWROK", "", + "wS5_PWR_Ready", "", + "wS0_ON_N", "PWRGD_P1V0_AUX"; + status =3D "okay"; +}; + +// BIOS Flash +&spi2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_spi2_default>; + status =3D "okay"; + reg =3D <0x1e631000 0xc4>, <0x50000000 0x8000000>; + + flash@0 { + compatible =3D "jedec,spi-nor"; + label =3D "pnor"; + spi-max-frequency =3D <12000000>; + spi-tx-bus-width =3D <2>; + spi-rx-bus-width =3D <2>; + status =3D "okay"; + }; +}; + +// HOST BIOS Debug +&uart1 { + status =3D "okay"; +}; + +&uart3 { + status =3D "okay"; +}; + +&uart4 { + status =3D "okay"; +}; + +// BMC Debug Console +&uart5 { + status =3D "okay"; +}; + +&uart_routing { + status =3D "okay"; +}; + +&uhci { + status =3D "okay"; +}; + +&vhub { + status =3D "okay"; + pinctrl-names =3D "default"; +}; + +&video { + status =3D "okay"; + memory-region =3D <&video_engine_memory>; +}; + +&wdt1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_wdtrst1_default>; + aspeed,reset-type =3D "soc"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + aspeed,ext-pulse-duration =3D <256>; + status =3D "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts b/arc= h/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts index 1fddf3a5d138..209eef65cedb 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts @@ -1,1079 +1,4 @@ // SPDX-License-Identifier: GPL-2.0-or-later =20 -/dts-v1/; -#include "aspeed-g6.dtsi" -#include -#include +#include "aspeed-bmc-facebook-anacapa-evt1.dts" =20 -/ { - model =3D "Facebook Anacapa BMC"; - compatible =3D "facebook,anacapa-bmc", "aspeed,ast2600"; - - aliases { - serial0 =3D &uart1; - serial1 =3D &uart2; - serial2 =3D &uart3; - serial3 =3D &uart4; - serial4 =3D &uart5; - i2c16 =3D &i2c0mux0ch0; - i2c17 =3D &i2c0mux0ch1; - i2c18 =3D &i2c0mux0ch2; - i2c19 =3D &i2c0mux0ch3; - i2c20 =3D &i2c1mux0ch0; - i2c21 =3D &i2c1mux0ch1; - i2c22 =3D &i2c1mux0ch2; - i2c23 =3D &i2c1mux0ch3; - i2c24 =3D &i2c4mux0ch0; - i2c25 =3D &i2c4mux0ch1; - i2c26 =3D &i2c4mux0ch2; - i2c27 =3D &i2c4mux0ch3; - i2c28 =3D &i2c4mux0ch4; - i2c29 =3D &i2c4mux0ch5; - i2c30 =3D &i2c4mux0ch6; - i2c31 =3D &i2c4mux0ch7; - i2c32 =3D &i2c8mux0ch0; - i2c33 =3D &i2c8mux0ch1; - i2c34 =3D &i2c8mux0ch2; - i2c35 =3D &i2c8mux0ch3; - i2c36 =3D &i2c10mux0ch0; - i2c37 =3D &i2c10mux0ch1; - i2c38 =3D &i2c10mux0ch2; - i2c39 =3D &i2c10mux0ch3; - i2c40 =3D &i2c10mux0ch4; - i2c41 =3D &i2c10mux0ch5; - i2c42 =3D &i2c10mux0ch6; - i2c43 =3D &i2c10mux0ch7; - i2c44 =3D &i2c11mux0ch0; - i2c45 =3D &i2c11mux0ch1; - i2c46 =3D &i2c11mux0ch2; - i2c47 =3D &i2c11mux0ch3; - i2c48 =3D &i2c11mux0ch4; - i2c49 =3D &i2c11mux0ch5; - i2c50 =3D &i2c11mux0ch6; - i2c51 =3D &i2c11mux0ch7; - i2c52 =3D &i2c13mux0ch0; - i2c53 =3D &i2c13mux0ch1; - i2c54 =3D &i2c13mux0ch2; - i2c55 =3D &i2c13mux0ch3; - i2c56 =3D &i2c13mux0ch4; - i2c57 =3D &i2c13mux0ch5; - i2c58 =3D &i2c13mux0ch6; - i2c59 =3D &i2c13mux0ch7; - }; - - chosen { - stdout-path =3D "serial4:57600n8"; - }; - - iio-hwmon { - compatible =3D "iio-hwmon"; - io-channels =3D <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, - <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, - <&adc1 2>; - }; - - leds { - compatible =3D "gpio-leds"; - - led-0 { - label =3D "bmc_heartbeat_amber"; - gpios =3D <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>; - linux,default-trigger =3D "heartbeat"; - }; - - led-1 { - label =3D "fp_id_amber"; - default-state =3D "off"; - gpios =3D <&gpio0 ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>; - }; - }; - - memory@80000000 { - device_type =3D "memory"; - reg =3D <0x80000000 0x80000000>; - }; - - reserved-memory { - #address-cells =3D <1>; - #size-cells =3D <1>; - ranges; - - video_engine_memory: video { - size =3D <0x02c00000>; - alignment =3D <0x00100000>; - compatible =3D "shared-dma-pool"; - reusable; - }; - - gfx_memory: framebuffer { - size =3D <0x01000000>; - alignment =3D <0x01000000>; - compatible =3D "shared-dma-pool"; - reusable; - }; - }; - - p3v3_bmc_aux: regulator-p3v3-bmc-aux { - compatible =3D "regulator-fixed"; - regulator-name =3D "p3v3_bmc_aux"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - regulator-always-on; - }; - - spi_gpio: spi { - compatible =3D "spi-gpio"; - #address-cells =3D <1>; - #size-cells =3D <0>; - - sck-gpios =3D <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; - mosi-gpios =3D <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; - miso-gpios =3D <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>; - cs-gpios =3D <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; - num-chipselects =3D <1>; - status =3D "okay"; - - tpm@0 { - compatible =3D "infineon,slb9670", "tcg,tpm_tis-spi"; - spi-max-frequency =3D <33000000>; - reg =3D <0>; - }; - }; -}; - -&adc0 { - aspeed,int-vref-microvolt =3D <2500000>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_adc0_default &pinctrl_adc1_default - &pinctrl_adc2_default &pinctrl_adc3_default - &pinctrl_adc4_default &pinctrl_adc5_default - &pinctrl_adc6_default &pinctrl_adc7_default>; - status =3D "okay"; -}; - -&adc1 { - aspeed,int-vref-microvolt =3D <2500000>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_adc10_default>; - status =3D "okay"; -}; - -&ehci1 { - status =3D "okay"; -}; - -&fmc { - status =3D "okay"; - - flash@0 { - status =3D "okay"; - m25p,fast-read; - label =3D "bmc"; - spi-max-frequency =3D <50000000>; -#include "openbmc-flash-layout-128.dtsi" - }; - - flash@1 { - status =3D "okay"; - m25p,fast-read; - label =3D "alt-bmc"; - spi-max-frequency =3D <50000000>; - }; -}; - -&gfx { - status =3D "okay"; - memory-region =3D <&gfx_memory>; -}; - -&gpio0 { - gpio-line-names =3D - - /*A0-A7*/ - "","","","","","","","", - - /*B0-B7*/ - "BATTERY_DETECT", "", "", "BMC_READY", - "", "FM_ID_LED", "", "", - - /*C0-C7*/ - "","","","","","","","", - - /*D0-D7*/ - "","","","","","","","", - - /*E0-E7*/ - "","","","","","","","", - - /*F0-F7*/ - "","","","","","","","", - - /*G0-G7*/ - "FM_MUX1_SEL", "", "", "", - "", "", "FM_DEBUG_PORT_PRSNT_N", "FM_BMC_DBP_PRESENT_N", - - /*H0-H7*/ - "","","","","","","","", - - /*I0-I7*/ - "", "", "", "", - "", "FLASH_WP_STATUS", "BMC_JTAG_MUX_SEL", "", - - /*J0-J7*/ - "","","","","","","","", - - /*K0-K7*/ - "","","","","","","","", - - /*L0-L7*/ - "","","","","","","","", - - /*M0-M7*/ - "", "BMC_FRU_WP", "", "", - "", "", "", "", - - /*N0-N7*/ - "LED_POSTCODE_0", "LED_POSTCODE_1", "LED_POSTCODE_2", "LED_POSTCODE_3", - "LED_POSTCODE_4", "LED_POSTCODE_5", "LED_POSTCODE_6", "LED_POSTCODE_7", - - /*O0-O7*/ - "","","","","","","","", - - /*P0-P7*/ - "PWR_BTN_BMC_BUF_N", "", "ID_RST_BTN_BMC_N", "", - "PWR_LED", "", "", "BMC_HEARTBEAT_N", - - /*Q0-Q7*/ - "","","","","","","","", - - /*R0-R7*/ - "","","","","","","","", - - /*S0-S7*/ - "", "", "SYS_BMC_PWRBTN_N", "", - "", "", "", "RUN_POWER_FAULT", - - /*T0-T7*/ - "","","","","","","","", - - /*U0-U7*/ - "","","","","","","","", - - /*V0-V7*/ - "","","","","","","","", - - /*W0-W7*/ - "","","","","","","","", - - /*X0-X7*/ - "","","","","","","","", - - /*Y0-Y7*/ - "","","","","","","","", - - /*Z0-Z7*/ - "SPI_BMC_TPM_CS2_N", "", "", "SPI_BMC_TPM_CLK", - "SPI_BMC_TPM_MOSI", "SPI_BMC_TPM_MISO", "", ""; -}; - -&gpio1 { - gpio-line-names =3D - /*18A0-18A7*/ - "","","","","","","","", - - /*18B0-18B7*/ - "","","","", - "FM_BOARD_BMC_REV_ID0", "FM_BOARD_BMC_REV_ID1", - "FM_BOARD_BMC_REV_ID2", "", - - /*18C0-18C7*/ - "","","","","","","","", - - /*18D0-18D7*/ - "","","","","","","","", - - /*18E0-18E3*/ - "FM_BMC_PROT_LS_EN", "AC_PWR_BMC_BTN_N", "", ""; -}; - -// L Bridge Board -&i2c0 { - status =3D "okay"; - - eeprom@50 { - compatible =3D "atmel,24c2048"; - reg =3D <0x50>; - pagesize =3D <128>; - }; - - i2c-mux@70 { - compatible =3D "nxp,pca9546"; - reg =3D <0x70>; - #address-cells =3D <1>; - #size-cells =3D <0>; - i2c-mux-idle-disconnect; - - i2c0mux0ch0: i2c@0 { - reg =3D <0>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c0mux0ch1: i2c@1 { - reg =3D <1>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c0mux0ch2: i2c@2 { - reg =3D <2>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c0mux0ch3: i2c@3 { - reg =3D <3>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - }; -}; - -// R Bridge Board -&i2c1 { - status =3D "okay"; - - eeprom@50 { - compatible =3D "atmel,24c2048"; - reg =3D <0x50>; - pagesize =3D <128>; - }; - - i2c-mux@70 { - compatible =3D "nxp,pca9546"; - reg =3D <0x70>; - #address-cells =3D <1>; - #size-cells =3D <0>; - i2c-mux-idle-disconnect; - - i2c1mux0ch0: i2c@0 { - reg =3D <0>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c1mux0ch1: i2c@1 { - reg =3D <1>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c1mux0ch2: i2c@2 { - reg =3D <2>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c1mux0ch3: i2c@3 { - reg =3D <3>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - }; -}; - -// MB - E1.S -&i2c4 { - status =3D "okay"; - - i2c-mux@70 { - compatible =3D "nxp,pca9548"; - reg =3D <0x70>; - #address-cells =3D <1>; - #size-cells =3D <0>; - i2c-mux-idle-disconnect; - - i2c4mux0ch0: i2c@0 { - reg =3D <0>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c4mux0ch1: i2c@1 { - reg =3D <1>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c4mux0ch2: i2c@2 { - reg =3D <2>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c4mux0ch3: i2c@3 { - reg =3D <3>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c4mux0ch4: i2c@4 { - reg =3D <4>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c4mux0ch5: i2c@5 { - reg =3D <5>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c4mux0ch6: i2c@6 { - reg =3D <6>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c4mux0ch7: i2c@7 { - reg =3D <7>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - }; -}; - -// AMC -&i2c5 { - status =3D "okay"; -}; - -// MB -&i2c6 { - status =3D "okay"; - - // HPM FRU - eeprom@50 { - compatible =3D "atmel,24c256"; - reg =3D <0x50>; - }; -}; - -// SCM -&i2c7 { - status =3D "okay"; - - -}; - -// MB - PDB -&i2c8 { - status =3D "okay"; - - i2c-mux@72 { - compatible =3D "nxp,pca9546"; - reg =3D <0x72>; - #address-cells =3D <1>; - #size-cells =3D <0>; - i2c-mux-idle-disconnect; - - i2c8mux0ch0: i2c@0 { - reg =3D <0>; - #address-cells =3D <1>; - #size-cells =3D <0>; - - adc@1f { - compatible =3D "ti,adc128d818"; - reg =3D <0x1f>; - ti,mode =3D /bits/ 8 <1>; - }; - - gpio@22 { - compatible =3D "nxp,pca9555"; - reg =3D <0x22>; - gpio-controller; - #gpio-cells =3D <2>; - - interrupt-parent =3D <&sgpiom0>; - interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; - - gpio-line-names =3D - "RPDB_FAN_FULL_SPEED_R_N", "RPDB_I2C_TEMP75_U8_ALERT_R_N", - "RPDB_I2C_TMP432_U29_ALERT_R_N", "RPDB_GLOBAL_WP", - "RPDB_FAN_CT_FAN_FAIL_R_N", "", - "", "", - "RPDB_ALERT_P50V_HSC2_R_N", "RPDB_ALERT_P50V_HSC3_R_N", - "RPDB_ALERT_P50V_HSC4_R_N", "RPDB_ALERT_P50V_STBY_R_N", - "RPDB_I2C_P12V_MB_VRM_ALERT_R_N", - "RPDB_I2C_P12V_STBY_VRM_ALERT_R_N", - "RPDB_PGD_P3V3_STBY_PWRGD_R", - "RPDB_P12V_STBY_VRM_PWRGD_BUF_R"; - }; - - gpio@24 { - compatible =3D "nxp,pca9555"; - reg =3D <0x24>; - gpio-controller; - #gpio-cells =3D <2>; - - interrupt-parent =3D <&sgpiom0>; - interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; - - gpio-line-names =3D - "RPDB_EAM2_PRSNT_MOS_N_R", "RPDB_EAM3_PRSNT_MOS_N_R", - "RPDB_PWRGD_P50V_HSC4_SYS_R", - "RPDB_PWRGD_P50V_STBY_SYS_BUF_R", - "RPDB_P50V_FAN1_R2_PG", "RPDB_P50V_FAN2_R2_PG", - "RPDB_P50V_FAN3_R2_PG", "RPDB_P50V_FAN4_R2_PG", - "", "RPDB_FAN1_PRSNT_N_R", - "", "RPDB_FAN2_PRSNT_N_R", - "RPDB_FAN3_PRSNT_N_R", "RPDB_FAN4_PRSNT_N_R", - "", ""; - }; - - // R-PDB FRU - eeprom@50 { - compatible =3D "atmel,24c128"; - reg =3D <0x50>; - }; - }; - i2c8mux0ch1: i2c@1 { - reg =3D <1>; - #address-cells =3D <1>; - #size-cells =3D <0>; - - gpio@22 { - compatible =3D "nxp,pca9555"; - reg =3D <0x22>; - gpio-controller; - #gpio-cells =3D <2>; - - interrupt-parent =3D <&sgpiom0>; - interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; - - gpio-line-names =3D - "LPDB_FAN_FULL_SPEED_R_N","LPDB_I2C_TEMP75_U8_ALERT_R_N", - "LPDB_I2C_TMP432_U29_ALERT_R_N","LPDB_GLOBAL_WP", - "LPDB_FAN_CT_FAN_FAIL_R_N","", - "","", - "LPDB_ALERT_P50V_HSC0_R_N","LPDB_ALERT_P50V_HSC1_R_N", - "LPDB_ALERT_P50V_HSC5_R_N","LPDB_I2C_P12V_SW_VRM_ALERT_R_N", - "LPDB_EAM0_PRSNT_MOS_N_R","LPDB_EAM1_PRSNT_MOS_N_R", - "LPDB_PWRGD_P50V_HSC5_SYS_R",""; - }; - - gpio@24 { - compatible =3D "nxp,pca9555"; - reg =3D <0x24>; - gpio-controller; - #gpio-cells =3D <2>; - - interrupt-parent =3D <&sgpiom0>; - interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; - - gpio-line-names =3D - "LPDB_P50V_FAN1_R2_PG","LPDB_P50V_FAN2_R2_PG", - "LPDB_P50V_FAN3_R2_PG","LPDB_P50V_FAN4_R2_PG", - "LPDB_P50V_FAN5_R2_PG","LPDB_FAN1_PRSNT_N_R", - "LPDB_FAN2_PRSNT_N_R","LPDB_FAN3_PRSNT_N_R", - "LPDB_FAN4_PRSNT_N_R","LPDB_FAN5_PRSNT_N_R", - "","", - "","", - "",""; - }; - - // L-PDB FRU - eeprom@50 { - compatible =3D "atmel,24c128"; - reg =3D <0x50>; - }; - }; - i2c8mux0ch2: i2c@2 { - reg =3D <2>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c8mux0ch3: i2c@3 { - reg =3D <3>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - }; -}; - -// SCM -&i2c9 { - status =3D "okay"; - - // SCM FRU - eeprom@50 { - compatible =3D "atmel,24c128"; - reg =3D <0x50>; - }; - - // BSM FRU - eeprom@56 { - compatible =3D "atmel,24c64"; - reg =3D <0x56>; - }; -}; - -// R Bridge Board -&i2c10 { - status =3D "okay"; - - i2c-mux@71 { - compatible =3D "nxp,pca9548"; - reg =3D <0x71>; - #address-cells =3D <1>; - #size-cells =3D <0>; - i2c-mux-idle-disconnect; - - i2c10mux0ch0: i2c@0 { - reg =3D <0>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c10mux0ch1: i2c@1 { - reg =3D <1>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c10mux0ch2: i2c@2 { - reg =3D <2>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c10mux0ch3: i2c@3 { - reg =3D <3>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c10mux0ch4: i2c@4 { - reg =3D <4>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c10mux0ch5: i2c@5 { - reg =3D <5>; - #address-cells =3D <1>; - #size-cells =3D <0>; - - gpio@22 { - compatible =3D "nxp,pca9555"; - reg =3D <0x22>; - gpio-controller; - #gpio-cells =3D <2>; - - gpio-line-names =3D - "","", - "","RBB_CPLD_REFRESH_IN_PRGRS_R_L", - "RBB_EAM0_NIC_CBL_PRSNT_R_L","RBB_EAM1_NIC_CBL_PRSNT_R_L", - "RBB_AINIC_JTAG_MUX_R2_SEL","RBB_SPI_MUX0_R2_SEL", - "RBB_AINIC_PRSNT_R_L","RBB_AINIC_OE_R_N", - "RBB_AINIC_BOARD_R2_ID","RBB_RST_USB2_HUB_R_N", - "RBB_RST_FT4222_R_N","RBB_RST_MCP2210_R_N", - "",""; - }; - - // R Bridge Board FRU - eeprom@52 { - compatible =3D "atmel,24c256"; - reg =3D <0x52>; - }; - }; - i2c10mux0ch6: i2c@6 { - reg =3D <6>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c10mux0ch7: i2c@7 { - reg =3D <7>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - }; -}; - -// L Bridge Board -&i2c11 { - status =3D "okay"; - - i2c-mux@71 { - compatible =3D "nxp,pca9548"; - reg =3D <0x71>; - #address-cells =3D <1>; - #size-cells =3D <0>; - i2c-mux-idle-disconnect; - - i2c11mux0ch0: i2c@0 { - reg =3D <0>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c11mux0ch1: i2c@1 { - reg =3D <1>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c11mux0ch2: i2c@2 { - reg =3D <2>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c11mux0ch3: i2c@3 { - reg =3D <3>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c11mux0ch4: i2c@4 { - reg =3D <4>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c11mux0ch5: i2c@5 { - reg =3D <5>; - #address-cells =3D <1>; - #size-cells =3D <0>; - - gpio@22 { - compatible =3D "nxp,pca9555"; - reg =3D <0x22>; - gpio-controller; - #gpio-cells =3D <2>; - - gpio-line-names =3D - "","", - "","LBB_CPLD_REFRESH_IN_PRGRS_R_L", - "LBB_EAM0_NIC_CBL_PRSNT_R_L","LBB_EAM1_NIC_CBL_PRSNT_R_L", - "LBB_AINIC_JTAG_MUX_R2_SEL","LBB_SPI_MUX0_R2_SEL", - "LBB_AINIC_PRSNT_R_L","LBB_AINIC_OE_R_N", - "LBB_AINIC_BOARD_R2_ID","LBB_RST_USB2_HUB_R_N", - "LBB_RST_FT4222_R_N","LBB_RST_MCP2210_R_N", - "",""; - }; - - // L Bridge Board FRU - eeprom@52 { - compatible =3D "atmel,24c256"; - reg =3D <0x52>; - }; - }; - i2c11mux0ch6: i2c@6 { - reg =3D <6>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c11mux0ch7: i2c@7 { - reg =3D <7>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - }; -}; - -// Debug Card -&i2c12 { - status =3D "okay"; -}; - -// MB -&i2c13 { - status =3D "okay"; - - i2c-mux@70 { - compatible =3D "nxp,pca9548"; - reg =3D <0x70>; - #address-cells =3D <1>; - #size-cells =3D <0>; - i2c-mux-idle-disconnect; - - i2c13mux0ch0: i2c@0 { - reg =3D <0>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c13mux0ch1: i2c@1 { - reg =3D <1>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c13mux0ch2: i2c@2 { - reg =3D <2>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c13mux0ch3: i2c@3 { - reg =3D <3>; - #address-cells =3D <1>; - #size-cells =3D <0>; - - adc@1f { - compatible =3D "ti,adc128d818"; - reg =3D <0x1f>; - ti,mode =3D /bits/ 8 <1>; - }; - }; - i2c13mux0ch4: i2c@4 { - reg =3D <4>; - #address-cells =3D <1>; - #size-cells =3D <0>; - - // HPM BRD ID FRU - eeprom@51 { - compatible =3D "atmel,24c256"; - reg =3D <0x51>; - }; - }; - i2c13mux0ch5: i2c@5 { - reg =3D <5>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c13mux0ch6: i2c@6 { - reg =3D <6>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - i2c13mux0ch7: i2c@7 { - reg =3D <7>; - #address-cells =3D <1>; - #size-cells =3D <0>; - - nfc@28 { - compatible =3D "nxp,nxp-nci-i2c"; - reg =3D <0x28>; - - interrupt-parent =3D <&sgpiom0>; - interrupts =3D <156 IRQ_TYPE_LEVEL_HIGH>; - - enable-gpios =3D <&sgpiom0 241 GPIO_ACTIVE_HIGH>; - }; - }; - }; -}; - -// SCM -&i2c14 { - status =3D "okay"; -}; - -&i2c15 { - status =3D "okay"; -}; - -&kcs2 { - aspeed,lpc-io-reg =3D <0xca8>; - status =3D "okay"; -}; - -&kcs3 { - aspeed,lpc-io-reg =3D <0xca2>; - status =3D "okay"; -}; - -&lpc_ctrl { - status =3D "okay"; -}; - -&mac2 { - status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_ncsi3_default>; - use-ncsi; -}; - -&sgpiom0 { - ngpios =3D <128>; - bus-frequency =3D <2000000>; - gpio-line-names =3D - /*in - out - in - out */ - /* A0-A7 line 0-15 */ - "", "FM_CPU0_SYS_RESET_N", "", "CPU0_KBRST_N", - "", "FM_CPU0_PROCHOT_trigger_N", "", "FM_CLR_CMOS_R_P0", - "", "Force_I3C_SEL", "", "SYSTEM_Force_Run_AC_Cycle", - "", "", "", "", - - /* B0-B7 line 16-31 */ - "Channel0_leakage_EAM3", "FM_CPU_FPGA_JTAG_MUX_SEL", - "Channel1_leakage_EAM0", "FM_SCM_JTAG_MUX_SEL", - "Channel2_leakage_Manifold1", "FM_BRIDGE_JTAG_MUX_SEL", - "Channel3_leakage", "FM_CPU0_NMI_SYNC_FLOOD_N", - "Channel4_leakage_Manifold2", "", - "Channel5_leakage_EAM1", "", - "Channel6_leakage_CPU_DIMM", "", - "Channel7_leakage_EAM2", "", - - /* C0-C7 line 32-47 */ - "RSVD_RMC_GPIO3", "", "", "", - "", "", "", "", - "LEAK_DETECT_RMC_N", "JTAG_CPLD_TRST_R_N", "", "", - "", "", "", "", - - /* D0-D7 line 48-63 */ - "PWRGD_PDB_EAMHSC0_CPLD_PG_R", "", - "PWRGD_PDB_EAMHSC1_CPLD_PG_R", "", - "PWRGD_PDB_EAMHSC2_CPLD_PG_R", "", - "PWRGD_PDB_EAMHSC3_CPLD_PG_R", "", - "AMC_BRD_PRSNT_CPLD_L", "", "", "", - "", "", "", "", - - /* E0-E7 line 64-79 */ - "AMC_PDB_EAMHSC0_CPLD_EN_R", "", - "AMC_PDB_EAMHSC1_CPLD_EN_R", "", - "AMC_PDB_EAMHSC2_CPLD_EN_R", "", - "AMC_PDB_EAMHSC3_CPLD_EN_R", "", - "", "", "", "", - "", "", "", "", - - /* F0-F7 line 80-95 */ - "PWRGD_PVDDCR_CPU1_P0", "SGPIO_READY", - "PWRGD_PVDDCR_CPU0_P0", "", - "", "", "", "", - "", "", "", "", - - /* G0-G7 line 96-111 */ - "L_PRSNT_EDSFF0_N", "", - "L_PRSNT_EDSFF1_N", "", - "R_PRSNT_EDSFF2_N", "", - "R_PRSNT_EDSFF3_N", "", - "HPM_EDSFF_PG", "", - "PWRGD_CHEH_CPU0_FPGA", "", - "PWRGD_CHAD_CPU0_FPGA", "FM_BMC_READY_PLD", - "", "", - - /* H0-H7 line 112-127 */ - "PWRGD_P3V3", "", - "P12V_DDR_IP_PWRGD_R", "", - "P12V_DDR_AH_PWRGD_R", "", - "PWRGD_P12V_VRM1_CPLD_PG_R", "", - "PWRGD_P12V_VRM0_CPLD_PG_R", "", - "PWRGD_PDB_HSC4_CPLD_PG_R", "", - "PWRGD_PVDD18_S5_P0_PG", "", - "PWRGD_PVDD33_S5_P0_PG", "", - - /* I0-I7 line 128-143 */ - "EAM0_BRD_PRSNT_R_L", "", - "EAM1_BRD_PRSNT_R_L", "", - "EAM2_BRD_PRSNT_R_L", "", - "EAM3_BRD_PRSNT_R_L", "", - "EAM0_CPU_MOD_PWR_GD_R", "", - "EAM1_CPU_MOD_PWR_GD_R", "", - "PRSNT_EDSFF_BOOT_N", "", - "EAM3_CPU_MOD_PWR_GD_R", "", - - /* J0-J7 line 144-159 */ - "PRSNT_L_BIRDGE_R", "", - "PRSNT_R_BIRDGE_R", "", - "BRIDGE_L_MAIN_PG_R", "", - "BRIDGE_R_MAIN_PG_R", "", - "BRIDGE_L_STBY_PG_R", "", - "BRIDGE_R_STBY_PG_R", "", - "", "", "", "", - - /* K0-K7 line 160-175 */ - "ADC_I2C_ALERT_N", "", - "TEMP_I2C_ALERT_R_L", "", - "CPU0_VR_SMB_ALERT_CPLD_N", "", - "COVER_INTRUDER_R_N", "", - "HANDLE_INTRUDER_CPLD_N", "", - "IRQ_MCIO_CPLD_WAKE_R_N", "", - "APML_CPU0_ALERT_R_N", "", - "PDB_ALERT_R_N", "", - - /* L0-L7 line 176-191 */ - "L_EDSFF0_PG", "", "L_EDSFF1_PG", "", - "R_EDSFF2_PG", "", "R_EDSFF3_PG", "", - "CPU0_CORETYPE0", "", "CPU0_CORETYPE1", "", - "CPU0_CORETYPE2", "", "FM_BIOS_POST_CMPLT_R_N", "", - - /* M0-M7 line 192-207 */ - "EAM0_SMERR_CPLD_R_L", "", - "EAM1_SMERR_CPLD_R_L", "", - "EAM2_SMERR_CPLD_R_L", "", - "EAM3_SMERR_CPLD_R_L", "", - "CPU0_SMERR_N_R", "", - "CPU0_NV_SAVE_N_R", "", - "PDB_PWR_LOSS_CPLD_N", "", - "IRQ_BMC_SMI_ACTIVE_R_N", "", - - /* N0-N7 line 208-223 */ - "AMCROT_BMC_S5_RDY_R", "", - "AMC_RDY_R", "", - "AMC_STBY_PGOOD_R", "", - "CPU_AMC_SLP_S5_R_L", "", - "AMC_CPU_EAMPG_R", "", - "", "", "", "", - - /* O0-O7 line 224-239 */ - "HPM_PWR_FAIL", "Port80_b0", - "FM_DIMM_IP_FAIL", "Port80_b1", - "FM_DIMM_AH_FAIL", "Port80_b2", - "AMC_THERMTRIP_ASSERT", "Port80_b3", - "CPU_THERMTRIP_ASSERT", "Port80_b4", - "PVDDCR_SOC_P0_OCP_L", "Port80_b5", - "CPLD_SGPIO_RDY", "Port80_b6", - "", "Port80_b7", - - /* P0-P7 line 240-255 */ - "CPU0_SLP_S5_N_R", "NFC_VEN", - "CPU0_SLP_S3_N_R", "", - "FM_CPU0_PWRGD", "", - "PWRGD_RMC", "", - "FM_RST_CPU0_RESET_N", "", - "FM_PWRGD_CPU0_PWROK", "", - "wS5_PWR_Ready", "", - "wS0_ON_N", "PWRGD_P1V0_AUX"; - status =3D "okay"; -}; - -// BIOS Flash -&spi2 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_spi2_default>; - status =3D "okay"; - reg =3D <0x1e631000 0xc4>, <0x50000000 0x8000000>; - - flash@0 { - compatible =3D "jedec,spi-nor"; - label =3D "pnor"; - spi-max-frequency =3D <12000000>; - spi-tx-bus-width =3D <2>; - spi-rx-bus-width =3D <2>; - status =3D "okay"; - }; -}; - -// HOST BIOS Debug -&uart1 { - status =3D "okay"; -}; - -&uart3 { - status =3D "okay"; -}; - -&uart4 { - status =3D "okay"; -}; - -// BMC Debug Console -&uart5 { - status =3D "okay"; -}; - -&uart_routing { - status =3D "okay"; -}; - -&uhci { - status =3D "okay"; -}; - -&vhub { - status =3D "okay"; - pinctrl-names =3D "default"; -}; - -&video { - status =3D "okay"; - memory-region =3D <&video_engine_memory>; -}; - -&wdt1 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_wdtrst1_default>; - aspeed,reset-type =3D "soc"; - aspeed,external-signal; - aspeed,ext-push-pull; - aspeed,ext-active-high; - aspeed,ext-pulse-duration =3D <256>; - status =3D "okay"; -}; --=20 2.34.1 From nobody Sat Oct 3 04:32:05 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8BB0470115; Wed, 5 Aug 2026 13:03:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785934989; cv=none; b=mtJ9i4DjY6iaSTdnePsTq8ERWyNQ7WH9YwXhCBoV5UJhuLqMB67orAHljrTK6RwtuEmkdTd0MiJK+c4rVknliJ+15Op4KQvXUKzkpJ2hSvVYHh+UM4xX2enAVGRnG4o9HHqJtvAyrL2SGTX0z+YLFDU9eT6nvIjhAI2orqQsOnA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785934989; c=relaxed/simple; bh=KXlTSNgL7obcfAAu2qQszrvsiNWFTE6hySuQAhmN6t4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=uq43trCJ/zB7FwdeUy0jLp/UDbLZ+P6mpBZGYpruFEhJNogMENwZ4zh1mPPn+bgNQJ6ePAFB27uTR05lu8nF7e4ynDHsPH3MkKSZWFQ/WoStmdo2Dnw40DjEzB2ObrgDH07tfMxfUqs3vBr3Qv6O+csMclvFlek4LuFhpJteO00= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=abyV2tzp; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="abyV2tzp" Received: by smtp.kernel.org (Postfix) with ESMTPS id F05EDC2BCFD; Wed, 5 Aug 2026 13:03:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1785934989; bh=KXlTSNgL7obcfAAu2qQszrvsiNWFTE6hySuQAhmN6t4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=abyV2tzpmA6MvTIbiHS1CriNpn4Nr0nZeh5r+KfkJKTx7GXLemxlIcy8yQitFU7eZ R9JHh9/ywIo9WgIkfqYBQrncrIt7PrcHJCJIoCACDl+d5ZZnvujiImzCPZVWxe+LBB xYls0hz9aYcme6BqopC+TQLkjyhjahRYCidgBT55DfB6PcD3Yl66Rdjl6yWxGIef3m VicKfURlckeZDD9wz+TuO7DOgpCNSJxOpJR7SChokYFQQWG3B285VcXXM9vbGv1n7A QzHCq+/0ajnra33WeB+sWEjebE/oO3M0LKTPQCkydp6uRt7n94ehlMQvoIxJHKBBHH /yjQjWiUSSuBA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA4E5C56203; Wed, 5 Aug 2026 13:03:08 +0000 (UTC) From: Colin Huang via B4 Relay Date: Wed, 05 Aug 2026 21:02:31 +0800 Subject: [PATCH v4 03/12] ARM: dts: aspeed: anacapa: Add EVT2 devicetree inheriting EVT1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260805-anacapa-devlop-phase-devicetree-v4-3-5d67e0efa6c5@gmail.com> References: <20260805-anacapa-devlop-phase-devicetree-v4-0-5d67e0efa6c5@gmail.com> In-Reply-To: <20260805-anacapa-devlop-phase-devicetree-v4-0-5d67e0efa6c5@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, colin.huang2@amd.com, Colin Huang X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1785934963; l=5864; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=uFd3k24VxEypaHLespXpLRjwFFWss5Y43arELHuz9Hk=; b=SkdKTGEvk8jsigqVuJdydvi2X5wzytOn8bfUsuO/KVZ8Suew7vZUenAHTbzIIeqol+cNp0DZJ ZvHJ0qhKqdKBcv8cBhvqrxcFXXh/fZLBHx9/1FF6zGmxOq9m22qnQkf X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 X-Original-From: Colin Huang Reply-To: u8813345@gmail.com From: Colin Huang Add a development-phase devicetree for the Facebook Anacapa BMC EVT2 hardware revision and update the Anacapa wrapper DTS to reference it. Signed-off-by: Colin Huang --- .../aspeed/aspeed-bmc-facebook-anacapa-evt2.dts | 178 +++++++++++++++++= ++++ .../dts/aspeed/aspeed-bmc-facebook-anacapa.dts | 2 +- 2 files changed, 179 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts = b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts new file mode 100644 index 000000000000..4a6ae7c6cbf8 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/dts-v1/; +#include "aspeed-bmc-facebook-anacapa-evt1.dts" + +/ { + model =3D "Facebook Anacapa BMC"; + compatible =3D "facebook,anacapa-bmc-evt2", "aspeed,ast2600"; +}; + +&sgpiom0 { + ngpios =3D <128>; + bus-frequency =3D <2000000>; + gpio-line-names =3D + /*in - out */ + /* A0-A7 line 0-15 */ + "L_FNIC_FLT", "FM_CPU0_SYS_RESET_N", + "L_BNIC0_FLT", "CPU0_KBRST_N", + "L_BNIC1_FLT", "FM_CPU0_PROCHOT_trigger_N", + "L_BNIC2_FLT", "FM_CLR_CMOS_R_P0", + "L_BNIC3_FLT", "Force_I3C_SEL", + "L_RTM_SW_FLT", "SYSTEM_Force_Run_AC_Cycle", + "", "", + "", "", + + /* B0-B7 line 16-31 */ + "Channel0_leakage_EAM3", "FM_CPU_FPGA_JTAG_MUX_SEL", + "Channel1_leakage_EAM0", "FM_SCM_JTAG_MUX_SEL", + "Channel2_leakage_Manifold1", "FM_BRIDGE_JTAG_MUX_SEL", + "Channel5_leakage_present_EAM1", "FM_CPU0_NMI_SYNC_FLOOD_N", + "Channel4_leakage_Manifold2", "BMC_AINIC0_WP_R2_L", + "Channel5_leakage_EAM1", "BMC_AINIC1_WP_R2_L", + "Channel6_leakage_CPU_DIMM", "CPLD_BUF_R_AGPIO330", + "Channel7_leakage_EAM2", "CPLD_BUF_R_AGPIO331", + + /* C0-C7 line 32-47 */ + "RSVD_RMC_GPIO3", "RTM_MUX_L", + "LEAK_DETECT_RMC_N", "RTM_MUX_R", + "HDR_P0_NMI_BTN_BUF_R_N", "FPGA_JTAG_SCM_DBREQ_N", + "Channel6_leakage_present_CPU_DIMM", "whdt_sel", + "", "JTAG_CPLD_TRST_R_N", + "", "", + "", "", + "", "", + + /* D0-D7 line 48-63 */ + "Channel0_leakage_present_EAM3", "", + "Channel1_leakage_present_EAM0", "", + "Channel2_leakage_present_Manifold1", "", + "Channel4_leakage_present_Manifold2", "", + "AMC_BRD_PRSNT_CPLD_L", "", + "Channel7_leakage_present_EAM2", "", + "", "", + "", "", + + /* E0-E7 line 64-79 */ + "L_PRSNT_B_FENIC_R2_N", "", + "L_PRSNT_B_BENIC0_R2_N", "", + "L_PRSNT_B_BENIC1_R2_N", "", + "L_PRSNT_B_BENIC2_R2_N", "", + "L_PRSNT_B_BENIC3_R2_N", "", + "", "", + "", "", + "", "", + + /* F0-F7 line 80-95 */ + "R_PRSNT_B_FENIC_R2_N", "SGPIO_READY", + "R_PRSNT_B_BENIC0_R2_N", "", + "R_PRSNT_B_BENIC1_R2_N", "", + "R_PRSNT_B_BENIC2_R2_N", "", + "R_PRSNT_B_BENIC3_R2_N", "", + "", "", + "", "", + "", "", + + /* G0-G7 line 96-111 */ + "L_PRSNT_EDSFF0_N", "", + "L_PRSNT_EDSFF1_N", "", + "R_PRSNT_EDSFF2_N", "", + "R_PRSNT_EDSFF3_N", "", + "HPM_EDSFF_PG", "", + "", "", + "", "FM_BMC_READY_PLD", + "PRSNT_NFC_BOARD_R", "", + + /* H0-H7 line 112-127 */ + "R_FNIC_FLT", "", + "R_BNIC0_FLT", "", + "R_BNIC1_FLT", "", + "R_BNIC2_FLT", "", + "R_BNIC3_FLT", "", + "R_RTM_SW_FLT", "", + "", "", + "", "", + + /* I0-I7 line 128-143 */ + "EAM0_BRD_PRSNT_R_L", "", + "EAM1_BRD_PRSNT_R_L", "", + "EAM2_BRD_PRSNT_R_L", "", + "EAM3_BRD_PRSNT_R_L", "", + "FM_TPM_PRSNT_R_N", "", + "PDB_L_PRSNT_R_N", "", + "PRSNT_EDSFF_BOOT_N", "", + "PRSNT_CPU0_N", "", + + /* J0-J7 line 144-159 */ + "PRSNT_L_BRIDGE_R", "", + "PRSNT_R_BRIDGE_R", "", + "BRIDGE_L_MAIN_PG_R", "", + "BRIDGE_R_MAIN_PG_R", "", + "BRIDGE_L_STBY_PG_R", "", + "BRIDGE_R_STBY_PG_R", "", + "IRQ_NFC_BOARD_R", "", + "RSMRST_N", "", + + /* K0-K7 line 160-175 */ + "ADC_I2C_ALERT_N", "", + "TEMP_I2C_ALERT_R_L", "", + "CPU0_VR_SMB_ALERT_CPLD_N", "", + "COVER_INTRUDER_R_N", "", + "HANDLE_INTRUDER_CPLD_N", "", + "IRQ_MCIO_CPLD_WAKE_R_N", "", + "APML_CPU0_ALERT_R_N", "", + "PDB_ALERT_R_N", "", + + /* L0-L7 line 176-191 */ + "L_EDSFF0_PG", "", + "L_EDSFF1_PG", "", + "R_EDSFF2_PG", "", + "R_EDSFF3_PG", "", + "HPM_CPLD_HEART_BIT", "", + "RBB_CPLD_HEART_BIT", "", + "LBB_CPLD_HEART_BIT", "", + "FM_BIOS_POST_CMPLT_R_N", "", + + /* M0-M7 line 192-207 */ + "EAM0_SMERR_CPLD_R_L", "", + "EAM1_SMERR_CPLD_R_L", "", + "EAM2_SMERR_CPLD_R_L", "", + "EAM3_SMERR_CPLD_R_L", "", + "CPU0_SMERR_N_R", "", + "CPU0_NV_SAVE_N_R", "", + "PDB_PWR_LOSS_CPLD_N", "", + "IRQ_BMC_SMI_ACTIVE_R_N", "", + + /* N0-N7 line 208-223 */ + "AMCROT_BMC_S5_RDY_R", "", + "AMC_RDY_R", "", + "AMC_STBY_PGOOD_R", "", + "CPU_AMC_SLP_S5_R_L", "", + "AMC_CPU_EAMPG_R", "", + "DIMM_PMIC_PG_TIMEOUT", "", + "EAM_MOD_PWR_GD_TIMEOUT", "", + "CPLD_AMC_STBY_PWR_EN", "", + + /* O0-O7 line 224-239 */ + "HPM_PWR_FAIL", "Port80_b0", + "FM_DIMM_IP_FAIL", "Port80_b1", + "FM_DIMM_AH_FAIL", "Port80_b2", + "AMC_THERMTRIP_ASSERT", "Port80_b3", + "CPU_THERMTRIP_ASSERT", "Port80_b4", + "PVDDCR_SOC_P0_OCP_L", "Port80_b5", + "CPLD_SGPIO_RDY", "Port80_b6", + "FM_MAIN_PWREN_RMC_EN_ISO", "Port80_b7", + + /* P0-P7 line 240-255 */ + "CPU0_SLP_S5_N_R", "NFC_VEN", + "CPU0_SLP_S3_N_R", "", + "FM_CPU0_PWRGD", "", + "PWRGD_RMC", "", + "FM_RST_CPU0_RESET_N", "RBB_CPLD_RISCV_RST", + "FM_PWRGD_CPU0_PWROK", "LBB_CPLD_RISCV_RST", + "AMC_FAIL", "HPM_CPLD_RISCV_RST", + "S0_ON", ""; + + status =3D "okay"; +}; + diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts b/arc= h/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts index 209eef65cedb..1848ca347621 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts @@ -1,4 +1,4 @@ // SPDX-License-Identifier: GPL-2.0-or-later =20 -#include "aspeed-bmc-facebook-anacapa-evt1.dts" +#include "aspeed-bmc-facebook-anacapa-evt2.dts" =20 --=20 2.34.1 From nobody Sat Oct 3 04:32:05 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 895C147011F; Wed, 5 Aug 2026 13:03:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785934990; cv=none; b=BpXav+KnaQlVfC5issG1wINdN/Hfa25eIh1TR8OsPrUevFzG3U/BTVZR9hnUeNEWUyZzNcjSYJUQqrbA/JGE9WQjEd1LoHtoLQ+WSZhL+2BD6sGq85rv1yL5nwwaUTm+fhJ/W1RfGNMCtpn5zkBy+ZxYRAkJnXTkxPQ0jCX/GRM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785934990; c=relaxed/simple; bh=llREHz/Ut+hQdQkpSFZF+fPnWztP0SkUaAfxensGHXU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=UCh6mNV8kBwGyHJ5hHdpHDF4ZVxSi7zZF5OGw4k151b8ZTX8vPgrQDB9SggI7dE/N+dIddVIlACLMEMQFywErchjmZaMR+hu8cbXeHVIkYVq20OV/YyG/fLq5f8QT9mzRzieF6PBUzSeK9eNEqnIGAz1CwU3PJLQ95KlkkOQqXY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=miBc+Sae; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="miBc+Sae" Received: by smtp.kernel.org (Postfix) with ESMTPS id 0F3D8C2BD01; Wed, 5 Aug 2026 13:03:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1785934989; bh=llREHz/Ut+hQdQkpSFZF+fPnWztP0SkUaAfxensGHXU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=miBc+Saepbe6qGyU8T8nU5YPt6p+ISccJuig6pr85TJ71k1bykXAI6CD9DNQquB/8 4e9kKnc1KgZhCQ/VUE654yuKGmvTtuxAKdRL89kPNZ8FDfvPTsLLJZyh++aCDYaNwB 1uFC59N+cwO0yOUZ08ErA70wtCRPMq84BpAuuaoCvJ/cuu2AgNOQdfF37NqmwSyK6O AtCdDIje8xK1+b3VKrTI5NNutPNkch+RJSr9UMdkr8web35/z6rWEiYb8+1ZthrzHM 7nlDfPrqP/oya0sUeW5o7MWk+P6FiWxOl51qJSDbBS4YzRAVw1DevaZv4lbSF5c5sG Z9bpxDtJNforw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB77FC56208; Wed, 5 Aug 2026 13:03:08 +0000 (UTC) From: Colin Huang via B4 Relay Date: Wed, 05 Aug 2026 21:02:32 +0800 Subject: [PATCH v4 04/12] ARM: dts: aspeed: anacapa: Add DVT devicetree inheriting EVT2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260805-anacapa-devlop-phase-devicetree-v4-4-5d67e0efa6c5@gmail.com> References: <20260805-anacapa-devlop-phase-devicetree-v4-0-5d67e0efa6c5@gmail.com> In-Reply-To: <20260805-anacapa-devlop-phase-devicetree-v4-0-5d67e0efa6c5@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, colin.huang2@amd.com, Colin Huang X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1785934963; l=6004; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=4qBFnetVkREYSIu12suaMhNwE7VlH8Jb8tWdL8ayTVM=; b=CsvGZouG0veW9AjXNp25g/DLxigjoarl+AE4K2swICo18N+hCn5C7qNi/e0616cYYOD6aW/XW Ttm1YfLiO6HCXgbZMGtRLlogj1N9Byh5gVTrOZodXKaQ1lHDtYoLcKS X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 X-Original-From: Colin Huang Reply-To: u8813345@gmail.com From: Colin Huang Add a development-phase devicetree for the Facebook Anacapa BMC DVT hardware revision and update the Anacapa wrapper DTS to reference it. Signed-off-by: Colin Huang --- .../dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts | 178 +++++++++++++++++= ++++ .../dts/aspeed/aspeed-bmc-facebook-anacapa.dts | 2 +- 2 files changed, 179 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts b= /arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts new file mode 100644 index 000000000000..0eb547ad0ec1 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/dts-v1/; +#include "aspeed-bmc-facebook-anacapa-evt2.dts" + +/ { + model =3D "Facebook Anacapa BMC"; + compatible =3D "facebook,anacapa-bmc-dvt", "aspeed,ast2600"; +}; + +&sgpiom0 { + ngpios =3D <128>; + bus-frequency =3D <2000000>; + gpio-line-names =3D + /*in - out */ + /* A0-A7 line 0-15 */ + "L_FNIC_FLT", "FM_CPU0_SYS_RESET_N", + "L_BNIC0_FLT", "CPU0_KBRST_N", + "L_BNIC1_FLT", "FM_CPU0_PROCHOT_trigger_N", + "L_BNIC2_FLT", "FM_CLR_CMOS_R_P0", + "L_BNIC3_FLT", "Force_I3C_SEL", + "L_RTM_SW_FLT", "SYSTEM_Force_Run_AC_Cycle", + "", "", + "", "", + + /* B0-B7 line 16-31 */ + "Channel0_leakage_EAM3", "FM_CPU_FPGA_JTAG_MUX_SEL", + "Channel1_leakage_EAM0", "FM_SCM_JTAG_MUX_SEL", + "Channel2_leakage_Manifold1", "FM_BRIDGE_JTAG_MUX_SEL", + "Channel5_leakage_present_EAM1", "FM_CPU0_NMI_SYNC_FLOOD_N", + "Channel4_leakage_Manifold2", "BMC_AINIC0_WP_R2_L", + "Channel5_leakage_EAM1", "BMC_AINIC1_WP_R2_L", + "Channel6_leakage_CPU_DIMM", "CPLD_BUF_R_AGPIO330", + "Channel7_leakage_EAM2", "CPLD_BUF_R_AGPIO331", + + /* C0-C7 line 32-47 */ + "RSVD_RMC_GPIO3", "RTM_MUX_L", + "LEAK_DETECT_RMC_N", "RTM_MUX_R", + "HDR_P0_NMI_BTN_BUF_R_N", "FPGA_JTAG_SCM_DBREQ_N", + "Channel6_leakage_present_CPU_DIMM", "whdt_sel", + "R_EAM0_NIC_CBL_PRSNT_L", "JTAG_CPLD_TRST_R_N", + "R_EAM1_NIC_CBL_PRSNT_L", "", + "L_EAM0_NIC_CBL_PRSNT_L", "", + "L_EAM1_NIC_CBL_PRSNT_L", "", + + /* D0-D7 line 48-63 */ + "Channel0_leakage_present_EAM3", "", + "Channel1_leakage_present_EAM0", "", + "Channel2_leakage_present_Manifold1", "", + "Channel4_leakage_present_Manifold2", "", + "AMC_BRD_PRSNT_CPLD_L", "", + "Channel7_leakage_present_EAM2", "", + "", "", + "", "", + + /* E0-E7 line 64-79 */ + "L_PRSNT_B_FENIC_R2_N", "", + "L_PRSNT_B_BENIC0_R2_N", "", + "L_PRSNT_B_BENIC1_R2_N", "", + "L_PRSNT_B_BENIC2_R2_N", "", + "L_PRSNT_B_BENIC3_R2_N", "", + "", "", + "", "", + "", "", + + /* F0-F7 line 80-95 */ + "R_PRSNT_B_FENIC_R2_N", "SGPIO_READY", + "R_PRSNT_B_BENIC0_R2_N", "", + "R_PRSNT_B_BENIC1_R2_N", "", + "R_PRSNT_B_BENIC2_R2_N", "", + "R_PRSNT_B_BENIC3_R2_N", "", + "", "", + "", "", + "", "", + + /* G0-G7 line 96-111 */ + "L_PRSNT_EDSFF0_N", "", + "L_PRSNT_EDSFF1_N", "", + "R_PRSNT_EDSFF2_N", "", + "R_PRSNT_EDSFF3_N", "", + "HPM_EDSFF_PG", "", + "", "", + "P12V_PWR_CABLE_PRSNT_L_R", "FM_BMC_READY_PLD", + "PRSNT_NFC_BOARD_R", "", + + /* H0-H7 line 112-127 */ + "R_FNIC_FLT", "", + "R_BNIC0_FLT", "", + "R_BNIC1_FLT", "", + "R_BNIC2_FLT", "", + "R_BNIC3_FLT", "", + "R_RTM_SW_FLT", "", + "RBB_Cable_Present", "", + "LBB_Cable_Present", "", + + /* I0-I7 line 128-143 */ + "EAM0_BRD_PRSNT_R_L", "", + "EAM1_BRD_PRSNT_R_L", "", + "EAM2_BRD_PRSNT_R_L", "", + "EAM3_BRD_PRSNT_R_L", "", + "FM_TPM_PRSNT_R_N", "", + "PDB_L_PRSNT_R_N", "", + "PRSNT_EDSFF_BOOT_N", "", + "PRSNT_CPU0_N", "", + + /* J0-J7 line 144-159 */ + "PRSNT_L_BRIDGE_R", "", + "PRSNT_R_BRIDGE_R", "", + "BRIDGE_L_MAIN_PG_R", "", + "BRIDGE_R_MAIN_PG_R", "", + "BRIDGE_L_STBY_PG_R", "", + "BRIDGE_R_STBY_PG_R", "", + "IRQ_NFC_BOARD_R", "", + "RSMRST_N", "", + + /* K0-K7 line 160-175 */ + "ADC_I2C_ALERT_N", "", + "TEMP_I2C_ALERT_R_L", "", + "CPU0_VR_SMB_ALERT_CPLD_N", "", + "COVER_INTRUDER_R_N", "", + "HANDLE_INTRUDER_CPLD_N", "", + "IRQ_MCIO_CPLD_WAKE_R_N", "", + "APML_CPU0_ALERT_R_N", "", + "PDB_ALERT_R_N", "", + + /* L0-L7 line 176-191 */ + "L_EDSFF0_PG", "", + "L_EDSFF1_PG", "", + "R_EDSFF2_PG", "", + "R_EDSFF3_PG", "", + "HPM_CPLD_HEART_BIT", "", + "RBB_CPLD_HEART_BIT", "", + "LBB_CPLD_HEART_BIT", "", + "FM_BIOS_POST_CMPLT_R_N", "", + + /* M0-M7 line 192-207 */ + "EAM0_SMERR_CPLD_R_L", "", + "EAM1_SMERR_CPLD_R_L", "", + "EAM2_SMERR_CPLD_R_L", "", + "EAM3_SMERR_CPLD_R_L", "", + "CPU0_SMERR_N_R", "", + "CPU0_NV_SAVE_N_R", "", + "PDB_PWR_LOSS_CPLD_N", "", + "IRQ_BMC_SMI_ACTIVE_R_N", "", + + /* N0-N7 line 208-223 */ + "AMCROT_BMC_S5_RDY_R", "", + "AMC_RDY_R", "", + "AMC_STBY_PGOOD_R", "", + "CPU_AMC_SLP_S5_R_L", "", + "AMC_CPU_EAMPG_R", "", + "DIMM_PMIC_PG_TIMEOUT", "", + "EAM_MOD_PWR_GD_TIMEOUT", "", + "CPLD_AMC_STBY_PWR_EN", "", + + /* O0-O7 line 224-239 */ + "HPM_PWR_FAIL", "Port80_b0", + "FM_DIMM_IP_FAIL", "Port80_b1", + "FM_DIMM_AH_FAIL", "Port80_b2", + "AMC_THERMTRIP_ASSERT", "Port80_b3", + "CPU_THERMTRIP_ASSERT", "Port80_b4", + "PVDDCR_SOC_P0_OCP_L", "Port80_b5", + "CPLD_SGPIO_RDY", "Port80_b6", + "FM_MAIN_PWREN_RMC_EN_ISO", "Port80_b7", + + /* P0-P7 line 240-255 */ + "CPU0_SLP_S5_N_R", "NFC_VEN", + "CPU0_SLP_S3_N_R", "", + "FM_CPU0_PWRGD", "", + "PWRGD_RMC", "", + "FM_RST_CPU0_RESET_N", "RBB_CPLD_RISCV_RST", + "FM_PWRGD_CPU0_PWROK", "LBB_CPLD_RISCV_RST", + "AMC_FAIL", "HPM_CPLD_RISCV_RST", + "S0_ON", ""; + + status =3D "okay"; +}; + diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts b/arc= h/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts index 1848ca347621..c74b211c42e6 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts @@ -1,4 +1,4 @@ // SPDX-License-Identifier: GPL-2.0-or-later =20 -#include "aspeed-bmc-facebook-anacapa-evt2.dts" +#include "aspeed-bmc-facebook-anacapa-dvt.dts" =20 --=20 2.34.1 From nobody Sat Oct 3 04:32:05 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E5C8B470454; Wed, 5 Aug 2026 13:03:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785934991; cv=none; b=vDnGJHpJd9gQmnU/JIEEMwADFXRosLeJuSVJskBZ0EacRYG8iNFCiTE3S2sXL+efDx5hkIZ3xEmfbHAyQXUgW9rmI5b/SZfB4I/pa+hfuF5rvcRMhhIP0ufmP9oWLW+UQvXwSQ3V1OmRBMqIJPHrYEJnd+K8+eSEv3k3SDpbHiU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785934991; c=relaxed/simple; bh=LdloDJM8DI8AB4ZLQsP/+vZzjiWKgFCiLWLBMA7iRMU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=esI07Y0wRLtDqMx5ky8rJDZMyab6NXXW7XSyPdfnu0QjqjyQWPDcQf+VPdnFkyz7jawBV0N/0mUh/ac4qSbl5P5HGoctmtCr/hFwe+DrW8dSIKehFjJdzAzUUqpTK6CexTllfwFwYhvr7VOYjQOa9zfc4bq6H/Lfid0ltOhdmHU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=eWqxjPCj; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="eWqxjPCj" Received: by smtp.kernel.org (Postfix) with ESMTPS id 1E649C2BD04; Wed, 5 Aug 2026 13:03:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1785934989; bh=LdloDJM8DI8AB4ZLQsP/+vZzjiWKgFCiLWLBMA7iRMU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=eWqxjPCjwCfgR/epli6oVNNb/qBgurRKnG61rPed6+cNt7L/dr9Z8+pnPQD5UJL6E 01SNxuHOmj5fxEGa9Ip2EVYLTUvCvBSCit4R4tJKXKRyex+1Un7VH2P1HdD/T/FfU/ h2V5/hP3C/CkCm61TvoAJa1rUllapXYRKgtHGUzlTVm4avFViBo9KbdshM8WwKk3PR pT49Xa6XkhP8984wDU8lWYaqCPKFiLBXPLRaRfrH1fU5Bek/Puy/BNanNC4ujzj6gc jwoRF1BDuWCGs6R8c/6WEdZ6hlz+xNt/DUF9LLUuVbPQw2k7Qn6HfrlGoq8WqzaE6F dggNI0Ky+oATQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09059C56207; Wed, 5 Aug 2026 13:03:09 +0000 (UTC) From: Colin Huang via B4 Relay Date: Wed, 05 Aug 2026 21:02:33 +0800 Subject: [PATCH v4 05/12] ARM: dts: aspeed: anacapa: Add additional EEPROM node for SCM Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260805-anacapa-devlop-phase-devicetree-v4-5-5d67e0efa6c5@gmail.com> References: <20260805-anacapa-devlop-phase-devicetree-v4-0-5d67e0efa6c5@gmail.com> In-Reply-To: <20260805-anacapa-devlop-phase-devicetree-v4-0-5d67e0efa6c5@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, colin.huang2@amd.com, Colin Huang X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1785934963; l=1250; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=NAF+xcmhfBdWvCk+Ea9KmPCdarcFxDgMq2cQBYIvfaY=; b=wpqf0DC+1LYoo74qwFuJLHClCkzNFOqzu9etJpRAXMv19z6UtEFsANYU7piTdC53+d2rvOpU9 ELG5mCU+j7QAQmdgL6n//ZCOtfQ4pb/yTyh9KNGmWK8vfT0Xu05wZ9k X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 X-Original-From: Colin Huang Reply-To: u8813345@gmail.com From: Colin Huang The SCM FRU EEPROM I2C address differs between SCM revisions: - Rev B uses address 0x50 - Rev C/D/E/F and later use address 0x51 Add an additional AT24C128 EEPROM node at 0x51 on i2c9 so the same device tree can support multiple SCM revisions. Signed-off-by: Colin Huang --- .../boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts | 14 ++++++++++= ++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts = b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts index 4a6ae7c6cbf8..1901a325c72c 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts @@ -8,6 +8,20 @@ / { compatible =3D "facebook,anacapa-bmc-evt2", "aspeed,ast2600"; }; =20 +// SCM +&i2c9 { + + // SCM FRU + // | DC-SCM Rev | Slave address of eeprom | + // |-------------------|--------------------------| + // | Rev B | 0x50 | + // | Rev C/D/E/F/above | 0x51 | + eeprom@51 { + compatible =3D "atmel,24c128"; + reg =3D <0x51>; + }; +}; + &sgpiom0 { ngpios =3D <128>; bus-frequency =3D <2000000>; --=20 2.34.1 From nobody Sat Oct 3 04:32:05 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E68E5470456; Wed, 5 Aug 2026 13:03:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785934991; cv=none; b=CM0b+/AEMtOCft3BTF38TKqT29ZvKrTyrScHXnpXinGl2ELRNxEssUHY+Hzp2yQ5Y7HpLB+vpFsBhtdaTnW1bvFcZF/ztXSlFHjx819JdvQy5+ApF+v6GbQAep2fdsb2N82a0+jzUSvwkfQs7Uh5fh8yJpA4mM5IEPh43zBIvdE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785934991; c=relaxed/simple; bh=FoLZfGD6uyaU5BQXg5Am0hO9ZEAWctWsieG0YVFNjNM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=d3za3CagwIKGo/Tv73/Ulf+sN1SWPhpHbqxqREc0WwG1jahf4J66VTRD8hJCc98QfNPowBWXfM8akCipfTzwRdlgblKdRNVz5ZgZPG8bENF580mq498xbJniCtyAqDOTbtnJwY52D4jx6NCJt2ZzZd3H0CFyAbbRZXmEksMJABU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=dr8Gu4WR; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="dr8Gu4WR" Received: by smtp.kernel.org (Postfix) with ESMTPS id 33DC6C2BD00; Wed, 5 Aug 2026 13:03:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1785934989; bh=FoLZfGD6uyaU5BQXg5Am0hO9ZEAWctWsieG0YVFNjNM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=dr8Gu4WRgQgVNIAIdD55kno1nIHZsnfEwN/jsJ96Gi4W0GuvK5S9xO0qh9ojRGnrW Xnj63vmpgabGaZqpdRoFSD/tK1XvmqfJfJ1lE1YdQFWGFdMIMIDV0AXdc3/k1V/Xh7 c0Y0zlGn4tYHCg1OdkSG7cLbTnhCA0M0sSQg3RIxhNoITl8mga8CZNi9DFC21roaw1 uqtxyfeMPkFPJpmKEBBG9vA7V4khfhe+dE8vJ8u4RgbsXGr5PiNW8rp92YVKL6jtSt 0F1U1FrwwjC6PO5q0eJcESnod9KljAxyYeXkUqB0Hk7RiQfZxOfPOR6i8JhvXoUhHP PFGZBoLnxOkEA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20B8EC55ABF; Wed, 5 Aug 2026 13:03:09 +0000 (UTC) From: Colin Huang via B4 Relay Date: Wed, 05 Aug 2026 21:02:34 +0800 Subject: [PATCH v4 06/12] ARM: dts: aspeed: anacapa: Add eeprom device node for NFC adaptor board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260805-anacapa-devlop-phase-devicetree-v4-6-5d67e0efa6c5@gmail.com> References: <20260805-anacapa-devlop-phase-devicetree-v4-0-5d67e0efa6c5@gmail.com> In-Reply-To: <20260805-anacapa-devlop-phase-devicetree-v4-0-5d67e0efa6c5@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, colin.huang2@amd.com, Colin Huang , Carl Lee X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1785934963; l=854; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=ogPWoxlP9zHHWVbVILynjOOXZGqV6RgIxVGA6kDFSUc=; b=/z4nvmSJvhRzs0g+CPh58slDGf0C8IT4bhg5QND24yWyfa8GVxhDS4CFvka3p6F+TTW1eybjs Z2vhqivCuPSCR1JDbutj6KtxGU2P75NaPgrUYmlzNLMRZmSQbl6XRCj X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 X-Original-From: Colin Huang Reply-To: u8813345@gmail.com From: Carl Lee Add eeprom device node for NFC adaptor board FRU. Signed-off-by: Carl Lee --- .../boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts | 13 +++++++++= ++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts = b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts index 1901a325c72c..c7bffa7c6557 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts @@ -22,6 +22,19 @@ eeprom@51 { }; }; =20 +// MB +&i2c13 { + i2c-mux@70 { + i2c13mux0ch7: i2c@7 { + // NFC adaptor board FRU + eeprom@50 { + compatible =3D "atmel,24c128"; + reg =3D <0x50>; + }; + }; + }; +}; + &sgpiom0 { ngpios =3D <128>; bus-frequency =3D <2000000>; --=20 2.34.1 From nobody Sat Oct 3 04:32:05 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA87E470453; Wed, 5 Aug 2026 13:03:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785934991; cv=none; b=gfKRut+gObwCJ3Z6re30epC5rcSYM+SEvoQPATXhSxWJykPqIgAaHRZsQYbJGI329Hpigahk6RX8SY3qrAWmzc5mUG4NVdPVfE7xYkipFWks5ITO4TweFGAjyPUbkfiagV7Viu56dNZ6p373hBRUrbO+4vFeyy6KaCfajVX1aRU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785934991; c=relaxed/simple; bh=k65C478t9LS6ybUmJ6TjN8D7vgzFZCksmeumxEQZ8Wo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=omf5v/6duArtZrgtpqJxjbZq+7V9qZW+zYcntZgc2R9b6ArFRd41HoxmvuWm1DMIQ4CuDoDdCXZl3Auakq+bztAA8HJcJdHLW3AV+hgzK+092ebvUZAn9OZ/Gl9dcpg/zZD0XOrxxJuyoXwWxnbFjd3rsebmiVSO80D9P+9pZZ8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Fxm5/cTh; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Fxm5/cTh" Received: by smtp.kernel.org (Postfix) with ESMTPS id 47479C2BCFC; Wed, 5 Aug 2026 13:03:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1785934989; bh=k65C478t9LS6ybUmJ6TjN8D7vgzFZCksmeumxEQZ8Wo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Fxm5/cThPIOZevQ5H3UJS6ntN6TxdyemxKhBvJmyM8u0MsBV6hddkD/Ur1mSSd3Sl T/J5Mhbxp00V3RaGs8ZMlEsI4+vrh56u5Oe6FF1s0k7xc6I6ZTxK8xK5Dess2ohh7E do6/v73W8GXYHPJANpuXFET1Jdb9blfCJyCBbMogbNsLMDUoIxALwh50DZE4OcpzJ1 Nb8+cDCLmsF7SnZbG15MZVyeYnYfmmZ0or8T6GwPzi3D7pYB/L2A9wLbTFfCqSSwd6 CIvR9QYd7/ncACUbY8cVf4HUfTb2hONMzZIPrMmWSbrLr1t4WA1EdK9uTK00RxC1ry ssnE+D1iHpwmQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 335F5C55ABA; Wed, 5 Aug 2026 13:03:09 +0000 (UTC) From: Colin Huang via B4 Relay Date: Wed, 05 Aug 2026 21:02:35 +0800 Subject: [PATCH v4 07/12] ARM: dts: aspeed: anacapa: Align PDB fan GPIO numbering Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260805-anacapa-devlop-phase-devicetree-v4-7-5d67e0efa6c5@gmail.com> References: <20260805-anacapa-devlop-phase-devicetree-v4-0-5d67e0efa6c5@gmail.com> In-Reply-To: <20260805-anacapa-devlop-phase-devicetree-v4-0-5d67e0efa6c5@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, colin.huang2@amd.com, Colin Huang , Rex Fu X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1785934963; l=1875; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=3/IZc5ckSnwOY8uhbyA0jZSDZ3Dvh/PJORxqtTJG7yA=; b=O5IL2KSFBxgc8QKzSuEQthUwjyEZXJA7+1rRi8koNG46B/9VSFv59zU4WETzBSUE2UmRLIpNh In/jcJiv2YZDfHvX/UaW8z4IjDi/+VKmpHKJCx63UyyLW8D83EwJP7w X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 X-Original-From: Colin Huang Reply-To: u8813345@gmail.com From: Rex Fu Update the LPDB and RPDB fan GPIO line names to align with the platform fan numbering scheme. The LPDB fan GPIOs are named FAN0 through FAN4, while the RPDB fan GPIOs are named FAN5 through FAN8. This keeps the GPIO line names consistent with the fan inventory and platform-level fan numbering. Signed-off-by: Rex Fu Signed-off-by: Colin Huang --- .../aspeed/aspeed-bmc-facebook-anacapa-evt2.dts | 33 ++++++++++++++++++= ++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts = b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts index c7bffa7c6557..ff393ad7cdb7 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts @@ -8,6 +8,39 @@ / { compatible =3D "facebook,anacapa-bmc-evt2", "aspeed,ast2600"; }; =20 +// MB - PDB +&i2c8 { + i2c-mux@72 { + i2c8mux0ch0: i2c@0 { + gpio@24 { + gpio-line-names =3D + "RPDB_EAM2_PRSNT_MOS_N_R", "RPDB_EAM3_PRSNT_MOS_N_R", + "RPDB_PWRGD_P50V_HSC4_SYS_R", + "RPDB_PWRGD_P50V_STBY_SYS_BUF_R", + "RPDB_P50V_FAN5_R2_PG", "RPDB_P50V_FAN6_R2_PG", + "RPDB_P50V_FAN7_R2_PG", "RPDB_P50V_FAN8_R2_PG", + "", "RPDB_FAN5_PRSNT_N_R", + "", "RPDB_FAN6_PRSNT_N_R", + "RPDB_FAN7_PRSNT_N_R", "RPDB_FAN8_PRSNT_N_R", + "", ""; + }; + }; + i2c8mux0ch1: i2c@1 { + gpio@24 { + gpio-line-names =3D + "LPDB_P50V_FAN0_R2_PG","LPDB_P50V_FAN1_R2_PG", + "LPDB_P50V_FAN2_R2_PG","LPDB_P50V_FAN3_R2_PG", + "LPDB_P50V_FAN4_R2_PG","LPDB_FAN0_PRSNT_N_R", + "LPDB_FAN1_PRSNT_N_R","LPDB_FAN2_PRSNT_N_R", + "LPDB_FAN3_PRSNT_N_R","LPDB_FAN4_PRSNT_N_R", + "","", + "","", + "",""; + }; + }; + }; +}; + // SCM &i2c9 { =20 --=20 2.34.1 From nobody Sat Oct 3 04:32:05 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E5B1346F48F; Wed, 5 Aug 2026 13:03:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785934991; cv=none; b=rclpKygAJ/GMZpJa5nlfDbJz60OcCfbP0R8QIfIphvHu5j1hxlObf34V2bQy1DF0T9DlVFOIanhYvZ+DThTOXc1GO0EmKaI5IDOfa0VTaVdWjwYC/a17S9rgDnOvNHv7hBKtrgNEJsZkIdxSd9/GJnbTFxcejR9BRydJYAg5GrI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785934991; c=relaxed/simple; bh=U/VelihwE9/Y5DyVuu89kZaY6Foh61jZ62a+Hvygccg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=E74hToAPo9YnfNMG6HidVbV2mTzQGfgEJaUHbtY9bAz69sFSJngynrbq+t5HtDLqbF7aX3m13zNk3+IsTiRWn6GdC+WXND5B8Ajee5ZXy2UE9PNQGFQRAiVub2JvxPixYodJyh+Xqs0htGBldu0/C7fR2beskjQeEX2pRYlCV0Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=LpzPpe+C; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="LpzPpe+C" Received: by smtp.kernel.org (Postfix) with ESMTPS id 5657CC2BCFB; Wed, 5 Aug 2026 13:03:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1785934989; bh=U/VelihwE9/Y5DyVuu89kZaY6Foh61jZ62a+Hvygccg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=LpzPpe+CglNuxiT2pA5APAQP3umTEsbMMl5KOL0dAnhHgDmHgy0u5px872FsO3gY9 ejAE5kJY5R+CbefIjHM9sZpBklvujVmGnwcZlMkIrFP3a24nWguJWNQ8JDgzOJfMA/ ynbhErm7MmznT3x24isy4/GHKj4kd8Gi+TSvGwom59qYf2m9/EAUtJWVtg7j5w/oUW J0jwlaiEp88NFlKcyFXankhFNP8TNoOQoMR65wod26W97bzpOBUsjqo9cPob/WhoE/ H08LMnIKXW52/QCrL6Il3B4v3yKuY+y/d0V7tULk8FVvJjCkKWBNKQvsmlFmeiInKw IhNZODu55LCDA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45330C56205; Wed, 5 Aug 2026 13:03:09 +0000 (UTC) From: Colin Huang via B4 Relay Date: Wed, 05 Aug 2026 21:02:36 +0800 Subject: [PATCH v4 08/12] ARM: dts: aspeed: anacapa: Enable MCTP and FRU for NIC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260805-anacapa-devlop-phase-devicetree-v4-8-5d67e0efa6c5@gmail.com> References: <20260805-anacapa-devlop-phase-devicetree-v4-0-5d67e0efa6c5@gmail.com> In-Reply-To: <20260805-anacapa-devlop-phase-devicetree-v4-0-5d67e0efa6c5@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, colin.huang2@amd.com, Colin Huang , Andy Chung X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1785934963; l=3214; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=BGZCKTF8QAag1qskLE0ofPzySUEOSMb3NZgJbIMmwIo=; b=MpjikqOMq7zVXHAewpVwjarArr7otF1/OoOdZn2NtUC0MBbZ2MTzXrXKWYlc58Cq8PNSO30Fk uc7L3qxtYXqAKMDtrJBwbimeTtMwDSdYRLMzclKn5H+D1fnXnWJcYt/ X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 X-Original-From: Colin Huang Reply-To: u8813345@gmail.com From: Andy Chung Add the mctp-controller property to enable frontend NIC management via PLDM over MCTP. Also add EEPROM device for NIC FRU and reorder the I2C virtual bus index accroding to the system silkscreen index. Signed-off-by: Andy Chung --- .../aspeed/aspeed-bmc-facebook-anacapa-evt2.dts | 119 +++++++++++++++++= ++++ 1 file changed, 119 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts = b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts index ff393ad7cdb7..703284721224 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts @@ -8,6 +8,25 @@ / { compatible =3D "facebook,anacapa-bmc-evt2", "aspeed,ast2600"; }; =20 +&{/aliases} { + i2c36 =3D &i2c11mux0ch5; + i2c37 =3D &i2c11mux0ch6; + i2c38 =3D &i2c11mux0ch7; + i2c39 =3D &i2c11mux0ch0; + i2c40 =3D &i2c11mux0ch1; + i2c41 =3D &i2c11mux0ch2; + i2c42 =3D &i2c11mux0ch3; + i2c43 =3D &i2c11mux0ch4; + i2c44 =3D &i2c10mux0ch1; + i2c45 =3D &i2c10mux0ch2; + i2c46 =3D &i2c10mux0ch3; + i2c47 =3D &i2c10mux0ch4; + i2c48 =3D &i2c10mux0ch5; + i2c49 =3D &i2c10mux0ch6; + i2c50 =3D &i2c10mux0ch7; + i2c51 =3D &i2c10mux0ch0; +}; + // MB - PDB &i2c8 { i2c-mux@72 { @@ -55,6 +74,106 @@ eeprom@51 { }; }; =20 +// R Bridge Board +&i2c10 { + multi-master; + mctp@10 { + compatible =3D "mctp-i2c-controller"; + reg =3D <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; + + i2c-mux@71 { + /delete-property/ i2c-mux-idle-disconnect; + + i2c10mux0ch1: i2c@1 { + mctp-controller; + // BE NIC FRU + eeprom@50 { + compatible =3D "atmel,24c32"; + reg =3D <0x50>; + }; + }; + i2c10mux0ch2: i2c@2 { + mctp-controller; + // BE NIC FRU + eeprom@50 { + compatible =3D "atmel,24c32"; + reg =3D <0x50>; + }; + }; + i2c10mux0ch3: i2c@3 { + mctp-controller; + // BE NIC FRU + eeprom@50 { + compatible =3D "atmel,24c32"; + reg =3D <0x50>; + }; + }; + i2c10mux0ch4: i2c@4 { + mctp-controller; + // BE NIC FRU + eeprom@50 { + compatible =3D "atmel,24c32"; + reg =3D <0x50>; + }; + }; + }; +}; + +// L Bridge Board +&i2c11 { + multi-master; + mctp@10 { + compatible =3D "mctp-i2c-controller"; + reg =3D <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; + + i2c-mux@71 { + /delete-property/ i2c-mux-idle-disconnect; + + i2c11mux0ch0: i2c@0 { + mctp-controller; + // FE NIC FRU + eeprom@50 { + compatible =3D "atmel,24c32"; + reg =3D <0x50>; + }; + }; + i2c11mux0ch1: i2c@1 { + mctp-controller; + // BE NIC FRU + eeprom@50 { + compatible =3D "atmel,24c32"; + reg =3D <0x50>; + }; + }; + i2c11mux0ch2: i2c@2 { + mctp-controller; + // BE NIC FRU + eeprom@50 { + compatible =3D "atmel,24c32"; + reg =3D <0x50>; + }; + }; + i2c11mux0ch3: i2c@3 { + mctp-controller; + // BE NIC FRU + eeprom@50 { + compatible =3D "atmel,24c32"; + reg =3D <0x50>; + }; + }; + i2c11mux0ch4: i2c@4 { + mctp-controller; + // BE NIC FRU + eeprom@50 { + compatible =3D "atmel,24c32"; + reg =3D <0x50>; + }; + }; + }; +}; + // MB &i2c13 { i2c-mux@70 { --=20 2.34.1 From nobody Sat Oct 3 04:32:05 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EB5F5470457; Wed, 5 Aug 2026 13:03:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785934991; cv=none; b=R079axLD63MHWHdzGK2ANC0B3H147dB4P+07p+97cc6LCTcomkrAB+EKUx29mWNe7znNclmuWTguOQk64hUSXV2Kz7a8as1eaJtW18AaogzxC0lt0Q8XZXcuV5Vj+e41LlygFF6BbEBQsIEmrHSkM4el6fUdwA4hOT0qzQIdkqs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785934991; c=relaxed/simple; bh=TvfqYkcyVz8NemCQfEvCt2KSWTiyYhcCTYK5XdDbYxQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=V62Ax7ptAhCjF8gUGQ0f+4RPyPES0G25xrnMc+e7QChGbdGgI7USm2iQUF+S+DLC1ymABJdgYRW+auwr+vOiAu4n4/QIS7KyWKKIdsowPlsezd6iw/PTzbXp57ccu2J30XQrlHxJKrd2q2iVIM2bmWn3v8sBKgU14q39YU3eyO4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Q7yZ8h2P; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Q7yZ8h2P" Received: by smtp.kernel.org (Postfix) with ESMTPS id 6DA45C2BCFF; Wed, 5 Aug 2026 13:03:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1785934989; bh=TvfqYkcyVz8NemCQfEvCt2KSWTiyYhcCTYK5XdDbYxQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Q7yZ8h2P2ITxKAoa24C4wI5SGaKb4L1kncD6PiP9xZc9Fs88nwZw7ISE0a8dGKcYd esusn6l2cF3tCWXwumVt6vjJAEgXKT0AvfXm0uzakjkRpRc9DFl4QCfZofKcGtI7iJ u2cYFhhyEmnSw3hVeQB/aJTKZ7FbJBZX/DhCRQ59+BrlJ8xCBJX1I+ZwdTulZWhjU+ lnX8SbVvNkfxWStm3g+QlRf/H8FN/VVGobQuwu+bsZIQjyF3Iot5oUcxbfa+Sns9ki A0A7TrYYeSPJTTfnEnVOVX0U/TOjV8AqlbEqWdR3i03hwOb1XI9UKvDHl8WWOICCFh gTvmzNqz9gNyA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59786C56203; Wed, 5 Aug 2026 13:03:09 +0000 (UTC) From: Colin Huang via B4 Relay Date: Wed, 05 Aug 2026 21:02:37 +0800 Subject: [PATCH v4 09/12] ARM: dts: aspeed: anacapa: evt2: Add shunt resistor values for HSC monitors Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260805-anacapa-devlop-phase-devicetree-v4-9-5d67e0efa6c5@gmail.com> References: <20260805-anacapa-devlop-phase-devicetree-v4-0-5d67e0efa6c5@gmail.com> In-Reply-To: <20260805-anacapa-devlop-phase-devicetree-v4-0-5d67e0efa6c5@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, colin.huang2@amd.com, Colin Huang , Peter Shen X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1785934963; l=2147; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=WNTfq2afBfA8+J3QozrER71+gm8MPJIV48F5xeH186s=; b=QLogMmJXmliinv4lrYX+5lFkN2Uhf9TjbCvPpr8Q7cqQCrkftYtW5bdPILzTkrAsJ4GjoaIkv 9EkQqG8ds2UCEX8WWM0UoFv4B0a6wR90PQE4Vzz7YLzQkqQ7s47RCWx X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 X-Original-From: Colin Huang Reply-To: u8813345@gmail.com From: Colin Huang Add shunt resistor configuration for LTC4287 hot-swap controllers on Anacapa EVT2 platform. The resistor values are required for accurate current and power measurement by the driver. These settings reflect the actual BOM used on EVT2, where different sense resistor values (150 uOhm and 250 uOhm) are populated across rails. Without this configuration, the reported readings would be incorrect. Signed-off-by: Peter Shen --- .../aspeed/aspeed-bmc-facebook-anacapa-evt2.dts | 35 ++++++++++++++++++= ++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts = b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts index 703284721224..f913fa3f622d 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts @@ -31,6 +31,26 @@ / { &i2c8 { i2c-mux@72 { i2c8mux0ch0: i2c@0 { + power-monitor@42 { + compatible =3D "lltc,ltc4287"; + reg =3D <0x42>; + shunt-resistor-micro-ohms =3D <150>; + }; + power-monitor@43 { + compatible =3D "lltc,ltc4287"; + reg =3D <0x43>; + shunt-resistor-micro-ohms =3D <150>; + }; + power-monitor@44 { + compatible =3D "lltc,ltc4287"; + reg =3D <0x44>; + shunt-resistor-micro-ohms =3D <250>; + }; + power-monitor@45 { + compatible =3D "lltc,ltc4287"; + reg =3D <0x45>; + shunt-resistor-micro-ohms =3D <250>; + }; gpio@24 { gpio-line-names =3D "RPDB_EAM2_PRSNT_MOS_N_R", "RPDB_EAM3_PRSNT_MOS_N_R", @@ -45,6 +65,21 @@ gpio@24 { }; }; i2c8mux0ch1: i2c@1 { + power-monitor@40 { + compatible =3D "lltc,ltc4287"; + reg =3D <0x40>; + shunt-resistor-micro-ohms =3D <150>; + }; + power-monitor@41 { + compatible =3D "lltc,ltc4287"; + reg =3D <0x41>; + shunt-resistor-micro-ohms =3D <150>; + }; + power-monitor@45 { + compatible =3D "lltc,ltc4287"; + reg =3D <0x45>; + shunt-resistor-micro-ohms =3D <250>; + }; gpio@24 { gpio-line-names =3D "LPDB_P50V_FAN0_R2_PG","LPDB_P50V_FAN1_R2_PG", --=20 2.34.1 From nobody Sat Oct 3 04:32:05 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 00C7C46EF94; Wed, 5 Aug 2026 13:03:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785934991; cv=none; b=HGiy/vWpXK3zxlTOxmrcMH64NBuR2DvdY1e49BKGU2Af+5VHdEHpD+ZB7e/RIsAhLThdLWstuItxXCd+ZxUs7/38hcygrGcsBXdAdzeAJYliyVuz4OQOK9CtjyV7REoK7Vt6Em1uXWMwSBDfnkpMat7TGqX35g/J2BYio1Z4jnU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785934991; c=relaxed/simple; bh=8axNV0qz+55gS2UiiJda4kv4M/AoCvvKFE19+hHj11I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mgv1o8O4XoG9Y4lcexdKABPBrngaFk8zXw3dHXbo5cpXLCtuR+uSl0xEe1BbGhRkp/zOpnqfMkpXDiB5rqcr5LZQOnMl4uI5fYTTu7x2CjWOarDMGdUV9eNygkQmrL5R2jy5S40U3JFkwT3Ark6IoG2juaN/KDxJcu0qdoIDuIU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=S/EwwSmx; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="S/EwwSmx" Received: by smtp.kernel.org (Postfix) with ESMTPS id 84EEBC32781; Wed, 5 Aug 2026 13:03:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1785934989; bh=8axNV0qz+55gS2UiiJda4kv4M/AoCvvKFE19+hHj11I=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=S/EwwSmxwQD9OrzOJZ88LCvr5u572OasVBJ6eyuQF0fwbmM5lfnL3TmeGrJEMH2DC lNPgxvvg6bksyJgJMNFVFqBche5eAaRObrw3WyMpebvXvQ9gl8xENuiy5I50uZfoUZ 4tfy5c9fYMwUhyqtNyj3V/WDSTlcI5M+tTspph7OZPYr+MnEka9ifrfaXBS93ELdc3 0yIY45xEfOvRCse8o9E8LKOO/Hgz5Tk24VX9Fw3oqBLLgso4jFiBtRmwbQG8497gAJ EYtZgkseLCDdeCcJKdfRU5Rh9wE6E8Tq3XsVAJAchOGpnC/HHZ9KvtlEDxmDztRo8Q deJtW3DRBfHOA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72BA7C56205; Wed, 5 Aug 2026 13:03:09 +0000 (UTC) From: Colin Huang via B4 Relay Date: Wed, 05 Aug 2026 21:02:38 +0800 Subject: [PATCH v4 10/12] ARM: dts: aspeed: anacapa: Add LPDB fuse monitor GPIO expander Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260805-anacapa-devlop-phase-devicetree-v4-10-5d67e0efa6c5@gmail.com> References: <20260805-anacapa-devlop-phase-devicetree-v4-0-5d67e0efa6c5@gmail.com> In-Reply-To: <20260805-anacapa-devlop-phase-devicetree-v4-0-5d67e0efa6c5@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, colin.huang2@amd.com, Colin Huang , Rex Fu X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1785934963; l=3520; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=kGTVHDij4WGDqWe9Tp6hUO68XWQC9ip/+ELRTxuQLWs=; b=T/R1BvgIP4u03YPyUa5vxerDdM8cZYUmxK8T/yWCFavVndMWWIftCzROXI1hq0pEQ58entGwE bX4b0pYVUkXC+4HGEYJwM6VZWGqp4R8MIG4r8v/+KpjYC9i6xteKpUz X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 X-Original-From: Colin Huang Reply-To: u8813345@gmail.com From: Rex Fu Add the PCA9554 GPIO expander for PDB fuse monitor signals. Signed-off-by: Rex Fu --- .../dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts | 87 ++++++++++++++++++= ++++ 1 file changed, 87 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts b= /arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts index 0eb547ad0ec1..f09dd1abe77d 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts @@ -8,6 +8,93 @@ / { compatible =3D "facebook,anacapa-bmc-dvt", "aspeed,ast2600"; }; =20 +// MB - PDB +&i2c8 { + i2c-mux@72 { + i2c8mux0ch0: i2c@0 { + gpio@22 { + gpio-line-names =3D + "RPDB_FAN_FULL_SPEED_R_N", "RPDB_I2C_TMP432_U8_ALERT_R_N", + "RPDB_I2C_TMP432_U29_ALERT_R_N", "RPDB_GLOBAL_WP", + "RPDB_FAN_CT_FAN_FAIL_R_N", "RPDB_VERID_A0", + "RPDB_VERID_A1", "RPDB_VERID_A2", + "RPDB_ALERT_P50V_HSC2_R_N", "RPDB_ALERT_P50V_HSC3_R_N", + "RPDB_ALERT_P50V_HSC4_R_N", "RPDB_ALERT_P50V_STBY_R_N", + "RPDB_P12V_MB_VRM_ALERT_R_N", + "RPDB_P12V_STBY_VRM_ALERT_R_N", + "RPDB_PGD_P3V3_STBY_PWRGD_R", + "RPDB_P12V_STBY_VRM_PWRGD_BUF_R"; + }; + gpio@24 { + gpio-line-names =3D + "RPDB_EAM2_PRSNT_MOS_N_R", "RPDB_EAM3_PRSNT_MOS_N_R", + "RPDB_PWRGD_P50V_HSC4_SYS_R", + "RPDB_PWRGD_P50V_STBY_SYS_BUF_R", + "RPDB_P50V_FAN5_R2_PG", "RPDB_P50V_FAN6_R2_PG", + "RPDB_P50V_FAN7_R2_PG", "RPDB_P50V_FAN8_R2_PG", + "RPDB_SKU_ID0", "RPDB_FAN5_PRSNT_N_R", + "", "RPDB_FAN6_PRSNT_N_R", + "RPDB_FAN7_PRSNT_N_R", "RPDB_FAN8_PRSNT_N_R", + "", ""; + }; + gpio@38 { + compatible =3D "nxp,pca9554"; + reg =3D <0x38>; + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-parent =3D <&sgpiom0>; + interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names =3D + "RPDB_P50V_FUSE2_TVS1", "RPDB_P50V_FUSE2_TVS2", + "RPDB_P50V_FUSE3_TVS1", "RPDB_P50V_FUSE3_TVS2", + "RPDB_P50V_FUSE4_TVS1", "", + "", ""; + }; + }; + i2c8mux0ch1: i2c@1 { + gpio@22 { + gpio-line-names =3D + "LPDB_FAN_FULL_SPEED_R_N", "LPDB_I2C_TEMP75_U8_ALERT_R_N", + "LPDB_I2C_TMP432_U29_ALERT_R_N", "LPDB_GLOBAL_WP", + "LPDB_FAN_CT_FAN_FAIL_R_N", "LPDB_VERID_A0", + "LPDB_VERID_A1", "LPDB_VERID_A2", + "LPDB_ALERT_P50V_HSC0_R_N", "LPDB_ALERT_P50V_HSC1_R_N", + "LPDB_ALERT_P50V_HSC5_R_N", "LPDB_I2C_P12V_SW_VRM_ALERT_R_N", + "LPDB_EAM0_PRSNT_MOS_N_R", "LPDB_EAM1_PRSNT_MOS_N_R", + "LPDB_PWRGD_P50V_HSC5_SYS_R", "BARKLIP_PRSNT_N_R3"; + }; + gpio@24 { + gpio-line-names =3D + "LPDB_P50V_FAN0_R2_PG", "LPDB_P50V_FAN1_R2_PG", + "LPDB_P50V_FAN2_R2_PG", "LPDB_P50V_FAN3_R2_PG", + "LPDB_P50V_FAN4_R2_PG", "LPDB_FAN0_PRSNT_N_R", + "LPDB_FAN1_PRSNT_N_R", "LPDB_FAN2_PRSNT_N_R", + "LPDB_FAN3_PRSNT_N_R", "LPDB_FAN4_PRSNT_N_R", + "LPDB_SKU_ID0", "", + "", "", + "", "LPDB_PG_P3V3_R"; + }; + gpio@38 { + compatible =3D "nxp,pca9554"; + reg =3D <0x38>; + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-parent =3D <&sgpiom0>; + interrupts =3D <174 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names =3D + "LPDB_P50V_FUSE0_TVS1", "LPDB_P50V_FUSE0_TVS2", + "LPDB_P50V_FUSE1_TVS1", "LPDB_P50V_FUSE1_TVS2", + "LPDB_P50V_FUSE5_TVS1", "", + "", ""; + }; + }; + }; +}; + &sgpiom0 { ngpios =3D <128>; bus-frequency =3D <2000000>; --=20 2.34.1 From nobody Sat Oct 3 04:32:05 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EBA57470458; Wed, 5 Aug 2026 13:03:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785934991; cv=none; b=aBvBayHyHDDklhqk0uspirVhfGR1Iaob2BFCSuQgKdwHRfX/IhVUrNMht/NumTdoI5oeApQgxii9y51cvE89/Fp13lpoYoMDWrs7VnbG2phZA8NUJjEaEF5fUqwM2/CKk/bFo6sa6CD6OWp1isEfXy52dXNUI1xQBAMgrn0TzIM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785934991; c=relaxed/simple; bh=0w+n+lPjz3WSPIo2NDXp6hSQIIS7CvZuDO3z2haGJjQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=YPN9kF0rdgRqifUfGfdNfo+3azXHFneWqPZCb7uWmO2M5QYf2nNr966UAmyPSxuelZohifK9nwHT9EY7ylF2KR026cHEQwQ1HaeCIY29gn3KRDHI54DjavFRuaKPD+hFvFKrJLhU8sPpPkUpgD6YyCBBrZR3Ak1MCOb1R24aRTs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=J+FODLMK; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="J+FODLMK" Received: by smtp.kernel.org (Postfix) with ESMTPS id 96CF3C2BD05; Wed, 5 Aug 2026 13:03:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1785934989; bh=0w+n+lPjz3WSPIo2NDXp6hSQIIS7CvZuDO3z2haGJjQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=J+FODLMKTmgNAeJBNptOobGpd/5SKQldBH9uAeSgQXEMGCbYd8erJtgiFIi5eh/9Y e297kJ9EbnwWzwGwOXcmeMX6EcY7R3JKF8IVf6PDprc7yX0wPTNtTdntjHUVJrL71j VCvrE26/xxpu6qi8Mywt/S1A9TLp72MQrT2GGhhyznXqvZSsozYm8ViF1Ld7X1B8TR E0Qd5+NlZOYNiULbfro4CxeLGbVOLNf/UCjyr3/lIvwFnomKPrnYVcB8iMIT1iVJn6 JCaKCeeFrSNjqCn2jGvt89avEnFWL0o+kTOmewexsB19jH/W0MBfXClOl1Lv6+MJsE huKr3GUWy6gBg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8487CC55ABA; Wed, 5 Aug 2026 13:03:09 +0000 (UTC) From: Colin Huang via B4 Relay Date: Wed, 05 Aug 2026 21:02:39 +0800 Subject: [PATCH v4 11/12] ARM: dts: aspeed: anacapa: Simplify leakage GPIO line names Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260805-anacapa-devlop-phase-devicetree-v4-11-5d67e0efa6c5@gmail.com> References: <20260805-anacapa-devlop-phase-devicetree-v4-0-5d67e0efa6c5@gmail.com> In-Reply-To: <20260805-anacapa-devlop-phase-devicetree-v4-0-5d67e0efa6c5@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, colin.huang2@amd.com, Colin Huang , Rex Fu X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1785934963; l=2439; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=vmghXUBmwzP2rgOwg7WGwWzuzw+iRgP5cEGqkIrQPXw=; b=lYkSmtdWOulgcjWFT7dVAobVXYRqBZUmA/Uo4cUne5jpvs8yitJrNubRm40QbbsJsSq6pEsCO ckmop/r0c2cAl/JhRTGpkewDg7Fcerimo/SQB3popOyIdrW3qtGvg8i X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 X-Original-From: Colin Huang Reply-To: u8813345@gmail.com From: Rex Fu Remove the board location suffixes from the leakage present GPIO line names. The channel number is enough to identify each leakage present signal. Signed-off-by: Rex Fu --- .../dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts | 28 +++++++++++-------= ---- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts b= /arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts index f09dd1abe77d..f710046f79bc 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts @@ -111,32 +111,32 @@ &sgpiom0 { "", "", =20 /* B0-B7 line 16-31 */ - "Channel0_leakage_EAM3", "FM_CPU_FPGA_JTAG_MUX_SEL", - "Channel1_leakage_EAM0", "FM_SCM_JTAG_MUX_SEL", - "Channel2_leakage_Manifold1", "FM_BRIDGE_JTAG_MUX_SEL", - "Channel5_leakage_present_EAM1", "FM_CPU0_NMI_SYNC_FLOOD_N", - "Channel4_leakage_Manifold2", "BMC_AINIC0_WP_R2_L", - "Channel5_leakage_EAM1", "BMC_AINIC1_WP_R2_L", - "Channel6_leakage_CPU_DIMM", "CPLD_BUF_R_AGPIO330", - "Channel7_leakage_EAM2", "CPLD_BUF_R_AGPIO331", + "Channel0_leakage", "FM_CPU_FPGA_JTAG_MUX_SEL", + "Channel1_leakage", "FM_SCM_JTAG_MUX_SEL", + "Channel2_leakage", "FM_BRIDGE_JTAG_MUX_SEL", + "Channel5_leakage_present", "FM_CPU0_NMI_SYNC_FLOOD_N", + "Channel4_leakage", "BMC_AINIC0_WP_R2_L", + "Channel5_leakage", "BMC_AINIC1_WP_R2_L", + "Channel6_leakage", "CPLD_BUF_R_AGPIO330", + "Channel7_leakage", "CPLD_BUF_R_AGPIO331", =20 /* C0-C7 line 32-47 */ "RSVD_RMC_GPIO3", "RTM_MUX_L", "LEAK_DETECT_RMC_N", "RTM_MUX_R", "HDR_P0_NMI_BTN_BUF_R_N", "FPGA_JTAG_SCM_DBREQ_N", - "Channel6_leakage_present_CPU_DIMM", "whdt_sel", + "Channel6_leakage_present", "whdt_sel", "R_EAM0_NIC_CBL_PRSNT_L", "JTAG_CPLD_TRST_R_N", "R_EAM1_NIC_CBL_PRSNT_L", "", "L_EAM0_NIC_CBL_PRSNT_L", "", "L_EAM1_NIC_CBL_PRSNT_L", "", =20 /* D0-D7 line 48-63 */ - "Channel0_leakage_present_EAM3", "", - "Channel1_leakage_present_EAM0", "", - "Channel2_leakage_present_Manifold1", "", - "Channel4_leakage_present_Manifold2", "", + "Channel0_leakage_present", "", + "Channel1_leakage_present", "", + "Channel2_leakage_present", "", + "Channel4_leakage_present", "", "AMC_BRD_PRSNT_CPLD_L", "", - "Channel7_leakage_present_EAM2", "", + "Channel7_leakage_present", "", "", "", "", "", =20 --=20 2.34.1 From nobody Sat Oct 3 04:32:05 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3F5A1470E8F; Wed, 5 Aug 2026 13:03:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785934991; cv=none; b=Fz/iuE1b2qy7z1ukLSGL5NVa2/TxDaHkcKqyVGrfCZF2p5C/wfv5YxSTAaw123Hw5nlgYZscH06IEMhxQN4bRwKfw3HIpBdamg8o6/OskXdTTR+MfH5XCouynVyr8jm8am7aSSy5D9AqA2r8e6+r+D2EuVU/tF0D3V1a8cxsnuQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785934991; c=relaxed/simple; bh=295IKqaeCumSuUEaZhnHHBluCh18/amZPEFle+tiP3I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Vp1VhVaP7mJMwBRQLzQwiRTdrj5GLq/qzKC5S/IgCk9UKe5GM1WRICzJUN97+webtWv6trPI2G/EB2xG6WxSrnQWwK8dfXzdbNca3flEn0S/fUuzvKvMyjOE4EmoDph+/qXoMwB4miQpo6wRb+sSB13K+DdXuyykebC6C1l9l/k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=aqUtzAz7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="aqUtzAz7" Received: by smtp.kernel.org (Postfix) with ESMTPS id A8E8AC32782; Wed, 5 Aug 2026 13:03:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1785934989; bh=295IKqaeCumSuUEaZhnHHBluCh18/amZPEFle+tiP3I=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=aqUtzAz7wMWIifL/9j2Sp0mbsil3VkPEhviwvPTfrYov+yKHlq+d/NrOTLgw8S8eF P3ChY3fpGGeLiL3UOAV2rrFKOLomSQmSs5nfTMwMWB6N9EqZLYejL+RpVY4ElPbJC1 dDXevHUtaods4lOMHHN7kqMn8aXth7dBqzAN7hHFloAFpX71JDM4jjbRUDxGcJsNrg 0+r+dJJSflGUXL8hzvSvpYtO1/0m/Czk1i7BJnAhDO8mVIWh/dDMHvJVglVkK/z8UM 3PR2MKjP3rKmb8EjKa8gczHjdLPrXuuUITWP60Qx0ofxhWRTlD8cc3qPauJufxS+PV p+J17SilMJ3lw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97801C55ABF; Wed, 5 Aug 2026 13:03:09 +0000 (UTC) From: Colin Huang via B4 Relay Date: Wed, 05 Aug 2026 21:02:40 +0800 Subject: [PATCH v4 12/12] ARM: dts: aspeed: anacapa: Add SPI flash VCC supply Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260805-anacapa-devlop-phase-devicetree-v4-12-5d67e0efa6c5@gmail.com> References: <20260805-anacapa-devlop-phase-devicetree-v4-0-5d67e0efa6c5@gmail.com> In-Reply-To: <20260805-anacapa-devlop-phase-devicetree-v4-0-5d67e0efa6c5@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, colin.huang2@amd.com, Colin Huang , Rex Fu X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1785934963; l=941; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=f6LU0FAv4z223NfwbW5+xtWf2s69Q4QEuw+6jPL4YpI=; b=GU4HitdnZN9sIeaoEOIxc65OCZhYrjGp2dE2uozcgTcLXfDoR3GiEE+rtDALj7McAzfnsWjol g0HDu9Sad81Bonn1sgWxibVjHcRfneq+glygtwO4gZYOXQaVxuvb6zd X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= X-Endpoint-Received: by B4 Relay for u8813345@gmail.com/20260202 with auth_id=761 X-Original-From: Colin Huang Reply-To: u8813345@gmail.com From: Rex Fu Specify the 3.3 V auxiliary rail as the SPI flash VCC supply to avoid using the dummy regulator during device initialization. Signed-off-by: Rex Fu --- .../boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts | 16 ++++++++++++= ++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts = b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts index f913fa3f622d..cb4b815f1803 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts @@ -27,6 +27,22 @@ / { i2c51 =3D &i2c10mux0ch0; }; =20 +&fmc { + flash@0 { + vcc-supply =3D <&p3v3_bmc_aux>; + }; + flash@1 { + vcc-supply =3D <&p3v3_bmc_aux>; + }; +}; + +// BIOS Flash +&spi2 { + flash@0 { + vcc-supply =3D <&p3v3_bmc_aux>; + }; +}; + // MB - PDB &i2c8 { i2c-mux@72 { --=20 2.34.1