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Add the generic spi-device-addr property for describing these hardware addresses. The property is placed on the SPI peripheral node and may contain multiple addresses. Acked-by: Nuno S=C3=A1 Reviewed-by: Conor Dooley Reviewed-by: Marcus Folkesson Signed-off-by: Janani Sunil --- Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yam= l b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml index 880a9f624566..4894196c8f9c 100644 --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml @@ -142,6 +142,13 @@ properties: minItems: 2 maxItems: 4 =20 + spi-device-addr: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + Device addresses used when multiple peripherals share a single chip + select. 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Signed-off-by: Janani Sunil Reviewed-by: Conor Dooley --- .../devicetree/bindings/iio/dac/adi,ad5529r.yaml | 254 +++++++++++++++++= ++++ MAINTAINERS | 7 + 2 files changed, 261 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad5529r.yaml b/D= ocumentation/devicetree/bindings/iio/dac/adi,ad5529r.yaml new file mode 100644 index 000000000000..9c390d460e5f --- /dev/null +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad5529r.yaml @@ -0,0 +1,254 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/dac/adi,ad5529r.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD5529R 16-Channel 12/16-bit High Voltage DAC + +maintainers: + - Janani Sunil + +description: | + The AD5529R is a 16-channel, 12-bit or 16-bit, high voltage, buffered vo= ltage + output digital-to-analog converter (DAC) with an integrated precision re= ference. + The device operates from unipolar and bipolar supplies. It is guaranteed + monotonic and has built-in rail-to-rail output buffers that can source or + sink up to 25mA. + + Specifications: + * 16 independent 12-bit or 16-bit DAC channels + * Independently programmable output ranges: 0V to 5V, 0V to 10V, 0V to 2= 0V, + 0V to 40V, =C2=B15V, =C2=B110V, =C2=B115V, and =C2=B120V + * The device supports SPI communication with Mode 0 and Mode 3. + * 4.096V precision reference, 12ppm/=C2=B0C maximum + * Built-in function generation: Toggle, Sinusoidal Dither, and Ramp wave= forms + * Multiplexer for output voltage, load current sense and die temperature + + Datasheet: https://www.analog.com/media/en/technical-documentation/data-= sheets/ad5529r.pdf + +properties: + compatible: + enum: + - adi,ad5529r-16 # 16-bit variant + - adi,ad5529r-12 # 12-bit variant + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 25000000 + description: + Maximum SPI frequency. The device supports SPI Mode 0 and Mode 3. + Read operations are limited to 25MHz maximum. + + reset-gpios: + maxItems: 1 + description: + GPIO connected to the RESET pin. Active low. When asserted low, + performs a power-on reset and initializes the device to its default = state. + + clear-gpios: + maxItems: 1 + description: + GPIO connected to the CLEAR pin. Active low. When asserted low, + clears all DAC data registers without affecting configuration settin= gs. + + interrupts: + maxItems: 1 + description: + Interrupt connected to the ALARM pin. Active low interrupt output + for overtemperature conditions, SPI CRC errors, and function complet= ion. + + pwms: + minItems: 1 + maxItems: 4 + description: + PWM signals connected to the TG0-TG3 toggle pins. Pulsing these pins + based on trigger edge settings allows selected DACs to be updated + synchronously for digital function generation. + + pwm-names: + minItems: 1 + maxItems: 4 + items: + enum: [ tg0, tg1, tg2, tg3 ] + + io-channels: + maxItems: 1 + description: + ADC channel connected to the MUXOUT pin for monitoring output voltag= e, + load current sense, and die temperature. + + io-channel-names: + const: muxout + + vdd-io-supply: + description: Digital power supply (1.08V to 1.98V) + + vdd-5v-supply: + description: Analog power supply (4.75V to 5.25V) + + vdd-hv0-supply: + description: + High voltage positive supply (7V to 45V) for channels 0 to 3. + + vdd-hv1-supply: + description: + High voltage positive supply (7V to 45V) for channels 4 to 7. + + vdd-hv2-supply: + description: + High voltage positive supply (7V to 45V) for channels 8 to 11. + + vdd-hv3-supply: + description: + High voltage positive supply (7V to 45V) for channels 12 to 15. + + vss-hv0-supply: + description: + High voltage negative supply (-22.5V to 0V) for channels 0 to 3. + + vss-hv1-supply: + description: + High voltage negative supply (-22.5V to 0V) for channels 4 to 7. + + vss-hv2-supply: + description: + High voltage negative supply (-22.5V to 0V) for channels 8 to 11. + + vss-hv3-supply: + description: + High voltage negative supply (-22.5V to 0V) for channels 12 to 15. + + vref-supply: + description: + External voltage reference supply (4.056V to 4.136V, typically 4.096= V). + When specified, the device uses external reference mode and the VREF= pin + becomes an input. The device uses the internal 4.096V precision refe= rence + otherwise. + + spi-device-addr: + minItems: 1 + maxItems: 4 + items: + enum: [0, 1, 2, 3] + default: 0 + description: + Hardware address of each device, selected by the ID0 and ID1 pins. + Up to four AD5529R devices can share a single SPI chip select. + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^channel@([0-9a-f]{1,2})$": + $ref: dac.yaml + type: object + description: Child nodes for individual channel configuration + + properties: + reg: + description: + Flattened channel number across all AD5529R devices sharing the = chip + select. Within each 16-channel block, the physical channel numbe= r is reg % 16. + minimum: 0 + maximum: 63 + + output-range-microvolt: + description: + Output voltage range for this channel as [min, max] in + microvolts. + oneOf: + - items: + - const: 0 + default: 0 + - enum: [5000000, 10000000, 20000000, 40000000] + default: 5000000 + - items: + - const: -5000000 + - const: 5000000 + - items: + - const: -10000000 + - const: 10000000 + - items: + - const: -15000000 + - const: 15000000 + - items: + - const: -20000000 + - const: 20000000 + + required: + - reg + + additionalProperties: false + +required: + - compatible + - reg + - vdd-io-supply + - vdd-5v-supply + - vdd-hv0-supply + - vdd-hv1-supply + - vdd-hv2-supply + - vdd-hv3-supply + +dependencies: + spi-cpha: [ spi-cpol ] + spi-cpol: [ spi-cpha ] + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + dac@0 { + compatible =3D "adi,ad5529r-16"; + reg =3D <0>; + spi-max-frequency =3D <25000000>; + spi-device-addr =3D <0>; + + vdd-io-supply =3D <&vdd_io_regulator>; + vdd-5v-supply =3D <&vdd_5v_regulator>; + vdd-hv0-supply =3D <&vdd_hv0_regulator>; + vdd-hv1-supply =3D <&vdd_hv1_regulator>; + vdd-hv2-supply =3D <&vdd_hv2_regulator>; + vdd-hv3-supply =3D <&vdd_hv3_regulator>; + vss-hv0-supply =3D <&vss_hv0_regulator>; + vss-hv1-supply =3D <&vss_hv1_regulator>; + vss-hv2-supply =3D <&vss_hv2_regulator>; + vss-hv3-supply =3D <&vss_hv3_regulator>; + + reset-gpios =3D <&gpio0 87 GPIO_ACTIVE_LOW>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + channel@0 { + reg =3D <0>; + output-range-microvolt =3D <0 5000000>; + }; + + channel@1 { + reg =3D <1>; + output-range-microvolt =3D <(-10000000) 10000000>; + }; + + channel@2 { + reg =3D <2>; + output-range-microvolt =3D <0 40000000>; + }; + }; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index d6c3c7d22403..320e84765ce6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1507,6 +1507,13 @@ W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/adc/adi,ad4851.yaml F: drivers/iio/adc/ad4851.c =20 +ANALOG DEVICES INC AD5529R DRIVER +M: Janani Sunil +L: linux-iio@vger.kernel.org +S: Supported +W: https://ez.analog.com/linux-software-drivers +F: Documentation/devicetree/bindings/iio/dac/adi,ad5529r.yaml + ANALOG DEVICES INC AD5706R DRIVER M: Alexis Czezar Torreno L: linux-iio@vger.kernel.org --=20 2.43.0 From nobody Fri Oct 2 03:56:02 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E69113E1680; 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The device communicates over SPI and supports per-channel output range configuration. An optional external 4.096V reference can be used in place of the internal reference. Signed-off-by: Janani Sunil --- MAINTAINERS | 1 + drivers/iio/dac/Kconfig | 17 ++ drivers/iio/dac/Makefile | 1 + drivers/iio/dac/ad5529r.c | 530 ++++++++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 549 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 320e84765ce6..143714e27d51 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1513,6 +1513,7 @@ L: linux-iio@vger.kernel.org S: Supported W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/dac/adi,ad5529r.yaml +F: drivers/iio/dac/ad5529r.c =20 ANALOG DEVICES INC AD5706R DRIVER M: Alexis Czezar Torreno diff --git a/drivers/iio/dac/Kconfig b/drivers/iio/dac/Kconfig index 657c68e75542..bb1d59889a2a 100644 --- a/drivers/iio/dac/Kconfig +++ b/drivers/iio/dac/Kconfig @@ -134,6 +134,23 @@ config AD5449 To compile this driver as a module, choose M here: the module will be called ad5449. =20 +config AD5529R + tristate "Analog Devices AD5529R High Voltage DAC driver" + depends on SPI_MASTER + select REGMAP_SPI + help + Say yes here to build support for Analog Devices AD5529R + 16-Channel, 12-Bit/16-Bit, 40V High Voltage Precision Digital to Analog + Converter. + + The device features multiple output voltage ranges from -20V to +20V, + built-in 4.096V voltage reference, and digital functions including + toggle, dither, and ramp modes. Supports both 12-bit and 16-bit + resolution variants. + + To compile this driver as a module, choose M here: the + module will be called ad5529r. + config AD5592R_BASE tristate =20 diff --git a/drivers/iio/dac/Makefile b/drivers/iio/dac/Makefile index 003431798498..f35e060b3643 100644 --- a/drivers/iio/dac/Makefile +++ b/drivers/iio/dac/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_AD5446) +=3D ad5446.o obj-$(CONFIG_AD5446_SPI) +=3D ad5446-spi.o obj-$(CONFIG_AD5446_I2C) +=3D ad5446-i2c.o obj-$(CONFIG_AD5449) +=3D ad5449.o +obj-$(CONFIG_AD5529R) +=3D ad5529r.o obj-$(CONFIG_AD5592R_BASE) +=3D ad5592r-base.o obj-$(CONFIG_AD5592R) +=3D ad5592r.o obj-$(CONFIG_AD5593R) +=3D ad5593r.o diff --git a/drivers/iio/dac/ad5529r.c b/drivers/iio/dac/ad5529r.c new file mode 100644 index 000000000000..1ea0ddfdda99 --- /dev/null +++ b/drivers/iio/dac/ad5529r.c @@ -0,0 +1,530 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * AD5529R Digital-to-Analog Converter Driver + * 16-Channel, 12/16-Bit, 40V High Voltage Precision DAC + * + * Copyright 2026 Analog Devices Inc. + * Author: Janani Sunil + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define AD5529R_REG_INTERFACE_CONFIG_A 0x00 +#define AD5529R_INTERFACE_CONFIG_A_SW_RESET (BIT(7) | BIT(0)) +#define AD5529R_INTERFACE_CONFIG_A_ADDR_ASCENSION BIT(5) +#define AD5529R_INTERFACE_CONFIG_A_SDO_ENABLE BIT(4) +#define AD5529R_REG_DEVICE_CONFIG 0x02 +#define AD5529R_REG_CHIP_GRADE 0x06 +#define AD5529R_REG_SCRATCH_PAD 0x0A +#define AD5529R_REG_SPI_REVISION 0x0B +#define AD5529R_REG_VENDOR_H 0x0D +#define AD5529R_REG_STREAM_MODE 0x0E +#define AD5529R_REG_INTERFACE_STATUS_A 0x11 +#define AD5529R_REG_MULTI_DAC_CH_SEL 0x14 +#define AD5529R_REG_OUT_RANGE_BASE 0x3C +#define AD5529R_REG_OUT_RANGE(ch) (AD5529R_REG_OUT_RANGE_BASE + (ch) * 2) +#define AD5529R_REG_DAC_INPUT_A_BASE 0x148 +#define AD5529R_REG_DAC_INPUT_A(ch) (AD5529R_REG_DAC_INPUT_A_BASE + (ch) = * 2) +#define AD5529R_REG_DAC_DATA_READBACK_BASE 0x16A +#define AD5529R_REG_TSENS_ALERT_FLAG 0x18C +#define AD5529R_REG_TSENS_SHTD_FLAG 0x18E +#define AD5529R_REG_FUNC_BUSY 0x1A0 +#define AD5529R_REG_REF_SEL 0x1A2 +#define AD5529R_REF_SEL_INTERNAL_REF BIT(0) +#define AD5529R_REG_INIT_CRC_ERR_STAT 0x1A4 +#define AD5529R_REG_MULTI_DAC_HOTPATH_SW_LDAC 0x1A8 + +#define AD5529R_MAX_REGISTER 0x232 +#define AD5529R_8BIT_REG_MAX 0x13 +#define AD5529R_MAX_CHANNELS 16 +#define AD5529R_SPI_READ_FLAG 0x80 +#define AD5529R_ADDR_SHIFT 12 + +struct ad5529r_model_data { + const char *model_name; + unsigned int resolution; +}; + +#define AD5529R_DAC_CHANNEL(chan) ((struct iio_chan_spec) { \ + .type =3D IIO_VOLTAGE, \ + .indexed =3D 1, \ + .output =3D 1, \ + .channel =3D (chan), \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_SCALE) | \ + BIT(IIO_CHAN_INFO_OFFSET), \ +}) + +static const char * const ad5529r_supply_names[] =3D { + "vdd-io", + "vdd-5v", + "vdd-hv0", + "vdd-hv1", + "vdd-hv2", + "vdd-hv3", +}; + +static const char * const ad5529r_vss_supply_names[] =3D { + "vss-hv0", + "vss-hv1", + "vss-hv2", + "vss-hv3", +}; + +static const struct ad5529r_model_data ad5529r_16bit_model_data =3D { + .model_name =3D "ad5529r-16", + .resolution =3D 16, +}; + +static const struct ad5529r_model_data ad5529r_12bit_model_data =3D { + .model_name =3D "ad5529r-12", + .resolution =3D 12, +}; + +enum ad5529r_output_range { + AD5529R_RANGE_0V_5V, + AD5529R_RANGE_0V_10V, + AD5529R_RANGE_0V_20V, + AD5529R_RANGE_0V_40V, + AD5529R_RANGE_NEG5V_5V, + AD5529R_RANGE_NEG10V_10V, + AD5529R_RANGE_NEG15V_15V, + AD5529R_RANGE_NEG20V_20V, +}; + +static const s32 ad5529r_output_ranges_mV[8][2] =3D { + [AD5529R_RANGE_0V_5V] =3D { 0, 5000 }, + [AD5529R_RANGE_0V_10V] =3D { 0, 10000 }, + [AD5529R_RANGE_0V_20V] =3D { 0, 20000 }, + [AD5529R_RANGE_0V_40V] =3D { 0, 40000 }, + [AD5529R_RANGE_NEG5V_5V] =3D { -5000, 5000 }, + [AD5529R_RANGE_NEG10V_10V] =3D { -10000, 10000 }, + [AD5529R_RANGE_NEG15V_15V] =3D { -15000, 15000 }, + [AD5529R_RANGE_NEG20V_20V] =3D { -20000, 20000 }, +}; + +struct ad5529r_state { + struct spi_device *spi; + const struct ad5529r_model_data *model_data; + struct regmap *regmap_8bit; + struct regmap *regmap_16bit; + struct iio_chan_spec channels[AD5529R_MAX_CHANNELS]; + unsigned int num_channels; + enum ad5529r_output_range output_range_idx[AD5529R_MAX_CHANNELS]; +}; + +static const struct regmap_range ad5529r_8bit_readable_ranges[] =3D { + regmap_reg_range(AD5529R_REG_INTERFACE_CONFIG_A, AD5529R_REG_CHIP_GRADE), + regmap_reg_range(AD5529R_REG_SCRATCH_PAD, AD5529R_REG_VENDOR_H), + regmap_reg_range(AD5529R_REG_STREAM_MODE, AD5529R_REG_INTERFACE_STATUS_A), +}; + +static const struct regmap_range ad5529r_16bit_readable_ranges[] =3D { + regmap_reg_range(AD5529R_REG_MULTI_DAC_CH_SEL, AD5529R_REG_INIT_CRC_ERR_S= TAT), + regmap_reg_range(AD5529R_REG_MULTI_DAC_HOTPATH_SW_LDAC, AD5529R_MAX_REGIS= TER), +}; + +static const struct regmap_access_table ad5529r_8bit_readable_table =3D { + .yes_ranges =3D ad5529r_8bit_readable_ranges, + .n_yes_ranges =3D ARRAY_SIZE(ad5529r_8bit_readable_ranges), +}; + +static const struct regmap_access_table ad5529r_16bit_readable_table =3D { + .yes_ranges =3D ad5529r_16bit_readable_ranges, + .n_yes_ranges =3D ARRAY_SIZE(ad5529r_16bit_readable_ranges), +}; + +static const struct regmap_range ad5529r_8bit_read_only_ranges[] =3D { + regmap_reg_range(AD5529R_REG_DEVICE_CONFIG, AD5529R_REG_CHIP_GRADE), + regmap_reg_range(AD5529R_REG_SPI_REVISION, AD5529R_REG_VENDOR_H), +}; + +static const struct regmap_range ad5529r_16bit_read_only_ranges[] =3D { + regmap_reg_range(AD5529R_REG_DAC_DATA_READBACK_BASE, + AD5529R_REG_DAC_DATA_READBACK_BASE + + (AD5529R_MAX_CHANNELS - 1) * 2), + regmap_reg_range(AD5529R_REG_TSENS_ALERT_FLAG, AD5529R_REG_TSENS_SHTD_FLA= G), + regmap_reg_range(AD5529R_REG_FUNC_BUSY, AD5529R_REG_FUNC_BUSY), + regmap_reg_range(AD5529R_REG_INIT_CRC_ERR_STAT, AD5529R_REG_INIT_CRC_ERR_= STAT), +}; + +static const struct regmap_access_table ad5529r_8bit_writeable_table =3D { + .no_ranges =3D ad5529r_8bit_read_only_ranges, + .n_no_ranges =3D ARRAY_SIZE(ad5529r_8bit_read_only_ranges), +}; + +static const struct regmap_access_table ad5529r_16bit_writeable_table =3D { + .no_ranges =3D ad5529r_16bit_read_only_ranges, + .n_no_ranges =3D ARRAY_SIZE(ad5529r_16bit_read_only_ranges), +}; + +static struct regmap *ad5529r_get_regmap(struct ad5529r_state *st, + unsigned int reg) +{ + if (reg <=3D AD5529R_8BIT_REG_MAX) + return st->regmap_8bit; + + return st->regmap_16bit; +} + +static int ad5529r_reset(struct ad5529r_state *st) +{ + struct reset_control *rst; + int ret; + + rst =3D devm_reset_control_get_optional_exclusive(&st->spi->dev, NULL); + if (IS_ERR(rst)) + return PTR_ERR(rst); + + if (rst) { + ret =3D reset_control_assert(rst); + if (ret) + return ret; + + /* Minimum reset low width (t_reset) is 20 ns per datasheet. */ + ndelay(20); + + ret =3D reset_control_deassert(rst); + if (ret) + return ret; + } else { + ret =3D regmap_write(st->regmap_8bit, AD5529R_REG_INTERFACE_CONFIG_A, + AD5529R_INTERFACE_CONFIG_A_SW_RESET); + if (ret) + return ret; + } + + /* + * Wait 10 ms for digital initialization to complete. + * Per datasheet, Interface Status A register NOT_READY_ERR bit is + * set if SPI transactions are attempted before digital initialization + * completes. + */ + fsleep(10 * USEC_PER_MSEC); + + return regmap_write(st->regmap_8bit, AD5529R_REG_INTERFACE_CONFIG_A, + AD5529R_INTERFACE_CONFIG_A_SDO_ENABLE | + AD5529R_INTERFACE_CONFIG_A_ADDR_ASCENSION); +} + +static int ad5529r_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long mask) +{ + struct ad5529r_state *st =3D iio_priv(indio_dev); + unsigned int reg_addr, reg_val_h; + int ret, range_idx, span_mv; + + switch (mask) { + case IIO_CHAN_INFO_RAW: + /* + * Read from DAC_INPUT_A register rather than DAC_DATA_READBACK. + * The DAC operates in transparent mode and directly reflects + * whatever value is written to the INPUT_A register. + */ + reg_addr =3D AD5529R_REG_DAC_INPUT_A(chan->channel); + ret =3D regmap_read(st->regmap_16bit, reg_addr, ®_val_h); + if (ret) + return ret; + + *val =3D reg_val_h; + + return IIO_VAL_INT; + case IIO_CHAN_INFO_SCALE: + range_idx =3D st->output_range_idx[chan->channel]; + + span_mv =3D ad5529r_output_ranges_mV[range_idx][1] - + ad5529r_output_ranges_mV[range_idx][0]; + *val =3D span_mv; + *val2 =3D st->model_data->resolution; + + return IIO_VAL_FRACTIONAL_LOG2; + case IIO_CHAN_INFO_OFFSET: + range_idx =3D st->output_range_idx[chan->channel]; + + if (ad5529r_output_ranges_mV[range_idx][0] < 0) + *val =3D -(1 << (st->model_data->resolution - 1)); + else + *val =3D 0; + + return IIO_VAL_INT; + default: + return -EINVAL; + } +} + +static int ad5529r_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int val, int val2, long mask) +{ + struct ad5529r_state *st =3D iio_priv(indio_dev); + unsigned int reg_addr; + + switch (mask) { + case IIO_CHAN_INFO_RAW: + if (val < 0 || val > GENMASK(st->model_data->resolution - 1, 0)) + return -EINVAL; + + reg_addr =3D AD5529R_REG_DAC_INPUT_A(chan->channel); + + return regmap_write(st->regmap_16bit, reg_addr, val); + default: + return -EINVAL; + } +} + +static int ad5529r_find_output_range(const s32 *vals) +{ + for (unsigned int i =3D 0; i < ARRAY_SIZE(ad5529r_output_ranges_mV); i++)= { + const s32 *range =3D ad5529r_output_ranges_mV[i]; + + if (vals[0] =3D=3D range[0] * (MICRO / MILLI) && + vals[1] =3D=3D range[1] * (MICRO / MILLI)) + return i; + } + + return -EINVAL; +} + +static int ad5529r_parse_channel_ranges(struct device *dev, + struct ad5529r_state *st) +{ + unsigned long channel_mask =3D 0; + s32 vals[2]; + int ret, range_idx; + u32 ch; + + device_for_each_child_node_scoped(dev, child) { + if (st->num_channels =3D=3D ARRAY_SIZE(st->channels)) + return dev_err_probe(dev, -EINVAL, "Too many channels\n"); + + ret =3D fwnode_property_read_u32(child, "reg", &ch); + if (ret) + return dev_err_probe(dev, ret, + "Missing reg property in channel node\n"); + + if (ch >=3D AD5529R_MAX_CHANNELS) + return dev_err_probe(dev, -EINVAL, + "Channel %u exceeds maximum 15\n", + ch); + + if (channel_mask & BIT(ch)) + return dev_err_probe(dev, -EINVAL, + "Duplicate channel %u\n", ch); + + channel_mask |=3D BIT(ch); + + if (fwnode_property_present(child, "output-range-microvolt")) { + /* + * DT stores cells as raw 32-bit values; signed endpoints are + * encoded by dtc in two's-complement and then interpreted + * here as s32. + */ + ret =3D fwnode_property_read_u32_array(child, + "output-range-microvolt", + (u32 *)vals, ARRAY_SIZE(vals)); + if (ret < 0) + return dev_err_probe(dev, ret, + "Failed to read range for ch %u\n", + ch); + + range_idx =3D ad5529r_find_output_range(vals); + if (range_idx < 0) + return dev_err_probe(dev, range_idx, + "Invalid range [%d %d] for ch %u\n", + vals[0], vals[1], ch); + } else { + range_idx =3D AD5529R_RANGE_0V_5V; + } + + st->output_range_idx[ch] =3D range_idx; + ret =3D regmap_write(st->regmap_16bit, + AD5529R_REG_OUT_RANGE(ch), range_idx); + if (ret) + return dev_err_probe(dev, ret, + "Failed to configure range for ch %u\n", + ch); + + st->channels[st->num_channels++] =3D AD5529R_DAC_CHANNEL(ch); + } + + return 0; +} + +static int ad5529r_reg_access(struct iio_dev *indio_dev, + unsigned int reg, + unsigned int writeval, + unsigned int *readval) +{ + struct ad5529r_state *st =3D iio_priv(indio_dev); + + if (readval) + return regmap_read(ad5529r_get_regmap(st, reg), reg, readval); + + return regmap_write(ad5529r_get_regmap(st, reg), reg, writeval); +} + +static const struct iio_info ad5529r_info =3D { + .read_raw =3D ad5529r_read_raw, + .write_raw =3D ad5529r_write_raw, + .debugfs_reg_access =3D ad5529r_reg_access, +}; + +static int ad5529r_probe(struct spi_device *spi) +{ + struct device *dev =3D &spi->dev; + struct iio_dev *indio_dev; + struct ad5529r_state *st; + struct regmap_config regmap_8bit_cfg; + struct regmap_config regmap_16bit_cfg; + bool external_vref; + u32 dev_addr =3D 0; + unsigned int i; + int ret; + + indio_dev =3D devm_iio_device_alloc(dev, sizeof(*st)); + if (!indio_dev) + return -ENOMEM; + + st =3D iio_priv(indio_dev); + + st->spi =3D spi; + + st->model_data =3D spi_get_device_match_data(spi); + if (!st->model_data) + return dev_err_probe(dev, -ENODATA, + "Failed to identify device variant\n"); + + device_property_read_u32(dev, "spi-device-addr", &dev_addr); + if (dev_addr > 3) + return dev_err_probe(dev, -EINVAL, + "spi-device-addr %u out of range [0, 3]\n", + dev_addr); + + regmap_8bit_cfg =3D (struct regmap_config) { + .name =3D "ad5529r-8bit", + .reg_bits =3D 16, + .val_bits =3D 8, + .max_register =3D AD5529R_8BIT_REG_MAX, + .read_flag_mask =3D AD5529R_SPI_READ_FLAG, + .rd_table =3D &ad5529r_8bit_readable_table, + .wr_table =3D &ad5529r_8bit_writeable_table, + .reg_base =3D dev_addr << AD5529R_ADDR_SHIFT, + }; + regmap_16bit_cfg =3D (struct regmap_config) { + .name =3D "ad5529r-16bit", + .reg_bits =3D 16, + .val_bits =3D 16, + .max_register =3D AD5529R_MAX_REGISTER, + .read_flag_mask =3D AD5529R_SPI_READ_FLAG, + .val_format_endian =3D REGMAP_ENDIAN_LITTLE, + .rd_table =3D &ad5529r_16bit_readable_table, + .wr_table =3D &ad5529r_16bit_writeable_table, + .reg_stride =3D 2, + .reg_base =3D dev_addr << AD5529R_ADDR_SHIFT, + }; + + ret =3D devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(ad5529r_supply_nam= es), + ad5529r_supply_names); + if (ret) + return dev_err_probe(dev, ret, + "Failed to get and enable regulators\n"); + + for (i =3D 0; i < ARRAY_SIZE(ad5529r_vss_supply_names); i++) { + ret =3D devm_regulator_get_enable_optional(dev, + ad5529r_vss_supply_names[i]); + if (ret && ret !=3D -ENODEV) + return dev_err_probe(dev, ret, + "Failed to get and enable %s regulator\n", + ad5529r_vss_supply_names[i]); + } + + ret =3D devm_regulator_get_enable_optional(dev, "vref"); + if (ret =3D=3D -ENODEV) + external_vref =3D false; + else if (ret) + return dev_err_probe(dev, ret, + "Failed to get and enable vref regulator\n"); + else + external_vref =3D true; + + st->regmap_8bit =3D devm_regmap_init_spi(spi, ®map_8bit_cfg); + if (IS_ERR(st->regmap_8bit)) + return dev_err_probe(dev, PTR_ERR(st->regmap_8bit), + "Failed to initialize 8-bit regmap\n"); + + st->regmap_16bit =3D devm_regmap_init_spi(spi, ®map_16bit_cfg); + if (IS_ERR(st->regmap_16bit)) + return dev_err_probe(dev, PTR_ERR(st->regmap_16bit), + "Failed to initialize 16-bit regmap\n"); + + ret =3D ad5529r_reset(st); + if (ret) + return dev_err_probe(dev, ret, "Failed to reset device\n"); + + ret =3D regmap_assign_bits(st->regmap_16bit, AD5529R_REG_REF_SEL, + AD5529R_REF_SEL_INTERNAL_REF, + !external_vref); + if (ret) + return dev_err_probe(dev, ret, "Failed to configure reference\n"); + + ret =3D ad5529r_parse_channel_ranges(dev, st); + if (ret) + return ret; + + indio_dev->name =3D st->model_data->model_name; + indio_dev->info =3D &ad5529r_info; + indio_dev->modes =3D INDIO_DIRECT_MODE; + indio_dev->channels =3D st->channels; + indio_dev->num_channels =3D st->num_channels; + + return devm_iio_device_register(dev, indio_dev); +} + +static const struct of_device_id ad5529r_of_match[] =3D { + { .compatible =3D "adi,ad5529r-16", .data =3D &ad5529r_16bit_model_data }, + { .compatible =3D "adi,ad5529r-12", .data =3D &ad5529r_12bit_model_data }, + { } +}; +MODULE_DEVICE_TABLE(of, ad5529r_of_match); + +static const struct spi_device_id ad5529r_id[] =3D { + { + .name =3D "ad5529r-16", + .driver_data =3D (kernel_ulong_t)&ad5529r_16bit_model_data, + }, + { + .name =3D "ad5529r-12", + .driver_data =3D (kernel_ulong_t)&ad5529r_12bit_model_data, + }, + { } +}; +MODULE_DEVICE_TABLE(spi, ad5529r_id); + +static struct spi_driver ad5529r_driver =3D { + .driver =3D { + .name =3D "ad5529r", + .of_match_table =3D ad5529r_of_match, + }, + .probe =3D ad5529r_probe, + .id_table =3D ad5529r_id, +}; +module_spi_driver(ad5529r_driver); + +MODULE_AUTHOR("Janani Sunil "); +MODULE_DESCRIPTION("Analog Devices AD5529R 12/16-bit DAC driver"); +MODULE_LICENSE("GPL"); --=20 2.43.0