From nobody Fri Oct 2 06:17:10 2026 Received: from mail-pf1-f199.google.com (mail-pf1-f199.google.com [209.85.210.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E194043CE5A for ; Tue, 4 Aug 2026 21:00:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.199 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785877252; cv=none; b=OmVBXEiDrXg5Qk3067acHwcyLudtDomYwckJDvGMQBhjnM64DUwd6KOMsIH60CkdlI1pXAN/ndnOWfrgPOXiW0GcPckwDSonsoFTxaMhIS3LwqlXQ9aMQAsj3E17FwQGD3NFV9MMN2bQfqNHsl0y2tXxWYbg10NTKiqhnomHoqo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785877252; c=relaxed/simple; bh=cxsYu/SAZXKKH+qzPWN68EM5LaGATeu0vffi9KXr19s=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=PVaFbB83BbecV6zPUL0afLHjiMuU4WXzctxYFVgDcGSFHJXYz2YQgjYAlSBFxd0FOjPhPvKgL455embi2yvl4jLqfSKlNqm+YUnm4i7jRBJCCYDxEtgE74Xo4ID5QV+i4emdkc9aPJRJNvDL2EMTOUn5WmccvwXtPDyi/SivHhU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=IYUweXdH; arc=none smtp.client-ip=209.85.210.199 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="IYUweXdH" Received: by mail-pf1-f199.google.com with SMTP id d2e1a72fcca58-84a67b16217so343178b3a.3 for ; Tue, 04 Aug 2026 14:00:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20251104; t=1785877250; x=1786482050; darn=vger.kernel.org; h=content-type:cc:to:from:subject:message-id:references:mime-version :in-reply-to:date:reply-to:from:to:cc:subject:date:message-id :reply-to:content-type; bh=UeyWwtdawyJZ7yaU5xxuUItmJbT+/6l6O65XfniG79w=; b=IYUweXdHYWSPRtxGr6juyRxIGuRlR49fgbWbYEwBPGxmUmcqBaxHJ77v9m/j8eFEr2 pQDlBF/PKa0nu/0KOJT4ySqrgPiDh4L+fBQ3RHEbIYa0msUoUCNhUMq5SzIu+t9ddLCH 2EgYZkTbdmDSvgK22X/AVRppTU1b6gQv45uJ8pxke0CAVwrohY+tZ2R0L0am6owB8v7D 2uXEN5Lq9jPyxz2sSc/bwEb2hVyhP6ksDMv7QPlWJ6y0HBKKjJKJhi7rUoGt7AOmdBEz ppEgE+xfxwbho722dD9n2f60JfG1q/NOM3IAgXW8/pxaGu1/pRnJaQ+y9hDrUpfFDERU i2lA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1785877250; x=1786482050; h=content-type:cc:to:from:subject:message-id:references:mime-version :in-reply-to:date:reply-to:x-gm-message-state:from:to:cc:subject :date:message-id:reply-to:content-type; bh=UeyWwtdawyJZ7yaU5xxuUItmJbT+/6l6O65XfniG79w=; b=l3lSDAZ82ocIK4N/+g00GMxoN6oYtc+L33HgczFlHaCARHn4QTW102VesYW5CxHMee KpVoaW9Zqjni/u4izDD0pQJUSyTViJF31kWgiJMe5Skfnoo4tMCT5eUSPKBuORsxMe5M XbtT038W9L0LNX8vcMvj0ir5z752O8oldc8/mhsGH+AQLSCRFQuXnIML4Rsrpp+aLAaV adwZ+nJympxIgWiai4EnBMPjJ4RbQ2yeQyiVg0CSXFiHQaVrr60dSDhT6DAGNHV8u3Yu mHXVgg263MBQX2emt1b+1cGljQdWa5sk7YiU6W/9CaiWQrt/714RcBEXB3OruQEFE25S dMzw== X-Forwarded-Encrypted: i=1; AHgh+RpYNfoeaU8mh/vdh4lnBjhOXFWrQj57BXca3pJb82wkJg7DzWDG2Cqev8mkAA+JBVwjNd8R/ll9p4HfXys=@vger.kernel.org X-Gm-Message-State: AOJu0YxJnT2I8Lk/g6BaGQxZSDj0exPNOX8uETFHzbPB0SLu+6aEh0aX QdFNImX3LecVxixViR5lOmWQo0jppE4pkjgsUgpGbxOKTpwRDbdQcOILKlGIq+hyCGe+p/8/cnF KNnM6rg== X-Received: from pfx48.prod.google.com ([2002:a05:6a00:a470:b0:848:81e8:f2d9]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a00:3d54:b0:847:8b1d:230d with SMTP id d2e1a72fcca58-84f2e014151mr1449461b3a.3.1785877250032; Tue, 04 Aug 2026 14:00:50 -0700 (PDT) Reply-To: Sean Christopherson Date: Tue, 4 Aug 2026 14:00:45 -0700 In-Reply-To: <20260804210046.3413149-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260804210046.3413149-1-seanjc@google.com> X-Mailer: git-send-email 2.55.0.571.g244d577d93-goog Message-ID: <20260804210046.3413149-2-seanjc@google.com> Subject: [PATCH v3 1/2] KVM: selftests: Test one random GP counter in PMU arch events testcase From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" To significantly reduce the PMU counter test's runtime, without sacrificing test coverage in the aggregate, test a random GP counter in the arch events testcase instead of testing every possible GP counter. Testing every PMC in every run of the test significantly increases the runtime of the test, without providing an equivalent increase in validation coverage, as the odds of a KVM having a bug that only affected a subset of counters and only when testing all other counters are extremely low. Opportunistically clean up kvm_random_u64_in_range() to eliminate unnecessary newlines. Signed-off-by: Sean Christopherson --- .../testing/selftests/kvm/include/test_util.h | 4 ++-- tools/testing/selftests/kvm/lib/test_util.c | 22 +++++++++++++++---- .../selftests/kvm/x86/pmu_counters_test.c | 18 +++++++-------- 3 files changed, 28 insertions(+), 16 deletions(-) diff --git a/tools/testing/selftests/kvm/include/test_util.h b/tools/testin= g/selftests/kvm/include/test_util.h index e8356ee54d7b..a6a3e1657895 100644 --- a/tools/testing/selftests/kvm/include/test_util.h +++ b/tools/testing/selftests/kvm/include/test_util.h @@ -135,8 +135,8 @@ static inline u64 kvm_random_u64(struct kvm_random_stat= e *state) return ((u64)kvm_random_u32(state) << 32) | kvm_random_u32(state); } =20 -u64 kvm_random_u64_in_range(struct kvm_random_state *state, u64 min, - u64 max); +u32 kvm_random_u32_in_range(struct kvm_random_state *state, u32 min, u32 m= ax); +u64 kvm_random_u64_in_range(struct kvm_random_state *state, u64 min, u64 m= ax); =20 enum vm_mem_backing_src_type { VM_MEM_SRC_ANONYMOUS, diff --git a/tools/testing/selftests/kvm/lib/test_util.c b/tools/testing/se= lftests/kvm/lib/test_util.c index 6b00ab11f3c0..4dff72f6bd34 100644 --- a/tools/testing/selftests/kvm/lib/test_util.c +++ b/tools/testing/selftests/kvm/lib/test_util.c @@ -43,12 +43,26 @@ u32 kvm_random_u32(struct kvm_random_state *state) return state->seed; } =20 +/* Returns a random u32 in the inclusive range [min, max] */ +u32 kvm_random_u32_in_range(struct kvm_random_state *state, u32 min, u32 m= ax) +{ + u32 value, range; + + TEST_ASSERT(min <=3D max, "PEBKAC, min =3D 0x%x, max =3D 0x%x", min, max); + + value =3D kvm_random_u32(state); + + range =3D max - min; + if (range =3D=3D UINT_MAX) + return value; + + return min + (value % (range + 1)); +} + /* Returns a random u64 in the inclusive range [min, max] */ -u64 kvm_random_u64_in_range(struct kvm_random_state *state, u64 min, - u64 max) +u64 kvm_random_u64_in_range(struct kvm_random_state *state, u64 min, u64 m= ax) { - u64 value; - u64 range; + u64 value, range; =20 TEST_ASSERT(min <=3D max, "PEBKAC, min =3D 0x%lx, max =3D 0x%lx", min, ma= x); =20 diff --git a/tools/testing/selftests/kvm/x86/pmu_counters_test.c b/tools/te= sting/selftests/kvm/x86/pmu_counters_test.c index dc6afac3aa91..8abf17cc9469 100644 --- a/tools/testing/selftests/kvm/x86/pmu_counters_test.c +++ b/tools/testing/selftests/kvm/x86/pmu_counters_test.c @@ -273,6 +273,7 @@ static void guest_test_arch_event(u8 idx) struct kvm_x86_pmu_feature gp_event, fixed_event; u32 base_pmc_msr; unsigned int i; + u64 eventsel; =20 /* The host side shouldn't invoke this without a guest PMU. */ GUEST_ASSERT(pmu_version); @@ -287,19 +288,16 @@ static void guest_test_arch_event(u8 idx) GUEST_ASSERT_EQ(idx, gp_event.f.bit); =20 GUEST_ASSERT(nr_gp_counters); + i =3D kvm_random_u32_in_range(&kvm_rng, 0, nr_gp_counters - 1); =20 - for (i =3D 0; i < nr_gp_counters; i++) { - u64 eventsel =3D ARCH_PERFMON_EVENTSEL_OS | - ARCH_PERFMON_EVENTSEL_ENABLE | - intel_pmu_arch_events[idx]; + eventsel =3D ARCH_PERFMON_EVENTSEL_OS | ARCH_PERFMON_EVENTSEL_ENABLE | + intel_pmu_arch_events[idx]; =20 - wrmsr(MSR_P6_EVNTSEL0 + i, 0); - if (guest_has_perf_global_ctrl) - wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, BIT_ULL(i)); + wrmsr(MSR_P6_EVNTSEL0 + i, 0); + if (guest_has_perf_global_ctrl) + wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, BIT_ULL(i)); =20 - __guest_test_arch_event(idx, i, base_pmc_msr + i, - MSR_P6_EVNTSEL0 + i, eventsel); - } + __guest_test_arch_event(idx, i, base_pmc_msr + i, MSR_P6_EVNTSEL0 + i, ev= entsel); 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AHgh+Ro8l+u2X1VHtwbGsZbDWLWi/zZhi7gsZYtaEyy+NMoQUlpuQ97NyntWRohPHFLwdrNwBTS73HVAYxSeU8A=@vger.kernel.org X-Gm-Message-State: AOJu0YxHyZnmxwDx2/TicTGu0Tg7hvAZ0LYH0N4m7CCr9UH836gQ+QPm ZDVetKyNXkWsc/D4x/n7yakSdnYVXNoipOlCbds8x3lmWUjHHwPeOoFb3xfnk0HPJ8DKeTBSQ/P +/XXO4Q== X-Received: from pgbl13.prod.google.com ([2002:a63:570d:0:b0:c88:868c:a1c2]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a00:44cd:b0:84e:216d:7e4e with SMTP id d2e1a72fcca58-84f2e031748mr1536968b3a.1.1785877251181; Tue, 04 Aug 2026 14:00:51 -0700 (PDT) Reply-To: Sean Christopherson Date: Tue, 4 Aug 2026 14:00:46 -0700 In-Reply-To: <20260804210046.3413149-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260804210046.3413149-1-seanjc@google.com> X-Mailer: git-send-email 2.55.0.571.g244d577d93-goog Message-ID: <20260804210046.3413149-3-seanjc@google.com> Subject: [PATCH v3 2/2] KVM: selftests: Create one VM with many vCPUs for each major PMU counters test From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" To reduce the runtime of the PMU counters test by an order of magnitude, create one VM per category of test (arch events, GP PMCs, fixed PMCs), with N vCPUs per VM, where 'N' is the number of testscases to run per category. The vast majority of the test's runtime is spent creating VMs, because while creating a VM only takes a few milliseconds, the total time adds up when creating hundreds of VMs. The only reason the test creates so many VMs is because KVM disallows changing the virtual PMU model after a vCPU runs, so rather than create an entirely new VM just to get a "fresh" vCPUs, simply use a different vCPU. On an Emerald Rapids host, this reduces the runtime from 75+ seconds to less than 6 seconds. Signed-off-by: Sean Christopherson --- .../selftests/kvm/x86/pmu_counters_test.c | 211 ++++++++++-------- 1 file changed, 121 insertions(+), 90 deletions(-) diff --git a/tools/testing/selftests/kvm/x86/pmu_counters_test.c b/tools/te= sting/selftests/kvm/x86/pmu_counters_test.c index 8abf17cc9469..08bfa82d7ab8 100644 --- a/tools/testing/selftests/kvm/x86/pmu_counters_test.c +++ b/tools/testing/selftests/kvm/x86/pmu_counters_test.c @@ -87,14 +87,18 @@ static struct kvm_intel_pmu_event intel_event_to_featur= e(u8 idx) return __intel_event_to_feature[idx]; } =20 -static struct kvm_vm *pmu_vm_create_with_one_vcpu(struct kvm_vcpu **vcpu, - void *guest_code, - u8 pmu_version, - u64 perf_capabilities) +static struct kvm_vm *pmu_vm_create_with_vcpus(u32 nr_vcpus, void *guest_c= ode, + u8 pmu_version, + u64 perf_capabilities, + struct kvm_vcpu **__vcpus[]) { + struct kvm_vcpu **vcpus =3D calloc(nr_vcpus, sizeof(*vcpus)); struct kvm_vm *vm; + int i; =20 - vm =3D vm_create_with_one_vcpu(vcpu, guest_code); + *__vcpus =3D vcpus; + + vm =3D vm_create_with_vcpus(nr_vcpus, guest_code, vcpus); sync_global_to_guest(vm, kvm_pmu_version); sync_global_to_guest(vm, hardware_pmu_arch_events); =20 @@ -102,13 +106,22 @@ static struct kvm_vm *pmu_vm_create_with_one_vcpu(str= uct kvm_vcpu **vcpu, * Set PERF_CAPABILITIES before PMU version as KVM disallows enabling * features via PERF_CAPABILITIES if the guest doesn't have a vPMU. */ - if (kvm_has_perf_caps) - vcpu_set_msr(*vcpu, MSR_IA32_PERF_CAPABILITIES, perf_capabilities); + for (i =3D 0; i < nr_vcpus; i++) { + if (kvm_has_perf_caps) + vcpu_set_msr(vcpus[i], MSR_IA32_PERF_CAPABILITIES, perf_capabilities); + + vcpu_set_cpuid_property(vcpus[i], X86_PROPERTY_PMU_VERSION, pmu_version); + } =20 - vcpu_set_cpuid_property(*vcpu, X86_PROPERTY_PMU_VERSION, pmu_version); return vm; } =20 +static void pmu_vm_free(struct kvm_vm *vm, struct kvm_vcpu **vcpus) +{ + kvm_vm_free(vm); + free(vcpus); +} + static void run_vcpu(struct kvm_vcpu *vcpu) { struct ucall uc; @@ -326,30 +339,72 @@ static void guest_test_arch_events(void) GUEST_DONE(); } =20 -static void test_arch_events(u8 pmu_version, u64 perf_capabilities, - u8 length, u32 unavailable_mask) +static void __test_arch_events(struct kvm_vcpu *vcpu, u64 perf_capabilitie= s, + u8 length, u32 unavailable_mask) { - struct kvm_vcpu *vcpu; - struct kvm_vm *vm; - - /* Testing arch events requires a vPMU (there are no negative tests). */ - if (!pmu_version) - return; - unavailable_mask &=3D GENMASK(X86_PROPERTY_PMU_EVENTS_MASK.hi_bit, X86_PROPERTY_PMU_EVENTS_MASK.lo_bit); =20 - vm =3D pmu_vm_create_with_one_vcpu(&vcpu, guest_test_arch_events, - pmu_version, perf_capabilities); - vcpu_set_cpuid_property(vcpu, X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH, length); vcpu_set_cpuid_property(vcpu, X86_PROPERTY_PMU_EVENTS_MASK, unavailable_mask); =20 run_vcpu(vcpu); +} =20 - kvm_vm_free(vm); +static void test_arch_events(u8 pmu_version, u64 perf_capabilities) +{ + struct kvm_vcpu **vcpus; + struct kvm_vm *vm; + int i =3D 0; + u32 k; + u8 j; + + /* + * To keep the total runtime reasonable, test only a handful of select, + * semi-arbitrary values for the mask of unavailable PMU events. Test + * 0 (all events available) and all ones (no events available) as well + * as alternating bit sequencues, e.g. to detect if KVM is checking the + * wrong bit(s). + */ + const u32 unavailable_masks[] =3D { + 0x0, + 0xffffffffu, + 0xaaaaaaaau, + 0x55555555u, + 0xf0f0f0f0u, + 0x0f0f0f0fu, + 0xa0a0a0a0u, + 0x0a0a0a0au, + 0x50505050u, + 0x05050505u, + }; + + pr_info("Testing arch events, PMU version %u, perf_caps =3D %lx\n", + pmu_version, perf_capabilities); + + /* Testing arch events requires a vPMU (there are no negative tests). */ + if (!pmu_version) + return; + + vm =3D pmu_vm_create_with_vcpus((NR_INTEL_ARCH_EVENTS + 2) * (ARRAY_SIZE(= unavailable_masks) - 1), + guest_test_arch_events, pmu_version, + perf_capabilities, &vcpus); + + /* + * Test single bits for all PMU version and lengths up the number of + * events +1 (to verify KVM doesn't do weird things if the guest length + * is greater than the host length). Explicitly test a mask of '0' and + * all ones i.e. all events being available and unavailable. + */ + for (j =3D 0; j <=3D NR_INTEL_ARCH_EVENTS + 1; j++) { + for (k =3D 1; k < ARRAY_SIZE(unavailable_masks); k++) + __test_arch_events(vcpus[i++], perf_capabilities, j, + unavailable_masks[k]); + } + + pmu_vm_free(vm, vcpus); } =20 /* @@ -493,21 +548,26 @@ static void guest_test_gp_counters(void) GUEST_DONE(); } =20 -static void test_gp_counters(u8 pmu_version, u64 perf_capabilities, - u8 nr_gp_counters) +static void test_gp_counters(u8 pmu_version, u64 perf_capabilities) { - struct kvm_vcpu *vcpu; + u8 nr_gp_counters =3D kvm_cpu_property(X86_PROPERTY_PMU_NR_GP_COUNTERS); + struct kvm_vcpu **vcpus; struct kvm_vm *vm; + u8 j; =20 - vm =3D pmu_vm_create_with_one_vcpu(&vcpu, guest_test_gp_counters, - pmu_version, perf_capabilities); + pr_info("Testing %u GP counters, PMU version %u, perf_caps =3D %lx\n", + nr_gp_counters, pmu_version, perf_capabilities); =20 - vcpu_set_cpuid_property(vcpu, X86_PROPERTY_PMU_NR_GP_COUNTERS, - nr_gp_counters); + vm =3D pmu_vm_create_with_vcpus(nr_gp_counters + 1, guest_test_gp_counter= s, + pmu_version, perf_capabilities, &vcpus); =20 - run_vcpu(vcpu); + for (j =3D 0; j <=3D nr_gp_counters; j++) { + vcpu_set_cpuid_property(vcpus[j], X86_PROPERTY_PMU_NR_GP_COUNTERS, j); =20 - kvm_vm_free(vm); + run_vcpu(vcpus[j]); + } + + pmu_vm_free(vm, vcpus); } =20 static void guest_test_fixed_counters(void) @@ -559,59 +619,53 @@ static void guest_test_fixed_counters(void) GUEST_DONE(); } =20 -static void test_fixed_counters(u8 pmu_version, u64 perf_capabilities, - u8 nr_fixed_counters, u32 supported_bitmask) +static void __test_fixed_counters(struct kvm_vcpu *vcpu, u8 nr_fixed_count= ers, + u32 supported_bitmask) { - struct kvm_vcpu *vcpu; - struct kvm_vm *vm; - - vm =3D pmu_vm_create_with_one_vcpu(&vcpu, guest_test_fixed_counters, - pmu_version, perf_capabilities); - vcpu_set_cpuid_property(vcpu, X86_PROPERTY_PMU_FIXED_COUNTERS_BITMASK, supported_bitmask); vcpu_set_cpuid_property(vcpu, X86_PROPERTY_PMU_NR_FIXED_COUNTERS, nr_fixed_counters); =20 run_vcpu(vcpu); - - kvm_vm_free(vm); } =20 -static void test_intel_counters(void) +static void test_fixed_counters(u8 pmu_version, u64 perf_capabilities) { u8 nr_fixed_counters =3D kvm_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNT= ERS); - u8 nr_gp_counters =3D kvm_cpu_property(X86_PROPERTY_PMU_NR_GP_COUNTERS); + struct kvm_vcpu **vcpus; + struct kvm_vm *vm; + int i =3D 0; + u32 k; + u8 j; + + pr_info("Testing %u fixed counters, PMU version %u, perf_caps =3D %lx\n", + nr_fixed_counters, pmu_version, perf_capabilities); + + + vm =3D pmu_vm_create_with_vcpus((nr_fixed_counters + 1) * BIT(nr_fixed_co= unters), + guest_test_fixed_counters, + pmu_version, perf_capabilities, &vcpus); + + for (j =3D 0; j <=3D nr_fixed_counters; j++) { + for (k =3D 0; k <=3D (BIT(nr_fixed_counters) - 1); k++) + __test_fixed_counters(vcpus[i++], j, k); + } + + pmu_vm_free(vm, vcpus); +} + +static void test_intel_counters(void) +{ u8 pmu_version =3D kvm_cpu_property(X86_PROPERTY_PMU_VERSION); unsigned int i; - u8 v, j; - u32 k; + u8 v; =20 const u64 perf_caps[] =3D { 0, PMU_CAP_FW_WRITES, }; =20 - /* - * To keep the total runtime reasonable, test only a handful of select, - * semi-arbitrary values for the mask of unavailable PMU events. Test - * 0 (all events available) and all ones (no events available) as well - * as alternating bit sequencues, e.g. to detect if KVM is checking the - * wrong bit(s). - */ - const u32 unavailable_masks[] =3D { - 0x0, - 0xffffffffu, - 0xaaaaaaaau, - 0x55555555u, - 0xf0f0f0f0u, - 0x0f0f0f0fu, - 0xa0a0a0a0u, - 0x0a0a0a0au, - 0x50505050u, - 0x05050505u, - }; - /* * Test up to PMU v5, which is the current maximum version defined by * Intel, i.e. is the last version that is guaranteed to be backwards @@ -647,32 +701,9 @@ static void test_intel_counters(void) if (!kvm_has_perf_caps && perf_caps[i]) continue; =20 - pr_info("Testing arch events, PMU version %u, perf_caps =3D %lx\n", - v, perf_caps[i]); - - /* - * Test single bits for all PMU version and lengths up - * the number of events +1 (to verify KVM doesn't do - * weird things if the guest length is greater than the - * host length). Explicitly test a mask of '0' and all - * ones i.e. all events being available and unavailable. - */ - for (j =3D 0; j <=3D NR_INTEL_ARCH_EVENTS + 1; j++) { - for (k =3D 1; k < ARRAY_SIZE(unavailable_masks); k++) - test_arch_events(v, perf_caps[i], j, unavailable_masks[k]); - } - - pr_info("Testing GP counters, PMU version %u, perf_caps =3D %lx\n", - v, perf_caps[i]); - for (j =3D 0; j <=3D nr_gp_counters; j++) - test_gp_counters(v, perf_caps[i], j); - - pr_info("Testing fixed counters, PMU version %u, perf_caps =3D %lx\n", - v, perf_caps[i]); - for (j =3D 0; j <=3D nr_fixed_counters; j++) { - for (k =3D 0; k <=3D (BIT(nr_fixed_counters) - 1); k++) - test_fixed_counters(v, perf_caps[i], j, k); - } + test_arch_events(v, perf_caps[i]); + test_gp_counters(v, perf_caps[i]); + test_fixed_counters(v, perf_caps[i]); } } } --=20 2.55.0.571.g244d577d93-goog