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charset="utf-8" Split the Grace CPER processing into a separate decode step and a print step so the parser can be exercised by KUnit without a live ACPI device. Introduce ghes-nvidia.h to hold shared types that the Vera decoder added in the next commit will also reference. Parse the Grace wire payload with __packed structs and get_unaligned_le*() for multi-byte fields, matching the Vera decoder style. Reject nvidia_ghes_grace_reg_pair() calls with a non-zero register count and a NULL grace_regs pointer, and rate-limit Grace decoder diagnostics. Signed-off-by: Kai-Heng Feng --- v3: - Use __packed + get_unaligned_le*() for Grace multi-byte fields, including register pairs (Shuai Xue). - Keep __counted_by / struct_size; reject NULL grace_regs when number_regs !=3D 0; document the helper contract. - Rate-limit Grace decoder and notify error messages. v2: - No change. --- MAINTAINERS | 2 +- drivers/acpi/apei/ghes-nvidia.c | 160 ++++++++++++++++++++++---------- drivers/acpi/apei/ghes-nvidia.h | 50 ++++++++++ 3 files changed, 160 insertions(+), 52 deletions(-) create mode 100644 drivers/acpi/apei/ghes-nvidia.h diff --git a/MAINTAINERS b/MAINTAINERS index 5114e6db7307..aa9c2ae58ac5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19348,7 +19348,7 @@ NVIDIA GHES VENDOR CPER RECORD HANDLER M: Kai-Heng Feng L: linux-acpi@vger.kernel.org S: Maintained -F: drivers/acpi/apei/ghes-nvidia.c +F: drivers/acpi/apei/ghes-nvidia* =20 NVIDIA VRS RTC DRIVER M: Shubhi Garg diff --git a/drivers/acpi/apei/ghes-nvidia.c b/drivers/acpi/apei/ghes-nvidi= a.c index 597275d81de8..e7cc912344fd 100644 --- a/drivers/acpi/apei/ghes-nvidia.c +++ b/drivers/acpi/apei/ghes-nvidia.c @@ -9,13 +9,18 @@ #include #include #include +#include #include #include =20 -static const guid_t nvidia_sec_guid =3D +#include +#include "ghes-nvidia.h" + +static const guid_t nvidia_grace_sec_guid =3D GUID_INIT(0x6d5244f2, 0x2712, 0x11ec, 0xbe, 0xa7, 0xcb, 0x3f, 0xdb, 0x95, 0xc7, 0x86); =20 +/* Grace CPER section wire layout (header without flexible register array)= . */ struct cper_sec_nvidia { char signature[16]; __le16 error_type; @@ -25,84 +30,137 @@ struct cper_sec_nvidia { u8 number_regs; u8 reserved; __le64 instance_base; - struct { - __le64 addr; - __le64 val; - } regs[] __counted_by(number_regs); -}; + struct nvidia_ghes_grace_reg regs[] __counted_by(number_regs); +} __packed; + +static_assert(sizeof(struct cper_sec_nvidia) =3D=3D 32); =20 struct nvidia_ghes_private { struct notifier_block nb; struct device *dev; }; =20 -static void nvidia_ghes_print_error(struct device *dev, - const struct cper_sec_nvidia *nvidia_err, - size_t error_data_length, bool fatal) +VISIBLE_IF_KUNIT +int nvidia_ghes_decode_grace(struct device *dev, const void *buf, + size_t len, + struct nvidia_ghes_decoded *decoded) { - const char *level =3D fatal ? KERN_ERR : KERN_INFO; + const struct cper_sec_nvidia *nvidia_err =3D buf; size_t min_size; + u8 number_regs; + + if (!buf || !decoded) + return -EINVAL; + if (len < sizeof(*nvidia_err)) { + if (dev) + dev_err_ratelimited(dev, "Section too small (%zu < %zu)\n", + len, sizeof(*nvidia_err)); + return -ENODATA; + } =20 - dev_printk(level, dev, "signature: %.16s\n", nvidia_err->signature); - dev_printk(level, dev, "error_type: %u\n", le16_to_cpu(nvidia_err->error_= type)); - dev_printk(level, dev, "error_instance: %u\n", le16_to_cpu(nvidia_err->er= ror_instance)); - dev_printk(level, dev, "severity: %u\n", nvidia_err->severity); - dev_printk(level, dev, "socket: %u\n", nvidia_err->socket); - dev_printk(level, dev, "number_regs: %u\n", nvidia_err->number_regs); - dev_printk(level, dev, "instance_base: 0x%016llx\n", - le64_to_cpu(nvidia_err->instance_base)); - - if (nvidia_err->number_regs =3D=3D 0) - return; - - /* - * Validate that all registers fit within error_data_length. - * Each register pair is two little-endian u64s. - */ - min_size =3D struct_size(nvidia_err, regs, nvidia_err->number_regs); - if (error_data_length < min_size) { - dev_err(dev, "Invalid number_regs %u (section size %zu, need %zu)\n", - nvidia_err->number_regs, error_data_length, min_size); - return; + number_regs =3D nvidia_err->number_regs; + min_size =3D struct_size(nvidia_err, regs, number_regs); + if (len < min_size) { + if (dev) + dev_err_ratelimited(dev, + "Invalid number_regs %u (section size %zu, need %zu)\n", + number_regs, len, min_size); + return -ENODATA; } =20 - for (int i =3D 0; i < nvidia_err->number_regs; i++) + memset(decoded, 0, sizeof(*decoded)); + decoded->format =3D NVIDIA_GHES_FORMAT_GRACE; + memcpy(decoded->signature, nvidia_err->signature, sizeof(nvidia_err->sign= ature)); + decoded->signature[sizeof(nvidia_err->signature)] =3D '\0'; + decoded->error_type =3D get_unaligned_le16(&nvidia_err->error_type); + decoded->error_instance =3D get_unaligned_le16(&nvidia_err->error_instanc= e); + decoded->severity =3D nvidia_err->severity; + decoded->socket =3D nvidia_err->socket; + decoded->number_regs =3D number_regs; + decoded->instance_base =3D get_unaligned_le64(&nvidia_err->instance_base); + if (number_regs) + decoded->grace_regs =3D nvidia_err->regs; + + return 0; +} +EXPORT_SYMBOL_IF_KUNIT(nvidia_ghes_decode_grace); + +VISIBLE_IF_KUNIT +int nvidia_ghes_grace_reg_pair(const struct nvidia_ghes_decoded *decoded, + unsigned int index, u64 *addr, u64 *val) +{ + const struct nvidia_ghes_grace_reg *regs; + + if (!decoded || decoded->format !=3D NVIDIA_GHES_FORMAT_GRACE || !addr ||= !val) + return -EINVAL; + if (decoded->number_regs && !decoded->grace_regs) + return -EINVAL; + if (index >=3D decoded->number_regs) + return -ERANGE; + + regs =3D decoded->grace_regs; + *addr =3D get_unaligned_le64(®s[index].addr); + *val =3D get_unaligned_le64(®s[index].val); + + return 0; +} +EXPORT_SYMBOL_IF_KUNIT(nvidia_ghes_grace_reg_pair); + +static void nvidia_ghes_print_grace(struct device *dev, + const struct nvidia_ghes_decoded *decoded, + bool fatal) +{ + const char *level =3D fatal ? KERN_ERR : KERN_INFO; + u64 addr, val; + + dev_printk(level, dev, "signature: %s\n", decoded->signature); + dev_printk(level, dev, "error_type: %u\n", decoded->error_type); + dev_printk(level, dev, "error_instance: %u\n", decoded->error_instance); + dev_printk(level, dev, "severity: %u\n", decoded->severity); + dev_printk(level, dev, "socket: %u\n", decoded->socket); + dev_printk(level, dev, "number_regs: %u\n", decoded->number_regs); + dev_printk(level, dev, "instance_base: 0x%016llx\n", decoded->instance_ba= se); + + for (int i =3D 0; i < decoded->number_regs; i++) { + if (nvidia_ghes_grace_reg_pair(decoded, i, &addr, &val)) + break; dev_printk(level, dev, "register[%d]: address=3D0x%016llx value=3D0x%016= llx\n", - i, le64_to_cpu(nvidia_err->regs[i].addr), - le64_to_cpu(nvidia_err->regs[i].val)); + i, addr, val); + } } =20 static int nvidia_ghes_notify(struct notifier_block *nb, unsigned long event, void *data) { struct acpi_hest_generic_data *gdata =3D data; + struct nvidia_ghes_decoded decoded =3D {}; struct nvidia_ghes_private *priv; - const struct cper_sec_nvidia *nvidia_err; + const void *payload; guid_t sec_guid; + u32 len; + int ret; + bool fatal; =20 import_guid(&sec_guid, gdata->section_type); - if (!guid_equal(&sec_guid, &nvidia_sec_guid)) + if (!guid_equal(&sec_guid, &nvidia_grace_sec_guid)) return NOTIFY_DONE; =20 priv =3D container_of(nb, struct nvidia_ghes_private, nb); - - if (acpi_hest_get_error_length(gdata) < sizeof(*nvidia_err)) { - dev_err(priv->dev, "Section too small (%d < %zu)\n", - acpi_hest_get_error_length(gdata), sizeof(*nvidia_err)); + len =3D acpi_hest_get_error_length(gdata); + payload =3D acpi_hest_get_payload(gdata); + fatal =3D event >=3D GHES_SEV_RECOVERABLE; + + ret =3D nvidia_ghes_decode_grace(priv->dev, payload, len, &decoded); + if (ret) { + dev_err_ratelimited(priv->dev, + "Malformed NVIDIA CPER section, error_data_length: %u, ret: %d\n", + len, ret); return NOTIFY_OK; } =20 - nvidia_err =3D acpi_hest_get_payload(gdata); - - if (event >=3D GHES_SEV_RECOVERABLE) - dev_err(priv->dev, "NVIDIA CPER section, error_data_length: %u\n", - acpi_hest_get_error_length(gdata)); - else - dev_info(priv->dev, "NVIDIA CPER section, error_data_length: %u\n", - acpi_hest_get_error_length(gdata)); - - nvidia_ghes_print_error(priv->dev, nvidia_err, acpi_hest_get_error_length= (gdata), - event >=3D GHES_SEV_RECOVERABLE); + dev_printk(fatal ? KERN_ERR : KERN_INFO, priv->dev, + "NVIDIA CPER section, error_data_length: %u\n", len); + nvidia_ghes_print_grace(priv->dev, &decoded, fatal); =20 return NOTIFY_OK; } diff --git a/drivers/acpi/apei/ghes-nvidia.h b/drivers/acpi/apei/ghes-nvidi= a.h new file mode 100644 index 000000000000..965abe3d5c49 --- /dev/null +++ b/drivers/acpi/apei/ghes-nvidia.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef GHES_NVIDIA_H +#define GHES_NVIDIA_H + +#include +#include +#include + +struct device; + +enum nvidia_ghes_format { + NVIDIA_GHES_FORMAT_UNKNOWN, + NVIDIA_GHES_FORMAT_GRACE, +}; + +struct nvidia_ghes_grace_reg { + __le64 addr; + __le64 val; +} __packed; + +struct nvidia_ghes_decoded { + enum nvidia_ghes_format format; + char signature[17]; + u16 error_type; + u16 error_instance; + u8 severity; + u8 socket; + u8 number_regs; + u64 instance_base; + const struct nvidia_ghes_grace_reg *grace_regs; +}; + +/** + * nvidia_ghes_grace_reg_pair() - Read one Grace register address/value pa= ir + * @decoded: Decoded Grace section; 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Received: from SJ0PR12MB6733.namprd12.prod.outlook.com (2603:10b6:a03:477::9) by CHAPR12MB999224.namprd12.prod.outlook.com (2603:10b6:610:302::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.292.15; Tue, 4 Aug 2026 12:23:34 +0000 Received: from SJ0PR12MB6733.namprd12.prod.outlook.com ([fe80::f00d:2f6b:6f9b:8f97]) by SJ0PR12MB6733.namprd12.prod.outlook.com ([fe80::f00d:2f6b:6f9b:8f97%6]) with mapi id 15.21.0270.017; Tue, 4 Aug 2026 12:23:34 +0000 From: Kai-Heng Feng To: rafael@kernel.org, linux-acpi@vger.kernel.org Cc: tony.luck@intel.com, bp@alien8.de, guohanjun@huawei.com, mchehab@kernel.org, xueshuai@linux.alibaba.com, lenb@kernel.org, kees@kernel.org, gustavoars@kernel.org, linux-hardening@vger.kernel.org, linux-kernel@vger.kernel.org, Kai-Heng Feng Subject: [PATCH v3 2/3] ACPI: APEI: GHES: Add NVIDIA Vera decoder Date: Tue, 4 Aug 2026 20:23:16 +0800 Message-ID: <20260804122318.88193-3-kaihengf@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260804122318.88193-1-kaihengf@nvidia.com> References: <20260724122054.36162-1-kaihengf@nvidia.com> <20260804122318.88193-1-kaihengf@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SI3PR02CA0006.apcprd02.prod.outlook.com (2603:1096:4:295::13) To SJ0PR12MB6733.namprd12.prod.outlook.com (2603:10b6:a03:477::9) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ0PR12MB6733:EE_|CHAPR12MB999224:EE_ X-MS-Office365-Filtering-Correlation-Id: 4a8ad878-46fb-4bc0-0364-08def22333cc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|376014|7416014|366016|1800799024|10067099003|11063799006|56012099006|18002099003|22082099003|3023799007|4143699003|6133799003; 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charset="utf-8" Vera is the next-generation NVIDIA server SoC. Its CPER section uses a different GUID and binary layout from Grace, so firmware-reported hardware errors need a dedicated decoder. Follow the NVIDIA event-section CtxSize contract. Require CtxSize to be 16-byte aligned, validate that each context covers its header and data, and advance by CtxSize so alignment padding is skipped. Preserve the legacy format-0 header-only CtxSize used by existing opaque firmware records. Assert all three Vera wire-header sizes and keep the decoded object on the stack. Print at most 32 key/value entries across the entire section, report omitted entries, and retain successfully decoded contexts when a later context is malformed. Keep detailed fatal decode errors unratelimited while rate-limiting those diagnostics for non-fatal records. Signed-off-by: Kai-Heng Feng --- v3: - Validate and traverse CtxSize according to the firmware contract and libcper implementation; accept aligned padding. - Preserve the legacy format-0 header-only CtxSize encoding. - Add wire-layout assertions and use Vera key/value terminology. - Bound entry output to 32 entries per section and report omissions. - Print partial Vera contexts when decode fails mid-section. - Keep fatal diagnostics unratelimited and non-fatal diagnostics ratelimited. --- drivers/acpi/apei/Kconfig | 4 +- drivers/acpi/apei/ghes-nvidia.c | 665 +++++++++++++++++++++++++++++++- drivers/acpi/apei/ghes-nvidia.h | 69 +++- 3 files changed, 710 insertions(+), 28 deletions(-) diff --git a/drivers/acpi/apei/Kconfig b/drivers/acpi/apei/Kconfig index 428458c623f0..2dcea74c1677 100644 --- a/drivers/acpi/apei/Kconfig +++ b/drivers/acpi/apei/Kconfig @@ -80,8 +80,8 @@ config ACPI_APEI_GHES_NVIDIA help Support for decoding NVIDIA-specific CPER sections delivered via the APEI GHES vendor record notifier chain. Registers a handler - for the NVIDIA section GUID and logs error signatures, severity, - socket, and diagnostic register address-value pairs. + for the NVIDIA Grace and Vera section GUIDs and logs decoded + metadata and per-context key/value entries (bounded). =20 Enable on NVIDIA server platforms (e.g. DGX, HGX) that expose ACPI device NVDA2012 in their firmware tables. diff --git a/drivers/acpi/apei/ghes-nvidia.c b/drivers/acpi/apei/ghes-nvidi= a.c index e7cc912344fd..adf298dc722b 100644 --- a/drivers/acpi/apei/ghes-nvidia.c +++ b/drivers/acpi/apei/ghes-nvidia.c @@ -6,20 +6,54 @@ */ =20 #include +#include +#include #include +#include #include #include #include #include +#include #include =20 -#include #include "ghes-nvidia.h" =20 +#define NVIDIA_GHES_VERA_VERSION 1 +#define NVIDIA_GHES_VERA_CPU_INFO_MAJOR 0 +/* Cap section-wide entry log lines so a large dump cannot flood the conso= le. */ +#define NVIDIA_GHES_MAX_PRINT_ENTRIES 32 +#define NVIDIA_GHES_MAX_PRINT_CONTEXTS 16 + +static __printf(3, 4) void nvidia_ghes_decode_err(struct device *dev, + bool fatal, const char *fmt, ...) +{ + struct va_format vaf; + va_list args; + + if (!dev) + return; + + va_start(args, fmt); + vaf.fmt =3D fmt; + vaf.va =3D &args; + + if (fatal) + dev_err(dev, "%pV", &vaf); + else + dev_err_ratelimited(dev, "%pV", &vaf); + + va_end(args); +} + static const guid_t nvidia_grace_sec_guid =3D GUID_INIT(0x6d5244f2, 0x2712, 0x11ec, 0xbe, 0xa7, 0xcb, 0x3f, 0xdb, 0x95, 0xc7, 0x86); =20 +static const guid_t nvidia_vera_sec_guid =3D + GUID_INIT(0x9068e568, 0x6ca0, 0x11f0, + 0xae, 0xaf, 0x15, 0x93, 0x43, 0x59, 0x1e, 0xac); + /* Grace CPER section wire layout (header without flexible register array)= . */ struct cper_sec_nvidia { char signature[16]; @@ -35,15 +69,61 @@ struct cper_sec_nvidia { =20 static_assert(sizeof(struct cper_sec_nvidia) =3D=3D 32); =20 +struct cper_sec_nvidia_vera_event { + u8 version; + u8 event_context_count; + u8 source_device_type; + u8 reserved; + __le16 event_type; + __le16 event_sub_type; + __le64 event_link_id; + char source_module_signature[16]; +} __packed; + +static_assert(sizeof(struct cper_sec_nvidia_vera_event) =3D=3D 32); + +struct cper_sec_nvidia_vera_cpu_info { + __le16 info_version; + u8 info_size; + u8 socket_number; + __le32 architecture; + u8 chip_serial_number[16]; + __le64 instance_base; +} __packed; + +static_assert(sizeof(struct cper_sec_nvidia_vera_cpu_info) =3D=3D 32); + +struct cper_sec_nvidia_vera_context { + __le32 context_size; + __le16 context_version; + __le16 reserved; + __le16 data_format_type; + __le16 data_format_version; + __le32 data_size; +} __packed; + +static_assert(sizeof(struct cper_sec_nvidia_vera_context) =3D=3D 16); + struct nvidia_ghes_private { struct notifier_block nb; struct device *dev; }; =20 VISIBLE_IF_KUNIT -int nvidia_ghes_decode_grace(struct device *dev, const void *buf, - size_t len, - struct nvidia_ghes_decoded *decoded) +enum nvidia_ghes_format nvidia_ghes_format_from_guid(const guid_t *guid) +{ + if (guid_equal(guid, &nvidia_grace_sec_guid)) + return NVIDIA_GHES_FORMAT_GRACE; + if (guid_equal(guid, &nvidia_vera_sec_guid)) + return NVIDIA_GHES_FORMAT_VERA; + return NVIDIA_GHES_FORMAT_UNKNOWN; +} +EXPORT_SYMBOL_IF_KUNIT(nvidia_ghes_format_from_guid); + +static int __nvidia_ghes_decode_grace(struct device *dev, const void *buf, + size_t len, + struct nvidia_ghes_decoded *decoded, + bool fatal) { const struct cper_sec_nvidia *nvidia_err =3D buf; size_t min_size; @@ -52,19 +132,18 @@ int nvidia_ghes_decode_grace(struct device *dev, const= void *buf, if (!buf || !decoded) return -EINVAL; if (len < sizeof(*nvidia_err)) { - if (dev) - dev_err_ratelimited(dev, "Section too small (%zu < %zu)\n", - len, sizeof(*nvidia_err)); + nvidia_ghes_decode_err(dev, fatal, + "Section too small (%zu < %zu)\n", + len, sizeof(*nvidia_err)); return -ENODATA; } =20 number_regs =3D nvidia_err->number_regs; min_size =3D struct_size(nvidia_err, regs, number_regs); if (len < min_size) { - if (dev) - dev_err_ratelimited(dev, - "Invalid number_regs %u (section size %zu, need %zu)\n", - number_regs, len, min_size); + nvidia_ghes_decode_err(dev, fatal, + "Invalid number_regs %u (section size %zu, need %zu)\n", + number_regs, len, min_size); return -ENODATA; } =20 @@ -83,6 +162,14 @@ int nvidia_ghes_decode_grace(struct device *dev, const = void *buf, =20 return 0; } + +VISIBLE_IF_KUNIT +__maybe_unused int nvidia_ghes_decode_grace(struct device *dev, const void= *buf, + size_t len, + struct nvidia_ghes_decoded *decoded) +{ + return __nvidia_ghes_decode_grace(dev, buf, len, decoded, false); +} EXPORT_SYMBOL_IF_KUNIT(nvidia_ghes_decode_grace); =20 VISIBLE_IF_KUNIT @@ -106,6 +193,361 @@ int nvidia_ghes_grace_reg_pair(const struct nvidia_gh= es_decoded *decoded, } EXPORT_SYMBOL_IF_KUNIT(nvidia_ghes_grace_reg_pair); =20 +static int nvidia_ghes_vera_validate_context_data(u16 data_format_type, + u32 data_size) +{ + switch (data_format_type) { + case 0: + return 0; + case 1: + return data_size % 16 ? -EINVAL : 0; + case 2: + case 3: + return data_size % 8 ? -EINVAL : 0; + case 4: + return data_size % 4 ? -EINVAL : 0; + default: + return -EOPNOTSUPP; + } +} + +static void +__nvidia_ghes_vera_cursor_init(const struct nvidia_ghes_decoded *decoded, + struct nvidia_ghes_vera_cursor *cursor, u8 count) +{ + *cursor =3D (struct nvidia_ghes_vera_cursor) { + .pos =3D decoded->vera_contexts, + .remaining =3D decoded->vera_contexts_len, + .contexts_left =3D count, + }; +} + +VISIBLE_IF_KUNIT +void nvidia_ghes_vera_cursor_init(const struct nvidia_ghes_decoded *decode= d, + struct nvidia_ghes_vera_cursor *cursor) +{ + if (!cursor) + return; + + memset(cursor, 0, sizeof(*cursor)); + if (!decoded || decoded->format !=3D NVIDIA_GHES_FORMAT_VERA) + return; + + __nvidia_ghes_vera_cursor_init(decoded, cursor, + decoded->valid_context_count); +} +EXPORT_SYMBOL_IF_KUNIT(nvidia_ghes_vera_cursor_init); + +VISIBLE_IF_KUNIT +int nvidia_ghes_vera_cursor_next(struct nvidia_ghes_vera_cursor *cursor, + struct nvidia_ghes_vera_context *ctx) +{ + const struct cper_sec_nvidia_vera_context *wire; + size_t data_end_advance; + size_t advance; + u32 context_size; + u32 data_size; + u16 data_format_type; + int ret; + + if (!cursor || !ctx) + return -EINVAL; + if (!cursor->contexts_left) + return 0; + if (!cursor->pos || cursor->remaining < sizeof(*wire)) + return -ENODATA; + + wire =3D (const void *)cursor->pos; + context_size =3D get_unaligned_le32(&wire->context_size); + data_format_type =3D get_unaligned_le16(&wire->data_format_type); + data_size =3D get_unaligned_le32(&wire->data_size); + + if (context_size < sizeof(*wire) || !IS_ALIGNED(context_size, 16)) + return -EINVAL; + + ret =3D nvidia_ghes_vera_validate_context_data(data_format_type, data_siz= e); + if (ret) + return ret; + if (check_add_overflow((size_t)data_size, sizeof(*wire), + &data_end_advance)) + return -EOVERFLOW; + if (data_end_advance > cursor->remaining) + return -ENODATA; + + /* + * CtxSize covers the header, data, and alignment padding. Older opaque + * records used a header-only CtxSize, so advance over their data directl= y. + */ + if (data_format_type =3D=3D 0 && context_size =3D=3D sizeof(*wire)) { + advance =3D data_end_advance; + } else { + if (data_end_advance > context_size) + return -EINVAL; + if (context_size > cursor->remaining) + return -ENODATA; + advance =3D context_size; + } + + *ctx =3D (struct nvidia_ghes_vera_context) { + .context_size =3D context_size, + .context_version =3D get_unaligned_le16(&wire->context_version), + .data_format_type =3D data_format_type, + .data_format_version =3D get_unaligned_le16(&wire->data_format_version), + .data_size =3D data_size, + .data =3D cursor->pos + sizeof(*wire), + }; + cursor->pos +=3D advance; + cursor->remaining -=3D advance; + cursor->contexts_left--; + + return 1; +} +EXPORT_SYMBOL_IF_KUNIT(nvidia_ghes_vera_cursor_next); + +static int __nvidia_ghes_decode_vera(struct device *dev, const void *buf, + size_t len, + struct nvidia_ghes_decoded *decoded, + bool fatal) +{ + const struct cper_sec_nvidia_vera_event *event =3D buf; + const struct cper_sec_nvidia_vera_cpu_info *cpu_info; + struct nvidia_ghes_vera_cursor cursor; + struct nvidia_ghes_vera_context context; + const u8 *bytes =3D buf; + size_t offset; + u16 info_version; + int ret; + + if (!buf || !decoded) + return -EINVAL; + if (len < sizeof(*event)) { + nvidia_ghes_decode_err(dev, fatal, + "Vera event header truncated (%zu < %zu)\n", + len, sizeof(*event)); + return -ENODATA; + } + if (event->version !=3D NVIDIA_GHES_VERA_VERSION) + return -EOPNOTSUPP; + if (event->source_device_type !=3D 0) + return -EOPNOTSUPP; + + offset =3D sizeof(*event); + if (len - offset < sizeof(*cpu_info)) { + nvidia_ghes_decode_err(dev, fatal, + "Vera CPU info truncated (%zu < %zu)\n", + len - offset, sizeof(*cpu_info)); + return -ENODATA; + } + + cpu_info =3D (const void *)(bytes + offset); + info_version =3D get_unaligned_le16(&cpu_info->info_version); + if ((info_version >> 8) !=3D NVIDIA_GHES_VERA_CPU_INFO_MAJOR) + return -EOPNOTSUPP; + if (cpu_info->info_size < sizeof(*cpu_info)) { + nvidia_ghes_decode_err(dev, fatal, + "Vera CPU info size %u smaller than header %zu\n", + cpu_info->info_size, sizeof(*cpu_info)); + return -EINVAL; + } + if (len - offset < cpu_info->info_size) { + nvidia_ghes_decode_err(dev, fatal, + "Vera CPU info extends past section (%u > %zu)\n", + cpu_info->info_size, len - offset); + return -ENODATA; + } + + offset +=3D cpu_info->info_size; + + memset(decoded, 0, sizeof(*decoded)); + decoded->format =3D NVIDIA_GHES_FORMAT_VERA; + memcpy(decoded->signature, event->source_module_signature, + sizeof(event->source_module_signature)); + decoded->signature[sizeof(event->source_module_signature)] =3D '\0'; + decoded->event_context_count =3D event->event_context_count; + decoded->source_device_type =3D event->source_device_type; + decoded->event_type =3D get_unaligned_le16(&event->event_type); + decoded->event_sub_type =3D get_unaligned_le16(&event->event_sub_type); + decoded->event_link_id =3D get_unaligned_le64(&event->event_link_id); + decoded->socket =3D cpu_info->socket_number; + decoded->architecture =3D get_unaligned_le32(&cpu_info->architecture); + memcpy(decoded->chip_serial_number, cpu_info->chip_serial_number, + sizeof(cpu_info->chip_serial_number)); + decoded->instance_base =3D get_unaligned_le64(&cpu_info->instance_base); + decoded->vera_contexts =3D bytes + offset; + decoded->vera_contexts_len =3D len - offset; + __nvidia_ghes_vera_cursor_init(decoded, &cursor, + event->event_context_count); + while ((ret =3D nvidia_ghes_vera_cursor_next(&cursor, &context)) > 0) + decoded->valid_context_count++; + if (ret < 0) { + nvidia_ghes_decode_err(dev, fatal, + "Vera context[%u] is malformed (ret=3D%d)\n", + decoded->valid_context_count, ret); + return ret; + } + + if (cursor.remaining && dev) + dev_dbg(dev, + "Vera section has %zu trailing byte(s) after %u context(s)\n", + cursor.remaining, decoded->valid_context_count); + + return 0; +} + +VISIBLE_IF_KUNIT +__maybe_unused int nvidia_ghes_decode_vera(struct device *dev, const void = *buf, + size_t len, + struct nvidia_ghes_decoded *decoded) +{ + return __nvidia_ghes_decode_vera(dev, buf, len, decoded, false); +} +EXPORT_SYMBOL_IF_KUNIT(nvidia_ghes_decode_vera); + +VISIBLE_IF_KUNIT +int nvidia_ghes_vera_context_entry_count(const struct nvidia_ghes_vera_con= text *ctx) +{ + if (!ctx) + return -EINVAL; + if (ctx->data_size && !ctx->data) + return -EINVAL; + if (ctx->data_size > INT_MAX) + return -EOVERFLOW; + + switch (ctx->data_format_type) { + case 0: + return 0; + case 1: + return ctx->data_size / 16; + case 2: + return ctx->data_size / 8; + case 3: + return ctx->data_size / 8; + case 4: + return ctx->data_size / 4; + default: + return -EINVAL; + } +} +EXPORT_SYMBOL_IF_KUNIT(nvidia_ghes_vera_context_entry_count); + +VISIBLE_IF_KUNIT +int nvidia_ghes_vera_context_u64_pair(const struct nvidia_ghes_vera_contex= t *ctx, + unsigned int index, u64 *key, u64 *val) +{ + int count; + + if (!ctx || !key || !val || ctx->data_format_type !=3D 1) + return -EINVAL; + + count =3D nvidia_ghes_vera_context_entry_count(ctx); + if (count < 0) + return count; + if (index >=3D count) + return -ERANGE; + + *key =3D get_unaligned_le64(ctx->data + index * 16); + *val =3D get_unaligned_le64(ctx->data + index * 16 + 8); + + return 0; +} +EXPORT_SYMBOL_IF_KUNIT(nvidia_ghes_vera_context_u64_pair); + +VISIBLE_IF_KUNIT +int nvidia_ghes_vera_context_u32_pair(const struct nvidia_ghes_vera_contex= t *ctx, + unsigned int index, u32 *key, u32 *val) +{ + int count; + + if (!ctx || !key || !val || ctx->data_format_type !=3D 2) + return -EINVAL; + + count =3D nvidia_ghes_vera_context_entry_count(ctx); + if (count < 0) + return count; + if (index >=3D count) + return -ERANGE; + + *key =3D get_unaligned_le32(ctx->data + index * 8); + *val =3D get_unaligned_le32(ctx->data + index * 8 + 4); + + return 0; +} +EXPORT_SYMBOL_IF_KUNIT(nvidia_ghes_vera_context_u32_pair); + +VISIBLE_IF_KUNIT +int nvidia_ghes_vera_context_u64_value(const struct nvidia_ghes_vera_conte= xt *ctx, + unsigned int index, u64 *val) +{ + int count; + + if (!ctx || !val || ctx->data_format_type !=3D 3) + return -EINVAL; + + count =3D nvidia_ghes_vera_context_entry_count(ctx); + if (count < 0) + return count; + if (index >=3D count) + return -ERANGE; + + *val =3D get_unaligned_le64(ctx->data + index * 8); + + return 0; +} +EXPORT_SYMBOL_IF_KUNIT(nvidia_ghes_vera_context_u64_value); + +VISIBLE_IF_KUNIT +int nvidia_ghes_vera_context_u32_value(const struct nvidia_ghes_vera_conte= xt *ctx, + unsigned int index, u32 *val) +{ + int count; + + if (!ctx || !val || ctx->data_format_type !=3D 4) + return -EINVAL; + + count =3D nvidia_ghes_vera_context_entry_count(ctx); + if (count < 0) + return count; + if (index >=3D count) + return -ERANGE; + + *val =3D get_unaligned_le32(ctx->data + index * 4); + + return 0; +} +EXPORT_SYMBOL_IF_KUNIT(nvidia_ghes_vera_context_u32_value); + +VISIBLE_IF_KUNIT +int nvidia_ghes_vera_context_print_count(const struct nvidia_ghes_vera_con= text *ctx, + unsigned int *remaining) +{ + int entries; + int count; + + if (!remaining) + return -EINVAL; + + entries =3D nvidia_ghes_vera_context_entry_count(ctx); + if (entries < 0) + return entries; + + count =3D min_t(unsigned int, entries, *remaining); + *remaining -=3D count; + + return count; +} +EXPORT_SYMBOL_IF_KUNIT(nvidia_ghes_vera_context_print_count); + +VISIBLE_IF_KUNIT +int nvidia_ghes_vera_print_context_count(const struct nvidia_ghes_decoded = *decoded) +{ + if (!decoded || decoded->format !=3D NVIDIA_GHES_FORMAT_VERA) + return -EINVAL; + + return min_t(unsigned int, decoded->valid_context_count, + NVIDIA_GHES_MAX_PRINT_CONTEXTS); +} +EXPORT_SYMBOL_IF_KUNIT(nvidia_ghes_vera_print_context_count); + static void nvidia_ghes_print_grace(struct device *dev, const struct nvidia_ghes_decoded *decoded, bool fatal) @@ -113,13 +555,16 @@ static void nvidia_ghes_print_grace(struct device *de= v, const char *level =3D fatal ? KERN_ERR : KERN_INFO; u64 addr, val; =20 - dev_printk(level, dev, "signature: %s\n", decoded->signature); + dev_printk(level, dev, "signature: %*pE\n", + (int)strnlen(decoded->signature, sizeof(decoded->signature)), + decoded->signature); dev_printk(level, dev, "error_type: %u\n", decoded->error_type); dev_printk(level, dev, "error_instance: %u\n", decoded->error_instance); dev_printk(level, dev, "severity: %u\n", decoded->severity); dev_printk(level, dev, "socket: %u\n", decoded->socket); dev_printk(level, dev, "number_regs: %u\n", decoded->number_regs); - dev_printk(level, dev, "instance_base: 0x%016llx\n", decoded->instance_ba= se); + dev_printk(level, dev, "instance_base: 0x%016llx\n", + decoded->instance_base); =20 for (int i =3D 0; i < decoded->number_regs; i++) { if (nvidia_ghes_grace_reg_pair(decoded, i, &addr, &val)) @@ -129,12 +574,157 @@ static void nvidia_ghes_print_grace(struct device *d= ev, } } =20 +static void nvidia_ghes_print_vera(struct device *dev, + const struct nvidia_ghes_decoded *decoded, + bool fatal, unsigned long ghes_severity) +{ + struct nvidia_ghes_vera_cursor cursor; + struct nvidia_ghes_vera_context context; + const char *level =3D fatal ? KERN_ERR : KERN_INFO; + unsigned int remaining =3D NVIDIA_GHES_MAX_PRINT_ENTRIES; + unsigned int print_contexts; + + dev_printk(level, dev, "signature: %*pE\n", + (int)strnlen(decoded->signature, sizeof(decoded->signature)), + decoded->signature); + dev_printk(level, dev, "event_type: %u\n", decoded->event_type); + dev_printk(level, dev, "event_sub_type: %u\n", decoded->event_sub_type); + dev_printk(level, dev, "ghes_severity: %lu\n", ghes_severity); + dev_printk(level, dev, "event_link_id: 0x%016llx\n", + decoded->event_link_id); + dev_printk(level, dev, "socket: %u\n", decoded->socket); + dev_printk(level, dev, "architecture: 0x%x\n", decoded->architecture); + dev_printk(level, dev, "chip_serial_number: %*phN\n", + (int)sizeof(decoded->chip_serial_number), + decoded->chip_serial_number); + dev_printk(level, dev, "instance_base: 0x%016llx\n", decoded->instance_ba= se); + dev_printk(level, dev, "event_context_count: %u\n", decoded->event_contex= t_count); + if (decoded->valid_context_count !=3D decoded->event_context_count) + dev_printk(level, dev, "valid_context_count: %u\n", + decoded->valid_context_count); + + print_contexts =3D nvidia_ghes_vera_print_context_count(decoded); + nvidia_ghes_vera_cursor_init(decoded, &cursor); + for (int i =3D 0; i < print_contexts; i++) { + const struct nvidia_ghes_vera_context *ctx =3D &context; + int entries; + int print_n; + + if (nvidia_ghes_vera_cursor_next(&cursor, &context) !=3D 1) + break; + entries =3D nvidia_ghes_vera_context_entry_count(ctx); + dev_printk(level, dev, + "context[%d]: version=3D%u format=3D%u format_version=3D%u context_s= ize=3D%u data_size=3D%u\n", + i, ctx->context_version, ctx->data_format_type, + ctx->data_format_version, ctx->context_size, ctx->data_size); + if (ctx->data_format_type =3D=3D 0 && ctx->data_size > 0) { + int prefix_len =3D ctx->data_size > 16 ? 16 : ctx->data_size; + + dev_printk(level, dev, "context[%d]_opaque_prefix: %*phN\n", + i, prefix_len, ctx->data); + continue; + } + if (entries < 0) + continue; + + dev_printk(level, dev, "context[%d]_entries: %d\n", i, entries); + print_n =3D nvidia_ghes_vera_context_print_count(ctx, &remaining); + if (print_n < 0) + continue; + for (int j =3D 0; j < print_n; j++) { + u64 key64, val64; + u32 key32, val32; + + switch (ctx->data_format_type) { + case 1: + if (nvidia_ghes_vera_context_u64_pair(ctx, j, &key64, &val64)) + break; + dev_printk(level, dev, + "context[%d]_entry[%d]: key=3D0x%016llx value=3D0x%016llx\n", + i, j, key64, val64); + break; + case 2: + if (nvidia_ghes_vera_context_u32_pair(ctx, j, &key32, &val32)) + break; + dev_printk(level, dev, + "context[%d]_entry[%d]: key=3D0x%08x value=3D0x%08x\n", + i, j, key32, val32); + break; + case 3: + if (nvidia_ghes_vera_context_u64_value(ctx, j, &val64)) + break; + dev_printk(level, dev, + "context[%d]_entry[%d]: value=3D0x%016llx\n", + i, j, val64); + break; + case 4: + if (nvidia_ghes_vera_context_u32_value(ctx, j, &val32)) + break; + dev_printk(level, dev, + "context[%d]_entry[%d]: value=3D0x%08x\n", + i, j, val32); + break; + default: + break; + } + } + if (entries > print_n) + dev_printk(level, dev, + "context[%d]_entries_omitted: %d\n", + i, entries - print_n); + } + if (decoded->valid_context_count > print_contexts) + dev_printk(level, dev, "contexts_omitted: %u\n", + decoded->valid_context_count - print_contexts); +} + +static void nvidia_ghes_log_decode_failure(struct device *dev, + enum nvidia_ghes_format format, + bool fatal, u32 len, int ret) +{ + const char *level =3D fatal ? KERN_ERR : KERN_INFO; + + if (ret =3D=3D -EOPNOTSUPP && format =3D=3D NVIDIA_GHES_FORMAT_VERA) { + if (fatal) + dev_printk(level, dev, + "Unsupported NVIDIA Vera CPER section, error_data_length: %u, ret: = %d\n", + len, ret); + else + dev_info_ratelimited(dev, + "Unsupported NVIDIA Vera CPER section, error_data_length: %u, re= t: %d\n", + len, ret); + return; + } + + if (format =3D=3D NVIDIA_GHES_FORMAT_GRACE) { + if (fatal) + dev_printk(level, dev, + "Malformed NVIDIA Grace CPER section, error_data_length: %u, ret: %= d\n", + len, ret); + else + dev_err_ratelimited(dev, + "Malformed NVIDIA Grace CPER section, error_data_length: %u, ret:= %d\n", + len, ret); + return; + } + + if (fatal) + dev_printk(level, dev, + "Malformed NVIDIA Vera CPER section, error_data_length: %u, ret: %d\= n", + len, ret); + else + dev_err_ratelimited(dev, + "Malformed NVIDIA Vera CPER section, error_data_length: %u, ret: %= d\n", + len, ret); +} + static int nvidia_ghes_notify(struct notifier_block *nb, unsigned long event, void *data) { struct acpi_hest_generic_data *gdata =3D data; struct nvidia_ghes_decoded decoded =3D {}; struct nvidia_ghes_private *priv; + enum nvidia_ghes_format format; const void *payload; guid_t sec_guid; u32 len; @@ -142,25 +732,58 @@ static int nvidia_ghes_notify(struct notifier_block *= nb, bool fatal; =20 import_guid(&sec_guid, gdata->section_type); - if (!guid_equal(&sec_guid, &nvidia_grace_sec_guid)) + format =3D nvidia_ghes_format_from_guid(&sec_guid); + if (format =3D=3D NVIDIA_GHES_FORMAT_UNKNOWN) return NOTIFY_DONE; =20 priv =3D container_of(nb, struct nvidia_ghes_private, nb); len =3D acpi_hest_get_error_length(gdata); + payload =3D acpi_hest_get_payload(gdata); fatal =3D event >=3D GHES_SEV_RECOVERABLE; =20 - ret =3D nvidia_ghes_decode_grace(priv->dev, payload, len, &decoded); + switch (format) { + case NVIDIA_GHES_FORMAT_GRACE: + ret =3D __nvidia_ghes_decode_grace(priv->dev, payload, len, + &decoded, fatal); + break; + case NVIDIA_GHES_FORMAT_VERA: + ret =3D __nvidia_ghes_decode_vera(priv->dev, payload, len, + &decoded, fatal); + break; + default: + ret =3D -EOPNOTSUPP; + break; + } + if (ret) { - dev_err_ratelimited(priv->dev, - "Malformed NVIDIA CPER section, error_data_length: %u, ret: %d\n", - len, ret); + nvidia_ghes_log_decode_failure(priv->dev, format, fatal, len, ret); + /* + * Print any contexts successfully decoded before the failure. + * Raw section bytes remain available via log_non_standard_event(). + */ + if (format =3D=3D NVIDIA_GHES_FORMAT_VERA && + decoded.format =3D=3D NVIDIA_GHES_FORMAT_VERA && + decoded.valid_context_count > 0) { + dev_printk(fatal ? KERN_ERR : KERN_INFO, priv->dev, + "NVIDIA Vera CPER section (partial), error_data_length: %u\n", + len); + nvidia_ghes_print_vera(priv->dev, &decoded, fatal, event); + } return NOTIFY_OK; } =20 - dev_printk(fatal ? KERN_ERR : KERN_INFO, priv->dev, - "NVIDIA CPER section, error_data_length: %u\n", len); - nvidia_ghes_print_grace(priv->dev, &decoded, fatal); + if (format =3D=3D NVIDIA_GHES_FORMAT_GRACE) + dev_printk(fatal ? KERN_ERR : KERN_INFO, priv->dev, + "NVIDIA Grace CPER section, error_data_length: %u\n", len); + else + dev_printk(fatal ? KERN_ERR : KERN_INFO, priv->dev, + "NVIDIA Vera CPER section, error_data_length: %u\n", len); + + if (format =3D=3D NVIDIA_GHES_FORMAT_VERA) + nvidia_ghes_print_vera(priv->dev, &decoded, fatal, event); + else + nvidia_ghes_print_grace(priv->dev, &decoded, fatal); =20 return NOTIFY_OK; } diff --git a/drivers/acpi/apei/ghes-nvidia.h b/drivers/acpi/apei/ghes-nvidi= a.h index 965abe3d5c49..b5f0312499fc 100644 --- a/drivers/acpi/apei/ghes-nvidia.h +++ b/drivers/acpi/apei/ghes-nvidia.h @@ -4,13 +4,13 @@ =20 #include #include +#include #include =20 -struct device; - enum nvidia_ghes_format { NVIDIA_GHES_FORMAT_UNKNOWN, NVIDIA_GHES_FORMAT_GRACE, + NVIDIA_GHES_FORMAT_VERA, }; =20 struct nvidia_ghes_grace_reg { @@ -18,18 +18,52 @@ struct nvidia_ghes_grace_reg { __le64 val; } __packed; =20 +struct nvidia_ghes_vera_context { + u32 context_size; + u16 context_version; + u16 data_format_type; + u16 data_format_version; + u32 data_size; + const u8 *data; +}; + +struct nvidia_ghes_vera_cursor { + const u8 *pos; + size_t remaining; + u8 contexts_left; +}; + struct nvidia_ghes_decoded { enum nvidia_ghes_format format; char signature[17]; u16 error_type; u16 error_instance; + u16 event_type; + u16 event_sub_type; u8 severity; u8 socket; u8 number_regs; + u8 source_device_type; + u8 event_context_count; + u8 valid_context_count; + u32 architecture; + u64 event_link_id; u64 instance_base; + u8 chip_serial_number[16]; const struct nvidia_ghes_grace_reg *grace_regs; + const u8 *vera_contexts; + size_t vera_contexts_len; }; =20 +/* Bound the notifier stack frame. */ +static_assert(sizeof(struct nvidia_ghes_decoded) <=3D 128); + +struct device; + +VISIBLE_IF_KUNIT enum nvidia_ghes_format nvidia_ghes_format_from_guid(cons= t guid_t *guid); +VISIBLE_IF_KUNIT int nvidia_ghes_decode_grace(struct device *dev, const vo= id *buf, + size_t len, + struct nvidia_ghes_decoded *decoded); /** * nvidia_ghes_grace_reg_pair() - Read one Grace register address/value pa= ir * @decoded: Decoded Grace section; format must be NVIDIA_GHES_FORMAT_GRACE @@ -41,10 +75,35 @@ struct nvidia_ghes_decoded { * Returns -EINVAL for bad arguments / missing grace_regs, -ERANGE for * index >=3D number_regs, and 0 on success. */ -VISIBLE_IF_KUNIT int nvidia_ghes_decode_grace(struct device *dev, const vo= id *buf, - size_t len, - struct nvidia_ghes_decoded *decoded); VISIBLE_IF_KUNIT int nvidia_ghes_grace_reg_pair(const struct nvidia_ghes_d= ecoded *decoded, unsigned int index, u64 *addr, u64 *val); +VISIBLE_IF_KUNIT int nvidia_ghes_decode_vera(struct device *dev, const voi= d *buf, + size_t len, + struct nvidia_ghes_decoded *decoded); +VISIBLE_IF_KUNIT +void nvidia_ghes_vera_cursor_init(const struct nvidia_ghes_decoded *decode= d, + struct nvidia_ghes_vera_cursor *cursor); +VISIBLE_IF_KUNIT +int nvidia_ghes_vera_cursor_next(struct nvidia_ghes_vera_cursor *cursor, + struct nvidia_ghes_vera_context *ctx); +VISIBLE_IF_KUNIT +int nvidia_ghes_vera_print_context_count(const struct nvidia_ghes_decoded = *decoded); +VISIBLE_IF_KUNIT +int nvidia_ghes_vera_context_entry_count(const struct nvidia_ghes_vera_con= text *ctx); +VISIBLE_IF_KUNIT +int nvidia_ghes_vera_context_u64_pair(const struct nvidia_ghes_vera_contex= t *ctx, + unsigned int index, u64 *key, u64 *val); +VISIBLE_IF_KUNIT +int nvidia_ghes_vera_context_u32_pair(const struct nvidia_ghes_vera_contex= t *ctx, + unsigned int index, u32 *key, u32 *val); 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Tue, 4 Aug 2026 12:23:40 +0000 Received: from SJ0PR12MB6733.namprd12.prod.outlook.com ([fe80::f00d:2f6b:6f9b:8f97]) by SJ0PR12MB6733.namprd12.prod.outlook.com ([fe80::f00d:2f6b:6f9b:8f97%6]) with mapi id 15.21.0270.017; Tue, 4 Aug 2026 12:23:39 +0000 From: Kai-Heng Feng To: rafael@kernel.org, linux-acpi@vger.kernel.org Cc: tony.luck@intel.com, bp@alien8.de, guohanjun@huawei.com, mchehab@kernel.org, xueshuai@linux.alibaba.com, lenb@kernel.org, kees@kernel.org, gustavoars@kernel.org, linux-hardening@vger.kernel.org, linux-kernel@vger.kernel.org, Kai-Heng Feng Subject: [PATCH v3 3/3] ACPI: APEI: GHES: Add Grace and Vera KUnit coverage Date: Tue, 4 Aug 2026 20:23:17 +0800 Message-ID: <20260804122318.88193-4-kaihengf@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260804122318.88193-1-kaihengf@nvidia.com> References: <20260724122054.36162-1-kaihengf@nvidia.com> <20260804122318.88193-1-kaihengf@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SI3PR01CA0003.apcprd01.prod.exchangelabs.com (2603:1096:4:296::18) To SJ0PR12MB6733.namprd12.prod.outlook.com (2603:10b6:a03:477::9) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ0PR12MB6733:EE_|CHAPR12MB999224:EE_ X-MS-Office365-Filtering-Correlation-Id: 141e99c1-e50d-417e-b09d-08def22336d8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|376014|7416014|366016|1800799024|10067099003|11063799006|5023799004|56012099006|18002099003|22082099003|3023799007|4143699003|6133799003; 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charset="utf-8" Verify the Grace and Vera decoders against binary records captured from firmware and synthetic records for contract boundaries. Cover successful decoding, malformed inputs, unaligned Grace payloads, accessors, and GUID routing. Exercise Vera CtxSize alignment, padding traversal into the next context, section bounds, retained contexts before a later failure, and the legacy format-0 header-only encoding. Verify that the 32-entry print budget is shared across the complete Vera section. Signed-off-by: Kai-Heng Feng --- v3: - Add unaligned Grace decode and grace_reg_pair coverage. - Cover aligned Vera padding, next-context traversal, bounds, retained contexts before failure, and the legacy opaque encoding. - Exercise driver-exported Vera accessors rather than test-only copies. - Reject accessor inputs with positive data size and no backing data. - Verify section-wide print-budget accounting. - Document the ACPI-capable kunit.py invocation. - Keep EINJ firmware validation in ras-tools. --- drivers/acpi/apei/Kconfig | 20 + drivers/acpi/apei/Makefile | 1 + drivers/acpi/apei/ghes-nvidia-test-fixtures.h | 233 +++ drivers/acpi/apei/ghes-nvidia-test.c | 1274 +++++++++++++++++ 4 files changed, 1528 insertions(+) create mode 100644 drivers/acpi/apei/ghes-nvidia-test-fixtures.h create mode 100644 drivers/acpi/apei/ghes-nvidia-test.c diff --git a/drivers/acpi/apei/Kconfig b/drivers/acpi/apei/Kconfig index 2dcea74c1677..3374b4f0aa6e 100644 --- a/drivers/acpi/apei/Kconfig +++ b/drivers/acpi/apei/Kconfig @@ -88,6 +88,26 @@ config ACPI_APEI_GHES_NVIDIA =20 If unsure, say N. =20 +config ACPI_APEI_GHES_NVIDIA_KUNIT_TEST + tristate "NVIDIA GHES vendor record handler KUnit tests" if !KUNIT_ALL_TE= STS + depends on KUNIT && ACPI_APEI_GHES_NVIDIA + default KUNIT_ALL_TESTS + help + KUnit tests for NVIDIA GHES vendor CPER parser helpers. + They cover Grace helper decoding, Vera context parsing/accessors, + and GUID section routing. + They are enabled only for KUnit test builds. + They are not intended for production firmware paths. + + Run with an ACPI-capable architecture, e.g.: + tools/testing/kunit/kunit.py run --arch=3Dx86_64 \ + --kconfig_add CONFIG_ACPI=3Dy --kconfig_add CONFIG_ACPI_APEI=3Dy \ + --kconfig_add CONFIG_ACPI_APEI_GHES=3Dy \ + --kconfig_add CONFIG_ACPI_APEI_GHES_NVIDIA=3Dy \ + --kconfig_add CONFIG_ACPI_APEI_GHES_NVIDIA_KUNIT_TEST=3Dy + + If unsure, say N. + config ACPI_APEI_ERST_DEBUG tristate "APEI Error Record Serialization Table (ERST) Debug Support" depends on ACPI_APEI diff --git a/drivers/acpi/apei/Makefile b/drivers/acpi/apei/Makefile index 66588d6be56f..210a57242044 100644 --- a/drivers/acpi/apei/Makefile +++ b/drivers/acpi/apei/Makefile @@ -11,5 +11,6 @@ einj-y :=3D einj-core.o einj-$(CONFIG_ACPI_APEI_EINJ_CXL) +=3D einj-cxl.o obj-$(CONFIG_ACPI_APEI_ERST_DEBUG) +=3D erst-dbg.o obj-$(CONFIG_ACPI_APEI_GHES_NVIDIA) +=3D ghes-nvidia.o +obj-$(CONFIG_ACPI_APEI_GHES_NVIDIA_KUNIT_TEST) +=3D ghes-nvidia-test.o =20 apei-y :=3D apei-base.o hest.o erst.o bert.o diff --git a/drivers/acpi/apei/ghes-nvidia-test-fixtures.h b/drivers/acpi/a= pei/ghes-nvidia-test-fixtures.h new file mode 100644 index 000000000000..705c879c785e --- /dev/null +++ b/drivers/acpi/apei/ghes-nvidia-test-fixtures.h @@ -0,0 +1,233 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef GHES_NVIDIA_TEST_FIXTURES_H +#define GHES_NVIDIA_TEST_FIXTURES_H + +#include + +/* + * Source: cper-tools/test_data/vera_msft.json + * cper-tools commit: bf18f75406422e73e11b8b1ff80e3c9d9cfb032a + * Boundary: CPER.Oem.Nvidia.Unknown.Data. + * Each payload equals the Vera GUID section body located in DiagnosticDat= a. + */ + +/* Redfish Id 10, signature L1 RESET, real sample. */ +/* Vera section index 0, offset 200, length 80. */ +/* sha256 fc11639e506eb8d79e7ff16a0556463ac4b1304bface935c0cd13efc0b3e317f= . */ +static const u8 vera_l1_reset_id10[] =3D { + 0x01, 0x01, 0x00, 0x00, 0x01, 0x00, 0x27, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x4c, 0x31, 0x20, 0x52, 0x45, 0x53, 0x45, 0x54, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, + 0x07, 0x41, 0x01, 0x00, 0xc0, 0x01, 0xfe, 0x06, 0x00, 0x00, 0x00, 0x00, + 0x81, 0xc1, 0x18, 0x78, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, + 0x15, 0xfe, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; + +/* Redfish Id 40, signature CRASHDUMP-ID, real sample. */ +/* Vera section index 0, offset 200, length 304. */ +/* sha256 3ba93201740e6bd868b48ec40c3d52b235c1ebc59528fc81974079c21bf2a6a2= . */ +static const u8 vera_crashdump_id_id40[] =3D { + 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x43, 0x52, 0x41, 0x53, 0x48, 0x44, 0x55, 0x4d, + 0x50, 0x2d, 0x49, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, + 0x07, 0x41, 0x01, 0x00, 0xc0, 0x01, 0xfe, 0x06, 0x00, 0x00, 0x00, 0x00, + 0x81, 0xc1, 0x18, 0x78, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x83, 0x72, 0x65, 0x6c, 0x5f, 0x37, 0x33, 0x2e, 0x37, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x64, 0x69, 0x72, 0x74, + 0x79, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, + 0x44, 0x24, 0x4e, 0x9e, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x10, 0x00, + 0x14, 0xfe, 0x00, 0x00, 0x07, 0x41, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x04, 0x07, 0x03, 0x03, 0x14, 0xfe, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x20, 0x00, 0x15, 0xfe, 0x00, 0x00, + 0x9d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0a, 0x04, 0x00, + 0x14, 0xfe, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x14, 0x0a, 0x04, 0x00, 0x14, 0xfe, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x18, 0x0a, 0x04, 0x00, 0x14, 0xfe, 0x00, 0x00, + 0x40, 0x60, 0x30, 0x06, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x0a, 0x04, 0x00, + 0x14, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x20, 0x0a, 0x04, 0x00, 0x14, 0xfe, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x24, 0x0a, 0x04, 0x00, 0x14, 0xfe, 0x00, 0x00, + 0xfc, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x0a, 0x04, 0x00, + 0x14, 0xfe, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x2c, 0x0a, 0x04, 0x00, 0x14, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, +}; + +/* Redfish Id 41, signature CRASHDUMP-S1, real sample. */ +/* Vera section index 0, offset 200, length 2008. */ +/* sha256 54db30564d3324240f088a1533c113407f1d81bcd652ef0d27d958c490aee5ce= . */ +static const u8 vera_crashdump_s1_id41[] =3D { + 0x01, 0x01, 0x00, 0x00, 0x00, 0x10, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x43, 0x52, 0x41, 0x53, 0x48, 0x44, 0x55, 0x4d, + 0x50, 0x2d, 0x53, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, + 0x07, 0x41, 0x01, 0x00, 0xc0, 0x01, 0xfe, 0x06, 0x00, 0x00, 0x00, 0x00, + 0x81, 0xc1, 0x18, 0x78, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x88, 0x07, 0x00, 0x00, 0x53, 0x56, 0x7f, 0xa1, + 0xd1, 0xd7, 0x7f, 0xe5, 0xaa, 0x34, 0xde, 0x7d, 0xe9, 0x3e, 0xc4, 0xd4, + 0x92, 0xe8, 0x10, 0xa1, 0x4c, 0xfc, 0xf9, 0x2e, 0x02, 0x87, 0xc5, 0x6e, + 0x44, 0xfb, 0xb5, 0x59, 0xac, 0xfa, 0xa8, 0x15, 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0xfc, 0xa9, 0x66, 0xa9, + 0x95, 0x33, 0xcd, 0x8b, 0x22, 0x11, 0xd9, 0xff, 0x7e, 0x5c, 0x9d, 0x80, + 0xc5, 0xed, 0x99, 0x78, 0x5c, 0x33, 0xdd, 0x0e, 0xca, 0x6a, 0xe2, 0xb6, + 0x3a, 0x66, 0xbd, 0x1d, 0x60, 0x96, 0x28, 0x20, 0xbd, 0x8c, 0xf4, 0x6c, + 0xcb, 0xc3, 0x9b, 0x19, 0x78, 0xd7, 0x57, 0xa3, 0xc3, 0x12, 0x95, 0x11, + 0x3d, 0xab, 0x44, 0x0d, 0x78, 0xbb, 0x2e, 0x0b, 0x4e, 0x0c, 0x94, 0x75, + 0xe7, 0x8f, 0x5c, 0xad, 0xe4, 0x2f, 0x9c, 0x26, 0x00, 0x01, 0x71, 0xe1, + 0x36, 0xcf, 0xb1, 0x00, 0x8f, 0xf7, 0x86, 0x79, 0x2e, 0x79, 0x9e, 0xd5, + 0x8b, 0x53, 0x0d, 0x28, 0x6c, 0xb9, 0xa2, 0xdf, 0x04, 0xe3, 0x78, 0x6d, + 0xcb, 0xb7, 0xf9, 0xea, 0x20, 0x4a, 0x5d, 0x92, 0x64, 0x88, 0x7d, 0xc4, + 0x5a, 0x21, 0x86, 0x12, 0x46, 0x49, 0x6d, 0xbc, 0x03, 0xd5, 0xeb, 0xf6, + 0xe3, 0x38, 0x4a, 0xaa, 0xce, 0x45, 0x91, 0x6a, 0xc0, 0x59, 0x1b, 0x6c, + 0x98, 0xb2, 0xe0, 0x29, 0x91, 0x01, 0xb5, 0x44, 0x48, 0xa6, 0xd3, 0x78, + 0x5a, 0xe1, 0xe4, 0x8c, 0xd9, 0x33, 0xa0, 0xd5, 0xe1, 0x83, 0xd6, 0x5a, + 0xe3, 0x5f, 0xe6, 0xf8, 0xfd, 0x21, 0x12, 0xff, 0x9e, 0x71, 0x70, 0x7f, + 0x17, 0xe2, 0x41, 0xf2, 0xb1, 0x4a, 0x84, 0x6b, 0x88, 0xb6, 0xb9, 0xed, + 0xdb, 0x0b, 0x84, 0x6f, 0x07, 0x94, 0xc7, 0x8e, 0xcc, 0xc2, 0xb2, 0x49, + 0x3d, 0xf8, 0x70, 0x1a, 0x9b, 0x4d, 0x13, 0x0c, 0xe7, 0xeb, 0x75, 0x5d, + 0xfb, 0x10, 0x16, 0xf9, 0xf1, 0xac, 0x4b, 0xe3, 0x65, 0x5f, 0xaa, 0xbb, + 0x31, 0xac, 0x4d, 0x74, 0x11, 0x62, 0x64, 0xd1, 0x90, 0x6e, 0x45, 0xaf, + 0x2d, 0xb2, 0xa5, 0xfa, 0x57, 0x67, 0xaa, 0x4c, 0x3f, 0x81, 0x72, 0x93, + 0x8a, 0xfb, 0xeb, 0x19, 0x9d, 0x9a, 0x10, 0x8d, 0xce, 0xb8, 0xe9, 0x3f, + 0x97, 0x3e, 0xb2, 0x2d, 0x3e, 0xaf, 0x19, 0x39, 0xb0, 0xea, 0x33, 0x09, + 0x25, 0xbc, 0x6f, 0x88, 0x25, 0x75, 0x11, 0x2b, 0xd9, 0x42, 0x8d, 0x48, + 0x8e, 0xe7, 0x51, 0x4e, 0xd4, 0xee, 0xd4, 0xf1, 0xe1, 0x94, 0xfb, 0xbd, + 0x01, 0x87, 0xa5, 0xd6, 0x94, 0x36, 0x6f, 0x37, 0xcd, 0x70, 0x49, 0xfd, + 0x6a, 0x94, 0xb0, 0xc8, 0xe5, 0xb9, 0xdb, 0x83, 0x72, 0xa0, 0xd8, 0x5e, + 0x00, 0x3e, 0x3d, 0x56, 0xc9, 0xae, 0xf6, 0xe7, 0xb1, 0xba, 0xdd, 0x6d, + 0x59, 0x2a, 0x6a, 0x50, 0x66, 0xfd, 0xf1, 0x1f, 0x18, 0xe4, 0xf9, 0x59, + 0x16, 0xf1, 0x25, 0x42, 0x7c, 0xab, 0xc5, 0xea, 0x64, 0x31, 0xf7, 0xcf, + 0xdd, 0x56, 0xc4, 0xbd, 0xb5, 0xe6, 0xb4, 0xda, 0x41, 0xb7, 0xfa, 0x05, + 0x06, 0x57, 0x51, 0xd8, 0xc4, 0xf7, 0x3c, 0xc8, 0x54, 0x55, 0x5c, 0x2c, + 0xd2, 0x17, 0xec, 0x27, 0xd3, 0xbf, 0xf3, 0xc8, 0xba, 0xbf, 0x75, 0xcf, + 0x1f, 0x78, 0x42, 0x1a, 0x4f, 0xb0, 0xcb, 0xd7, 0x84, 0xc6, 0xbd, 0x40, + 0x07, 0xbf, 0x47, 0xe9, 0x17, 0x2f, 0xad, 0xec, 0x64, 0x8b, 0xca, 0x7c, + 0x49, 0x4c, 0xda, 0xf9, 0x5f, 0x28, 0x1d, 0x2d, 0xc3, 0x8d, 0x15, 0xa6, + 0x0f, 0x95, 0x76, 0x99, 0xb5, 0x76, 0x68, 0x97, 0x91, 0x93, 0xca, 0x9d, + 0x61, 0x50, 0xa7, 0xa7, 0xf7, 0xce, 0xd5, 0x14, 0xe5, 0xb2, 0x50, 0x50, + 0x21, 0x73, 0x00, 0x21, 0x4f, 0x12, 0x79, 0x7f, 0x68, 0x27, 0x52, 0xf2, + 0x2c, 0x9d, 0x2d, 0x4f, 0x66, 0x3e, 0xf1, 0xb5, 0x68, 0x77, 0xc9, 0xd5, + 0x16, 0x01, 0xb2, 0x6d, 0x46, 0x7c, 0xce, 0x8d, 0x67, 0x77, 0x27, 0xdd, + 0x4b, 0x16, 0xd7, 0x7b, 0x16, 0xfd, 0x6b, 0x18, 0x36, 0xeb, 0xa5, 0xd6, + 0xd1, 0x21, 0xdb, 0x27, 0x01, 0x9a, 0x22, 0xa1, 0xbf, 0x45, 0xda, 0xf7, + 0xe4, 0x07, 0x26, 0x0c, 0x84, 0xe1, 0x81, 0x1c, 0xf9, 0x38, 0x4a, 0x26, + 0xb3, 0xe3, 0x90, 0x13, 0x5e, 0xb7, 0xd5, 0xaf, 0xcb, 0x7d, 0xc1, 0xf7, + 0x23, 0x2d, 0x96, 0xc8, 0xe7, 0x3e, 0x21, 0x2c, 0xee, 0xa8, 0xd7, 0x83, + 0xf1, 0xd7, 0xf0, 0xce, 0xca, 0x80, 0xb5, 0xbd, 0x89, 0x10, 0x71, 0x38, + 0x8c, 0xa2, 0xa1, 0x07, 0x93, 0xa9, 0xd9, 0x4d, 0xa5, 0x9b, 0x66, 0x68, + 0x06, 0x65, 0x8d, 0x26, 0xff, 0xcb, 0xf2, 0xf5, 0x09, 0x7c, 0xf1, 0x7f, + 0x55, 0x3f, 0x61, 0x78, 0xb8, 0x27, 0x77, 0xb8, 0x30, 0x91, 0x10, 0x3f, + 0x57, 0xec, 0xfd, 0x82, 0xd2, 0xd3, 0x8a, 0x27, 0xa5, 0x26, 0x87, 0x01, + 0x8a, 0x20, 0x9a, 0x5d, 0xe9, 0x88, 0xa7, 0x70, 0xb0, 0x06, 0x04, 0xe8, + 0xa0, 0x15, 0x2c, 0x0b, 0xe5, 0xea, 0x79, 0x57, 0xad, 0x8c, 0xe2, 0x98, + 0xcd, 0xbf, 0x74, 0x1c, 0xb6, 0x06, 0xc6, 0x17, 0x12, 0x2b, 0xa4, 0xa6, + 0xfe, 0xe7, 0x94, 0xf9, 0xb6, 0x95, 0xf0, 0xfc, 0xe5, 0x57, 0xfe, 0xf9, + 0x1d, 0xd4, 0x29, 0xc0, 0x06, 0xf9, 0x5f, 0x14, 0x73, 0x14, 0x1d, 0x42, + 0x1f, 0x70, 0xa0, 0xd5, 0x3d, 0x0d, 0xbe, 0xfb, 0xb3, 0xe0, 0xae, 0x35, + 0x34, 0x40, 0xa9, 0xca, 0x5d, 0x6f, 0x4f, 0x3a, 0x3b, 0x9e, 0xe2, 0xed, + 0x85, 0xa9, 0x53, 0xb9, 0xb2, 0x43, 0x5e, 0x95, 0x7a, 0x30, 0x63, 0x2a, + 0x84, 0x40, 0x1b, 0x86, 0x2d, 0x74, 0xf6, 0xf3, 0x3b, 0x40, 0x5b, 0x16, + 0x51, 0xa1, 0xaa, 0x70, 0xed, 0xb3, 0x96, 0x66, 0x9b, 0x6b, 0x57, 0x4d, + 0x0d, 0x8b, 0x2a, 0x9b, 0x27, 0xb6, 0x04, 0xa5, 0x19, 0xb2, 0x17, 0xad, + 0x6f, 0x6f, 0xef, 0x8c, 0xae, 0x87, 0x58, 0xc9, 0xbd, 0x51, 0xf9, 0x6b, + 0x7d, 0x5c, 0xd1, 0x42, 0x10, 0xa1, 0x5c, 0x66, 0x13, 0xaa, 0xe0, 0xfc, + 0x91, 0x95, 0x63, 0x0a, 0x0b, 0x3d, 0x5c, 0xd1, 0x64, 0xda, 0xaf, 0x7b, + 0x1b, 0x0a, 0x09, 0x9f, 0xf8, 0xd9, 0x43, 0x7b, 0x7d, 0xe1, 0x34, 0x68, + 0x6a, 0xb2, 0x3a, 0x16, 0x99, 0x2f, 0x29, 0x5f, 0xa3, 0xe6, 0x03, 0x74, + 0x42, 0x49, 0x6a, 0x33, 0x15, 0x93, 0x5e, 0xa5, 0xab, 0x13, 0x77, 0x3a, + 0x1a, 0x78, 0x6d, 0xe5, 0x06, 0x1f, 0xa4, 0x6f, 0xdc, 0xa8, 0xc8, 0x93, + 0x9f, 0x4d, 0x99, 0xba, 0xb1, 0x6d, 0x8d, 0x1d, 0xc0, 0x6b, 0xff, 0x16, + 0x7d, 0xb3, 0xfc, 0xe0, 0xd7, 0xd4, 0xb2, 0x69, 0x32, 0x38, 0x64, 0xef, + 0x04, 0xba, 0x7b, 0xa5, 0x5e, 0xc6, 0x1f, 0x1d, 0xd0, 0xf8, 0x6b, 0xd8, + 0x35, 0xb9, 0x9e, 0x2f, 0x62, 0x36, 0xf5, 0x88, 0x41, 0x90, 0x1f, 0xc7, + 0xc3, 0x96, 0x1b, 0x4f, 0xc4, 0x87, 0x0c, 0xea, 0xdb, 0x8f, 0xea, 0x6a, + 0xe9, 0xdc, 0x30, 0xc4, 0x6c, 0x23, 0x9b, 0xac, 0x8b, 0xf6, 0xa6, 0xbf, + 0xc0, 0xd6, 0x00, 0xf6, 0x92, 0x3f, 0xd3, 0x83, 0xfe, 0x74, 0x7c, 0x19, + 0x74, 0xfb, 0xe7, 0x72, 0x81, 0x17, 0x32, 0x32, 0xb8, 0x4b, 0x5d, 0x70, + 0x67, 0x14, 0xe1, 0xee, +}; + +#endif diff --git a/drivers/acpi/apei/ghes-nvidia-test.c b/drivers/acpi/apei/ghes-= nvidia-test.c new file mode 100644 index 000000000000..38eacdaafff9 --- /dev/null +++ b/drivers/acpi/apei/ghes-nvidia-test.c @@ -0,0 +1,1274 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include +#include +#include + +#include "ghes-nvidia.h" +#include "ghes-nvidia-test-fixtures.h" + +static const u8 grace_valid_two_regs[] =3D { + 'N', 'V', 'D', 'A', '-', 'G', 'R', 'A', + 'C', 'E', 0, 0, 0, 0, 0, 0, + 0x34, 0x12, 0x78, 0x56, 0x02, 0x03, 0x02, 0x00, + 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, + 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x11, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x22, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; + +static const u8 grace_valid_zero_regs[] =3D { + 'N', 'V', 'D', 'A', '-', 'G', 'R', 'A', + 'C', 'E', 0, 0, 0, 0, 0, 0, + 0x01, 0x00, 0x02, 0x00, 0x00, 0x01, 0x00, 0x00, + 0xef, 0xbe, 0xad, 0xde, 0x00, 0x00, 0x00, 0x00, +}; + +static const u8 grace_valid_full_signature[] =3D { + 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', + 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', + 0x01, 0x00, 0x02, 0x00, 0x00, 0x01, 0x00, 0x00, + 0xef, 0xbe, 0xad, 0xde, 0x00, 0x00, 0x00, 0x00, +}; + +static void nvidia_ghes_grace_decodes_registers(struct kunit *test) +{ + struct nvidia_ghes_decoded decoded =3D {}; + u64 addr, val; + + KUNIT_ASSERT_EQ(test, 0, + nvidia_ghes_decode_grace(NULL, grace_valid_two_regs, + sizeof(grace_valid_two_regs), + &decoded)); + KUNIT_EXPECT_EQ(test, NVIDIA_GHES_FORMAT_GRACE, decoded.format); + KUNIT_EXPECT_STREQ(test, "NVDA-GRACE", decoded.signature); + KUNIT_EXPECT_EQ(test, 0x1234, decoded.error_type); + KUNIT_EXPECT_EQ(test, 0x5678, decoded.error_instance); + KUNIT_EXPECT_EQ(test, 2, decoded.severity); + KUNIT_EXPECT_EQ(test, 3, decoded.socket); + KUNIT_EXPECT_EQ(test, 2, decoded.number_regs); + KUNIT_EXPECT_EQ(test, 0x0102030405060708ULL, decoded.instance_base); + KUNIT_EXPECT_EQ(test, 0, + nvidia_ghes_grace_reg_pair(&decoded, 0, &addr, &val)); + KUNIT_EXPECT_EQ(test, 0x1000ULL, addr); + KUNIT_EXPECT_EQ(test, 0x1111ULL, val); + KUNIT_EXPECT_EQ(test, 0, + nvidia_ghes_grace_reg_pair(&decoded, 1, &addr, &val)); + KUNIT_EXPECT_EQ(test, 0x2000ULL, addr); + KUNIT_EXPECT_EQ(test, 0x2222ULL, val); +} + +static void nvidia_ghes_grace_decodes_unaligned_payload(struct kunit *test) +{ + struct nvidia_ghes_decoded decoded =3D {}; + u8 *buf; + u64 addr, val; + + buf =3D kunit_kzalloc(test, sizeof(grace_valid_two_regs) + 1, GFP_KERNEL); + KUNIT_ASSERT_NOT_NULL(test, buf); + memcpy(buf + 1, grace_valid_two_regs, sizeof(grace_valid_two_regs)); + + KUNIT_ASSERT_EQ(test, 0, + nvidia_ghes_decode_grace(NULL, buf + 1, + sizeof(grace_valid_two_regs), + &decoded)); + KUNIT_EXPECT_EQ(test, 0x1234, decoded.error_type); + KUNIT_EXPECT_EQ(test, 0x0102030405060708ULL, decoded.instance_base); + KUNIT_ASSERT_EQ(test, 0, + nvidia_ghes_grace_reg_pair(&decoded, 0, &addr, &val)); + KUNIT_EXPECT_EQ(test, 0x1000ULL, addr); + KUNIT_EXPECT_EQ(test, 0x1111ULL, val); + KUNIT_ASSERT_EQ(test, 0, + nvidia_ghes_grace_reg_pair(&decoded, 1, &addr, &val)); + KUNIT_EXPECT_EQ(test, 0x2000ULL, addr); + KUNIT_EXPECT_EQ(test, 0x2222ULL, val); +} + +static void nvidia_ghes_grace_accepts_zero_registers(struct kunit *test) +{ + struct nvidia_ghes_decoded decoded =3D {}; + + KUNIT_ASSERT_EQ(test, 0, + nvidia_ghes_decode_grace(NULL, grace_valid_zero_regs, + sizeof(grace_valid_zero_regs), + &decoded)); + KUNIT_EXPECT_EQ(test, NVIDIA_GHES_FORMAT_GRACE, decoded.format); + KUNIT_EXPECT_EQ(test, 0, decoded.number_regs); + KUNIT_EXPECT_PTR_EQ(test, NULL, decoded.grace_regs); +} + +static void nvidia_ghes_grace_copies_non_nul_signature(struct kunit *test) +{ + struct nvidia_ghes_decoded decoded =3D {}; + + KUNIT_ASSERT_EQ(test, 0, + nvidia_ghes_decode_grace(NULL, grace_valid_full_signature, + sizeof(grace_valid_full_signature), + &decoded)); + KUNIT_EXPECT_STREQ(test, "ABCDEFGHIJKLMNOP", decoded.signature); + KUNIT_EXPECT_EQ(test, '\0', decoded.signature[16]); +} + +static void nvidia_ghes_grace_rejects_truncated_header(struct kunit *test) +{ + struct nvidia_ghes_decoded decoded =3D {}; + + KUNIT_EXPECT_EQ(test, -ENODATA, + nvidia_ghes_decode_grace(NULL, grace_valid_two_regs, + sizeof(grace_valid_zero_regs) - 1, + &decoded)); +} + +static void nvidia_ghes_grace_rejects_truncated_registers(struct kunit *te= st) +{ + struct nvidia_ghes_decoded decoded =3D {}; + + KUNIT_EXPECT_EQ(test, -ENODATA, + nvidia_ghes_decode_grace(NULL, grace_valid_two_regs, + sizeof(grace_valid_two_regs) - 1, + &decoded)); +} + +static const u8 vera_chip_serial[] =3D { + 0xc0, 0x01, 0xfe, 0x06, 0x00, 0x00, 0x00, 0x00, + 0x81, 0xc1, 0x18, 0x78, 0x01, 0x00, 0x00, 0x00, +}; + +#define VERA_EVENT_HDR_SIZE 32 +#define VERA_CPU_INFO_SIZE 32 +#define VERA_CONTEXT_HDR_SIZE 16 +#define VERA_FIRST_CONTEXT_OFFSET (VERA_EVENT_HDR_SIZE + VERA_CPU_INFO_SIZ= E) + +struct vera_synth_context { + u32 context_size; + u16 context_version; + u16 format; + u16 data_format_version; + const u8 *data; + u32 data_size; +}; + +static u8 *nvidia_ghes_kunit_memdup(struct kunit *test, const u8 *src, siz= e_t len) +{ + u8 *buf; + + buf =3D kunit_kmalloc(test, len, GFP_KERNEL); + KUNIT_ASSERT_NOT_NULL(test, buf); + memcpy(buf, src, len); + + return buf; +} + +static u8 *vera_make_synthetic_contexts(struct kunit *test, u8 version, u8= info_size, + const struct vera_synth_context *contexts, + u8 count, size_t *len) +{ + u8 *buf; + size_t offset; + u8 i; + + KUNIT_ASSERT_TRUE(test, info_size >=3D VERA_CPU_INFO_SIZE); + *len =3D VERA_EVENT_HDR_SIZE + info_size; + for (i =3D 0; i < count; i++) { + u32 context_size =3D contexts[i].context_size; + u32 payload; + + KUNIT_ASSERT_TRUE(test, context_size >=3D VERA_CONTEXT_HDR_SIZE); + if (context_size =3D=3D VERA_CONTEXT_HDR_SIZE) + payload =3D contexts[i].data_size; + else + payload =3D context_size - VERA_CONTEXT_HDR_SIZE; + *len +=3D VERA_CONTEXT_HDR_SIZE + payload; + } + + buf =3D kunit_kzalloc(test, *len, GFP_KERNEL); + KUNIT_ASSERT_NOT_NULL(test, buf); + + buf[0] =3D version; + buf[1] =3D count; + buf[2] =3D 0; + put_unaligned_le16(0x22, &buf[4]); + memcpy(&buf[16], "SYNTH", 5); + put_unaligned_le16(0, &buf[32]); + buf[34] =3D info_size; + buf[35] =3D 0; + put_unaligned_le32(0x14107, &buf[36]); + memcpy(&buf[40], vera_chip_serial, sizeof(vera_chip_serial)); + put_unaligned_le64(0, &buf[56]); + + offset =3D VERA_EVENT_HDR_SIZE + info_size; + for (i =3D 0; i < count; i++) { + u32 context_size =3D contexts[i].context_size; + u32 payload; + + put_unaligned_le32(context_size, &buf[offset]); + put_unaligned_le16(contexts[i].context_version, + &buf[offset + 4]); + put_unaligned_le16(contexts[i].format, &buf[offset + 8]); + put_unaligned_le16(contexts[i].data_format_version, + &buf[offset + 10]); + put_unaligned_le32(contexts[i].data_size, &buf[offset + 12]); + if (contexts[i].data && contexts[i].data_size) + memcpy(&buf[offset + VERA_CONTEXT_HDR_SIZE], + contexts[i].data, contexts[i].data_size); + + if (context_size =3D=3D VERA_CONTEXT_HDR_SIZE) + payload =3D contexts[i].data_size; + else + payload =3D context_size - VERA_CONTEXT_HDR_SIZE; + offset +=3D VERA_CONTEXT_HDR_SIZE + payload; + } + + return buf; +} + +static u8 *vera_make_synthetic(struct kunit *test, u8 version, u8 info_siz= e, + u16 format, const u8 *data, u32 data_size, + size_t *len) +{ + struct vera_synth_context ctx =3D { + .context_size =3D format =3D=3D 0 ? VERA_CONTEXT_HDR_SIZE : + ALIGN(VERA_CONTEXT_HDR_SIZE + data_size, 16), + .format =3D format, + .data =3D data, + .data_size =3D data_size, + }; + + return vera_make_synthetic_contexts(test, version, info_size, &ctx, 1, le= n); +} + +static u8 *vera_make_synthetic_default(struct kunit *test, u16 format, + const u8 *data, u32 data_size, size_t *len) +{ + return vera_make_synthetic(test, 1, VERA_CPU_INFO_SIZE, format, data, + data_size, len); +} + +static int vera_context_at(const struct nvidia_ghes_decoded *decoded, + unsigned int index, + struct nvidia_ghes_vera_context *context) +{ + struct nvidia_ghes_vera_cursor cursor; + int ret; + + nvidia_ghes_vera_cursor_init(decoded, &cursor); + for (unsigned int i =3D 0; i <=3D index; i++) { + ret =3D nvidia_ghes_vera_cursor_next(&cursor, context); + if (ret !=3D 1) + return ret ?: -ERANGE; + } + + return 0; +} + +static void nvidia_ghes_vera_decodes_l1_reset(struct kunit *test) +{ + struct nvidia_ghes_decoded decoded =3D {}; + struct nvidia_ghes_vera_context context; + + KUNIT_ASSERT_EQ(test, 0, + nvidia_ghes_decode_vera(NULL, vera_l1_reset_id10, + sizeof(vera_l1_reset_id10), + &decoded)); + KUNIT_EXPECT_EQ(test, NVIDIA_GHES_FORMAT_VERA, decoded.format); + KUNIT_EXPECT_STREQ(test, "L1 RESET", decoded.signature); + KUNIT_EXPECT_EQ(test, 1, decoded.event_context_count); + KUNIT_EXPECT_EQ(test, 1, decoded.event_type); + KUNIT_EXPECT_EQ(test, 39, decoded.event_sub_type); + KUNIT_EXPECT_EQ(test, 0, decoded.source_device_type); + KUNIT_EXPECT_EQ(test, 0, decoded.socket); + KUNIT_EXPECT_EQ(test, 0x14107U, decoded.architecture); + KUNIT_EXPECT_MEMEQ(test, decoded.chip_serial_number, vera_chip_serial, + sizeof(vera_chip_serial)); + KUNIT_EXPECT_EQ(test, 0xfe1500200000ULL, decoded.instance_base); + KUNIT_ASSERT_EQ(test, 0, vera_context_at(&decoded, 0, &context)); + KUNIT_EXPECT_EQ(test, 16U, context.context_size); + KUNIT_EXPECT_EQ(test, 1, context.data_format_type); + KUNIT_EXPECT_EQ(test, 0U, context.data_size); +} + +static void nvidia_ghes_vera_decodes_crashdump_id(struct kunit *test) +{ + struct nvidia_ghes_decoded decoded =3D {}; + struct nvidia_ghes_vera_context context; + u64 key, val; + + KUNIT_ASSERT_EQ(test, 0, + nvidia_ghes_decode_vera(NULL, vera_crashdump_id_id40, + sizeof(vera_crashdump_id_id40), + &decoded)); + KUNIT_EXPECT_STREQ(test, "CRASHDUMP-ID", decoded.signature); + KUNIT_EXPECT_MEMEQ(test, decoded.chip_serial_number, vera_chip_serial, + sizeof(vera_chip_serial)); + KUNIT_ASSERT_EQ(test, 0, vera_context_at(&decoded, 0, &context)); + KUNIT_EXPECT_EQ(test, 240U, context.context_size); + KUNIT_EXPECT_EQ(test, 1, context.data_format_type); + KUNIT_EXPECT_EQ(test, 224U, context.data_size); + KUNIT_ASSERT_EQ(test, 14, nvidia_ghes_vera_context_entry_count(&context)); + KUNIT_ASSERT_EQ(test, 0, + nvidia_ghes_vera_context_u64_pair(&context, 0, &key, &val)); + KUNIT_EXPECT_EQ(test, 0x8300000000000000ULL, key); + KUNIT_EXPECT_EQ(test, 0x372e33375f6c6572ULL, val); +} + +static void nvidia_ghes_vera_decodes_crashdump_s1_opaque_context(struct ku= nit *test) +{ + struct nvidia_ghes_decoded decoded =3D {}; + struct nvidia_ghes_vera_context context; + u64 val; + + KUNIT_ASSERT_EQ(test, 0, + nvidia_ghes_decode_vera(NULL, vera_crashdump_s1_id41, + sizeof(vera_crashdump_s1_id41), + &decoded)); + KUNIT_EXPECT_STREQ(test, "CRASHDUMP-S1", decoded.signature); + KUNIT_EXPECT_EQ(test, 4096, decoded.event_type); + KUNIT_EXPECT_EQ(test, 2304, decoded.event_sub_type); + KUNIT_EXPECT_MEMEQ(test, decoded.chip_serial_number, vera_chip_serial, + sizeof(vera_chip_serial)); + KUNIT_ASSERT_EQ(test, 0, vera_context_at(&decoded, 0, &context)); + KUNIT_EXPECT_EQ(test, 16U, context.context_size); + KUNIT_EXPECT_EQ(test, 0, context.data_format_type); + KUNIT_EXPECT_EQ(test, 1928U, context.data_size); + KUNIT_ASSERT_NOT_NULL(test, context.data); + KUNIT_EXPECT_EQ(test, 0x53, context.data[0]); + KUNIT_EXPECT_EQ(test, 0x56, context.data[1]); + KUNIT_EXPECT_EQ(test, 0x7f, context.data[2]); + KUNIT_EXPECT_EQ(test, -EINVAL, + nvidia_ghes_vera_context_u64_value(&context, 0, &val)); +} + +static void nvidia_ghes_vera_decodes_multi_context_aligned(struct kunit *t= est) +{ + static const u8 first_data[] =3D { + 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, + }; + static const u8 second_data[] =3D { + 0xa0, 0xb0, 0xc0, 0xd0, + }; + struct vera_synth_context contexts[] =3D { + { + .context_size =3D VERA_CONTEXT_HDR_SIZE + 16, + .format =3D 3, + .data =3D first_data, + .data_size =3D sizeof(first_data), + }, + { + .context_size =3D VERA_CONTEXT_HDR_SIZE + 16, + .format =3D 4, + .data =3D second_data, + .data_size =3D sizeof(second_data), + }, + }; + struct nvidia_ghes_decoded decoded =3D {}; + struct nvidia_ghes_vera_context parsed[2]; + size_t len; + u8 *buf; + u64 val64; + u32 val32; + + buf =3D vera_make_synthetic_contexts(test, 1, VERA_CPU_INFO_SIZE, context= s, + ARRAY_SIZE(contexts), &len); + KUNIT_ASSERT_EQ(test, 0, nvidia_ghes_decode_vera(NULL, buf, len, &decoded= )); + KUNIT_EXPECT_EQ(test, 2, decoded.event_context_count); + KUNIT_ASSERT_EQ(test, 0, vera_context_at(&decoded, 0, &parsed[0])); + KUNIT_ASSERT_EQ(test, 0, vera_context_at(&decoded, 1, &parsed[1])); + KUNIT_EXPECT_EQ(test, VERA_CONTEXT_HDR_SIZE + 16, + parsed[0].context_size); + KUNIT_EXPECT_EQ(test, 3, parsed[0].data_format_type); + KUNIT_EXPECT_EQ(test, sizeof(first_data), parsed[0].data_size); + KUNIT_ASSERT_NOT_NULL(test, parsed[0].data); + KUNIT_ASSERT_EQ(test, 0, + nvidia_ghes_vera_context_u64_value(&parsed[0], 0, &val64)); + KUNIT_EXPECT_EQ(test, 0x8877665544332211ULL, val64); + KUNIT_EXPECT_EQ(test, VERA_CONTEXT_HDR_SIZE + 16, + parsed[1].context_size); + KUNIT_EXPECT_EQ(test, 4, parsed[1].data_format_type); + KUNIT_EXPECT_EQ(test, sizeof(second_data), parsed[1].data_size); + KUNIT_ASSERT_NOT_NULL(test, parsed[1].data); + KUNIT_ASSERT_EQ(test, 0, + nvidia_ghes_vera_context_u32_value(&parsed[1], 0, &val32)); + KUNIT_EXPECT_EQ(test, 0xd0c0b0a0U, val32); +} + +static void nvidia_ghes_vera_decodes_multi_context_covering_first(struct k= unit *test) +{ + static const u8 first_data[] =3D { + 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, + 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff, 0x00, + }; + static const u8 second_data[] =3D { + 0xa0, 0xb0, 0xc0, 0xd0, + }; + struct vera_synth_context contexts[] =3D { + { + .context_size =3D VERA_CONTEXT_HDR_SIZE + sizeof(first_data), + .format =3D 1, + .data =3D first_data, + .data_size =3D sizeof(first_data), + }, + { + .context_size =3D VERA_CONTEXT_HDR_SIZE + 16, + .format =3D 4, + .data =3D second_data, + .data_size =3D sizeof(second_data), + }, + }; + struct nvidia_ghes_decoded decoded =3D {}; + struct nvidia_ghes_vera_context parsed[2]; + size_t len; + u8 *buf; + u64 key, val; + u32 val32; + + buf =3D vera_make_synthetic_contexts(test, 1, VERA_CPU_INFO_SIZE, context= s, + ARRAY_SIZE(contexts), &len); + KUNIT_ASSERT_EQ(test, 0, nvidia_ghes_decode_vera(NULL, buf, len, &decoded= )); + KUNIT_EXPECT_EQ(test, 2, decoded.event_context_count); + KUNIT_ASSERT_EQ(test, 0, vera_context_at(&decoded, 0, &parsed[0])); + KUNIT_ASSERT_EQ(test, 0, vera_context_at(&decoded, 1, &parsed[1])); + KUNIT_EXPECT_EQ(test, VERA_CONTEXT_HDR_SIZE + sizeof(first_data), + parsed[0].context_size); + KUNIT_EXPECT_EQ(test, 1, parsed[0].data_format_type); + KUNIT_EXPECT_EQ(test, sizeof(first_data), parsed[0].data_size); + KUNIT_ASSERT_EQ(test, 0, + nvidia_ghes_vera_context_u64_pair(&parsed[0], 0, &key, &val)); + KUNIT_EXPECT_EQ(test, 0x8877665544332211ULL, key); + KUNIT_EXPECT_EQ(test, 0x00ffeeddccbbaa99ULL, val); + KUNIT_EXPECT_EQ(test, VERA_CONTEXT_HDR_SIZE + 16, + parsed[1].context_size); + KUNIT_EXPECT_EQ(test, 4, parsed[1].data_format_type); + KUNIT_EXPECT_EQ(test, sizeof(second_data), parsed[1].data_size); + KUNIT_ASSERT_EQ(test, 0, + nvidia_ghes_vera_context_u32_value(&parsed[1], 0, &val32)); + KUNIT_EXPECT_EQ(test, 0xd0c0b0a0U, val32); +} + +static void nvidia_ghes_vera_decodes_format2_u32_pairs(struct kunit *test) +{ + static const u8 data[] =3D { + 0x78, 0x56, 0x34, 0x12, 0xf0, 0xde, 0xbc, 0x9a, + }; + struct nvidia_ghes_decoded decoded =3D {}; + struct nvidia_ghes_vera_context context; + size_t len; + u8 *buf; + u32 key, val; + + buf =3D vera_make_synthetic_default(test, 2, data, sizeof(data), &len); + KUNIT_ASSERT_EQ(test, 0, nvidia_ghes_decode_vera(NULL, buf, len, &decoded= )); + KUNIT_ASSERT_EQ(test, 0, vera_context_at(&decoded, 0, &context)); + KUNIT_ASSERT_EQ(test, 1, nvidia_ghes_vera_context_entry_count(&context)); + KUNIT_ASSERT_EQ(test, 0, + nvidia_ghes_vera_context_u32_pair(&context, 0, &key, &val)); + KUNIT_EXPECT_EQ(test, 0x12345678U, key); + KUNIT_EXPECT_EQ(test, 0x9abcdef0U, val); +} + +static void nvidia_ghes_vera_decodes_format3_u64_values(struct kunit *test) +{ + static const u8 data[] =3D { + 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, + }; + struct nvidia_ghes_decoded decoded =3D {}; + struct nvidia_ghes_vera_context context; + size_t len; + u8 *buf; + u64 val; + + buf =3D vera_make_synthetic_default(test, 3, data, sizeof(data), &len); + KUNIT_ASSERT_EQ(test, 0, nvidia_ghes_decode_vera(NULL, buf, len, &decoded= )); + KUNIT_ASSERT_EQ(test, 0, vera_context_at(&decoded, 0, &context)); + KUNIT_ASSERT_EQ(test, 1, nvidia_ghes_vera_context_entry_count(&context)); + KUNIT_ASSERT_EQ(test, 0, + nvidia_ghes_vera_context_u64_value(&context, 0, &val)); + KUNIT_EXPECT_EQ(test, 0x0102030405060708ULL, val); +} + +static void nvidia_ghes_vera_decodes_format4_u32_values(struct kunit *test) +{ + static const u8 data[] =3D { + 0x78, 0x56, 0x34, 0x12, + }; + struct nvidia_ghes_decoded decoded =3D {}; + struct nvidia_ghes_vera_context context; + size_t len; + u8 *buf; + u32 val; + + buf =3D vera_make_synthetic_default(test, 4, data, sizeof(data), &len); + KUNIT_ASSERT_EQ(test, 0, nvidia_ghes_decode_vera(NULL, buf, len, &decoded= )); + KUNIT_ASSERT_EQ(test, 0, vera_context_at(&decoded, 0, &context)); + KUNIT_ASSERT_EQ(test, 1, nvidia_ghes_vera_context_entry_count(&context)); + KUNIT_ASSERT_EQ(test, 0, + nvidia_ghes_vera_context_u32_value(&context, 0, &val)); + KUNIT_EXPECT_EQ(test, 0x12345678U, val); +} + +static void nvidia_ghes_vera_rejects_truncated_event_header(struct kunit *= test) +{ + struct nvidia_ghes_decoded decoded =3D {}; + + KUNIT_EXPECT_EQ(test, -ENODATA, + nvidia_ghes_decode_vera(NULL, vera_l1_reset_id10, + VERA_EVENT_HDR_SIZE - 1, + &decoded)); +} + +static void nvidia_ghes_vera_rejects_truncated_cpu_info(struct kunit *test) +{ + struct nvidia_ghes_decoded decoded =3D {}; + + KUNIT_EXPECT_EQ(test, -ENODATA, + nvidia_ghes_decode_vera(NULL, vera_l1_reset_id10, + VERA_FIRST_CONTEXT_OFFSET - 1, + &decoded)); +} + +static void nvidia_ghes_vera_rejects_truncated_context_header(struct kunit= *test) +{ + struct nvidia_ghes_decoded decoded =3D {}; + + KUNIT_EXPECT_EQ(test, -ENODATA, + nvidia_ghes_decode_vera(NULL, vera_l1_reset_id10, + VERA_FIRST_CONTEXT_OFFSET + + VERA_CONTEXT_HDR_SIZE - 1, + &decoded)); +} + +static void nvidia_ghes_vera_rejects_bad_info_size(struct kunit *test) +{ + struct nvidia_ghes_decoded decoded =3D {}; + u8 *buf; + + buf =3D nvidia_ghes_kunit_memdup(test, vera_l1_reset_id10, sizeof(vera_l1= _reset_id10)); + buf[34] =3D 31; + + KUNIT_EXPECT_EQ(test, -EINVAL, + nvidia_ghes_decode_vera(NULL, buf, sizeof(vera_l1_reset_id10), &decoded= )); +} + +static void nvidia_ghes_vera_rejects_unsupported_version(struct kunit *tes= t) +{ + struct nvidia_ghes_decoded decoded =3D {}; + u8 *buf; + + buf =3D nvidia_ghes_kunit_memdup(test, vera_l1_reset_id10, sizeof(vera_l1= _reset_id10)); + buf[0] =3D 2; + + KUNIT_EXPECT_EQ(test, -EOPNOTSUPP, + nvidia_ghes_decode_vera(NULL, buf, sizeof(vera_l1_reset_id10), &decoded= )); +} + +static void nvidia_ghes_vera_rejects_unsupported_info_major_version(struct= kunit *test) +{ + struct nvidia_ghes_decoded decoded =3D {}; + u8 *buf; + int ret; + + buf =3D nvidia_ghes_kunit_memdup(test, vera_l1_reset_id10, + sizeof(vera_l1_reset_id10)); + put_unaligned_le16(0x0100, &buf[VERA_EVENT_HDR_SIZE]); + + ret =3D nvidia_ghes_decode_vera(NULL, buf, sizeof(vera_l1_reset_id10), + &decoded); + KUNIT_EXPECT_EQ(test, -EOPNOTSUPP, ret); +} + +static void nvidia_ghes_vera_accepts_newer_info_minor_version(struct kunit= *test) +{ + struct nvidia_ghes_decoded decoded =3D {}; + u8 *buf; + + buf =3D nvidia_ghes_kunit_memdup(test, vera_l1_reset_id10, + sizeof(vera_l1_reset_id10)); + put_unaligned_le16(0x00ff, &buf[VERA_EVENT_HDR_SIZE]); + + KUNIT_EXPECT_EQ(test, 0, + nvidia_ghes_decode_vera(NULL, buf, + sizeof(vera_l1_reset_id10), &decoded)); +} + +static void nvidia_ghes_vera_accepts_extended_cpu_info(struct kunit *test) +{ + static const u8 data[] =3D { + 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, + }; + struct nvidia_ghes_decoded decoded =3D {}; + struct nvidia_ghes_vera_context context; + size_t len; + u8 *buf; + u64 val; + + buf =3D vera_make_synthetic(test, 1, VERA_CPU_INFO_SIZE + 4, 3, + data, sizeof(data), &len); + KUNIT_ASSERT_EQ(test, 0, nvidia_ghes_decode_vera(NULL, buf, len, &decoded= )); + KUNIT_ASSERT_EQ(test, 0, vera_context_at(&decoded, 0, &context)); + KUNIT_EXPECT_EQ(test, VERA_CONTEXT_HDR_SIZE + 16, + context.context_size); + KUNIT_EXPECT_EQ(test, 3, context.data_format_type); + KUNIT_EXPECT_EQ(test, 8U, context.data_size); + KUNIT_EXPECT_EQ(test, 1, nvidia_ghes_vera_context_entry_count(&context)); + KUNIT_EXPECT_EQ(test, 0, + nvidia_ghes_vera_context_u64_value(&context, 0, &val)); + KUNIT_EXPECT_EQ(test, 0x0102030405060708ULL, val); +} + +static void nvidia_ghes_vera_rejects_short_context_size(struct kunit *test) +{ + struct nvidia_ghes_decoded decoded =3D {}; + u8 *buf; + + buf =3D nvidia_ghes_kunit_memdup(test, vera_l1_reset_id10, sizeof(vera_l1= _reset_id10)); + put_unaligned_le32(15, &buf[VERA_FIRST_CONTEXT_OFFSET]); + + KUNIT_EXPECT_EQ(test, -EINVAL, + nvidia_ghes_decode_vera(NULL, buf, sizeof(vera_l1_reset_id10), &decoded= )); +} + +static void nvidia_ghes_vera_rejects_data_size_exceeding_context_size(stru= ct kunit *test) +{ + static const u8 data[] =3D { + 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, + }; + struct nvidia_ghes_decoded decoded =3D {}; + size_t len; + u8 *buf; + + buf =3D vera_make_synthetic_default(test, 3, data, sizeof(data), &len); + put_unaligned_le32(VERA_CONTEXT_HDR_SIZE, + &buf[VERA_FIRST_CONTEXT_OFFSET]); + + KUNIT_EXPECT_EQ(test, -EINVAL, nvidia_ghes_decode_vera(NULL, buf, len, &d= ecoded)); +} + +static void nvidia_ghes_vera_rejects_unaligned_context_size(struct kunit *= test) +{ + static const u8 data[] =3D { + 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, + }; + struct nvidia_ghes_decoded decoded =3D {}; + size_t len; + u8 *buf; + + buf =3D vera_make_synthetic_default(test, 3, data, sizeof(data), &len); + put_unaligned_le32(VERA_CONTEXT_HDR_SIZE + sizeof(data), + &buf[VERA_FIRST_CONTEXT_OFFSET]); + + KUNIT_EXPECT_EQ(test, -EINVAL, nvidia_ghes_decode_vera(NULL, buf, len, &d= ecoded)); +} + +static void nvidia_ghes_vera_accepts_padded_context_size(struct kunit *tes= t) +{ + static const u8 first_data[] =3D { + 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, + }; + static const u8 second_data[] =3D { + 0x78, 0x56, 0x34, 0x12, + }; + struct vera_synth_context contexts[] =3D { + { + .context_size =3D VERA_CONTEXT_HDR_SIZE + 16, + .format =3D 3, + .data =3D first_data, + .data_size =3D sizeof(first_data), + }, + { + .context_size =3D VERA_CONTEXT_HDR_SIZE + 16, + .format =3D 4, + .data =3D second_data, + .data_size =3D sizeof(second_data), + }, + }; + struct nvidia_ghes_decoded decoded =3D {}; + struct nvidia_ghes_vera_context parsed[2]; + size_t len; + u8 *buf; + u32 val; + + buf =3D vera_make_synthetic_contexts(test, 1, VERA_CPU_INFO_SIZE, context= s, + ARRAY_SIZE(contexts), &len); + KUNIT_ASSERT_EQ(test, 0, nvidia_ghes_decode_vera(NULL, buf, len, &decoded= )); + KUNIT_EXPECT_EQ(test, 2, decoded.event_context_count); + KUNIT_ASSERT_EQ(test, 0, vera_context_at(&decoded, 0, &parsed[0])); + KUNIT_ASSERT_EQ(test, 0, vera_context_at(&decoded, 1, &parsed[1])); + KUNIT_EXPECT_EQ(test, VERA_CONTEXT_HDR_SIZE + 16, + parsed[0].context_size); + KUNIT_EXPECT_EQ(test, sizeof(first_data), parsed[0].data_size); + KUNIT_ASSERT_EQ(test, 0, + nvidia_ghes_vera_context_u32_value(&parsed[1], 0, &val)); + KUNIT_EXPECT_EQ(test, 0x12345678U, val); +} + +static void nvidia_ghes_vera_rejects_context_beyond_section(struct kunit *= test) +{ + static const u8 data[] =3D { + 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, + }; + struct nvidia_ghes_decoded decoded =3D {}; + size_t len; + u8 *buf; + + buf =3D vera_make_synthetic_default(test, 3, data, sizeof(data), &len); + KUNIT_EXPECT_EQ(test, -ENODATA, + nvidia_ghes_decode_vera(NULL, buf, len - 8, &decoded)); +} + +static void nvidia_ghes_vera_preserves_legacy_opaque_advance(struct kunit = *test) +{ + static const u8 opaque_data[] =3D { 0xaa, 0xbb, 0xcc }; + static const u8 value_data[] =3D { 0x78, 0x56, 0x34, 0x12 }; + struct vera_synth_context contexts[] =3D { + { + .context_size =3D VERA_CONTEXT_HDR_SIZE, + .format =3D 0, + .data =3D opaque_data, + .data_size =3D sizeof(opaque_data), + }, + { + .context_size =3D VERA_CONTEXT_HDR_SIZE + 16, + .format =3D 4, + .data =3D value_data, + .data_size =3D sizeof(value_data), + }, + }; + struct nvidia_ghes_decoded decoded =3D {}; + struct nvidia_ghes_vera_context parsed[2]; + size_t len; + u8 *buf; + u32 val; + + buf =3D vera_make_synthetic_contexts(test, 1, VERA_CPU_INFO_SIZE, context= s, + ARRAY_SIZE(contexts), &len); + KUNIT_ASSERT_EQ(test, 0, nvidia_ghes_decode_vera(NULL, buf, len, &decoded= )); + KUNIT_EXPECT_EQ(test, 2, decoded.event_context_count); + KUNIT_ASSERT_EQ(test, 0, vera_context_at(&decoded, 0, &parsed[0])); + KUNIT_ASSERT_EQ(test, 0, vera_context_at(&decoded, 1, &parsed[1])); + KUNIT_EXPECT_EQ(test, sizeof(opaque_data), parsed[0].data_size); + KUNIT_ASSERT_EQ(test, 0, + nvidia_ghes_vera_context_u32_value(&parsed[1], 0, &val)); + KUNIT_EXPECT_EQ(test, 0x12345678U, val); +} + +static void nvidia_ghes_vera_retains_contexts_before_failure(struct kunit = *test) +{ + static const u8 first_data[] =3D { 0x78, 0x56, 0x34, 0x12 }; + static const u8 second_data[] =3D { + 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, + }; + struct vera_synth_context contexts[] =3D { + { + .context_size =3D VERA_CONTEXT_HDR_SIZE + 16, + .format =3D 4, + .data =3D first_data, + .data_size =3D sizeof(first_data), + }, + { + .context_size =3D VERA_CONTEXT_HDR_SIZE + 16, + .format =3D 3, + .data =3D second_data, + .data_size =3D sizeof(second_data), + }, + }; + struct nvidia_ghes_decoded decoded =3D {}; + struct nvidia_ghes_vera_context context; + size_t second_offset =3D VERA_FIRST_CONTEXT_OFFSET + contexts[0].context_= size; + size_t len; + u8 *buf; + u32 val; + + buf =3D vera_make_synthetic_contexts(test, 1, VERA_CPU_INFO_SIZE, context= s, + ARRAY_SIZE(contexts), &len); + put_unaligned_le32(VERA_CONTEXT_HDR_SIZE + sizeof(second_data), + &buf[second_offset]); + + KUNIT_EXPECT_EQ(test, -EINVAL, + nvidia_ghes_decode_vera(NULL, buf, len, &decoded)); + KUNIT_EXPECT_EQ(test, 2, decoded.event_context_count); + KUNIT_EXPECT_EQ(test, 1, decoded.valid_context_count); + KUNIT_ASSERT_EQ(test, 0, vera_context_at(&decoded, 0, &context)); + KUNIT_EXPECT_EQ(test, sizeof(first_data), context.data_size); + KUNIT_ASSERT_EQ(test, 0, + nvidia_ghes_vera_context_u32_value(&context, 0, &val)); + KUNIT_EXPECT_EQ(test, 0x12345678U, val); +} + +static void nvidia_ghes_vera_accepts_all_wire_contexts(struct kunit *test) +{ + struct nvidia_ghes_vera_cursor cursor; + struct nvidia_ghes_vera_context context; + struct vera_synth_context *contexts; + struct nvidia_ghes_decoded decoded =3D {}; + static const u8 empty; + size_t len; + u8 *buf; + int i; + + contexts =3D kunit_kcalloc(test, U8_MAX, sizeof(*contexts), GFP_KERNEL); + KUNIT_ASSERT_NOT_NULL(test, contexts); + for (i =3D 0; i < U8_MAX; i++) { + contexts[i].context_size =3D VERA_CONTEXT_HDR_SIZE; + contexts[i].format =3D 0; + contexts[i].data =3D ∅ + contexts[i].data_size =3D 0; + } + + buf =3D vera_make_synthetic_contexts(test, 1, VERA_CPU_INFO_SIZE, context= s, + U8_MAX, &len); + KUNIT_ASSERT_EQ(test, 0, nvidia_ghes_decode_vera(NULL, buf, len, &decoded= )); + KUNIT_EXPECT_EQ(test, U8_MAX, decoded.event_context_count); + KUNIT_EXPECT_EQ(test, U8_MAX, decoded.valid_context_count); + + nvidia_ghes_vera_cursor_init(&decoded, &cursor); + for (i =3D 0; i < U8_MAX; i++) + KUNIT_ASSERT_EQ(test, 1, + nvidia_ghes_vera_cursor_next(&cursor, &context)); + KUNIT_EXPECT_EQ(test, 0, + nvidia_ghes_vera_cursor_next(&cursor, &context)); + KUNIT_EXPECT_EQ(test, 16, + nvidia_ghes_vera_print_context_count(&decoded)); +} + +static void nvidia_ghes_vera_accepts_zero_contexts(struct kunit *test) +{ + struct nvidia_ghes_vera_cursor cursor; + struct nvidia_ghes_vera_context context; + struct nvidia_ghes_decoded decoded =3D {}; + size_t len; + u8 *buf; + + buf =3D vera_make_synthetic_contexts(test, 1, VERA_CPU_INFO_SIZE, NULL, 0, + &len); + KUNIT_ASSERT_EQ(test, 0, + nvidia_ghes_decode_vera(NULL, buf, len, &decoded)); + KUNIT_EXPECT_EQ(test, 0, decoded.event_context_count); + KUNIT_EXPECT_EQ(test, 0, decoded.valid_context_count); + nvidia_ghes_vera_cursor_init(&decoded, &cursor); + KUNIT_EXPECT_EQ(test, 0, + nvidia_ghes_vera_cursor_next(&cursor, &context)); +} + +static void nvidia_ghes_vera_accepts_seventeen_contexts(struct kunit *test) +{ + struct nvidia_ghes_vera_cursor cursor; + struct nvidia_ghes_vera_context context; + struct vera_synth_context *contexts; + struct nvidia_ghes_decoded decoded =3D {}; + size_t len; + u8 *buf; + int i; + + contexts =3D kunit_kcalloc(test, 17, sizeof(*contexts), GFP_KERNEL); + KUNIT_ASSERT_NOT_NULL(test, contexts); + for (i =3D 0; i < 17; i++) + contexts[i].context_size =3D VERA_CONTEXT_HDR_SIZE; + + buf =3D vera_make_synthetic_contexts(test, 1, VERA_CPU_INFO_SIZE, context= s, + 17, &len); + KUNIT_ASSERT_EQ(test, 0, + nvidia_ghes_decode_vera(NULL, buf, len, &decoded)); + KUNIT_EXPECT_EQ(test, 17, decoded.event_context_count); + KUNIT_EXPECT_EQ(test, 17, decoded.valid_context_count); + nvidia_ghes_vera_cursor_init(&decoded, &cursor); + for (i =3D 0; i < 17; i++) + KUNIT_ASSERT_EQ(test, 1, + nvidia_ghes_vera_cursor_next(&cursor, &context)); + KUNIT_EXPECT_EQ(test, 0, + nvidia_ghes_vera_cursor_next(&cursor, &context)); +} + +static void nvidia_ghes_vera_accepts_schema_extensions_together(struct kun= it *test) +{ + static const u8 first_data[] =3D { + 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, + }; + struct vera_synth_context contexts[] =3D { + { + .context_size =3D VERA_CONTEXT_HDR_SIZE + 16, + .context_version =3D 2, + .format =3D 3, + .data_format_version =3D 3, + .data =3D first_data, + .data_size =3D sizeof(first_data), + }, + { + .context_size =3D VERA_CONTEXT_HDR_SIZE, + .context_version =3D 4, + .format =3D 0, + .data_format_version =3D 5, + }, + }; + struct nvidia_ghes_vera_cursor cursor; + struct nvidia_ghes_vera_context context; + struct nvidia_ghes_decoded decoded =3D {}; + size_t len; + u8 *section; + u8 *buf; + + buf =3D vera_make_synthetic_contexts(test, 1, VERA_CPU_INFO_SIZE + 4, + contexts, ARRAY_SIZE(contexts), + &len); + put_unaligned_le16(0x00ff, &buf[VERA_EVENT_HDR_SIZE]); + section =3D kunit_kzalloc(test, len + 7, GFP_KERNEL); + KUNIT_ASSERT_NOT_NULL(test, section); + memcpy(section, buf, len); + + KUNIT_ASSERT_EQ(test, 0, + nvidia_ghes_decode_vera(NULL, section, len + 7, &decoded)); + KUNIT_EXPECT_EQ(test, 2, decoded.event_context_count); + KUNIT_EXPECT_EQ(test, 2, decoded.valid_context_count); + nvidia_ghes_vera_cursor_init(&decoded, &cursor); + KUNIT_ASSERT_EQ(test, 1, + nvidia_ghes_vera_cursor_next(&cursor, &context)); + KUNIT_EXPECT_EQ(test, 2, context.context_version); + KUNIT_EXPECT_EQ(test, 3, context.data_format_version); + KUNIT_ASSERT_EQ(test, 1, + nvidia_ghes_vera_cursor_next(&cursor, &context)); + KUNIT_EXPECT_EQ(test, 4, context.context_version); + KUNIT_EXPECT_EQ(test, 5, context.data_format_version); + KUNIT_EXPECT_EQ(test, 7, cursor.remaining); + KUNIT_EXPECT_EQ(test, 0, + nvidia_ghes_vera_cursor_next(&cursor, &context)); +} + +static void nvidia_ghes_vera_retains_large_valid_prefix(struct kunit *test) +{ + struct nvidia_ghes_vera_cursor cursor; + struct nvidia_ghes_vera_context context; + struct vera_synth_context *contexts; + struct nvidia_ghes_decoded decoded =3D {}; + static const u8 empty; + size_t bad_offset; + size_t len; + u8 *buf; + int i; + + contexts =3D kunit_kcalloc(test, 18, sizeof(*contexts), GFP_KERNEL); + KUNIT_ASSERT_NOT_NULL(test, contexts); + for (i =3D 0; i < 18; i++) { + contexts[i].context_size =3D VERA_CONTEXT_HDR_SIZE; + contexts[i].format =3D 0; + contexts[i].data =3D ∅ + } + + buf =3D vera_make_synthetic_contexts(test, 1, VERA_CPU_INFO_SIZE, context= s, + 18, &len); + bad_offset =3D VERA_FIRST_CONTEXT_OFFSET + 17 * VERA_CONTEXT_HDR_SIZE; + put_unaligned_le32(VERA_CONTEXT_HDR_SIZE - 1, &buf[bad_offset]); + + KUNIT_EXPECT_EQ(test, -EINVAL, + nvidia_ghes_decode_vera(NULL, buf, len, &decoded)); + KUNIT_EXPECT_EQ(test, 18, decoded.event_context_count); + KUNIT_EXPECT_EQ(test, 17, decoded.valid_context_count); + KUNIT_EXPECT_EQ(test, 16, + nvidia_ghes_vera_print_context_count(&decoded)); + + nvidia_ghes_vera_cursor_init(&decoded, &cursor); + for (i =3D 0; i < 17; i++) + KUNIT_ASSERT_EQ(test, 1, + nvidia_ghes_vera_cursor_next(&cursor, &context)); + KUNIT_EXPECT_EQ(test, 0, + nvidia_ghes_vera_cursor_next(&cursor, &context)); +} + +static void nvidia_ghes_vera_rejects_data_beyond_section(struct kunit *tes= t) +{ + static const u8 data[] =3D { + 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, + }; + struct nvidia_ghes_decoded decoded =3D {}; + size_t len; + u8 *buf; + + buf =3D vera_make_synthetic_default(test, 3, data, sizeof(data), &len); + put_unaligned_le32(24, &buf[VERA_FIRST_CONTEXT_OFFSET + 12]); + + KUNIT_EXPECT_EQ(test, -ENODATA, nvidia_ghes_decode_vera(NULL, buf, len, &= decoded)); +} + +static void nvidia_ghes_vera_rejects_mis_sized_format1(struct kunit *test) +{ + struct nvidia_ghes_decoded decoded =3D {}; + u8 *buf; + + buf =3D nvidia_ghes_kunit_memdup(test, vera_crashdump_id_id40, + sizeof(vera_crashdump_id_id40)); + put_unaligned_le32(15, &buf[VERA_FIRST_CONTEXT_OFFSET + 12]); + + KUNIT_EXPECT_EQ(test, -EINVAL, + nvidia_ghes_decode_vera(NULL, buf, + sizeof(vera_crashdump_id_id40), + &decoded)); +} + +static void nvidia_ghes_vera_print_budget_is_section_wide(struct kunit *te= st) +{ + static const u8 data; + struct nvidia_ghes_vera_context ctx =3D { + .data_format_type =3D 1, + .data_size =3D 24 * 16, + .data =3D &data, + }; + unsigned int remaining =3D 32; + + KUNIT_EXPECT_EQ(test, 24, + nvidia_ghes_vera_context_print_count(&ctx, &remaining)); + KUNIT_EXPECT_EQ(test, 8U, remaining); + KUNIT_EXPECT_EQ(test, 8, + nvidia_ghes_vera_context_print_count(&ctx, &remaining)); + KUNIT_EXPECT_EQ(test, 0U, remaining); + KUNIT_EXPECT_EQ(test, 0, + nvidia_ghes_vera_context_print_count(&ctx, &remaining)); +} + +static void nvidia_ghes_vera_print_budget_rejects_null_remaining(struct ku= nit *test) +{ + struct nvidia_ghes_vera_context ctx =3D {}; + + KUNIT_EXPECT_EQ(test, -EINVAL, + nvidia_ghes_vera_context_print_count(&ctx, NULL)); +} + +static void nvidia_ghes_vera_accessors_reject_null_data(struct kunit *test) +{ + struct nvidia_ghes_vera_context ctx =3D { + .data_size =3D 16, + }; + u64 key64, val64; + u32 key32, val32; + + ctx.data_format_type =3D 1; + KUNIT_EXPECT_EQ(test, -EINVAL, + nvidia_ghes_vera_context_u64_pair(&ctx, 0, &key64, + &val64)); + ctx.data_format_type =3D 2; + KUNIT_EXPECT_EQ(test, -EINVAL, + nvidia_ghes_vera_context_u32_pair(&ctx, 0, &key32, + &val32)); + ctx.data_format_type =3D 3; + KUNIT_EXPECT_EQ(test, -EINVAL, + nvidia_ghes_vera_context_u64_value(&ctx, 0, &val64)); + ctx.data_format_type =3D 4; + KUNIT_EXPECT_EQ(test, -EINVAL, + nvidia_ghes_vera_context_u32_value(&ctx, 0, &val32)); +} + +static void nvidia_ghes_vera_rejects_mis_sized_format2(struct kunit *test) +{ + static const u8 data[] =3D { + 0x78, 0x56, 0x34, 0x12, 0xf0, 0xde, 0xbc, + }; + struct nvidia_ghes_decoded decoded =3D {}; + size_t len; + u8 *buf; + + buf =3D vera_make_synthetic_default(test, 2, data, sizeof(data), &len); + KUNIT_EXPECT_EQ(test, -EINVAL, nvidia_ghes_decode_vera(NULL, buf, len, &d= ecoded)); +} + +static void nvidia_ghes_vera_rejects_mis_sized_format3(struct kunit *test) +{ + static const u8 data[] =3D { + 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, + }; + struct nvidia_ghes_decoded decoded =3D {}; + size_t len; + u8 *buf; + + buf =3D vera_make_synthetic_default(test, 3, data, sizeof(data), &len); + KUNIT_EXPECT_EQ(test, -EINVAL, nvidia_ghes_decode_vera(NULL, buf, len, &d= ecoded)); +} + +static void nvidia_ghes_vera_rejects_mis_sized_format4(struct kunit *test) +{ + static const u8 data[] =3D { + 0x78, 0x56, 0x34, + }; + struct nvidia_ghes_decoded decoded =3D {}; + size_t len; + u8 *buf; + + buf =3D vera_make_synthetic_default(test, 4, data, sizeof(data), &len); + KUNIT_EXPECT_EQ(test, -EINVAL, nvidia_ghes_decode_vera(NULL, buf, len, &d= ecoded)); +} + +static void nvidia_ghes_vera_rejects_unsupported_source_device(struct kuni= t *test) +{ + struct nvidia_ghes_decoded decoded =3D {}; + u8 *buf; + + buf =3D nvidia_ghes_kunit_memdup(test, vera_l1_reset_id10, sizeof(vera_l1= _reset_id10)); + buf[2] =3D 1; + + KUNIT_EXPECT_EQ(test, -EOPNOTSUPP, + nvidia_ghes_decode_vera(NULL, buf, sizeof(vera_l1_reset_id10), &decoded= )); +} + +static void nvidia_ghes_vera_rejects_unsupported_data_format(struct kunit = *test) +{ + struct nvidia_ghes_decoded decoded =3D {}; + u8 *buf; + + buf =3D nvidia_ghes_kunit_memdup(test, vera_l1_reset_id10, sizeof(vera_l1= _reset_id10)); + put_unaligned_le16(5, &buf[VERA_FIRST_CONTEXT_OFFSET + 8]); + + KUNIT_EXPECT_EQ(test, -EOPNOTSUPP, + nvidia_ghes_decode_vera(NULL, buf, sizeof(vera_l1_reset_id10), &decoded= )); +} + +static void nvidia_ghes_vera_copies_non_nul_signature(struct kunit *test) +{ + struct nvidia_ghes_decoded decoded =3D {}; + u8 *buf; + + buf =3D nvidia_ghes_kunit_memdup(test, vera_l1_reset_id10, sizeof(vera_l1= _reset_id10)); + memcpy(&buf[16], "ABCDEFGHIJKLMNOP", 16); + + KUNIT_EXPECT_EQ(test, 0, + nvidia_ghes_decode_vera(NULL, buf, sizeof(vera_l1_reset_id10), &decoded= )); + KUNIT_EXPECT_STREQ(test, "ABCDEFGHIJKLMNOP", decoded.signature); + KUNIT_EXPECT_EQ(test, '\0', decoded.signature[16]); +} + +static void nvidia_ghes_guid_routes_grace(struct kunit *test) +{ + const guid_t guid =3D GUID_INIT(0x6d5244f2, 0x2712, 0x11ec, + 0xbe, 0xa7, 0xcb, 0x3f, 0xdb, 0x95, 0xc7, 0x86); + + KUNIT_EXPECT_EQ(test, NVIDIA_GHES_FORMAT_GRACE, + nvidia_ghes_format_from_guid(&guid)); +} + +static void nvidia_ghes_guid_routes_vera(struct kunit *test) +{ + const guid_t guid =3D GUID_INIT(0x9068e568, 0x6ca0, 0x11f0, + 0xae, 0xaf, 0x15, 0x93, 0x43, 0x59, 0x1e, 0xac); + + KUNIT_EXPECT_EQ(test, NVIDIA_GHES_FORMAT_VERA, + nvidia_ghes_format_from_guid(&guid)); +} + +static void nvidia_ghes_guid_rejects_unknown(struct kunit *test) +{ + const guid_t guid =3D GUID_INIT(0x00000000, 0x0000, 0x0000, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); + + KUNIT_EXPECT_EQ(test, NVIDIA_GHES_FORMAT_UNKNOWN, + nvidia_ghes_format_from_guid(&guid)); +} + +static void nvidia_ghes_grace_reg_pair_rejects_null_decoded(struct kunit *= test) +{ + u64 addr, val; + + KUNIT_EXPECT_EQ(test, -EINVAL, + nvidia_ghes_grace_reg_pair(NULL, 0, &addr, &val)); +} + +static void nvidia_ghes_grace_reg_pair_rejects_wrong_format(struct kunit *= test) +{ + struct nvidia_ghes_decoded decoded =3D { + .format =3D NVIDIA_GHES_FORMAT_VERA, + }; + u64 addr, val; + + KUNIT_EXPECT_EQ(test, -EINVAL, + nvidia_ghes_grace_reg_pair(&decoded, 0, &addr, &val)); +} + +static void nvidia_ghes_grace_reg_pair_rejects_null_regs(struct kunit *tes= t) +{ + struct nvidia_ghes_decoded decoded =3D { + .format =3D NVIDIA_GHES_FORMAT_GRACE, + .number_regs =3D 1, + .grace_regs =3D NULL, + }; + u64 addr, val; + + KUNIT_EXPECT_EQ(test, -EINVAL, + nvidia_ghes_grace_reg_pair(&decoded, 0, &addr, &val)); +} + +static void nvidia_ghes_grace_reg_pair_rejects_out_of_range(struct kunit *= test) +{ + struct nvidia_ghes_decoded decoded =3D { + .format =3D NVIDIA_GHES_FORMAT_GRACE, + .number_regs =3D 0, + }; + u64 addr, val; + + KUNIT_EXPECT_EQ(test, -ERANGE, + nvidia_ghes_grace_reg_pair(&decoded, 0, &addr, &val)); +} + +static struct kunit_case nvidia_ghes_test_cases[] =3D { + KUNIT_CASE(nvidia_ghes_grace_decodes_registers), + KUNIT_CASE(nvidia_ghes_grace_decodes_unaligned_payload), + KUNIT_CASE(nvidia_ghes_grace_accepts_zero_registers), + KUNIT_CASE(nvidia_ghes_grace_copies_non_nul_signature), + KUNIT_CASE(nvidia_ghes_grace_rejects_truncated_header), + KUNIT_CASE(nvidia_ghes_grace_rejects_truncated_registers), + KUNIT_CASE(nvidia_ghes_grace_reg_pair_rejects_null_decoded), + KUNIT_CASE(nvidia_ghes_grace_reg_pair_rejects_wrong_format), + KUNIT_CASE(nvidia_ghes_grace_reg_pair_rejects_null_regs), + KUNIT_CASE(nvidia_ghes_grace_reg_pair_rejects_out_of_range), + KUNIT_CASE(nvidia_ghes_vera_decodes_l1_reset), + KUNIT_CASE(nvidia_ghes_vera_decodes_crashdump_id), + KUNIT_CASE(nvidia_ghes_vera_decodes_crashdump_s1_opaque_context), + KUNIT_CASE(nvidia_ghes_vera_decodes_multi_context_aligned), + KUNIT_CASE(nvidia_ghes_vera_decodes_multi_context_covering_first), + KUNIT_CASE(nvidia_ghes_vera_decodes_format2_u32_pairs), + KUNIT_CASE(nvidia_ghes_vera_decodes_format3_u64_values), + KUNIT_CASE(nvidia_ghes_vera_decodes_format4_u32_values), + KUNIT_CASE(nvidia_ghes_vera_rejects_truncated_event_header), + KUNIT_CASE(nvidia_ghes_vera_rejects_truncated_cpu_info), + KUNIT_CASE(nvidia_ghes_vera_rejects_truncated_context_header), + KUNIT_CASE(nvidia_ghes_vera_rejects_bad_info_size), + KUNIT_CASE(nvidia_ghes_vera_rejects_unsupported_version), + KUNIT_CASE(nvidia_ghes_vera_rejects_unsupported_info_major_version), + KUNIT_CASE(nvidia_ghes_vera_accepts_newer_info_minor_version), + KUNIT_CASE(nvidia_ghes_vera_accepts_extended_cpu_info), + KUNIT_CASE(nvidia_ghes_vera_rejects_short_context_size), + KUNIT_CASE(nvidia_ghes_vera_rejects_data_size_exceeding_context_size), + KUNIT_CASE(nvidia_ghes_vera_rejects_unaligned_context_size), + KUNIT_CASE(nvidia_ghes_vera_accepts_padded_context_size), + KUNIT_CASE(nvidia_ghes_vera_rejects_context_beyond_section), + KUNIT_CASE(nvidia_ghes_vera_preserves_legacy_opaque_advance), + KUNIT_CASE(nvidia_ghes_vera_retains_contexts_before_failure), + KUNIT_CASE(nvidia_ghes_vera_accepts_all_wire_contexts), + KUNIT_CASE(nvidia_ghes_vera_accepts_zero_contexts), + KUNIT_CASE(nvidia_ghes_vera_accepts_seventeen_contexts), + KUNIT_CASE(nvidia_ghes_vera_accepts_schema_extensions_together), + KUNIT_CASE(nvidia_ghes_vera_retains_large_valid_prefix), + KUNIT_CASE(nvidia_ghes_vera_rejects_data_beyond_section), + KUNIT_CASE(nvidia_ghes_vera_rejects_mis_sized_format1), + KUNIT_CASE(nvidia_ghes_vera_print_budget_is_section_wide), + KUNIT_CASE(nvidia_ghes_vera_print_budget_rejects_null_remaining), + KUNIT_CASE(nvidia_ghes_vera_accessors_reject_null_data), + KUNIT_CASE(nvidia_ghes_vera_rejects_mis_sized_format2), + KUNIT_CASE(nvidia_ghes_vera_rejects_mis_sized_format3), + KUNIT_CASE(nvidia_ghes_vera_rejects_mis_sized_format4), + KUNIT_CASE(nvidia_ghes_vera_rejects_unsupported_source_device), + KUNIT_CASE(nvidia_ghes_vera_rejects_unsupported_data_format), + KUNIT_CASE(nvidia_ghes_vera_copies_non_nul_signature), + KUNIT_CASE(nvidia_ghes_guid_routes_grace), + KUNIT_CASE(nvidia_ghes_guid_routes_vera), + KUNIT_CASE(nvidia_ghes_guid_rejects_unknown), + {} +}; + +static struct kunit_suite nvidia_ghes_test_suite =3D { + .name =3D "acpi_apei_ghes_nvidia", + .test_cases =3D nvidia_ghes_test_cases, +}; + +kunit_test_suite(nvidia_ghes_test_suite); + +MODULE_IMPORT_NS("EXPORTED_FOR_KUNIT_TESTING"); +MODULE_DESCRIPTION("KUnit tests for NVIDIA GHES CPER parser helpers"); +MODULE_LICENSE("GPL"); --=20 2.50.1 (Apple Git-155)