From nobody Fri Oct 2 06:58:28 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 50A6A356773; Tue, 4 Aug 2026 11:34:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785843245; cv=none; b=m1y7QMWzUNsksv9HPC2HyrjaC/SgG8QW184jftVysHcDduLd9ffGtxVk2uzbEk/ZQgeRx7X68RNve1IBt9yajogR+BOkn45XJgqnMBLgbcASedXBMvmym9TiuLjak0EpWs7AG0+psleocwUmwYP9UVNfGNWmqhSSIJZZh+8vYn0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785843245; c=relaxed/simple; bh=G59VGDA6rhTXCxCP3iHlNCuRW3WqGdznOrZvREZZi/0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Bo46xx3HEFU0KpBIezXQVx/CQY3uEBes/nse6QsXXP/k09zi+06wJ9b+XdhERnM7atM2I5tWePtFsZvzUUkKsakf/gQmnolpFOAqNBt1HpozGcC06uHpcMnTc/aEEHodyS/+J5a+S2aKgldF4NY0wUA97mgMuGdF8D3qlWLNgks= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=H+sXVw+a; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="H+sXVw+a" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1785843244; x=1817379244; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=G59VGDA6rhTXCxCP3iHlNCuRW3WqGdznOrZvREZZi/0=; b=H+sXVw+a+Pg4TJvaKM34JdV+4FL3jenkUmRSk9AHwDQM3w3zI1bTjD5n 99ZMEYQhfPg0IGloI8Ro0ZY8XcNOhjYj8ARjqlA1AwaTTESqrFV6tcc4k 3Q4fFxxtXsZYjI2IYiXxaOq3l4WLSr5GTkBhUkjLBa13LNUPMc0rmXLq1 /mOSyz8qh6VM1sOzBr+JDoLfjkBbOAdW5E0E/cmbZUXOzMM30Ueyn5nVb 0cw0sqXtDcb09Zu1XcnhQi0gdU2Wfy63Thzgi003V6CWbQ8CLHMsY/v6W c0JaIw45yz9G/ktvDyU2QPMVT95tEZtzFnVGsLUztnahVuy8oDuVLPZz/ A==; X-CSE-ConnectionGUID: ZAh7y7BsQI2UUJU92+Rbdw== X-CSE-MsgGUID: 6x+8kSwqS3qVFry6LfnbDg== X-IronPort-AV: E=Sophos;i="6.25,204,1779174000"; d="scan'208";a="60737105" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Aug 2026 04:34:03 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.87.71) by chn-vm-ex4.mchp-main.com (10.10.87.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.45; Tue, 4 Aug 2026 04:34:03 -0700 Received: from che-ll-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 4 Aug 2026 04:33:52 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , CC: Krzysztof Kozlowski Subject: [PATCH v5 01/17] dt-bindings: iio: adc: at91-sama5d2: document sama7d65 Date: Tue, 4 Aug 2026 17:03:22 +0530 Message-ID: <20260804113338.261782-2-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260804113338.261782-1-varshini.rajendran@microchip.com> References: <20260804113338.261782-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add dt-binding documentation for sama7d65 ADC. sama7d65 requires an individual compatible to address the differences from its predecessor sama7g5. The main difference is the temperature calibration layout and its handling. Acked-by: Krzysztof Kozlowski Signed-off-by: Varshini Rajendran --- Documentation/devicetree/bindings/iio/adc/atmel,sama5d2-adc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iio/adc/atmel,sama5d2-adc.ya= ml b/Documentation/devicetree/bindings/iio/adc/atmel,sama5d2-adc.yaml index 4817b840977a..e8a65fdcd018 100644 --- a/Documentation/devicetree/bindings/iio/adc/atmel,sama5d2-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/atmel,sama5d2-adc.yaml @@ -15,6 +15,7 @@ properties: - atmel,sama5d2-adc - microchip,sam9x60-adc - microchip,sama7g5-adc + - microchip,sama7d65-adc =20 reg: maxItems: 1 --=20 2.34.1 From nobody Fri Oct 2 06:58:28 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B06CF34402B; Tue, 4 Aug 2026 11:34:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785843262; cv=none; b=XB7C0Th8bWefKzs5zsWL9v1KOefqTx8S6OJc1Xtq04sD2FmkqTvjQ4MDdmvFkxOtNKN/7Z9/xM7NRoQuoXKVALB1bnhkdXBBVYNV2ILYgUCfMd2O7cVkNxAldeDfRZK3PktQj4OMaT+xXyctAdkzHLMdPWMyi75iutSibP6um+I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785843262; c=relaxed/simple; bh=IZcSCPqZO3l5d2iyZ0Qc0KOp1vdICk1AW9fpfanl+M8=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=D3YJWKW1oxBFo05y/4GRsF3OP+nCpgHA1NmliLruZB62dFAm69Tm+32hi8mRfy+RcZn3j2vYfspHmVw4dwgo14AWUj/XN3GUGmHjmiKZo2Rj9B+LfI8jX7QpcZlrtUFJIXxlmG+ndY/7l/eZWbhErnevWNuJNWrb8ZvYBIfmi3M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=a7BgYKqy; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="a7BgYKqy" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1785843261; x=1817379261; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=IZcSCPqZO3l5d2iyZ0Qc0KOp1vdICk1AW9fpfanl+M8=; b=a7BgYKqyuW/Yvg8gMFvvVv6fRa5zZxjxIMTvkAbWS/P/dOfeJ5FWQ50N 1bW0digKzu/AY21g+CcEm9+bgq2eVbtPu4kSTci4yeA/WxWbghbdZ7TR1 7lzjLToIRd1xKfEvzrSO+OeoSH0ZJzmKBXYgdxsfKhy0Kg2M24lf9/L51 R6MFRiH155fh/miY0PBbXGhL2L5T0u1Vu5slohNR2hfaKPAH4NhDFCpDi IkyY6tCwv/LBUkFFtKOpWz0AejwG6nIJySLkJ8edAjxIKkvre/CwVajse FNZ4qZL8EaLQACvh8rB/c5LiPLWm3v5FpoE/+DFuWMLdJ3pQRYZPCpizJ A==; X-CSE-ConnectionGUID: 4yFAMHBdQxOTpCoL0PKOLA== X-CSE-MsgGUID: 9bo6NXMARqaViXPRtBB6Qg== X-IronPort-AV: E=Sophos;i="6.25,204,1779174000"; d="scan'208";a="61629495" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 04 Aug 2026 04:34:14 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Tue, 4 Aug 2026 04:34:13 -0700 Received: from che-ll-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 4 Aug 2026 04:34:03 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 02/17] nvmem: add DEFINE_FREE for nvmem_cell_put cleanup Date: Tue, 4 Aug 2026 17:03:23 +0530 Message-ID: <20260804113338.261782-3-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260804113338.261782-1-varshini.rajendran@microchip.com> References: <20260804113338.261782-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add cleanup.h helper for nvmem_cell_put() to enable automatic resource cleanup using __free(nvmem_cell_put) annotation. Use IS_ERR_OR_NULL() since nvmem_cell_get() can return error pointers, and passing an ERR_PTR to nvmem_cell_put() would cause issues. Signed-off-by: Varshini Rajendran --- include/linux/nvmem-consumer.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/linux/nvmem-consumer.h b/include/linux/nvmem-consumer.h index 34c0e58dfa26..35a2ea8b8957 100644 --- a/include/linux/nvmem-consumer.h +++ b/include/linux/nvmem-consumer.h @@ -9,6 +9,7 @@ #ifndef _LINUX_NVMEM_CONSUMER_H #define _LINUX_NVMEM_CONSUMER_H =20 +#include #include #include #include @@ -54,6 +55,9 @@ struct nvmem_cell *nvmem_cell_get(struct device *dev, con= st char *id); struct nvmem_cell *devm_nvmem_cell_get(struct device *dev, const char *id); void nvmem_cell_put(struct nvmem_cell *cell); void devm_nvmem_cell_put(struct device *dev, struct nvmem_cell *cell); + +DEFINE_FREE(nvmem_cell_put, struct nvmem_cell *, if (!IS_ERR_OR_NULL(_T)) = nvmem_cell_put(_T)) + void *nvmem_cell_read(struct nvmem_cell *cell, size_t *len); int nvmem_cell_write(struct nvmem_cell *cell, void *buf, size_t len); int nvmem_cell_read_u8(struct device *dev, const char *cell_id, u8 *val); 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charset="utf-8" Use __free(kfree) and __free(nvmem_cell_put) cleanup helpers in at91_adc_temp_sensor_init() to simplify error handling paths. Reviewed-by: Andy Shevchenko Signed-off-by: Varshini Rajendran --- drivers/iio/adc/at91-sama5d2_adc.c | 25 ++++++++++--------------- 1 file changed, 10 insertions(+), 15 deletions(-) diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama= 5d2_adc.c index e8a5285bb6d4..09390f082fc4 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -2249,8 +2249,6 @@ static int at91_adc_temp_sensor_init(struct at91_adc_= state *st, struct device *dev) { struct at91_adc_temp_sensor_clb *clb =3D &st->soc_info.temp_sensor_clb; - struct nvmem_cell *temp_calib; - u32 *buf; size_t len; int ret =3D 0; =20 @@ -2258,7 +2256,8 @@ static int at91_adc_temp_sensor_init(struct at91_adc_= state *st, return 0; =20 /* Get the calibration data from NVMEM. */ - temp_calib =3D nvmem_cell_get(dev, "temperature_calib"); + struct nvmem_cell *temp_calib __free(nvmem_cell_put) =3D + nvmem_cell_get(dev, "temperature_calib"); if (IS_ERR(temp_calib)) { ret =3D PTR_ERR(temp_calib); if (ret !=3D -ENOENT) @@ -2266,16 +2265,14 @@ static int at91_adc_temp_sensor_init(struct at91_ad= c_state *st, return ret; } =20 - buf =3D nvmem_cell_read(temp_calib, &len); - nvmem_cell_put(temp_calib); - if (IS_ERR(buf)) { - dev_err(dev, "Failed to read calibration data!\n"); - return PTR_ERR(buf); - } - if (len < AT91_ADC_TS_CLB_IDX_MAX * 4) { + u32 *buf __free(kfree) =3D nvmem_cell_read(temp_calib, &len); + if (IS_ERR(buf)) + return dev_err_probe(dev, PTR_ERR(buf), + "Failed to read calibration data!\n"); + + if (len < AT91_ADC_TS_CLB_IDX_MAX * sizeof(*buf)) { dev_err(dev, "Invalid calibration data!\n"); - ret =3D -EINVAL; - goto free_buf; + return -EINVAL; } =20 /* Store calibration data for later use. */ @@ -2288,9 +2285,7 @@ static int at91_adc_temp_sensor_init(struct at91_adc_= state *st, */ clb->p1 =3D clb->p1 * 1000; =20 -free_buf: - kfree(buf); - return ret; + return 0; } =20 static int at91_adc_probe(struct platform_device *pdev) --=20 2.34.1 From nobody Fri Oct 2 06:58:28 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 82E6B345CB2; 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charset="utf-8" Extend support to handle different temperature calibration layouts. Add a temperature calibration data layout structure to describe indexes of the factors P1, P4, P6, tag, minimum length of the packet and the scaling factors for P1 (p1_scale) which are SoC-specific instead of the older non scalable id structure. This helps handle the differences in the same function flow and prepare the calibration data to be applied. Reviewed-by: Eugen Hristev Signed-off-by: Varshini Rajendran --- drivers/iio/adc/at91-sama5d2_adc.c | 66 ++++++++++++++++++++++-------- 1 file changed, 48 insertions(+), 18 deletions(-) diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama= 5d2_adc.c index 09390f082fc4..82db8f2f4db0 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -444,6 +445,27 @@ static const struct at91_adc_reg_layout sama7g5_layout= =3D { #define at91_adc_writel(st, reg, val) \ writel_relaxed(val, (st)->base + (st)->soc_info.platform->layout->reg) =20 +/* Temperature calibration tag "ACST" in ASCII */ +#define AT91_TEMP_CALIB_TAG_ACST 0x41435354 + +/** + * struct at91_adc_temp_calib_layout - temperature calibration packet layo= ut + * @tag_idx: index of Packet tag in the NVMEM cell buffer + * @p1_idx: index of FT1_TEMP, equivalent to P1 in the NVMEM cell buffer + * @p4_idx: index of FT1_VPAT, equivalent to P4 in the NVMEM cell buffer + * @p6_idx: index of FT2_VBG, equivalent to P6 in the NVMEM cell buffer + * @min_len: minimum number of u32 words expected in the NVMEM cell buffer + * @p1_scale: scaling factor applied to P1 to convert to millicelcius + */ +struct at91_adc_temp_calib_layout { + unsigned int tag_idx; + unsigned int p1_idx; + unsigned int p4_idx; + unsigned int p6_idx; + unsigned int min_len; + struct u32_fract p1_scale; +}; + /** * struct at91_adc_platform - at91-sama5d2 platform information struct * @layout: pointer to the reg layout struct @@ -462,6 +484,7 @@ static const struct at91_adc_reg_layout sama7g5_layout = =3D { * @oversampling_avail_no: number of available oversampling values * @chan_realbits: realbits for registered channels * @temp_chan: temperature channel index + * @temp_calib_layout: temperature calibration packet layout * @temp_sensor: temperature sensor supported */ struct at91_adc_platform { @@ -479,6 +502,7 @@ struct at91_adc_platform { unsigned int oversampling_avail_no; unsigned int chan_realbits; unsigned int temp_chan; + const struct at91_adc_temp_calib_layout *temp_calib_layout; bool temp_sensor; }; =20 @@ -495,18 +519,13 @@ struct at91_adc_temp_sensor_clb { u32 p6; }; =20 -/** - * enum at91_adc_ts_clb_idx - calibration indexes in NVMEM buffer - * @AT91_ADC_TS_CLB_IDX_P1: index for P1 - * @AT91_ADC_TS_CLB_IDX_P4: index for P4 - * @AT91_ADC_TS_CLB_IDX_P6: index for P6 - * @AT91_ADC_TS_CLB_IDX_MAX: max index for temperature calibration packet = in OTP - */ -enum at91_adc_ts_clb_idx { - AT91_ADC_TS_CLB_IDX_P1 =3D 2, - AT91_ADC_TS_CLB_IDX_P4 =3D 5, - AT91_ADC_TS_CLB_IDX_P6 =3D 7, - AT91_ADC_TS_CLB_IDX_MAX =3D 19, +static const struct at91_adc_temp_calib_layout sama7g5_temp_calib =3D { + .tag_idx =3D 1, + .p1_idx =3D 2, + .p4_idx =3D 5, + .p6_idx =3D 7, + .min_len =3D 19, + .p1_scale =3D { .numerator =3D 1000, .denominator =3D 1 }, }; =20 /* Temperature sensor calibration - Vtemp voltage sensitivity to temperatu= re. */ @@ -744,6 +763,7 @@ static const struct at91_adc_platform sama7g5_platform = =3D { .chan_realbits =3D 16, .temp_sensor =3D true, .temp_chan =3D AT91_SAMA7G5_ADC_TEMP_CHANNEL, + .temp_calib_layout =3D &sama7g5_temp_calib, }; =20 static int at91_adc_chan_xlate(struct iio_dev *indio_dev, int chan) @@ -2249,12 +2269,19 @@ static int at91_adc_temp_sensor_init(struct at91_ad= c_state *st, struct device *dev) { struct at91_adc_temp_sensor_clb *clb =3D &st->soc_info.temp_sensor_clb; + const struct at91_adc_temp_calib_layout *layout; size_t len; int ret =3D 0; =20 if (!st->soc_info.platform->temp_sensor) return 0; =20 + layout =3D st->soc_info.platform->temp_calib_layout; + if (!layout) + return -ENODEV; + if (!layout->p1_scale.denominator) + return -EINVAL; + /* Get the calibration data from NVMEM. */ struct nvmem_cell *temp_calib __free(nvmem_cell_put) =3D nvmem_cell_get(dev, "temperature_calib"); @@ -2270,20 +2297,23 @@ static int at91_adc_temp_sensor_init(struct at91_ad= c_state *st, return dev_err_probe(dev, PTR_ERR(buf), "Failed to read calibration data!\n"); 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charset="utf-8" Add additional condition to validate the calibration data read from the NVMEM cell using the TAG of the packet. Signed-off-by: Varshini Rajendran --- drivers/iio/adc/at91-sama5d2_adc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama= 5d2_adc.c index 82db8f2f4db0..5b21367cf6b4 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -2297,7 +2297,8 @@ static int at91_adc_temp_sensor_init(struct at91_adc_= state *st, return dev_err_probe(dev, PTR_ERR(buf), "Failed to read calibration data!\n"); =20 - if (len < layout->min_len * sizeof(*buf)) { + if (len < layout->min_len * sizeof(*buf) || + buf[layout->tag_idx] !=3D AT91_TEMP_CALIB_TAG_ACST) { dev_err(dev, "Invalid calibration data!\n"); return -EINVAL; } --=20 2.34.1 From nobody Fri Oct 2 06:58:28 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E34E0349CD2; Tue, 4 Aug 2026 11:34:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785843300; cv=none; b=Gg9n3NctJgYR190dW6XxXtYHGBdA4PnRSkrEMOIr54RsAP2bI2uuoiCu2hu//lO2wf5X0niqI/RuEZrAxB+835mrN9uvNzy+1YIFHbC9avsbSD4ryqSoV3QCXL19TZFcoozzYDOkxAh3KCs7AlV/8EsS/xC46n9xbNY1RpWOGc4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785843300; c=relaxed/simple; bh=qCks5QmHaWli0znQDgqe7ceH6hFdVyHKYF2/F2T/0N0=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=nISJtjT24OvCXW96hnUhJ0U0WEnLj5+fPceL32vcy9jdG4PR9SwhUyrp8VyMA239cWCTAW5epVCMlFPQx13Ul6nBhqQ4L5Gs4eiWz/44JU+GgtiAnxJ8xmV+9R7X9hzVv3MJLwLdn/kF5LErz3Mcp6S8ziGHI9Lo7CjUTR6a5gk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=xBZ6+giu; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="xBZ6+giu" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1785843298; x=1817379298; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=qCks5QmHaWli0znQDgqe7ceH6hFdVyHKYF2/F2T/0N0=; b=xBZ6+giuVb6zNZ6j8mVGEI9GwQA5tmPtXmhO8EHSdzuVwOPiopujbhVk P18TdsUFJs6rs8yNAEnn484S8wN2NYZTtxNebQ0kS2ubWe45cX68TN1xS 3cenwdzr38UE35P7sO3g7LWDZKGd/C3GCdmrdfOobrBSNiw6vGKyvymmm 3dvWI+0r2GvK7NO0/9RbUbqOJ7XUSlO/nwO2ozRhIzhFCTeDIC653L9EN 3Y3cu2PcSSwENoHawj/gmH95Kr6N9jbTPp+enj2RpapXB0qvDc2l1h3AX Kp6yEKaxK5d9IPIr7FjFI66xz3L6D00YNGjolZ1a0OxZRDuMc1SoXNxhA g==; X-CSE-ConnectionGUID: 4xEEaEPvTgOvr5QEq3UPIQ== X-CSE-MsgGUID: 5r93qYngSDKfxPhyB9+CLg== X-IronPort-AV: E=Sophos;i="6.25,204,1779174000"; d="scan'208";a="71197889" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 04 Aug 2026 04:34:57 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Tue, 4 Aug 2026 04:34:57 -0700 Received: from che-ll-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 4 Aug 2026 04:34:47 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 06/17] iio: adc: at91-sama5d2_adc: remove unnecessary casts in of_device_id Date: Tue, 4 Aug 2026 17:03:27 +0530 Message-ID: <20260804113338.261782-7-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260804113338.261782-1-varshini.rajendran@microchip.com> References: <20260804113338.261782-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The .data field in struct of_device_id is 'const void *', so explicit casts are unnecessary when assigning addresses of const structs. Reviewed-by: Eugen Hristev Signed-off-by: Varshini Rajendran --- drivers/iio/adc/at91-sama5d2_adc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama= 5d2_adc.c index 5b21367cf6b4..3e9feb824a66 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -2628,10 +2628,10 @@ static const struct dev_pm_ops at91_adc_pm_ops =3D { static const struct of_device_id at91_adc_dt_match[] =3D { { .compatible =3D "atmel,sama5d2-adc", - .data =3D (const void *)&sama5d2_platform, + .data =3D &sama5d2_platform, }, { .compatible =3D "microchip,sama7g5-adc", - .data =3D (const void *)&sama7g5_platform, + .data =3D &sama7g5_platform, }, { /* sentinel */ } --=20 2.34.1 From nobody Fri Oct 2 06:58:28 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 17CDD345CB2; Tue, 4 Aug 2026 11:35:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785843310; cv=none; b=R0Jpp9B6xI8S9nORDAy9dNOYiJZZtNRhfV5w31659O5Yc/Fy1P8sb+GopyRkmIAIMdaeqyA/HxHpvXkekbb+e+QF07swhs0HL1KFUS0ghndUFal7oYdXkBvezFsapDkaIDlam3IU5h++6RZNFuqmGpz8S9dDFO7L5/pCdvoRkPY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785843310; c=relaxed/simple; bh=9TV+tsofy6TCtX8zVKSBqg0wGh2pcJEEZrqQnPraG7U=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=c78Vg/lQ9DJ/KPHKtc3qgB6PjKI5/KYyibtKzGPYL7P4Qx1gsyvVJTfMT3mEqKx4dlY5YAAFfLsS1g6zGo8fmoM/jGTFp7qhPfYOyFV1OO8kBOZf37fo7Bh+MqsPOHu3BqGM91zA9ez6sDgY/7bYC24ZWMRxtRWc/eCUCqGeXxg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=Yba0J31z; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="Yba0J31z" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1785843309; x=1817379309; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=9TV+tsofy6TCtX8zVKSBqg0wGh2pcJEEZrqQnPraG7U=; b=Yba0J31zOaXKkQLGLySznWEkLuzoNCz8mvmAcRe6wDcOsHWPRDePa3TU 6OUtmsOfcQPRjJCkmNnFBgXD2/x0HieNNst79dnDeurLQd0t7IC/wVVm7 TQmM9CuSza15zGRkbqjYa3jVwDhRGWLxuCwp4+uFH8H3JIxuuN496XlRW K9sAIXitUxUrQ3KgFKiRGbNzaTz70BTTIB46YnVXy9/zRgBrtuQzS6Rhf KI6YoE4Qtx17OCQpIOorkmjVUrTjID0ipsQvTXtE2LcBttGDh75w8Dscw CDe3aedWScWweq+SpVvRzFsUdk+oCsxBKI0Cd1hSw6HDgmeP6xKKwMhHN w==; X-CSE-ConnectionGUID: yfxC7KBAQd6vPqPozAyiQg== X-CSE-MsgGUID: GFuF1eQFRsChfJj6SXdpgA== X-IronPort-AV: E=Sophos;i="6.25,204,1779174000"; d="scan'208";a="60737177" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 04 Aug 2026 04:35:08 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Tue, 4 Aug 2026 04:35:07 -0700 Received: from che-ll-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 4 Aug 2026 04:34:57 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 07/17] iio: adc: at91-sama5d2_adc: adapt the driver for sama7d65 Date: Tue, 4 Aug 2026 17:03:28 +0530 Message-ID: <20260804113338.261782-8-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260804113338.261782-1-varshini.rajendran@microchip.com> References: <20260804113338.261782-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for sama7d65 ADC. The differences are highlighted with the compatible. The calibration data layout is the main difference. Update Kconfig help text to mention SAMA7 SoC family support. Signed-off-by: Varshini Rajendran --- drivers/iio/adc/Kconfig | 2 +- drivers/iio/adc/at91-sama5d2_adc.c | 30 ++++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+), 1 deletion(-) diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 3755a81c1efd..85b443853a08 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -647,7 +647,7 @@ config AT91_SAMA5D2_ADC select IIO_TRIGGERED_BUFFER help Say yes here to build support for Atmel SAMA5D2 ADC which is - available on SAMA5D2 SoC family. + available on SAMA5D2 and SAMA7 SoC families. =20 To compile this driver as a module, choose M here: the module will be called at91-sama5d2_adc. diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama= 5d2_adc.c index 3e9feb824a66..c1e5139a058c 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -528,6 +528,15 @@ static const struct at91_adc_temp_calib_layout sama7g5= _temp_calib =3D { .p1_scale =3D { .numerator =3D 1000, .denominator =3D 1 }, }; =20 +static const struct at91_adc_temp_calib_layout sama7d65_temp_calib =3D { + .tag_idx =3D 1, + .p1_idx =3D 3, + .p4_idx =3D 2, + .p6_idx =3D 5, + .min_len =3D 11, + .p1_scale =3D { .numerator =3D 1, .denominator =3D 1000 }, +}; + /* Temperature sensor calibration - Vtemp voltage sensitivity to temperatu= re. */ #define AT91_ADC_TS_VTEMP_DT (2080U) =20 @@ -766,6 +775,24 @@ static const struct at91_adc_platform sama7g5_platform= =3D { .temp_calib_layout =3D &sama7g5_temp_calib, }; =20 +static const struct at91_adc_platform sama7d65_platform =3D { + .layout =3D &sama7g5_layout, + .adc_channels =3D &at91_sama7g5_adc_channels, + .nr_channels =3D AT91_SAMA7G5_SINGLE_CHAN_CNT + + AT91_SAMA7G5_DIFF_CHAN_CNT + + AT91_SAMA7G5_TEMP_CHAN_CNT, + .max_channels =3D ARRAY_SIZE(at91_sama7g5_adc_channels), + .max_index =3D AT91_SAMA7G5_MAX_CHAN_IDX, + .hw_trig_cnt =3D AT91_SAMA7G5_HW_TRIG_CNT, + .osr_mask =3D GENMASK(18, 16), + .oversampling_avail =3D { 1, 4, 16, 64, 256 }, + .oversampling_avail_no =3D 5, + .chan_realbits =3D 16, + .temp_sensor =3D true, + .temp_chan =3D AT91_SAMA7G5_ADC_TEMP_CHANNEL, + .temp_calib_layout =3D &sama7d65_temp_calib, +}; + static int at91_adc_chan_xlate(struct iio_dev *indio_dev, int chan) { int i; @@ -2632,6 +2659,9 @@ static const struct of_device_id at91_adc_dt_match[] = =3D { }, { .compatible =3D "microchip,sama7g5-adc", .data =3D &sama7g5_platform, + }, { + .compatible =3D "microchip,sama7d65-adc", + .data =3D &sama7d65_platform, }, { /* sentinel */ } --=20 2.34.1 From nobody Fri Oct 2 06:58:28 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 41B0A345CB2; Tue, 4 Aug 2026 11:35:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785843321; cv=none; b=kj0HpM76N1eZ0NA0iK91MavjkQn7CPsXPyAYrtkVJG1YEir/Xn24qX4t+21PiB+fQ5eYqkiXLvB+4u7SuI9yMYKflogDDnNwRW+wbrfyKFijl3Z0RqTMHT4htiBebxKlKvSJCelGD/hZoqgAXrVYTXGYhLxektAmQRoa5udHq7M= ARC-Message-Signature: i=1; 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Tue, 4 Aug 2026 04:35:18 -0700 Received: from che-ll-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 4 Aug 2026 04:35:08 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , CC: Conor Dooley Subject: [PATCH v5 08/17] dt-bindings: nvmem: microchip,sama7g5-otpc: add sama7d65 and dt node example Date: Tue, 4 Aug 2026 17:03:29 +0530 Message-ID: <20260804113338.261782-9-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260804113338.261782-1-varshini.rajendran@microchip.com> References: <20260804113338.261782-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for sama7d65 and a dt node example that shows tag can be used to reference a packet stored in the OTP memory. Signed-off-by: Varshini Rajendran Acked-by: Conor Dooley --- .../nvmem/microchip,sama7g5-otpc.yaml | 28 +++++++++++++++++-- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc= .yaml b/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml index cc25f2927682..04b44660554e 100644 --- a/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml +++ b/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml @@ -20,9 +20,15 @@ allOf: =20 properties: compatible: - items: - - const: microchip,sama7g5-otpc - - const: syscon + oneOf: + - items: + - const: microchip,sama7g5-otpc + - const: syscon + - items: + - enum: + - microchip,sama7d65-otpc + - const: microchip,sama7g5-otpc + - const: syscon =20 reg: maxItems: 1 @@ -48,4 +54,20 @@ examples: }; }; =20 + - | + efuse@e8c00000 { + compatible =3D "microchip,sama7d65-otpc", "microchip,sama7g5-otpc"= , "syscon"; + reg =3D <0xe8c00000 0x100>; + + nvmem-layout { + compatible =3D "fixed-layout"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + calib@41435354 { + reg =3D <0x41435354 0x2c>; /* Temp calib data packet TA= G */ + }; + }; + }; + ... --=20 2.34.1 From nobody Fri Oct 2 06:58:28 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7083F357CFA; Tue, 4 Aug 2026 11:35:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785843333; cv=none; b=pfSqMxFq2AhfniVzZzNMPwpv5D/3AnnjO5IZE/vs5gDRs7+VL73TXTElqQqLq2Cw5qBqGQbt8cpqh2KxD3sHz50+dNqW+y9p9uQOufnYGLwYKlAB/6JcXbmijbrMrk1kB1OGRu+HP0RWKs0/zqkR0JUK1A/xPl/aIoXdJGJLz4U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785843333; c=relaxed/simple; bh=dG6ESQyQOwjAmFrHt474u7r/XzkQZj9i23i/nKYLZDs=; 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Tue, 4 Aug 2026 04:35:30 -0700 Received: from che-ll-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 4 Aug 2026 04:35:19 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 09/17] nvmem: microchip-otpc: nvmem: microchip-otpc: add tag-based packet lookup Date: Tue, 4 Aug 2026 17:03:30 +0530 Message-ID: <20260804113338.261782-10-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260804113338.261782-1-varshini.rajendran@microchip.com> References: <20260804113338.261782-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for accessing OTP packets by their tag which is a FourCC while preserving backward compatibility with the existing ID-based lookup. The OTP memory layout can vary across devices and may change over time, making the packet ID approach unreliable when the memory map is not known in advance. The packet tag provides a reliable way to identify and access packets without prior knowledge of the OTP memory layout. Two offset encodings are now supported: 1. Legacy ID-based: offset =3D OTP_PKT(id) =3D id * 4 Used in DT as: reg =3D ; 2. TAG-based: offset =3D 4-byte ASCII packet tag (FourCC) Used in DT as: reg =3D <0x41435354 0x4c>; (tag "ACST") The driver resolves offsets matching valid legacy selectors (multiples of 4 within the packet count) through ID lookup, falling back to tag lookup for other valid values. This ensures existing device trees continue to work while enabling new tag-based access. During probe, packet meta data including the tag is read and cached. The stride of the nvmem memory is set to 1 in order to support tag based offsets, comment in the header file is updated accordingly. Signed-off-by: Varshini Rajendran --- drivers/nvmem/microchip-otpc.c | 117 ++++++++++++++++-- .../nvmem/microchip,sama7g5-otpc.h | 4 +- 2 files changed, 110 insertions(+), 11 deletions(-) diff --git a/drivers/nvmem/microchip-otpc.c b/drivers/nvmem/microchip-otpc.c index df979e8549fd..a17f82afdc37 100644 --- a/drivers/nvmem/microchip-otpc.c +++ b/drivers/nvmem/microchip-otpc.c @@ -23,6 +23,8 @@ #define MCHP_OTPC_SR_READ BIT(6) #define MCHP_OTPC_HR (0x20) #define MCHP_OTPC_HR_SIZE GENMASK(15, 8) +#define MCHP_OTPC_HR_PACKET GENMASK(2, 0) +#define MCHP_OTPC_HR_PACKET_REGULAR 1 #define MCHP_OTPC_DR (0x24) =20 #define MCHP_OTPC_NAME "mchp-otpc" @@ -47,11 +49,13 @@ struct mchp_otpc { * @list: list head * @id: packet ID * @offset: packet offset (in words) in OTP memory + * @tag: 4-byte ASCII (FourCC) tag of the packet */ struct mchp_otpc_packet { struct list_head list; u32 id; u32 offset; + u32 tag; }; =20 static struct mchp_otpc_packet *mchp_otpc_id_to_packet(struct mchp_otpc *o= tpc, @@ -70,6 +74,52 @@ static struct mchp_otpc_packet *mchp_otpc_id_to_packet(s= truct mchp_otpc *otpc, return NULL; } =20 +static struct mchp_otpc_packet *mchp_otpc_tag_to_packet(struct mchp_otpc *= otpc, u32 tag) +{ + struct mchp_otpc_packet *packet; + + list_for_each_entry(packet, &otpc->packets, list) { + if (packet->tag =3D=3D tag) + return packet; + } + + return NULL; +} + +static bool mchp_otpc_is_valid_fourcc(u32 tag) +{ + int i; + u8 c; + + for (i =3D 0; i < 4; i++) { + c =3D (tag >> (i * 8)) & 0xff; + if (c < 0x20 || c > 0x7e) + return false; + } + + return true; +} + +static struct mchp_otpc_packet *mchp_otpc_resolve_packet(struct mchp_otpc = *otpc, u32 off) +{ + /* + * Legacy id based packet access: offset =3D id * 4 + * Inside the driver we use continuous unsigned integer numbers + * for packet id, thus divide off by 4 before passing it to + * mchp_otpc_id_to_packet(). + */ + u32 remainder =3D off % 4; + u32 id =3D off / 4; + + if (!remainder && id < otpc->npackets) + return mchp_otpc_id_to_packet(otpc, id); + + /* + * TAG-based packet access: offset is a 4-byte ASCII tag (FourCC) + */ + return mchp_otpc_tag_to_packet(otpc, off); +} + static int mchp_otpc_prepare_read(struct mchp_otpc *otpc, unsigned int offset) { @@ -140,8 +190,29 @@ static int mchp_otpc_prepare_read(struct mchp_otpc *ot= pc, * offset returned by hardware. * * For this, the read function will return the first requested bytes in the - * packet. The user will have to be aware of the memory footprint before d= oing - * the read request. + * packet. + * + * Two offset encodings are supported: + * + * 1. Legacy ID-based: offset =3D OTP_PKT(id) =3D id * 4 + * Used in DT as: reg =3D ; + * 2. TAG-based: offset =3D 4-byte ASCII packet tag (FourCC) + * Used in DT as: reg =3D <0x41435354 0x4c>; (tag "ACST") + * + * To use the legacy ID based packet lookup the user will have to be aware= of + * the memory footprint before doing the read request. + * + * But by using the TAG based packet lookup, the user won't have to be awa= re + * of the memory footprint before doing the read request since this driver= has + * it abstracted and taken care of. + * + * Practically, there is no way of knowing the mapping of the OTP memory t= able + * in advance for every device. But by using the packet tag - the identifi= er + * ASCII value (FourCC), the packets can be recognized without being aware= of the + * flashed OTP memory map table and the payload can be acquired reliably. + * + * While the legacy ID based lookup is still supported, TAG based approach= is + * recommended. */ static int mchp_otpc_read(void *priv, unsigned int off, void *val, size_t bytes) @@ -154,12 +225,11 @@ static int mchp_otpc_read(void *priv, unsigned int of= f, void *val, int ret, payload_size; =20 /* - * We reach this point with off being multiple of stride =3D 4 to - * be able to cross the subsystem. Inside the driver we use continuous - * unsigned integer numbers for packet id, thus divide off by 4 - * before passing it to mchp_otpc_id_to_packet(). + * From this point the offset has to be translated into the actual + * packet. For this we traverse the table of contents stored in a list + * "packet" based on the access type - packet id or tag. */ - packet =3D mchp_otpc_id_to_packet(otpc, off / 4); + packet =3D mchp_otpc_resolve_packet(otpc, off); if (!packet) return -EINVAL; offset =3D packet->offset; @@ -190,10 +260,25 @@ static int mchp_otpc_read(void *priv, unsigned int of= f, void *val, return 0; } =20 +static int mchp_otpc_read_packet_tag(struct mchp_otpc *otpc, unsigned int = offset, + unsigned int *tag) +{ + int ret; + + ret =3D mchp_otpc_prepare_read(otpc, offset); + if (ret) + return ret; + + writel_relaxed(0, otpc->base + MCHP_OTPC_AR); + *tag =3D readl_relaxed(otpc->base + MCHP_OTPC_DR); + + return 0; +} + static int mchp_otpc_init_packets_list(struct mchp_otpc *otpc, u32 *size) { struct mchp_otpc_packet *packet; - u32 word, word_pos =3D 0, id =3D 0, npackets =3D 0, payload_size; + u32 word, word_pos =3D 0, id =3D 0, npackets =3D 0, payload_size, type; int ret; =20 INIT_LIST_HEAD(&otpc->packets); @@ -215,6 +300,20 @@ static int mchp_otpc_init_packets_list(struct mchp_otp= c *otpc, u32 *size) =20 packet->id =3D id++; packet->offset =3D word_pos; + type =3D FIELD_GET(MCHP_OTPC_HR_PACKET, word); + + if (type =3D=3D MCHP_OTPC_HR_PACKET_REGULAR) { + ret =3D mchp_otpc_read_packet_tag(otpc, packet->offset, + &packet->tag); + if (ret) + return ret; + + if (!mchp_otpc_is_valid_fourcc(packet->tag)) + packet->tag =3D 0; + } else { + packet->tag =3D 0; + } + INIT_LIST_HEAD(&packet->list); list_add_tail(&packet->list, &otpc->packets); =20 @@ -236,7 +335,7 @@ static struct nvmem_config mchp_nvmem_config =3D { .type =3D NVMEM_TYPE_OTP, .read_only =3D true, .word_size =3D 4, - .stride =3D 4, + .stride =3D 1, .reg_read =3D mchp_otpc_read, }; =20 diff --git a/include/dt-bindings/nvmem/microchip,sama7g5-otpc.h b/include/d= t-bindings/nvmem/microchip,sama7g5-otpc.h index f570b23165a2..5f72e75ad091 100644 --- a/include/dt-bindings/nvmem/microchip,sama7g5-otpc.h +++ b/include/dt-bindings/nvmem/microchip,sama7g5-otpc.h @@ -4,8 +4,8 @@ #define _DT_BINDINGS_NVMEM_MICROCHIP_OTPC_H =20 /* - * Need to have it as a multiple of 4 as NVMEM memory is registered with - * stride =3D 4. + * Need to have it as a multiple of 4 for the legacy id based packet + * access. */ #define OTP_PKT(id) ((id) * 4) =20 --=20 2.34.1 From nobody Fri Oct 2 06:58:28 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1E81E35E1AE; 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charset="utf-8" Add validation of OTP memory accessibility and emulation mode status during probe. When the boot packet is not configured, emulation mode allows access to the other packets. When both are not available an informational message is logged to help with debugging. Signed-off-by: Varshini Rajendran --- drivers/nvmem/microchip-otpc.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/nvmem/microchip-otpc.c b/drivers/nvmem/microchip-otpc.c index a17f82afdc37..6b0184423463 100644 --- a/drivers/nvmem/microchip-otpc.c +++ b/drivers/nvmem/microchip-otpc.c @@ -18,6 +18,7 @@ #define MCHP_OTPC_CR_READ BIT(6) #define MCHP_OTPC_MR (0x4) #define MCHP_OTPC_MR_ADDR GENMASK(31, 16) +#define MCHP_OTPC_MR_EMUL BIT(7) #define MCHP_OTPC_AR (0x8) #define MCHP_OTPC_SR (0xc) #define MCHP_OTPC_SR_READ BIT(6) @@ -343,7 +344,8 @@ static int mchp_otpc_probe(struct platform_device *pdev) { struct nvmem_device *nvmem; struct mchp_otpc *otpc; - u32 size; + bool emul_enable; + u32 size, mr_val; int ret; =20 otpc =3D devm_kzalloc(&pdev->dev, sizeof(*otpc), GFP_KERNEL); @@ -355,10 +357,22 @@ static int mchp_otpc_probe(struct platform_device *pd= ev) return PTR_ERR(otpc->base); =20 otpc->dev =3D &pdev->dev; + + mr_val =3D readl_relaxed(otpc->base + MCHP_OTPC_MR); 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charset="utf-8" Add CPU OPPs table for SAMA7D65. Signed-off-by: Varshini Rajendran --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 36 +++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/= microchip/sama7d65.dtsi index ec200848c153..dfac17e34e65 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -35,6 +35,7 @@ cpu0: cpu@0 { d-cache-size =3D <0x8000>; // L1, 32 KB i-cache-size =3D <0x8000>; // L1, 32 KB next-level-cache =3D <&L2>; + operating-points-v2 =3D <&cpu_opp_table>; =20 L2: l2-cache { compatible =3D "cache"; @@ -45,6 +46,41 @@ L2: l2-cache { }; }; =20 + cpu_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-90000000 { + opp-hz =3D /bits/ 64 <90000000>; + opp-microvolt =3D <1050000 1050000 1225000>; + clock-latency-ns =3D <320000>; + }; + + opp-250000000 { + opp-hz =3D /bits/ 64 <250000000>; + opp-microvolt =3D <1050000 1050000 1225000>; + clock-latency-ns =3D <320000>; + }; + + opp-600000000 { + opp-hz =3D /bits/ 64 <600000000>; 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Tue, 4 Aug 2026 04:36:01 -0700 Received: from che-ll-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 4 Aug 2026 04:35:51 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 12/17] ARM: dts: microchip: sama7d65: Add ADC node Date: Tue, 4 Aug 2026 17:03:33 +0530 Message-ID: <20260804113338.261782-13-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260804113338.261782-1-varshini.rajendran@microchip.com> References: <20260804113338.261782-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add node for the ADC controller in sama7d65 SoC. Add the vddout25 fixed regulator node which provides the 2.5V reference voltage for the ADC. Signed-off-by: Varshini Rajendran --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 28 +++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/= microchip/sama7d65.dtsi index dfac17e34e65..c35f27615bc4 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -95,6 +96,15 @@ slow_xtal: clock-slowxtal { }; }; =20 + vddout25: fixed-regulator-vddout25 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VDDOUT25"; + regulator-min-microvolt =3D <2500000>; + regulator-max-microvolt =3D <2500000>; + regulator-boot-on; + status =3D "disabled"; + }; + ns_sram: sram@100000 { compatible =3D "mmio-sram"; reg =3D <0x100000 0x20000>; @@ -296,6 +306,24 @@ can4: can@e0838000 { status =3D "disabled"; }; =20 + adc: adc@e1000000 { + compatible =3D "microchip,sama7d65-adc"; + reg =3D <0xe1000000 0x200>; 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d="scan'208";a="61934892" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 04 Aug 2026 04:36:13 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Tue, 4 Aug 2026 04:36:12 -0700 Received: from che-ll-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 4 Aug 2026 04:36:02 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 13/17] ARM: dts: microchip: sama7d65_curiosity: Enable ADC, DVFS Date: Tue, 4 Aug 2026 17:03:34 +0530 Message-ID: <20260804113338.261782-14-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260804113338.261782-1-varshini.rajendran@microchip.com> References: <20260804113338.261782-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable ADC and DVFS on SAMA7D65 Curiosity board. Configure the necessary power supply (vddana, vref) for the ADC, and enable cpu-supply for DVFS. Signed-off-by: Varshini Rajendran Reviewed-by: Claudiu Beznea --- .../dts/microchip/at91-sama7d65_curiosity.dts | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts b/arch= /arm/boot/dts/microchip/at91-sama7d65_curiosity.dts index 927c27260b6c..c2d1e5308170 100644 --- a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts +++ b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts @@ -79,6 +79,14 @@ reg_5v: regulator-5v { }; }; =20 +&adc { + vddana-supply =3D <&vddout25>; + vref-supply =3D <&vddout25>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_adc_default &pinctrl_adtrg_default>; + status =3D "okay"; +}; + &can1 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_can1_default>; @@ -97,6 +105,10 @@ &can3 { status =3D "okay"; }; =20 +&cpu0 { + cpu-supply =3D <&vddcpu>; +}; + &dma0 { status =3D "okay"; }; @@ -334,6 +346,16 @@ &main_xtal { }; =20 &pioa { + pinctrl_adc_default: adc-default { + pinmux =3D ; + bias-disable; + }; + + pinctrl_adtrg_default: adtrg-default { + pinmux =3D ; + bias-pull-up; + }; + pinctrl_can1_default: can1-default { pinmux =3D , ; @@ -457,3 +479,8 @@ input@0 { &slow_xtal { clock-frequency =3D <32768>; }; + +&vddout25 { + vin-supply =3D <&vdd_3v3>; + status =3D "okay"; +}; --=20 2.34.1 From nobody Fri Oct 2 06:58:28 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F08F352008; Tue, 4 Aug 2026 11:36:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785843385; cv=none; b=joxNvU7Xb91Vz/lq8ixuUdX1ah2KaA3K0Ot+UWu3MeTB3CEDcSROfotbW6qKWNJEQtHJ9C24GNDGHkmGKl00YOXriFqRpciWM4Z0WTm2urx0Ot1bu7/LPI9lepDio/smfgkf02EqsHf9GeZfNWzikcntpOiuRw0RAm2aRrBYyhU= ARC-Message-Signature: i=1; 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Tue, 4 Aug 2026 04:36:23 -0700 Received: from che-ll-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 4 Aug 2026 04:36:13 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 14/17] ARM: dts: microchip: sama7d65: add otpc node Date: Tue, 4 Aug 2026 17:03:35 +0530 Message-ID: <20260804113338.261782-15-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260804113338.261782-1-varshini.rajendran@microchip.com> References: <20260804113338.261782-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add OTPC node along with temperature calibration cell. Signed-off-by: Varshini Rajendran --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/= microchip/sama7d65.dtsi index c35f27615bc4..aac2e22d96cb 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -15,6 +15,7 @@ #include #include #include +#include =20 / { model =3D "Microchip SAMA7D65 family SoC"; @@ -1111,6 +1112,21 @@ ddr3phy: ddr3phy@e3804000 { reg =3D <0xe3804000 0x1000>; }; =20 + otpc: efuse@e8c00000 { + compatible =3D "microchip,sama7d65-otpc", "microchip,sama7g5-otpc", "sy= scon"; + reg =3D <0xe8c00000 0x100>; + + nvmem-layout { + compatible =3D "fixed-layout"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + temperature_calib: calib@41435354 { + reg =3D <0x41435354 0x2c>; /* Temp calib data packet TAG */ + }; + }; + }; + gic: interrupt-controller@e8c11000 { compatible =3D "arm,cortex-a7-gic"; reg =3D <0xe8c11000 0x1000>, --=20 2.34.1 From nobody Fri Oct 2 06:58:28 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 61A2B352008; Tue, 4 Aug 2026 11:36:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785843396; cv=none; b=MvC41Vxh9ZtIyBpMPONriAd6psds71Cl7CB6IXKCTRKRcGlDBL2FKIvsDP3r3fxqmd06o8A04shllx5U09IqJFLCIAwemZzQDmT7lasYpfIkkZ3lhXSyDZmSHi1hbyyd7ZQ3bBRM+VPqZXchI4AKm7XeTusVI8psfDbUzJE1ES8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785843396; c=relaxed/simple; bh=ytkQl2qucpM7xa0UdkODTCkBUd467sNXQVdKVB1xcag=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=A/k05ZDXY4ZfKLghHKSexHj+Kfxv5Q7u/lBLUW3wSWGolpt5/EtnzZGgtrv3LJYDCG7ScelYCTx4RR+xphM3ik5DT/oW8T3/AiqhCReHp3YymRa757e67X6sBdJJVn0QvAPXUwGJ9AJibRGquMGJpmwynGBSSKj5aW9qKIDKuuE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=konyeQfS; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="konyeQfS" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1785843395; x=1817379395; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=ytkQl2qucpM7xa0UdkODTCkBUd467sNXQVdKVB1xcag=; b=konyeQfSWd4MNsMXlfoq/t2vfsVRja9FTOJjhf/85od8PW2Az3aTXVeG N8fTgK5mDAaExPABxiE47WpfFCpfCxVEh0FoeGTcpr5wys5QNdJdySRiW +O2L9vwNk3tL+Myh5yfIV7Ssr93gkWyVH9OexvQESX9mGo1LaZKuG2xCL 8GVFeevP8bg+lG6O+F1xOVMe6KY1nrzJRS98DMXiHZqApB0qVBGarulA3 6rw1Mo6UWH9jvKD3TGeWoOhuQBmgvy1uMQMrpmBkkT5Mbm9SMgSONL+Gc SmRJJYXmCyh3/4dBi7ojE5ackK4MYs52WJdTn0oj3jVECcM2VTpAEGm73 w==; X-CSE-ConnectionGUID: +Eg+lPfRSQmGrmY2j3vnew== X-CSE-MsgGUID: UOGQzfCSQkGMApPuGdpeaQ== X-IronPort-AV: E=Sophos;i="6.25,204,1779174000"; d="scan'208";a="61934900" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Aug 2026 04:36:34 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.87.71) by chn-vm-ex3.mchp-main.com (10.10.87.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.45; Tue, 4 Aug 2026 04:36:34 -0700 Received: from che-ll-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 4 Aug 2026 04:36:23 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 15/17] ARM: dts: microchip: sama7d65: add cells for temperature calibration Date: Tue, 4 Aug 2026 17:03:36 +0530 Message-ID: <20260804113338.261782-16-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260804113338.261782-1-varshini.rajendran@microchip.com> References: <20260804113338.261782-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add nvmem-cells for temperature calibration data to the ADC node. The calibration data is read from the OTPC. Signed-off-by: Varshini Rajendran Reviewed-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/= microchip/sama7d65.dtsi index aac2e22d96cb..a8b18ad0ef7f 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -318,6 +318,8 @@ adc: adc@e1000000 { dmas =3D <&dma0 AT91_XDMAC_DT_PERID(0)>; dma-names =3D "rx"; #io-channel-cells =3D <1>; + nvmem-cells =3D <&temperature_calib>; + nvmem-cell-names =3D "temperature_calib"; atmel,min-sample-rate-hz =3D <200000>; atmel,max-sample-rate-hz =3D <20000000>; atmel,trigger-edge-type =3D ; --=20 2.34.1 From nobody Fri Oct 2 06:58:28 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 78F0E361973; Tue, 4 Aug 2026 11:36:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785843406; cv=none; b=OkNX9/eIOGh9d9up5BuV3TJfoPsWRFPGEIjWJ6uJdOlwY97AJOqpbv/JssalJf4tUYkD5Ay1cdcVSufUMoAJ3aZPx0NEcEYH7rI1sWAQRk3a3nj3oYPPt0ccb6SbegvcYWxjw4g7ZxCHsCTj1v92dE8JkNCECR70FcgTJiwCuX0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785843406; c=relaxed/simple; bh=vtCrC8enOD/kvPEdYL79acFvpqmjSRWeBQpWufU1kl0=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=YNCIOL0sNrJhHxIcZMVjG/PpNkPWIOg1X8N1wENsI84jIuKbVK5KkCeqHnfPPdwDSvJPqfIo8uSk+SosAyPKOqZ0bxW59LTzsy4SE8Lx8nVWey0Ts7nNiQIdOmGulXjSadg6lwDVrYTufxRKZzqY4hIWa++9n30gVVISyFWDwyQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=OWaPPPSA; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="OWaPPPSA" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1785843405; x=1817379405; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=vtCrC8enOD/kvPEdYL79acFvpqmjSRWeBQpWufU1kl0=; b=OWaPPPSAvph3cwejIteQ2ZsiJxlI7rPJx9x28edWgWgAZC5W5uXV95jJ h2O9ecEN3TKFzXwqOairYZG1S0ScTaykUgzhZPgLImIXffilyn+V5c4TZ M/2J58BdBqJUMDt96YZrlGFHE8N5kBq8kQaq5r0j+F58XndmVtmvFWagH aX1tTLhZXgEozDdeLGVsgx5PgFaBac7yT8KxdHSGQ6PD+ghmy5ott/0F5 hPbOL8SmCCRiC80c62xguIKptbuLDlIKISpmJ2BNQi+UJPiNmYeAnHdw2 5dtunV5/lbQm30Or5CJ8s5t03pqZc/PJUlxoqTQGDn2SHufXQSbKZ8BDF g==; X-CSE-ConnectionGUID: +VjAUZOYScqI5j9vtqf4vQ== X-CSE-MsgGUID: qSZIpBD+Sy6rmPK33j1hQw== X-IronPort-AV: E=Sophos;i="6.25,204,1779174000"; d="scan'208";a="61934905" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 04 Aug 2026 04:36:44 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Tue, 4 Aug 2026 04:36:44 -0700 Received: from che-ll-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 4 Aug 2026 04:36:34 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 16/17] ARM: dts: microchip: sama7d65: add temperature sensor Date: Tue, 4 Aug 2026 17:03:37 +0530 Message-ID: <20260804113338.261782-17-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260804113338.261782-1-varshini.rajendran@microchip.com> References: <20260804113338.261782-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the generic-adc-thermal temperature sensor node for SAMA7D65. Signed-off-by: Varshini Rajendran Reviewed-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/= microchip/sama7d65.dtsi index a8b18ad0ef7f..3aba73983c79 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -119,6 +119,13 @@ pmu { interrupts =3D ; }; =20 + thermal_sensor: thermal-sensor { + compatible =3D "generic-adc-thermal"; + #thermal-sensor-cells =3D <0>; + io-channels =3D <&adc AT91_SAMA7G5_ADC_TEMP_CHANNEL>; + io-channel-names =3D "sensor-channel"; + }; + soc { compatible =3D "simple-bus"; ranges; --=20 2.34.1 From nobody Fri Oct 2 06:58:28 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A659D3546C0; Tue, 4 Aug 2026 11:36:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785843419; cv=none; b=BXiU/vKbAiLq0tSGYm1NlusnYNqo7h1DJFbFy4yU+pnF5UGI91qJZdxzb7PxqJxfTARxPGNDY5WiNSmQBKsTNYa7rUNl4BAKLyTRaEhbOklvSxSTcsN1GKHRrrSsQTHrIwuzQuhpqGrMRjnzYIDCMElckMu+05A3rw7Pl2SDqh8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785843419; c=relaxed/simple; bh=XNeG3M4dWAfIsmDBbwjWj2IXhD+Qtz4KOR6R5jwR+jw=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Swc9CK8llI8JAFLypprjQ/RHmj11cPZSGbUBaPRYFsYCCvUszaXPCwov75WVAsTgLSDHsY/OSLKXosB1b9MxIPKYgPgKZ1lnpAA7/ai3Oaj7c0+QpigNlOhy/G3POdR+gJxOjDBxRsTUSXitKYeVJMCHNQFpbCXMUrf58lvrV6U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=OuSGkuKN; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="OuSGkuKN" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1785843417; x=1817379417; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=XNeG3M4dWAfIsmDBbwjWj2IXhD+Qtz4KOR6R5jwR+jw=; b=OuSGkuKNH1sAeVWoJfLdr6t2lQGVZ8PINK9gaRqs9UYDD0QgsyLDbMst j5CqJGsnY5QCceuCVcAGozUu/XZwPef1QVAbDqACvmi2W/ehjrZBbc0ef W//mspeRvnW/ODeDEZDPOvkNzkwwyJcnPbAATyVlzwxDzv1tIh/xTbrPw iyyguo/8AO2FyGgJ6XyCpSkMJBr6wMccBRvhAuUSoAjViPVpbhj0LQ++1 2H361U1P7eoz7IJPcae31BRgWXbznZ618NON8z/0Edch2ANnfej0ApfLO EMfYGFaaEilDf1+ELZCc+YAIae+Di4goZz1owIl4w6/Fc+ZjyB+BPAt7H Q==; X-CSE-ConnectionGUID: 7CuNwgWqRGiaWdZkGYCKTQ== X-CSE-MsgGUID: sI5zwelDS8SKIypgjElsaA== X-IronPort-AV: E=Sophos;i="6.25,204,1779174000"; d="scan'208";a="292994117" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 04 Aug 2026 04:36:56 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Tue, 4 Aug 2026 04:36:55 -0700 Received: from che-ll-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 4 Aug 2026 04:36:44 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 17/17] ARM: dts: microchip: sama7d65: add thermal zones node Date: Tue, 4 Aug 2026 17:03:38 +0530 Message-ID: <20260804113338.261782-18-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260804113338.261782-1-varshini.rajendran@microchip.com> References: <20260804113338.261782-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add thermal zones node for SAMA7D65 with trip points for passive cooling and critical shutdown. Signed-off-by: Varshini Rajendran Reviewed-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 42 +++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/= microchip/sama7d65.dtsi index 3aba73983c79..7743f9e8f692 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -16,6 +16,7 @@ #include #include #include +#include =20 / { model =3D "Microchip SAMA7D65 family SoC"; @@ -38,6 +39,7 @@ cpu0: cpu@0 { i-cache-size =3D <0x8000>; // L1, 32 KB next-level-cache =3D <&L2>; operating-points-v2 =3D <&cpu_opp_table>; + #cooling-cells =3D <2>; /* min followed by max */ =20 L2: l2-cache { compatible =3D "cache"; @@ -126,6 +128,46 @@ thermal_sensor: thermal-sensor { io-channel-names =3D "sensor-channel"; }; =20 + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive =3D <1000>; + polling-delay =3D <5000>; + thermal-sensors =3D <&thermal_sensor>; + + trips { + cpu_normal: cpu-alert0 { + temperature =3D <90000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + cpu_hot: cpu-alert1 { + temperature =3D <95000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + cpu_critical: cpu-critical { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu_normal>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map1 { + trip =3D <&cpu_hot>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + soc { compatible =3D "simple-bus"; ranges; --=20 2.34.1