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Tue, 04 Aug 2026 04:19:05 -0700 (PDT) From: David Oberhollenzer To: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, vkoul@kernel.org, neil.armstrong@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, johan@kernel.org, rogerq@ti.com Cc: Julian.FRIEDRICH@frequentis.com, upstream+omap@sigma-star.at, David Oberhollenzer Subject: [PATCH 1/2] phy: ti: ti-pipe3: allow configuring ACSPCIe TX/RX mode Date: Tue, 4 Aug 2026 13:18:48 +0200 Message-ID: <20260804111849.92046-2-david.oberhollenzer@sigma-star.at> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260804111849.92046-1-david.oberhollenzer@sigma-star.at> References: <20260804111849.92046-1-david.oberhollenzer@sigma-star.at> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Besides power control, the PHY control logic in the OMAP PCIe PHY subsystem has a configurable reference clock selection. It can either use the ljcb_clkp/ljcb_clkn pin as inputs, recovering the clock from the bus (RX mode), or generate the reference clock internally, driving the bus pins as outputs (TX mode). This patch adds a device tree setting to the PIPE3 PHY, allowing the syscon node, register offset and RX/TX mode setting to be attached and set up correctly. Signed-off-by: David Oberhollenzer --- drivers/phy/ti/phy-ti-pipe3.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/phy/ti/phy-ti-pipe3.c b/drivers/phy/ti/phy-ti-pipe3.c index b5543b5c674c..801a6239328e 100644 --- a/drivers/phy/ti/phy-ti-pipe3.c +++ b/drivers/phy/ti/phy-ti-pipe3.c @@ -115,6 +115,9 @@ #define MEM_CDR_LOS_SOURCE_MASK GENMASK(10, 9) #define MEM_CDR_LOS_SOURCE_SHIFT 9 =20 +#define PCIE_TX_RX_CTRL_MASK GENMASK(17, 16) +#define PCIE_TX_RX_CTRL_SHIFT 16 + /* * This is an Empirical value that works, need to confirm the actual * value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status @@ -785,6 +788,24 @@ static int ti_pipe3_get_pll_base(struct ti_pipe3 *phy) return PTR_ERR_OR_ZERO(phy->pll_ctrl_base); } =20 +static int ti_pipe3_acspcie_tx_rx_mode(struct ti_pipe3 *phy) +{ + struct device_node *np =3D phy->dev->of_node; + struct regmap *regmap; + unsigned int args[2]; + + regmap =3D syscon_regmap_lookup_by_phandle_args(np, + "syscon-acspcie-tx-rx", + 2, args); + if (IS_ERR(regmap)) { + dev_warn(phy->dev, "can't get syscon-acspcie-tx-rx\n"); + return -EINVAL; + } + + return regmap_update_bits(regmap, args[0], PCIE_TX_RX_CTRL_MASK, + args[1] << PCIE_TX_RX_CTRL_SHIFT); +} + static int ti_pipe3_probe(struct platform_device *pdev) { struct ti_pipe3 *phy; @@ -807,6 +828,12 @@ static int ti_pipe3_probe(struct platform_device *pdev) phy->dpll_map =3D data->dpll_map; phy->settings =3D data->settings; =20 + if (phy->mode =3D=3D PIPE3_MODE_PCIE) { + ret =3D ti_pipe3_acspcie_tx_rx_mode(phy); + if (ret) + dev_warn(dev, "failed to set ACSPCIe TX/RX mode\n"); + } + ret =3D ti_pipe3_get_pll_base(phy); if (ret) return ret; --=20 2.55.0 From nobody Fri Oct 2 06:59:33 2026 Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36541438484 for ; Tue, 4 Aug 2026 11:19:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Tue, 04 Aug 2026 04:19:06 -0700 (PDT) Received: from localtoast.corp.sigma-star.at ([82.150.214.1]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47fd458b05fsm44414682f8f.28.2026.08.04.04.19.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Aug 2026 04:19:06 -0700 (PDT) From: David Oberhollenzer To: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, vkoul@kernel.org, neil.armstrong@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, johan@kernel.org, rogerq@ti.com Cc: Julian.FRIEDRICH@frequentis.com, upstream+omap@sigma-star.at, David Oberhollenzer Subject: [PATCH 2/2] dt-bindings: phy: ti,phy-usb3: document aspcie reference clock setting Date: Tue, 4 Aug 2026 13:18:49 +0200 Message-ID: <20260804111849.92046-3-david.oberhollenzer@sigma-star.at> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260804111849.92046-1-david.oberhollenzer@sigma-star.at> References: <20260804111849.92046-1-david.oberhollenzer@sigma-star.at> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add syscon-acspcie-tx-rx property to the PHY bindings. Signed-off-by: David Oberhollenzer --- Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml b/Docum= entation/devicetree/bindings/phy/ti,phy-usb3.yaml index 84f538aa587c..4fb017df2898 100644 --- a/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml +++ b/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml @@ -52,6 +52,15 @@ properties: enum: [wkupclk, sysclk, refclk, dpll_ref, dpll_ref_m2, phy-div, div-clk] =20 + syscon-acspcie-tx-rx: + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + items: + items: + - description: Phandle to the system control module + - description: Register offset of CTRL_CORE_SMA_SW_6 + - description: Setting for PCIE_TX_RX_CONTROL + syscon-phy-power: $ref: /schemas/types.yaml#/definitions/phandle-array maxItems: 1 --=20 2.55.0