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charset="utf-8" From: Pritesh Patel Add reset generator node for EIC7700 SoC Signed-off-by: Pritesh Patel Signed-off-by: Pinkesh Vaghela --- arch/riscv/boot/dts/eswin/eic7700.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/e= swin/eic7700.dtsi index c3ed93008bca..430a210f01e6 100644 --- a/arch/riscv/boot/dts/eswin/eic7700.dtsi +++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi @@ -4,6 +4,7 @@ */ =20 /dts-v1/; +#include =20 / { #address-cells =3D <2>; @@ -341,5 +342,11 @@ gpioD: gpio-port@3 { #gpio-cells =3D <2>; }; }; + + reset: reset-controller@51828300 { + compatible =3D "eswin,eic7700-reset"; + reg =3D <0x0 0x51828300 0x0 0x200>; + #reset-cells =3D <1>; + }; }; }; --=20 2.34.1 From nobody Fri Oct 2 06:59:09 2026 Received: from naesa05.arrow.com (naesa05.arrow.com [216.150.161.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 005114503E9; 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charset="utf-8" From: Pritesh Patel Add clock generator node for EIC7700 SoC. HiFive Premier P550 boards have 24MHz crystal oscillator to provide the input clock. Signed-off-by: Pritesh Patel Signed-off-by: Pinkesh Vaghela --- .../boot/dts/eswin/eic7700-hifive-premier-p550.dts | 5 +++++ arch/riscv/boot/dts/eswin/eic7700.dtsi | 13 +++++++++++++ 2 files changed, 18 insertions(+) diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/ar= ch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts index 131ed1fc6b2e..a5c76b14a38f 100644 --- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts +++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts @@ -20,6 +20,11 @@ chosen { }; }; =20 +&osc { + clock-frequency =3D <24000000>; + clock-output-names =3D "osc_24m"; +}; + &uart0 { status =3D "okay"; }; diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/e= swin/eic7700.dtsi index 430a210f01e6..b3a230870315 100644 --- a/arch/riscv/boot/dts/eswin/eic7700.dtsi +++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi @@ -4,6 +4,7 @@ */ =20 /dts-v1/; +#include #include =20 / { @@ -203,6 +204,11 @@ pmu { <0x00000000 0x0000000f 0xfffffffc 0x000000ff 0x00000078>; }; =20 + osc: oscillator { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + soc { compatible =3D "simple-bus"; ranges; @@ -343,6 +349,13 @@ gpioD: gpio-port@3 { }; }; =20 + clk: clock-controller@51828000 { + compatible =3D "eswin,eic7700-clock"; + reg =3D <0x0 0x51828000 0x0 0x300>; + clocks =3D <&osc>; + #clock-cells =3D <1>; + }; + reset: reset-controller@51828300 { compatible =3D "eswin,eic7700-reset"; reg =3D <0x0 0x51828300 0x0 0x200>; --=20 2.34.1 From nobody Fri Oct 2 06:59:09 2026 Received: from naesa05.arrow.com (naesa05.arrow.com [216.150.161.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69F374503E7; Tue, 4 Aug 2026 10:45:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=216.150.161.26 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785840350; cv=none; b=r6/X6uhFlPXq2bViW9yuOqnS1waQnbbkRWjxsXOAQg99SwHD3kFCEBSeZwseQWZ8ghkYzd8CztqKH04nAPW57Uh2HHsoz+dlTpResbRzgtQMwAIIbBrpz8E8uM5srIDXiTFkAJkOELjhpRCPp22ozd38XjQV7iVzhs35THLMMNE= ARC-Message-Signature: i=1; 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Tue, 4 Aug 2026 16:14:31 +0530 From: Pinkesh Vaghela To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Andi Shyti , Mika Westerberg , linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Min Lin Cc: Yulin Lu , Samuel Holland , Darshan Prajapati , Pinkesh Vaghela , Pritesh Patel Subject: [PATCH v3 3/8] riscv: dts: eswin: eic7700: add pinctrl support Date: Tue, 4 Aug 2026 16:14:26 +0530 Message-Id: <20260804104431.1391839-4-pinkesh.vaghela@einfochips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260804104431.1391839-1-pinkesh.vaghela@einfochips.com> References: <20260804104431.1391839-1-pinkesh.vaghela@einfochips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 04 Aug 2026 10:44:31.0650 (UTC) FILETIME=[3B6AC020:01DD23FE] Content-Type: text/plain; charset="utf-8" From: Yulin Lu Add pinctrl node and related pin configuration for EIC7700 SoC Co-developed-by: Pritesh Patel Signed-off-by: Pritesh Patel Signed-off-by: Yulin Lu Signed-off-by: Pinkesh Vaghela --- .../dts/eswin/eic7700-hifive-premier-p550.dts | 119 +++ .../riscv/boot/dts/eswin/eic7700-pinctrl.dtsi | 888 ++++++++++++++++++ arch/riscv/boot/dts/eswin/eic7700.dtsi | 5 + 3 files changed, 1012 insertions(+) create mode 100644 arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/ar= ch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts index a5c76b14a38f..3101fd90d171 100644 --- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts +++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts @@ -6,6 +6,7 @@ /dts-v1/; =20 #include "eic7700.dtsi" +#include "eic7700-pinctrl.dtsi" =20 / { compatible =3D "sifive,hifive-premier-p550", "eswin,eic7700"; @@ -18,6 +19,15 @@ aliases { chosen { stdout-path =3D "serial0:115200n8"; }; + + vcc_1v8: regulator-vcc1v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; }; =20 &osc { @@ -25,10 +35,119 @@ &osc { clock-output-names =3D "osc_24m"; }; =20 +&gpio0_pins { + bias-disable; + input-enable; +}; + +&gpio5_pins { + bias-disable; + input-enable; +}; + +&gpio11_pins { + bias-disable; + input-enable; +}; + +&gpio14_pins { + bias-pull-up; + input-disable; +}; + +&gpio15_pins { + bias-disable; + input-enable; +}; + +&gpio28_pins { + bias-disable; + input-enable; +}; + +&gpio43_pins { + bias-disable; + input-disable; +}; + +&gpio71_pins { + bias-pull-up; + input-disable; +}; + +&gpio74_pins { + bias-pull-up; + input-disable; +}; + +&gpio76_pins { + bias-disable; + input-disable; +}; + +&gpio77_pins { + bias-pull-up; + input-disable; +}; + +&gpio79_pins { + bias-disable; + input-disable; +}; + +&gpio80_pins { + bias-pull-up; + input-disable; +}; + +&gpio82_pins { + bias-pull-up; + input-disable; +}; + +&gpio84_pins { + bias-disable; + input-disable; +}; + +&gpio85_pins { + bias-pull-up; + input-disable; +}; + +&gpio94_pins { + bias-disable; + input-disable; +}; + +&gpio106_pins { + bias-disable; + input-disable; +}; + +&gpio111_pins { + bias-disable; + input-disable; +}; + +&pinctrl { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gpio0_pins>, <&gpio5_pins>, <&gpio11_pins>, + <&gpio14_pins>, <&gpio15_pins>, <&gpio28_pins>, <&gpio43_pins>, + <&gpio71_pins>, <&gpio74_pins>, <&gpio76_pins>, <&gpio77_pins>, + <&gpio79_pins>, <&gpio80_pins>, <&gpio82_pins>, <&gpio84_pins>, + <&gpio85_pins>, <&gpio94_pins>, <&gpio106_pins>, <&gpio111_pins>; + vrgmii-supply =3D <&vcc_1v8>; +}; + &uart0 { status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart0_pins>; }; =20 &uart2 { status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart2_pins>; }; diff --git a/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi b/arch/riscv/bo= ot/dts/eswin/eic7700-pinctrl.dtsi new file mode 100644 index 000000000000..2d655b442982 --- /dev/null +++ b/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi @@ -0,0 +1,888 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2025 Beijing ESWIN Computing Technology Co., Ltd. + * + * ESWIN's EIC7700 SoC pin-mux and pin-config options are listed as + * device tree nodes in this file. + * + * Authors: Yulin Lu + */ + +&pinctrl{ + default-pins-grp { + sata_act_led_pins: sata-act-led-pins{ + pins =3D "gpio27"; + function =3D "sata"; + }; + + emmc_led_ctrl_pins: emmc-led-ctrl-pins { + pins =3D "gpio29"; + function =3D "emmc"; + }; + + sd0_led_ctrl_pins: sd0-led-ctrl-pins { + pins =3D "gpio34"; + function =3D "sdio"; + }; + + sd1_led_ctrl_pins: sd1-led-ctrl-pins { + pins =3D "spi1_d2"; + function =3D "sdio"; + }; + + i2c6_pins: i2c6-pins { + pins =3D "uart1_cts", "uart1_rts"; + function =3D "i2c"; + }; + + i2c7_pins: i2c7-pins { + pins =3D "uart2_tx", "uart2_rx"; + function =3D "i2c"; + }; + + i2c9_pins: i2c9-pins { + pins =3D "spi1_d0", "spi1_d1"; + function =3D "i2c"; + }; + + pwm1_pins: pwm1-pins { + pins =3D "spi1_d3"; + function =3D "pwm"; + }; + + pwm2_pins: pwm2-pins { + pins =3D "spi1_cs1_n"; + function =3D "pwm"; + }; + + mipi_csi_xtrig0_pins: mipi-csi-xtrig0-pins { + pins =3D "gpio92"; + function =3D "mipi_csi"; + }; + + mipi_csi_xtrig1_pins: mipi-csi-xtrig1-pins { + pins =3D "gpio93"; + function =3D "mipi_csi"; + }; + + dual_spi2_pins: dual-spi2-pins { + pins =3D "spi2_cs0_n", "jtag0_tck", "jtag0_tms", "jtag0_tdi"; + function =3D "spi"; + }; + + quad_spi2_pins: quad-spi2-pins { + pins =3D "spi2_cs0_n", "spi2_cs1_n", "jtag0_tck", "jtag0_tms", + "jtag0_tdi", "jtag0_tdo", "gpio5"; + function =3D "spi"; + }; + + gpio1_pins: gpio1-pins { + pins =3D "jtag0_tck"; + function =3D "gpio"; + }; + + gpio2_pins: gpio2-pins { + pins =3D "jtag0_tms"; + function =3D "gpio"; + }; + + gpio3_pins: gpio3-pins { + pins =3D "jtag0_tdi"; + function =3D "gpio"; + }; + + gpio4_pins: gpio4-pins { + pins =3D "jtag0_tdo"; + function =3D "gpio"; + }; + + gpio6_pins: gpio6-pins { + pins =3D "spi2_cs0_n"; + function =3D "gpio"; + }; + + gpio7_pins: gpio7-pins { + pins =3D "jtag1_tck"; + function =3D "gpio"; + }; + + gpio8_pins: gpio8-pins { + pins =3D "jtag1_tms"; + function =3D "gpio"; + }; + + gpio9_pins: gpio9-pins { + pins =3D "jtag1_tdi"; + function =3D "gpio"; + }; + + gpio10_pins: gpio10-pins { + pins =3D "jtag1_tdo"; + function =3D "gpio"; + }; + + gpio12_pins: gpio12-pins { + pins =3D "spi2_cs1_n"; + function =3D "gpio"; + }; + + gpio13_pins: gpio13-pins { + pins =3D "mode_set0"; + function =3D "gpio"; + }; + + gpio14_pins: gpio14-pins { + pins =3D "mode_set1"; + function =3D "gpio"; + }; + + gpio15_pins: gpio15-pins { + pins =3D "mode_set2"; + function =3D "gpio"; + }; + + gpio16_pins: gpio16-pins { + pins =3D "mode_set3"; + function =3D "gpio"; + }; + + gpio17_pins: gpio17-pins { + pins =3D "jtag2_trst"; + function =3D "gpio"; + }; + + gpio18_pins: gpio18-pins { + pins =3D "i2s0_bclk"; + function =3D "gpio"; + }; + + gpio19_pins: gpio19-pins { + pins =3D "i2s0_wclk"; + function =3D "gpio"; + }; + + gpio20_pins: gpio20-pins { + pins =3D "i2s0_sdi"; + function =3D "gpio"; + }; + + gpio21_pins: gpio21-pins { + pins =3D "i2s0_sdo"; + function =3D "gpio"; + }; + + gpio22_pins: gpio22-pins { + pins =3D "i2s_mclk"; + function =3D "gpio"; + }; + + gpio23_pins: gpio23-pins { + pins =3D "i2s2_bclk"; + function =3D "gpio"; + }; + + gpio24_pins: gpio24-pins { + pins =3D "i2s2_wclk"; + function =3D "gpio"; + }; + + gpio25_pins: gpio25-pins { + pins =3D "i2s2_sdi"; + function =3D "gpio"; + }; + + gpio26_pins: gpio26-pins { + pins =3D "i2s2_sdo"; + function =3D "gpio"; + }; + + gpio29_pins: gpio29-pins { + pins =3D "gpio29"; + function =3D "gpio"; + }; + + gpio30_pins: gpio30-pins { + pins =3D "i2s1_bclk"; + function =3D "gpio"; + }; + + gpio31_pins: gpio31-pins { + pins =3D "i2s1_wclk"; + function =3D "gpio"; + }; + + gpio32_pins: gpio32-pins { + pins =3D "i2s1_sdi"; + function =3D "gpio"; + }; + + gpio33_pins: gpio33-pins { + pins =3D "i2s1_sdo"; + function =3D "gpio"; + }; + + gpio34_pins: gpio34-pins { + pins =3D "gpio34"; + function =3D "gpio"; + }; + + gpio35_pins: gpio35-pins { + pins =3D "spi1_cs0_n"; + function =3D "gpio"; + }; + + gpio36_pins: gpio36-pins { + pins =3D "spi1_clk"; + function =3D "gpio"; + }; + + gpio37_pins: gpio37-pins { + pins =3D "spi1_d0"; + function =3D "gpio"; + }; + + gpio38_pins: gpio38-pins { + pins =3D "spi1_d1"; + function =3D "gpio"; + }; + + gpio39_pins: gpio39-pins { + pins =3D "spi1_d2"; + function =3D "gpio"; + }; + + gpio40_pins: gpio40-pins { + pins =3D "spi1_d3"; + function =3D "gpio"; + }; + + gpio41_pins: gpio41-pins { + pins =3D "spi1_cs1_n"; + function =3D "gpio"; + }; + + gpio42_pins: gpio42-pins { + pins =3D "usb0_pwren"; + function =3D "gpio"; + }; + + gpio43_pins: gpio43-pins { + pins =3D "usb1_pwren"; + function =3D "gpio"; + }; + + gpio44_pins: gpio44-pins { + pins =3D "i2c0_scl"; + function =3D "gpio"; + }; + + gpio45_pins: gpio45-pins { + pins =3D "i2c0_sda"; + function =3D "gpio"; + }; + + gpio46_pins: gpio46-pins { + pins =3D "i2c1_scl"; + function =3D "gpio"; + }; + + gpio47_pins: gpio47-pins { + pins =3D "i2c1_sda"; + function =3D "gpio"; + }; + + gpio48_pins: gpio48-pins { + pins =3D "i2c2_scl"; + function =3D "gpio"; + }; + + gpio49_pins: gpio49-pins { + pins =3D "i2c2_sda"; + function =3D "gpio"; + }; + + gpio50_pins: gpio50-pins { + pins =3D "i2c3_scl"; + function =3D "gpio"; + }; + + gpio51_pins: gpio51-pins { + pins =3D "i2c3_sda"; + function =3D "gpio"; + }; + + gpio52_pins: gpio52-pins { + pins =3D "i2c4_scl"; + function =3D "gpio"; + }; + + gpio53_pins: gpio53-pins { + pins =3D "i2c4_sda"; + function =3D "gpio"; + }; + + gpio54_pins: gpio54-pins { + pins =3D "i2c5_scl"; + function =3D "gpio"; + }; + + gpio55_pins: gpio55-pins { + pins =3D "i2c5_sda"; + function =3D "gpio"; + }; + + gpio56_pins: gpio56-pins { + pins =3D "uart0_tx"; + function =3D "gpio"; + }; + + gpio57_pins: gpio57-pins { + pins =3D "uart0_rx"; + function =3D "gpio"; + }; + + gpio58_pins: gpio58-pins { + pins =3D "uart1_tx"; + function =3D "gpio"; + }; + + gpio59_pins: gpio59-pins { + pins =3D "uart1_rx"; + function =3D "gpio"; + }; + + gpio60_pins: gpio60-pins { + pins =3D "uart1_cts"; + function =3D "gpio"; + }; + + gpio61_pins: gpio61-pins { + pins =3D "uart1_rts"; + function =3D "gpio"; + }; + + gpio62_pins: gpio62-pins { + pins =3D "uart2_tx"; + function =3D "gpio"; + }; + + gpio63_pins: gpio63-pins { + pins =3D "uart2_rx"; + function =3D "gpio"; + }; + + gpio64_pins: gpio64-pins { + pins =3D "jtag2_tck"; + function =3D "gpio"; + }; + + gpio65_pins: gpio65-pins { + pins =3D "jtag2_tms"; + function =3D "gpio"; + }; + + gpio66_pins: gpio66-pins { + pins =3D "jtag2_tdi"; + function =3D "gpio"; + }; + + gpio67_pins: gpio67-pins { + pins =3D "jtag2_tdo"; + function =3D "gpio"; + }; + + gpio68_pins: gpio68-pins { + pins =3D "fan_pwm"; + function =3D "gpio"; + }; + + gpio69_pins: gpio69-pins { + pins =3D "fan_tach"; + function =3D "gpio"; + }; + + gpio70_pins: gpio70-pins { + pins =3D "mipi_csi0_xvs"; + function =3D "gpio"; + }; + + gpio71_pins: gpio71-pins { + pins =3D "mipi_csi0_xhs"; + function =3D "gpio"; + }; + + gpio72_pins: gpio72-pins { + pins =3D "mipi_csi0_mclk"; + function =3D "gpio"; + }; + + gpio73_pins: gpio73-pins { + pins =3D "mipi_csi1_xvs"; + function =3D "gpio"; + }; + + gpio74_pins: gpio74-pins { + pins =3D "mipi_csi1_xhs"; + function =3D "gpio"; + }; + + gpio75_pins: gpio75-pins { + pins =3D "mipi_csi1_mclk"; + function =3D "gpio"; + }; + + gpio76_pins: gpio76-pins { + pins =3D "mipi_csi2_xvs"; + function =3D "gpio"; + }; + + gpio77_pins: gpio77-pins { + pins =3D "mipi_csi2_xhs"; + function =3D "gpio"; + }; + + gpio78_pins: gpio78-pins { + pins =3D "mipi_csi2_mclk"; + function =3D "gpio"; + }; + + gpio79_pins: gpio79-pins { + pins =3D "mipi_csi3_xvs"; + function =3D "gpio"; + }; + + gpio80_pins: gpio80-pins { + pins =3D "mipi_csi3_xhs"; + function =3D "gpio"; + }; + + gpio81_pins: gpio81-pins { + pins =3D "mipi_csi3_mclk"; + function =3D "gpio"; + }; + + gpio82_pins: gpio82-pins { + pins =3D "mipi_csi4_xvs"; + function =3D "gpio"; + }; + + gpio83_pins: gpio83-pins { + pins =3D "mipi_csi4_xhs"; + function =3D "gpio"; + }; + + gpio84_pins: gpio84-pins { + pins =3D "mipi_csi4_mclk"; + function =3D "gpio"; + }; + + gpio85_pins: gpio85-pins { + pins =3D "mipi_csi5_xvs"; + function =3D "gpio"; + }; + + gpio86_pins: gpio86-pins { + pins =3D "mipi_csi5_xhs"; + function =3D "gpio"; + }; + + gpio87_pins: gpio87-pins { + pins =3D "mipi_csi5_mclk"; + function =3D "gpio"; + }; + + gpio88_pins: gpio88-pins { + pins =3D "spi3_cs_n"; + function =3D "gpio"; + }; + + gpio89_pins: gpio89-pins { + pins =3D "spi3_clk"; + function =3D "gpio"; + }; + + gpio90_pins: gpio90-pins { + pins =3D "spi3_di"; + function =3D "gpio"; + }; + + gpio91_pins: gpio91-pins { + pins =3D "spi3_do"; + function =3D "gpio"; + }; + + gpio92_pins: gpio92-pins { + pins =3D "gpio92"; + function =3D "gpio"; + }; + + gpio93_pins: gpio93-pins { + pins =3D "gpio93"; + function =3D "gpio"; + }; + + gpio94_pins: gpio94-pins { + pins =3D "s_mode"; + function =3D "gpio"; + }; + + gpio95_pins: gpio95-pins { + pins =3D "gpio95"; + function =3D "gpio"; + }; + + gpio96_pins: gpio96-pins { + pins =3D "spi0_cs_n"; + function =3D "gpio"; + }; + + gpio97_pins: gpio97-pins { + pins =3D "spi0_clk"; + function =3D "gpio"; + }; + + gpio98_pins: gpio98-pins { + pins =3D "spi0_d0"; + function =3D "gpio"; + }; + + gpio99_pins: gpio99-pins { + pins =3D "spi0_d1"; + function =3D "gpio"; + }; + + gpio100_pins: gpio100-pins { + pins =3D "spi0_d2"; + function =3D "gpio"; + }; + + gpio101_pins: gpio101-pins { + pins =3D "spi0_d3"; + function =3D "gpio"; + }; + + gpio102_pins: gpio102-pins { + pins =3D "i2c10_scl"; + function =3D "gpio"; + }; + + gpio103_pins: gpio103-pins { + pins =3D "i2c10_sda"; + function =3D "gpio"; + }; + + gpio104_pins: gpio104-pins { + pins =3D "i2c11_scl"; + function =3D "gpio"; + }; + + gpio105_pins: gpio105-pins { + pins =3D "i2c11_sda"; + function =3D "gpio"; + }; + + gpio107_pins: gpio107-pins { + pins =3D "boot_sel0"; + function =3D "gpio"; + }; + + gpio108_pins: gpio108-pins { + pins =3D "boot_sel1"; + function =3D "gpio"; + }; + + gpio109_pins: gpio109-pins { + pins =3D "boot_sel2"; + function =3D "gpio"; + }; + + gpio110_pins: gpio110-pins { + pins =3D "boot_sel3"; + function =3D "gpio"; + }; + + uart3_pins: uart3-pins { + pins =3D "gpio92", "gpio93"; + function =3D "uart"; + }; + + uart4_pins: uart4-pins { + pins =3D "spi1_d0", "spi1_d1"; + function =3D "uart"; + }; + + gpio0_pins: gpio0-pins { + pins =3D "gpio0"; + function =3D "gpio"; + }; + + gpio5_pins: gpio5-pins { + pins =3D "gpio5"; + function =3D "gpio"; + }; + + gpio11_pins: gpio11-pins { + pins =3D "gpio11"; + function =3D "gpio"; + }; + + gpio27_pins: gpio27-pins { + pins =3D "gpio27"; + function =3D "gpio"; + }; + + gpio28_pins: gpio28-pins { + pins =3D "gpio28"; + function =3D "gpio"; + }; + + gpio106_pins: gpio106-pins { + pins =3D "gpio106"; + function =3D "gpio"; + }; + + gpio111_pins: gpio111-pins { + pins =3D "gpio111"; + function =3D "gpio"; + }; + + chip_mode_pins: chip-mode-pins { + pins =3D "chip_mode"; + function =3D "chip_mode"; + }; + + sdio0_pins: sdio0-pins { + pins =3D "mode_set0", "mode_set1"; + function =3D "sdio"; + }; + + sdio1_pins: sdio1-pins { + pins =3D "mode_set2", "mode_set3"; + function =3D "sdio"; + }; + + jtag0_pins: jtag0-pins { + pins =3D "jtag0_tck", "jtag0_tms", "jtag0_tdi", "jtag0_tdo"; + function =3D "jtag"; + }; + + jtag1_pins: jtag1-pins { + pins =3D "jtag1_tck", "jtag1_tms", "jtag1_tdi", "jtag1_tdo"; + function =3D "jtag"; + }; + + jtag2_pins: jtag2-pins { + pins =3D "jtag2_trst", "jtag2_tck", "jtag2_tms", "jtag2_tdi", + "jtag2_tdo"; + function =3D "jtag"; + }; + + pcie_pins: pcie-pins { + pins =3D "pcie_clkreq_n", "pcie_wake_n", "pcie_perst_n"; + function =3D "pcie"; + }; + + hdmi_pins: hdmi-pins { + pins =3D "hdmi_scl", "hdmi_sda", "hdmi_cec"; + function =3D "hdmi"; + }; + + rgmii0_pins: rgmii0-pins { + pins =3D "rgmii0_clk_125", "rgmii0_txen", "rgmii0_txclk", "rgmii0_txd0", + "rgmii0_txd1", "rgmii0_txd2", "rgmii0_txd3", "rgmii0_rxclk", + "rgmii0_rxdv", "rgmii0_rxd0", "rgmii0_rxd1", "rgmii0_rxd2", + "rgmii0_rxd3", "rgmii0_mdc", "rgmii0_mdio", "rgmii0_intb"; + function =3D "rgmii"; + }; + + rgmii1_pins: rgmii1-pins { + pins =3D "rgmii1_clk_125", "rgmii1_txen", "rgmii1_txclk", "rgmii1_txd0", + "rgmii1_txd1", "rgmii1_txd2", "rgmii1_txd3", "rgmii1_rxclk", + "rgmii1_rxdv", "rgmii1_rxd0", "rgmii1_rxd1", "rgmii1_rxd2", + "rgmii1_rxd3", "rgmii1_mdc", "rgmii1_mdio", "rgmii1_intb"; + function =3D "rgmii"; + }; + + i2s0_pins: i2s0-pins { + pins =3D "i2s0_bclk", "i2s0_wclk", "i2s0_sdi", "i2s0_sdo", "i2s_mclk"; + function =3D "i2s"; + }; + + i2s1_pins: i2s1-pins { + pins =3D "i2s1_bclk", "i2s1_wclk", "i2s1_sdi", "i2s1_sdo", "i2s_mclk"; + function =3D "i2s"; + }; + + i2s2_pins: i2s2-pins { + pins =3D "i2s2_bclk", "i2s2_wclk", "i2s2_sdi", "i2s2_sdo", "i2s_mclk"; + function =3D "i2s"; + }; + + usb0_pwren_pins: usb0-pwren-pins { + pins =3D "usb0_pwren"; + function =3D "usb"; + }; + + usb1_pwren_pins: usb1-pwren-pins { + pins =3D "usb1_pwren"; + function =3D "usb"; + }; + + i2c0_pins: i2c0-pins { + pins =3D "i2c0_scl", "i2c0_sda"; + function =3D "i2c"; + }; + + i2c1_pins: i2c1-pins { + pins =3D "i2c1_scl", "i2c1_sda"; + function =3D "i2c"; + }; + + i2c2_pins: i2c2-pins { + pins =3D "i2c2_scl", "i2c2_sda"; + function =3D "i2c"; + }; + + i2c3_pins: i2c3-pins { + pins =3D "i2c3_scl", "i2c3_sda"; + function =3D "i2c"; + }; + + i2c4_pins: i2c4-pins { + pins =3D "i2c4_scl", "i2c4_sda"; + function =3D "i2c"; + }; + + i2c5_pins: i2c5-pins { + pins =3D "i2c5_scl", "i2c5_sda"; + function =3D "i2c"; + }; + + i2c8_pins: i2c8-pins { + pins =3D "gpio92", "gpio93"; + function =3D "i2c"; + }; + + i2c10_pins: i2c10-pins { + pins =3D "i2c10_scl", "i2c10_sda"; + function =3D "i2c"; + }; + + i2c11_pins: i2c11-pins { + pins =3D "i2c11_scl", "i2c11_sda"; + function =3D "i2c"; + }; + + uart0_pins: uart0-pins { + pins =3D "uart0_tx", "uart0_rx"; + function =3D "uart"; + }; + + uart1_pins: uart1-pins { + pins =3D "uart1_tx", "uart1_rx", "uart1_cts", "uart1_rts"; + function =3D "uart"; + }; + + uart2_pins: uart2-pins { + pins =3D "uart2_tx", "uart2_rx"; + function =3D "uart"; + }; + + fan_pwm_pins: fan-pwm-pins { + pins =3D "fan_pwm"; + function =3D "pwm"; + }; + + fan_tach_pins: fan-tach-pins { + pins =3D "fan_tach"; + function =3D "fan_tach"; + }; + + mipi_csi0_pins: mipi-csi0-pins { + pins =3D "mipi_csi0_xvs", "mipi_csi0_xhs", "mipi_csi0_mclk"; + function =3D "mipi_csi"; + }; + + mipi_csi1_pins: mipi-csi1-pins { + pins =3D "mipi_csi1_xvs", "mipi_csi1_xhs", "mipi_csi1_mclk"; + function =3D "mipi_csi"; + }; + + mipi_csi2_pins: mipi-csi2-pins { + pins =3D "mipi_csi2_xvs", "mipi_csi2_xhs", "mipi_csi2_mclk"; + function =3D "mipi_csi"; + }; + + mipi_csi3_pins: mipi-csi3-pins { + pins =3D "mipi_csi3_xvs", "mipi_csi3_xhs", "mipi_csi3_mclk"; + function =3D "mipi_csi"; + }; + + mipi_csi4_pins: mipi-csi4-pins { + pins =3D "mipi_csi4_xvs", "mipi_csi4_xhs", "mipi_csi4_mclk"; + function =3D "mipi_csi"; + }; + + mipi_csi5_pins: mipi-csi5-pins { + pins =3D "mipi_csi5_xvs", "mipi_csi5_xhs", "mipi_csi5_mclk"; + function =3D "mipi_csi"; + }; + + s_mode_pins: s-mode-pins { + pins =3D "s_mode"; + function =3D "s_mode"; + }; + + boot_sel0_pins: boot-sel0-pins { + pins =3D "boot_sel0"; + function =3D "boot_sel"; + }; + + boot_sel1_pins: boot-sel1-pins { + pins =3D "boot_sel1"; + function =3D "boot_sel"; + }; + + boot_sel2_pins: boot-sel2-pins { + pins =3D "boot_sel2"; + function =3D "boot_sel"; + }; + + boot_sel3_pins: boot-sel3-pins { + pins =3D "boot_sel3"; + function =3D "boot_sel"; + }; + + ddr_ref_clk_sel_pins: ddr-ref-clk-sel-pins { + pins =3D "gpio95"; + function =3D "ddr_ref_clk_sel"; + }; + + lpddr_ref_clk_pins: lpddr-ref-clk-pins { + pins =3D "lpddr_ref_clk"; + function =3D "lpddr_ref_clk"; + }; + + spi0_pins: spi0-pins { + pins =3D "spi0_cs_n", "spi0_clk", "spi0_d0", "spi0_d1", "spi0_d2", + "spi0_d3"; + function =3D "spi"; + }; + + dual_spi1_pins: dual-spi1-pins { + pins =3D "spi1_cs0_n", "spi1_clk", "spi1_d0", "spi1_d1"; + function =3D "spi"; + }; + + quad_spi1_pins: quad-spi1-pins { + pins =3D "spi1_cs0_n", "spi1_cs1_n", "spi1_clk", "spi1_d0", "spi1_d1", + "spi1_d2", "spi1_d3"; + function =3D "spi"; + }; + + spi3_pins: spi3-pins { + pins =3D "spi3_cs_n", "spi3_clk", "spi3_di", "spi3_do"; + function =3D "spi"; + }; + }; +}; diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/e= swin/eic7700.dtsi index b3a230870315..b16e3e28632c 100644 --- a/arch/riscv/boot/dts/eswin/eic7700.dtsi +++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi @@ -349,6 +349,11 @@ gpioD: gpio-port@3 { }; }; =20 + pinctrl: pinctrl@51600080 { + compatible =3D "eswin,eic7700-pinctrl"; + reg =3D <0x0 0x51600080 0x0 0x1fff80>; + }; + clk: clock-controller@51828000 { compatible =3D "eswin,eic7700-clock"; reg =3D <0x0 0x51828000 0x0 0x300>; --=20 2.34.1 From nobody Fri Oct 2 06:59:09 2026 Received: from naesa05.arrow.com (naesa05.arrow.com [216.150.161.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B8E330648A; Tue, 4 Aug 2026 10:44:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=216.150.161.26 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785840283; cv=none; b=fnzGTn2/8BpQhOO9aj+LXwQfFxZqeA496TPw80EPlrHS5pg14sZBQcVp0ruc/BaQ9yikY4LLofCrUxiS7058w4PIKDLwxoP5lNkoAfShvGyGzM+uC1M6e/yQs5OuqIe/HEB+tB1+vBhRMaZ67u+h/A64BaExasKgiW9KcXFvUoY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785840283; c=relaxed/simple; bh=l14NkZUeEmSiEliJNOziJ+7kDTrcYuUPelCIBKPHRYs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=sXGymBjUCb3vkgorumJZ4M95dvzPP90j3MrO/zwMTXC7Pt0eDQH9NzRHfzVw12jDRQ+NamXruLYl/M/9t/9an+z/jsPNRqY+N5NUBFGWwRyy5shVOq17PchANjR1r4zxJta33CdK6ECR70BYS60n/LPHSMu2LJSXSibDksbGWPI= ARC-Authentication-Results: i=1; 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X-CSE-ConnectionGUID: bffZQSOBSUGxI5Bw/j7g3g== X-CSE-MsgGUID: rLRGZas7SZKfwSz7pDkUFQ== X-IronPort-AV: E=Sophos;i="6.25,204,1779170400"; d="scan'208";a="59629004" Received: from unknown (HELO eicahmirelay01.einfochips.com) ([10.100.49.50]) by naesa05out.arrow.com with ESMTP; 04 Aug 2026 04:44:39 -0600 Received: from AHMCPU1888.localdomain ([172.25.5.100]) by eicahmirelay01.einfochips.com with Microsoft SMTPSVC(10.0.20348.1); Tue, 4 Aug 2026 16:14:31 +0530 From: Pinkesh Vaghela To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Andi Shyti , Mika Westerberg , linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Min Lin Cc: Yulin Lu , Samuel Holland , Darshan Prajapati , Pinkesh Vaghela , Pritesh Patel Subject: [PATCH v3 4/8] dt-bindings: mfd: syscon: add ESWIN EIC7700 compatible Date: Tue, 4 Aug 2026 16:14:27 +0530 Message-Id: <20260804104431.1391839-5-pinkesh.vaghela@einfochips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260804104431.1391839-1-pinkesh.vaghela@einfochips.com> References: <20260804104431.1391839-1-pinkesh.vaghela@einfochips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 04 Aug 2026 10:44:31.0712 (UTC) FILETIME=[3B743600:01DD23FE] Content-Type: text/plain; charset="utf-8" Document ESWIN EIC7700 SoC compatible for syscon registers. Acked-by: Conor Dooley Signed-off-by: Pinkesh Vaghela --- Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentat= ion/devicetree/bindings/mfd/syscon.yaml index fe882d3f828b..8e24c6be2fdd 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -59,6 +59,7 @@ properties: - cirrus,ep7209-syscon3 - cnxt,cx92755-uc - econet,en751221-chip-scu + - eswin,eic7700-syscfg - freecom,fsg-cs2-system-controller - fsl,imx93-aonmix-ns-syscfg - fsl,imx93-wakeupmix-syscfg --=20 2.34.1 From nobody Fri Oct 2 06:59:09 2026 Received: from naesa05.arrow.com (naesa05.arrow.com [216.150.161.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4E89A4477F1; Tue, 4 Aug 2026 10:44:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=216.150.161.26 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785840284; cv=none; b=nIuodY0VQJhlbzuheiRR0XKxMWSYKOygeYdiYDSR4bQke4euRJmNYZG+NvYzW5r1/paKL8EzkrGyQAA7QE11h52+epTcQlzx6JvKkVC5rn51tSyi+uPAv30QENaaXqVZEoSRvym9IShWmxQEMpk6C/8D7ixiHLVjJYG+WWC1d4M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785840284; c=relaxed/simple; bh=IgPFcaWjJKZXYSiDEOt9HHAeookxKAzELEI3gWtwbJ0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=I6wymcA9osz8ozzhIY5SCsYYPBR0VntiTAJPyCR9XNU4VrSZJJAtIy3N4VTNlvlFMt9mkOZ7If4TdCiMEZqcfZ+oEJQj/0mt+fuu0G/+zCtjxOkWdudDXgFIX8mu/y+w+4QfhS0/5uSEtdm+Q1J8t2QefAAbVdCs9iKnJhv/DFI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=einfochips.com; spf=pass smtp.mailfrom=einfochips.com; dkim=pass (2048-bit key) header.d=einfochips.com header.i=@einfochips.com header.b=k4fg2y3I; arc=none smtp.client-ip=216.150.161.26 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=einfochips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=einfochips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=einfochips.com header.i=@einfochips.com header.b="k4fg2y3I" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=einfochips.com; i=@einfochips.com; l=1135; q=dns/txt; s=NAESA-Selector1; t=1785840283; x=1817376283; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fhMulqfAdieip+w70VJod08BqyqQUojtyVidc3DwEBk=; b=k4fg2y3IP/+LRnH+CMXq4umTA8zb9sPNx1oPwGZIITZ8+TREpr8E3/XP 6u6l5V1O9C6Q+IGSZbUodPADPobSWORnDROF3Ywg8YgoM3JUrTYmoSRbA OAMVCz6VGga65Mn915nAmS37mY+PWuWxIAmsNfrEIUfp5xh1cFMy7T9/D ay4CzYZ61YTZOzDi99xjL4C+BoZV+VyGsuQ+gxgCRmpqpw9KpHRTFG9H1 pkOwRXxN+BPfXGJ9sIrDlIt0MPi03PCHDRvW2H4UBFAzVUK3N1+lM6ogt NaXTWWG1vnPLFPbGSqb93LSKCcJfIl5vEUWNjjJIxJUpqs1U85aGfUia6 g==; X-CSE-ConnectionGUID: rvS3T3juRemI57OTRGZ4DQ== X-CSE-MsgGUID: zIyuZ8rdSr2Tgr21PrQ3Nw== X-IronPort-AV: E=Sophos;i="6.25,204,1779170400"; d="scan'208";a="59629008" Received: from unknown (HELO eicahmirelay01.einfochips.com) ([10.100.49.50]) by naesa05out.arrow.com with ESMTP; 04 Aug 2026 04:44:41 -0600 Received: from AHMCPU1888.localdomain ([172.25.5.100]) by eicahmirelay01.einfochips.com with Microsoft SMTPSVC(10.0.20348.1); Tue, 4 Aug 2026 16:14:31 +0530 From: Pinkesh Vaghela To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Andi Shyti , Mika Westerberg , linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Min Lin Cc: Yulin Lu , Samuel Holland , Darshan Prajapati , Pinkesh Vaghela , Pritesh Patel Subject: [PATCH v3 5/8] riscv: dts: eswin: add hsp bus node Date: Tue, 4 Aug 2026 16:14:28 +0530 Message-Id: <20260804104431.1391839-6-pinkesh.vaghela@einfochips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260804104431.1391839-1-pinkesh.vaghela@einfochips.com> References: <20260804104431.1391839-1-pinkesh.vaghela@einfochips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 04 Aug 2026 10:44:31.0759 (UTC) FILETIME=[3B7B61F0:01DD23FE] Content-Type: text/plain; charset="utf-8" Add an HSP bus node to manage the HSP CFG clock used by HSP peripherals. This clock is required for accessing both the HSP CSR registers and the register spaces of HSP peripheral devices. Signed-off-by: Pinkesh Vaghela --- arch/riscv/boot/dts/eswin/eic7700.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/e= swin/eic7700.dtsi index b16e3e28632c..771a88645d83 100644 --- a/arch/riscv/boot/dts/eswin/eic7700.dtsi +++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi @@ -252,6 +252,19 @@ plic: interrupt-controller@c000000 { #interrupt-cells =3D <1>; }; =20 + hsp: bus@50400000 { + compatible =3D "simple-pm-bus"; + ranges =3D <0x0 0x50400000 0x0 0x50400000 0x0 0xa0000>; + clocks =3D <&clk EIC7700_CLK_GATE_HSP_CFG_CLK>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + syscon: syscon@50440000 { + compatible =3D "eswin,eic7700-syscfg", "syscon"; + reg =3D <0x0 0x50440000 0x0 0x2000>; + }; + }; + uart0: serial@50900000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0x0 0x50900000 0x0 0x10000>; --=20 2.34.1 From nobody Fri Oct 2 06:59:09 2026 Received: from naesa05.arrow.com (naesa05.arrow.com [216.150.161.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8093944E64B; Tue, 4 Aug 2026 10:44:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=216.150.161.26 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785840286; cv=none; b=YIoaG+UrpoAhylW6y4UU5VslYKmUKwMjMpLBD/SyyE05t74T7qbu/OolPZoG44VUXAl8ssGC+ACkvgIut7FOl590IKYACrfPy383YhJjt7V3gcazNNrjNGWxVfn8ijwmXAu0oCC5KA9DxWEpfuBVQlascw3RTyvLEoiWPVT04TI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785840286; c=relaxed/simple; bh=zhMkW4peb4ffgzKBsDrgfAIZ4eDoQR3OisNYIwJRv90=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=SsJMb7eb8IWG6WbZOVwL3iL8aPRzdfg9Isq32xs4lFspCEBfpfBj/V0UdZNVHGJxaN21fh5kCYtJn4TY4VlSVJnxdGJXvkWaKwmujtAYiVZCQ/QfquHLVK/Vb6LL1zNrEMfz1Xp6GQyU7OPVxCayztpSDGoaQ6FlZJkbDAEk9m8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=einfochips.com; spf=pass smtp.mailfrom=einfochips.com; dkim=pass (2048-bit key) header.d=einfochips.com header.i=@einfochips.com header.b=KtInZFKK; arc=none smtp.client-ip=216.150.161.26 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=einfochips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=einfochips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=einfochips.com header.i=@einfochips.com header.b="KtInZFKK" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=einfochips.com; i=@einfochips.com; l=1013; q=dns/txt; s=NAESA-Selector1; t=1785840284; x=1817376284; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RFCB65wa4dZGmLVFZqs+LWJsSkVireZtnJei79QMCq4=; b=KtInZFKKFZo1WOuzyn7si/DOXyxuHhvWdwI1ibTCnJxuaHubFTSV8uuH HC2CEy1z+I5uJlv9171eGvOUis7WC7Zam7StiiHKGkDY+G0Hj2Y1ZKsQv KMVu3PuRdZXofWkK3dMZsyDMDwaQ8D2O61n0vVkQzAqJRxyI8ZbLQWmy6 DWa3ZK+lkOYMuIxoc8UwpXTBFU7+cHr1OHR9KVVVMOkCSFHK0ijh1G9Nr /OvImWV9Q8s5pUCkyLID1reP6pHciHmLEbfn0DWu8Lqj+pU9IQCgSlPTg S4a+jV8NXt3nx1FkT753HDfphwW8/r9YiZDG0PACiyo6sC/K9MVL78kd6 A==; X-CSE-ConnectionGUID: hJTU34xeRMOIuzZLZDfWWw== X-CSE-MsgGUID: 4PFe7mSEQhKnRL01aFEQsw== X-IronPort-AV: E=Sophos;i="6.25,204,1779170400"; d="scan'208";a="59629011" Received: from unknown (HELO eicahmirelay01.einfochips.com) ([10.100.49.50]) by naesa05out.arrow.com with ESMTP; 04 Aug 2026 04:44:43 -0600 Received: from AHMCPU1888.localdomain ([172.25.5.100]) by eicahmirelay01.einfochips.com with Microsoft SMTPSVC(10.0.20348.1); Tue, 4 Aug 2026 16:14:31 +0530 From: Pinkesh Vaghela To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Andi Shyti , Mika Westerberg , linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Min Lin Cc: Yulin Lu , Samuel Holland , Darshan Prajapati , Pinkesh Vaghela , Pritesh Patel Subject: [PATCH v3 6/8] dt-bindings: i2c: dw: add ESWIN EIC7700 SoC I2C controller Date: Tue, 4 Aug 2026 16:14:29 +0530 Message-Id: <20260804104431.1391839-7-pinkesh.vaghela@einfochips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260804104431.1391839-1-pinkesh.vaghela@einfochips.com> References: <20260804104431.1391839-1-pinkesh.vaghela@einfochips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 04 Aug 2026 10:44:31.0806 (UTC) FILETIME=[3B828DE0:01DD23FE] Content-Type: text/plain; charset="utf-8" From: Pritesh Patel Add compatible string for the DesignWare-based I2C controllers present in ESWIN EIC7700 SoC. Signed-off-by: Pritesh Patel Acked-by: Conor Dooley Acked-by: Mika Westerberg Signed-off-by: Pinkesh Vaghela --- Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml= b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml index 467bdcbb8538..ea3d4d4c299f 100644 --- a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml @@ -40,6 +40,7 @@ properties: - const: snps,designware-i2c - items: - enum: + - eswin,eic7700-i2c - mobileye,eyeq6lplus-i2c - mscc,ocelot-i2c - sophgo,sg2044-i2c --=20 2.34.1 From nobody Fri Oct 2 06:59:09 2026 Received: from naesa05.arrow.com (naesa05.arrow.com [216.150.161.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F99944AB66; Tue, 4 Aug 2026 10:44:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=216.150.161.26 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785840288; cv=none; b=jbKsgD/Q6k9vcfGjiVcLz/G+Jx0y8bk0jKgStwS9czpdnQ189WRIA2ba1CVbAb/PEuo8u3czHbTyQXltuSovvUC3uBOqRMaOuVTqlCaelg9C/BDHUtIhMA34E/XHoJnuzapYv89elU9NX5ZMqwsDH6mO/m9hilIVLmPV6PubGyA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785840288; c=relaxed/simple; bh=17QzbtiB/shhV0BaVT/AFJ17Mwo+VmAs7UmgySXPeik=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ug0eoO6VPNnV9mP70mW/wuJxz3Vf5w3U3vGT5YR0D4fcpBSM69qObAiqglXV6hbWKdzx2lUpF0lHgrBwa7woCltgw86p6NTjoNM1TTHADK5HvThsgwvs0RbM1e4/6ePtinE9zRHWuCndLIrOD6VjfUegt0/QmFBdXJxI/T2s4fY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=einfochips.com; spf=pass smtp.mailfrom=einfochips.com; dkim=pass (2048-bit key) header.d=einfochips.com header.i=@einfochips.com header.b=Fkq07fWj; arc=none smtp.client-ip=216.150.161.26 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=einfochips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=einfochips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=einfochips.com header.i=@einfochips.com header.b="Fkq07fWj" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=einfochips.com; i=@einfochips.com; l=6794; q=dns/txt; s=NAESA-Selector1; t=1785840286; x=1817376286; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pMEf5JnKB6gHkx/2YvWwl/Wb8vfc28oBObkxqaU09UE=; b=Fkq07fWjMJAlU1D6i3aSoxH4OwkP8cR3BGkptIaj8NLHKQUXfgRS8dx+ V1L5kEkPeyhZdLvVmRgk8Tq+BXCIZBQvq38yiQpXKYomHdqc05ZzmacyU V50rhI4BhM7gB/GEE3kPqCONoji3Uk79VQqT3drX1doN0GbknoN8WM5mr X46CTpZ2RBiK1Hx+l3So/tMUfT77okpWlRblwfdxwX1hi9rbUuPmwQ0mJ GcK882Pj/z02in5j8IwzaRSCdGZ5v/vHUAjITNyVlYmq7aCFFHXfHrZcF a4aQDN9JGpfbkJso/d6s/5qyeq76u2RHy+Ww8aDJROIAvk1Jg6XfKGfYe g==; X-CSE-ConnectionGUID: t19JJJaHRYCuaJ98Lkkjgg== X-CSE-MsgGUID: qFrZlxxZQcyQchAKdUFuTA== X-IronPort-AV: E=Sophos;i="6.25,204,1779170400"; d="scan'208";a="59629013" Received: from unknown (HELO eicahmirelay01.einfochips.com) ([10.100.49.50]) by naesa05out.arrow.com with ESMTP; 04 Aug 2026 04:44:45 -0600 Received: from AHMCPU1888.localdomain ([172.25.5.100]) by eicahmirelay01.einfochips.com with Microsoft SMTPSVC(10.0.20348.1); Tue, 4 Aug 2026 16:14:31 +0530 From: Pinkesh Vaghela To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Andi Shyti , Mika Westerberg , linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Min Lin Cc: Yulin Lu , Samuel Holland , Darshan Prajapati , Pinkesh Vaghela , Pritesh Patel Subject: [PATCH v3 7/8] riscv: dts: eswin: add I2C controller support Date: Tue, 4 Aug 2026 16:14:30 +0530 Message-Id: <20260804104431.1391839-8-pinkesh.vaghela@einfochips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260804104431.1391839-1-pinkesh.vaghela@einfochips.com> References: <20260804104431.1391839-1-pinkesh.vaghela@einfochips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 04 Aug 2026 10:44:31.0822 (UTC) FILETIME=[3B84FEE0:01DD23FE] Content-Type: text/plain; charset="utf-8" From: Pritesh Patel Add I2C nodes for EIC7700 SoC. Also add nodes for corresponding slave devices in dts file and enable them for HiFive Premier P550 board Signed-off-by: Pritesh Patel Signed-off-by: Pinkesh Vaghela --- .../dts/eswin/eic7700-hifive-premier-p550.dts | 56 +++++++ arch/riscv/boot/dts/eswin/eic7700.dtsi | 156 ++++++++++++++++++ 2 files changed, 212 insertions(+) diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/ar= ch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts index 3101fd90d171..50c15e08a57f 100644 --- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts +++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts @@ -130,6 +130,62 @@ &gpio111_pins { input-disable; }; =20 +&aon_i2c0 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0_pins>; + + eeprom@50 { + compatible =3D "atmel,24c02"; + reg =3D <0x50>; + }; +}; + +&aon_i2c1 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c1_pins>; + + adc@10 { + compatible =3D "microchip,pac1934"; + reg =3D <0x10>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + channel@1 { + reg =3D <0x1>; + shunt-resistor-micro-ohms =3D <1000>; + label =3D "VDD_SOM"; + }; + + channel@2 { + reg =3D <0x2>; + shunt-resistor-micro-ohms =3D <1000>; + label =3D "VDD_SOC"; + }; + + channel@3 { + reg =3D <0x3>; + shunt-resistor-micro-ohms =3D <1000>; + label =3D "VDD_CPU"; + }; + + channel@4 { + reg =3D <0x4>; + shunt-resistor-micro-ohms =3D <1000>; + label =3D "VDD_LPDDR"; + }; + }; + + power-sensor@44 { + compatible =3D "ti,ina226"; + reg =3D <0x44>; + #io-channel-cells =3D <1>; + label =3D "sys_power"; + shunt-resistor =3D <1000>; + }; +}; + &pinctrl { pinctrl-names =3D "default"; pinctrl-0 =3D <&gpio0_pins>, <&gpio5_pins>, <&gpio11_pins>, diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/e= swin/eic7700.dtsi index 771a88645d83..c13432d14504 100644 --- a/arch/riscv/boot/dts/eswin/eic7700.dtsi +++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi @@ -315,6 +315,162 @@ uart4: serial@50940000 { status =3D "disabled"; }; =20 + i2c0: i2c@50950000 { + compatible =3D "eswin,eic7700-i2c", "snps,designware-i2c"; + reg =3D <0x0 0x50950000 0x0 0x8000>; + interrupts =3D <105>; + clocks =3D <&clk EIC7700_CLK_GATE_LSP_I2C0_PCLK>; + clock-names =3D "ref"; + clock-frequency =3D <100000>; + resets =3D <&reset EIC7700_RESET_I2C0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c1: i2c@50960000 { + compatible =3D "eswin,eic7700-i2c", "snps,designware-i2c"; + reg =3D <0x0 0x50960000 0x0 0x8000>; + interrupts =3D <106>; + clocks =3D <&clk EIC7700_CLK_GATE_LSP_I2C1_PCLK>; + clock-names =3D "ref"; + clock-frequency =3D <100000>; + resets =3D <&reset EIC7700_RESET_I2C1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c2: i2c@50970000 { + compatible =3D "eswin,eic7700-i2c", "snps,designware-i2c"; + reg =3D <0x0 0x50970000 0x0 0x8000>; + interrupts =3D <107>; + clocks =3D <&clk EIC7700_CLK_GATE_LSP_I2C2_PCLK>; + clock-names =3D "ref"; + clock-frequency =3D <100000>; + resets =3D <&reset EIC7700_RESET_I2C2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c3: i2c@50980000 { + compatible =3D "eswin,eic7700-i2c", "snps,designware-i2c"; + reg =3D <0x0 0x50980000 0x0 0x8000>; + interrupts =3D <108>; + clocks =3D <&clk EIC7700_CLK_GATE_LSP_I2C3_PCLK>; + clock-names =3D "ref"; + clock-frequency =3D <100000>; + resets =3D <&reset EIC7700_RESET_I2C3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c4: i2c@50990000 { + compatible =3D "eswin,eic7700-i2c", "snps,designware-i2c"; + reg =3D <0x0 0x50990000 0x0 0x8000>; + interrupts =3D <109>; + clocks =3D <&clk EIC7700_CLK_GATE_LSP_I2C4_PCLK>; + clock-names =3D "ref"; + clock-frequency =3D <100000>; + resets =3D <&reset EIC7700_RESET_I2C4>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c5: i2c@509a0000 { + compatible =3D "eswin,eic7700-i2c", "snps,designware-i2c"; + reg =3D <0x0 0x509a0000 0x0 0x8000>; + interrupts =3D <110>; + clocks =3D <&clk EIC7700_CLK_GATE_LSP_I2C5_PCLK>; + clock-names =3D "ref"; + clock-frequency =3D <100000>; + resets =3D <&reset EIC7700_RESET_I2C5>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c6: i2c@509b0000 { + compatible =3D "eswin,eic7700-i2c", "snps,designware-i2c"; + reg =3D <0x0 0x509b0000 0x0 0x8000>; + interrupts =3D <111>; + clocks =3D <&clk EIC7700_CLK_GATE_LSP_I2C6_PCLK>; + clock-names =3D "ref"; + clock-frequency =3D <100000>; + resets =3D <&reset EIC7700_RESET_I2C6>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c7: i2c@509c0000 { + compatible =3D "eswin,eic7700-i2c", "snps,designware-i2c"; + reg =3D <0x0 0x509c0000 0x0 0x8000>; + interrupts =3D <112>; + clocks =3D <&clk EIC7700_CLK_GATE_LSP_I2C7_PCLK>; + clock-names =3D "ref"; + clock-frequency =3D <100000>; + resets =3D <&reset EIC7700_RESET_I2C7>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c8: i2c@509d0000 { + compatible =3D "eswin,eic7700-i2c", "snps,designware-i2c"; + reg =3D <0x0 0x509d0000 0x0 0x8000>; + interrupts =3D <113>; + clocks =3D <&clk EIC7700_CLK_GATE_LSP_I2C8_PCLK>; + clock-names =3D "ref"; + clock-frequency =3D <100000>; + resets =3D <&reset EIC7700_RESET_I2C8>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c9: i2c@509e0000 { + compatible =3D "eswin,eic7700-i2c", "snps,designware-i2c"; + reg =3D <0x0 0x509e0000 0x0 0x8000>; + interrupts =3D <114>; + clocks =3D <&clk EIC7700_CLK_GATE_LSP_I2C9_PCLK>; + clock-names =3D "ref"; + clock-frequency =3D <100000>; + resets =3D <&reset EIC7700_RESET_I2C9>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + aon_i2c0: i2c@51830000 { + compatible =3D "eswin,eic7700-i2c", "snps,designware-i2c"; + reg =3D <0x0 0x51830000 0x0 0x8000>; + interrupts =3D <290>; + clocks =3D <&clk EIC7700_CLK_GATE_AON_I2C0_PCLK>; + clock-names =3D "ref"; + clock-frequency =3D <100000>; + resets =3D <&reset EIC7700_RESET_ANO0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + aon_i2c1: i2c@51838000 { + compatible =3D "eswin,eic7700-i2c", "snps,designware-i2c"; + reg =3D <0x0 0x51838000 0x0 0x8000>; + interrupts =3D <291>; + clocks =3D <&clk EIC7700_CLK_GATE_AON_I2C1_PCLK>; + clock-names =3D "ref"; + clock-frequency =3D <100000>; + resets =3D <&reset EIC7700_RESET_ANO1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + gpio@51600000 { compatible =3D "snps,dw-apb-gpio"; reg =3D <0x0 0x51600000 0x0 0x80>; --=20 2.34.1 From nobody Fri Oct 2 06:59:09 2026 Received: from naesa05.arrow.com (naesa05.arrow.com [216.150.161.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1E5A54519B7; Tue, 4 Aug 2026 10:44:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=216.150.161.26 ARC-Seal: i=1; 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d="scan'208";a="59629015" Received: from unknown (HELO eicahmirelay01.einfochips.com) ([10.100.49.50]) by naesa05out.arrow.com with ESMTP; 04 Aug 2026 04:44:46 -0600 Received: from AHMCPU1888.localdomain ([172.25.5.100]) by eicahmirelay01.einfochips.com with Microsoft SMTPSVC(10.0.20348.1); Tue, 4 Aug 2026 16:14:31 +0530 From: Pinkesh Vaghela To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Andi Shyti , Mika Westerberg , linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Min Lin Cc: Yulin Lu , Samuel Holland , Darshan Prajapati , Pinkesh Vaghela , Pritesh Patel Subject: [PATCH v3 8/8] riscv: dts: eswin: add watchdog support Date: Tue, 4 Aug 2026 16:14:31 +0530 Message-Id: <20260804104431.1391839-9-pinkesh.vaghela@einfochips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260804104431.1391839-1-pinkesh.vaghela@einfochips.com> References: <20260804104431.1391839-1-pinkesh.vaghela@einfochips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 04 Aug 2026 10:44:31.0884 (UTC) FILETIME=[3B8E74C0:01DD23FE] Content-Type: text/plain; charset="utf-8" From: Pritesh Patel Add watchdog node for ESWIN EIC7700 SoC and enable them for HiFive Premier P550 board Signed-off-by: Pritesh Patel Signed-off-by: Pinkesh Vaghela --- .../dts/eswin/eic7700-hifive-premier-p550.dts | 16 ++++++++ arch/riscv/boot/dts/eswin/eic7700.dtsi | 40 +++++++++++++++++++ 2 files changed, 56 insertions(+) diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/ar= ch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts index 50c15e08a57f..6f6cb45b3070 100644 --- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts +++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts @@ -207,3 +207,19 @@ &uart2 { pinctrl-names =3D "default"; pinctrl-0 =3D <&uart2_pins>; }; + +&wdt0 { + status =3D "okay"; +}; + +&wdt1 { + status =3D "okay"; +}; + +&wdt2 { + status =3D "okay"; +}; + +&wdt3 { + status =3D "okay"; +}; diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/e= swin/eic7700.dtsi index c13432d14504..f873e9eeb929 100644 --- a/arch/riscv/boot/dts/eswin/eic7700.dtsi +++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi @@ -265,6 +265,46 @@ syscon: syscon@50440000 { }; }; =20 + wdt0: watchdog@50800000 { + compatible =3D "snps,dw-wdt"; + reg =3D <0x0 0x50800000 0x0 0x4000>; + interrupts =3D <87>; + clocks =3D <&clk EIC7700_CLK_GATE_LSP_WDT0_PCLK>; + clock-names =3D "tclk"; + resets =3D <&reset EIC7700_RESET_WDT0>; + status =3D "disabled"; + }; + + wdt1: watchdog@50804000 { + compatible =3D "snps,dw-wdt"; + reg =3D <0x0 0x50804000 0x0 0x4000>; + interrupts =3D <88>; + clocks =3D <&clk EIC7700_CLK_GATE_LSP_WDT1_PCLK>; + clock-names =3D "tclk"; + resets =3D <&reset EIC7700_RESET_WDT1>; + status =3D "disabled"; + }; + + wdt2: watchdog@50808000 { + compatible =3D "snps,dw-wdt"; + reg =3D <0x0 0x50808000 0x0 0x4000>; + interrupts =3D <89>; + clocks =3D <&clk EIC7700_CLK_GATE_LSP_WDT2_PCLK>; + clock-names =3D "tclk"; + resets =3D <&reset EIC7700_RESET_WDT2>; + status =3D "disabled"; + }; + + wdt3: watchdog@5080c000 { + compatible =3D "snps,dw-wdt"; + reg =3D <0x0 0x5080c000 0x0 0x4000>; + interrupts =3D <90>; + clocks =3D <&clk EIC7700_CLK_GATE_LSP_WDT3_PCLK>; + clock-names =3D "tclk"; + resets =3D <&reset EIC7700_RESET_WDT3>; + status =3D "disabled"; + }; + uart0: serial@50900000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0x0 0x50900000 0x0 0x10000>; --=20 2.34.1