From nobody Fri Oct 2 06:58:27 2026 Received: from DM5PR21CU001.outbound.protection.outlook.com (mail-centralusazon11011021.outbound.protection.outlook.com [52.101.62.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8023243B495; Tue, 4 Aug 2026 08:37:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.62.21 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785832641; cv=fail; b=Cvjgt1F0JP2nFo1XBg7XCTQnTbxf3qyQeoF8/jeu8gPmIlZsUSunr+qX68pQgexOtxYTNZdYLccOU0rE6P9jI/ubdYkpIXvs8cCpm5k1W7rsynGXuFpWS7Op5AGsU/+zM6OliKmwAmyQ86Q5ccQGBVV2Kg4lTXDGCYInKx+phI4= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785832641; c=relaxed/simple; bh=IIr0K0BnQakrfZ+rTMnbrLtKNmLiI8b52LuQuaTmOMA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=oO+o93EBLcLNqgi3v2eAQBT/SeZIyNFjKyMyO0vm4+HGSUgOiJ6SF6PcOgD2vp/X7aGeCUZnKC4jI4aPLvR2fT9SXdjkK8peFLQdhtVrxxuxDJMO4z8TefwKrXTk2N5UCJ2ueCBzA8JM76jEtxY782tMCmlkm3m3yaZX9rtWR80= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=TFVZu3Qa; arc=fail smtp.client-ip=52.101.62.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="TFVZu3Qa" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=fkArlDqGfdlvtOQBAKgMCiJZW8TTIJ4LJdXDhYoEs/ZOw5WmaiYpDqhsu0uCXGapiphVRUDqKkSgrqW8A/1du+3DKME+wO5L6zyzAmGKpfuB84mtHaTRB6ivHnDatoQwyVpm7cxU51rnbhawegPGkpSN9mdwoXyd0V+vNULTUbf90FANcJH5LwzHog+C9QTRgj7bclb2hiL7gOX5TcI1Fr6KiBujFCw+tSPFcdEIPhPFNc+QsnP/Y/vgZ65jxIX+asryPzRS97gMIa7w52zpltJNcsBC7x8DDgGSmRxfLYm4xfbxqRQ+zc5PwB7gXWztBUT+AgZnV0DjFz4mlSWuFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=7VDKCytwk+PDwH2DIYibsqkK5dHGQnNzHXpkcLg7jMg=; b=la3hK8f4nW3jhrVGLy6Pa61zSxKaCtlK5WePRiR82WKDKWYI+kVaCx1/EQZrj1Oh1mUqbGB/a8yGnS/I1mCG5lx8iQ+QQSdsPKdUMXeOOpdbf3gLZVdk8FIxbMkJR5fG+xibITU4IzeZK1kGXbsDoKOdrs+gy5Z8V0ByBZz5B0anyTrgBYKpc+OPVJXi8jJ8HRV5qOF8g8D5Y+vERGyqbzbB1HATrk4Sj0Xb2qCI6QEw9nVoEUykoTj8afr2nmcycx8h0clxAiJnouRm5T209KLAEAM5eBX+nE6lrifuZiqueLSFomGl+1pFOVTmOHPEa810xLwwWrUpsbqlgcuEBg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=lunn.ch smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=7VDKCytwk+PDwH2DIYibsqkK5dHGQnNzHXpkcLg7jMg=; b=TFVZu3Qac7GTJH+1lMzjVue+UIzRGI60Y/dJuTKNhD3Me3ZNGncblwDu3n/EFS9s/9bXMscg1y+zQSweHlBl2htdNrj+iyWhlFGKDhVVgsBpls9Y6HFh6J1rgls3fanMIOnpwdN7fDBRs34fcMY1hdaoSoSlcHDPa7MrqpIVS9wweAOkMwzCeEYH1dmMI+EXdubDwnqpZVs+wxFKPCkVExLc/b+mAyop71QqLEdxUF6mVWPZBXl1tJEo7+NAw1L9jgZi8uU/spOjhMeVxKXvsnXS5rHN9K8PqUT8HP7THx+lJOgTJzVG2dXWhS7QoH8gkzd6jGxs5e2m9GaSs9S1yw== Received: from BL1PR13CA0127.namprd13.prod.outlook.com (2603:10b6:208:2bb::12) by MW6PR12MB8915.namprd12.prod.outlook.com (2603:10b6:303:23e::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.270.17; Tue, 4 Aug 2026 08:37:11 +0000 Received: from BL6PEPF00020E60.namprd04.prod.outlook.com (2603:10b6:208:2bb:cafe::40) by BL1PR13CA0127.outlook.office365.com (2603:10b6:208:2bb::12) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.292.15 via Frontend Transport; Tue, 4 Aug 2026 08:37:11 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by BL6PEPF00020E60.mail.protection.outlook.com (10.167.249.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.292.8 via Frontend Transport; Tue, 4 Aug 2026 08:37:10 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 4 Aug 2026 01:36:54 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 4 Aug 2026 01:36:53 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Tue, 4 Aug 2026 01:36:45 -0700 From: Tariq Toukan To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , , Paolo Abeni , Sabrina Dubroca CC: Aleksandr Loktionov , Alexei Lazar , Boris Pismenny , Carolina Jubran , Chris Mi , Cosmin Ratiu , Daniel Zahka , Doruk Tan Ozturk , Dragos Tatulea , Gal Pressman , Jacob Keller , Jianbo Liu , Kees Cook , Lama Kayal , Leon Romanovsky , , , , Mark Bloch , "Patrisious Haddad" , Raed Salem , Rahul Rameshbabu , Saeed Mahameed , Shuah Khan , Shuah Khan , Simon Horman , Stanislav Fomichev , Stanislav Fomichev , Tariq Toukan Subject: [PATCH net-next V2 01/13] net/mlx5e: Generalize TC <-> IPsec mutual exclusion Date: Tue, 4 Aug 2026 11:35:23 +0300 Message-ID: <20260804083535.2946459-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260804083535.2946459-1-tariqt@nvidia.com> References: <20260804083535.2946459-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00020E60:EE_|MW6PR12MB8915:EE_ X-MS-Office365-Filtering-Correlation-Id: 5b00a0e7-8e69-4c1d-418e-08def203939c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|1800799024|36860700016|23010399003|18002099003|22082099003|3023799007|6133799003|56012099006|10067099003|11063799006; X-Microsoft-Antispam-Message-Info: n1NZxQX2Xy10jaTqLY9+Apoyi5T6FGjXQZb7C70Xw68d0bCFmXfmPmjRbbA8lJgsWxw/zCDkcdWj33k1y3JFy1StbyIsg417jxp/OKUyDqsGK5rvfY/7BAnA5lm+oz27V/W0SeULIEw/otKNPmzWqIGg8XC7rUkQHPfik5tryyOZcxdaZdv79UEAQrftdne2191+VeWun8DyOYji4x0ONOMSyOm0PD+zFwbEs083CkX4H+Hgb8GV2SgmEZxcTjDViXeqrgPlK3EIJIWcdsdb/tTgBPn8h9yJfpgcZIpZQpLYV8Cb4EGcVRdQHo9HbSmt3hx2G20azosQpQY3ltb6trktPNdAv1X+oHMA7EAtVlS807ox0aB/tv8X/ufrVNosv9xIQuuKpvgJTbDFAG4siGV8cLkH+m3qNnO076aNvPfLF/mWehz2VKEg3DPuMNyst3CxZ4wvOK6Bw3AwMbGFSvk/XpykARBENLFUs37vJT0ZzlgpQBEqdokSGo18gE6sIq5IH2B0qGjEBXFFlynK6bgbVwb6Q+JiW5IkbSAierbJPhvt2GmdmChdO9KsrBI1H/5f62XVmpSZ/CDb4RMc1xXaRNIEy0rc7N438cxPHsbrA+6Q6AsE2en1GXDDZN4jRynRU5+M4yUv6Fh1XIkPLpAHo/q+QCQ9vYZBJliNY365Rb5cDhBFuvQHlhk7k4XutXkMxBsCP2mDVM5ecqdeAQ== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(82310400026)(1800799024)(36860700016)(23010399003)(18002099003)(22082099003)(3023799007)(6133799003)(56012099006)(10067099003)(11063799006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: zQX4b9nxliFiL4JFlKjCsGr1LkC5AcfQqCa65K5kKlHhBAJhONe3+XqQ28VVvFygdoaFjsYr6545HV2HmYVPfi5NySbLs4laYELUZXXpzQGzJN8lNRbA1J0hWGhxfrqC0x6FY5NW8HgU9q252ozntfI5985aGH08w92/zCAKxb3akSMr9g5aj4W9COcT/iZk82Smk9Owr7f5lwtuW2TMVyilZ0PGtopGwIKkq5aZIOtYjh/NAgKpsrvFhmd8pyaatRTU5LOshlWG7ZRjA7tLD2wJ7+/crb+oR67JSQb/Zx+g54vHcwCHF34PbfCF3DDEHtxg+ybATUE0qM6yZXd18oFf8rweibUIwUiuq8QGsIcxon5+Z3pbZWs6iSOREAyXsmAmthWz3KKLdlQ+u3zFfR/jgvjaXiZ+UuirDK72lhJjOtrL7hOCjOt/LNasr12B X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Aug 2026 08:37:10.6641 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5b00a0e7-8e69-4c1d-418e-08def203939c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E60.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB8915 Content-Type: text/plain; charset="utf-8" From: Cosmin Ratiu There is a mechanism to mutually exclude TC offload and IPsec offload from the same interface (commit [1]) due to ordering issues between SW and HW paths. TC offload makes use of flow_tag to carry the tc mark (even when 0). Upcoming changes to accel protocols will make use of flow_tag to carry the protocol marker. As the flow_tag cannot be partially modified by a steering rule, the last rule setting the flow_tag will overwrite any previous ones. This means that TC offload cannot be active at the same time with any of the currently implemented accel protocols (IPsec, MACsec, PSP). Generalize the TC <-> IPsec mutual exclusion mechanism to be usable by more accel protocols: - move the existing mlx5e_ipsec_{,un}block_tc_offload functions to en_accel.h, rename them to mlx5e_accel_{,un}block_tc_offload. - rename the mdev counter from num_block_ipsec to num_accel. - rename is_tc_ipsec_order_check_needed -> is_tc_accel_check_needed and make it not bail out when IPsec isn't configured. - replace the condition use of the esw write lock as a protection for incrementing the counter with a new mutex instead. The esw might not be available, and it wasn't used correctly on the decrement path anyway, allowing races to happen. Using a dedicated mutex for these counters makes it clear and avoids races. - add underflow warnings for the two counters to catch future miscounting bugs. - move counters and the new lock into a dedicated struct in mlx5_core_dev named 'offload_block'. Now offload_block.num_tc means the number of tc blocks due to accel rules and ofload_block.num_accel means the number of accel blocks due to tc rules. [1] commit c8e350e62fc5 ("net/mlx5e: Make TC and IPsec offloads mutually exclusive on a netdev") Signed-off-by: Cosmin Ratiu Reviewed-by: Dragos Tatulea Reviewed-by: Carolina Jubran Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/en_accel/en_accel.h | 22 ++++++++ .../mellanox/mlx5/core/en_accel/ipsec_fs.c | 54 +++---------------- .../net/ethernet/mellanox/mlx5/core/en_tc.c | 46 +++++++++------- .../net/ethernet/mellanox/mlx5/core/main.c | 3 ++ include/linux/mlx5/driver.h | 7 ++- 5 files changed, 64 insertions(+), 68 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h b/= drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h index 3f212e46fc2f..8a2ea7616440 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h @@ -218,6 +218,28 @@ static inline void mlx5e_accel_tx_finish(struct mlx5e_= txqsq *sq, #endif } =20 +static inline int mlx5e_accel_block_tc_offload(struct mlx5_core_dev *mdev) +{ + int ret =3D 0; + + mutex_lock(&mdev->offload_block.lock); + if (mdev->offload_block.num_accel) + ret =3D -EBUSY; + else + mdev->offload_block.num_tc++; + mutex_unlock(&mdev->offload_block.lock); + + return ret; +} + +static inline void mlx5e_accel_unblock_tc_offload(struct mlx5_core_dev *md= ev) +{ + mutex_lock(&mdev->offload_block.lock); + if (!WARN_ON_ONCE(!mdev->offload_block.num_tc)) + mdev->offload_block.num_tc--; + mutex_unlock(&mdev->offload_block.lock); +} + static inline int mlx5e_accel_init_rx(struct mlx5e_priv *priv) { return mlx5e_ktls_init_rx(priv); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c b/= drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c index 329608c59313..74e0aa5b6133 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c @@ -4,6 +4,7 @@ #include #include "en.h" #include "en/fs.h" +#include "en_accel/en_accel.h" #include "eswitch.h" #include "ipsec.h" #include "fs_core.h" @@ -2574,53 +2575,12 @@ void mlx5e_accel_ipsec_fs_read_stats(struct mlx5e_p= riv *priv, void *ipsec_stats) } } =20 -#ifdef CONFIG_MLX5_ESWITCH -static int mlx5e_ipsec_block_tc_offload(struct mlx5_core_dev *mdev) -{ - struct mlx5_eswitch *esw =3D mdev->priv.eswitch; - int err =3D 0; - - if (esw) { - err =3D mlx5_esw_lock(esw); - if (err) - return err; - } - - if (mdev->num_block_ipsec) { - err =3D -EBUSY; - goto unlock; - } - - mdev->num_block_tc++; - -unlock: - if (esw) - mlx5_esw_unlock(esw); - - return err; -} -#else -static int mlx5e_ipsec_block_tc_offload(struct mlx5_core_dev *mdev) -{ - if (mdev->num_block_ipsec) - return -EBUSY; - - mdev->num_block_tc++; - return 0; -} -#endif - -static void mlx5e_ipsec_unblock_tc_offload(struct mlx5_core_dev *mdev) -{ - mdev->num_block_tc--; -} - int mlx5e_accel_ipsec_fs_add_rule(struct mlx5e_ipsec_sa_entry *sa_entry) { int err; =20 if (sa_entry->attrs.type =3D=3D XFRM_DEV_OFFLOAD_PACKET) { - err =3D mlx5e_ipsec_block_tc_offload(sa_entry->ipsec->mdev); + err =3D mlx5e_accel_block_tc_offload(sa_entry->ipsec->mdev); if (err) return err; } @@ -2637,7 +2597,7 @@ int mlx5e_accel_ipsec_fs_add_rule(struct mlx5e_ipsec_= sa_entry *sa_entry) =20 err_out: if (sa_entry->attrs.type =3D=3D XFRM_DEV_OFFLOAD_PACKET) - mlx5e_ipsec_unblock_tc_offload(sa_entry->ipsec->mdev); + mlx5e_accel_unblock_tc_offload(sa_entry->ipsec->mdev); return err; } =20 @@ -2652,7 +2612,7 @@ void mlx5e_accel_ipsec_fs_del_rule(struct mlx5e_ipsec= _sa_entry *sa_entry) mlx5_packet_reformat_dealloc(mdev, ipsec_rule->pkt_reformat); =20 if (sa_entry->attrs.type =3D=3D XFRM_DEV_OFFLOAD_PACKET) - mlx5e_ipsec_unblock_tc_offload(mdev); + mlx5e_accel_unblock_tc_offload(mdev); =20 if (sa_entry->attrs.dir =3D=3D XFRM_DEV_OFFLOAD_OUT) { tx_ft_put(sa_entry->ipsec, sa_entry->attrs.type); @@ -2686,7 +2646,7 @@ int mlx5e_accel_ipsec_fs_add_pol(struct mlx5e_ipsec_p= ol_entry *pol_entry) { int err; =20 - err =3D mlx5e_ipsec_block_tc_offload(pol_entry->ipsec->mdev); + err =3D mlx5e_accel_block_tc_offload(pol_entry->ipsec->mdev); if (err) return err; =20 @@ -2701,7 +2661,7 @@ int mlx5e_accel_ipsec_fs_add_pol(struct mlx5e_ipsec_p= ol_entry *pol_entry) return 0; =20 err_out: - mlx5e_ipsec_unblock_tc_offload(pol_entry->ipsec->mdev); + mlx5e_accel_unblock_tc_offload(pol_entry->ipsec->mdev); return err; } =20 @@ -2712,7 +2672,7 @@ void mlx5e_accel_ipsec_fs_del_pol(struct mlx5e_ipsec_= pol_entry *pol_entry) =20 mlx5_del_flow_rules(ipsec_rule->rule); =20 - mlx5e_ipsec_unblock_tc_offload(pol_entry->ipsec->mdev); + mlx5e_accel_unblock_tc_offload(pol_entry->ipsec->mdev); =20 if (pol_entry->attrs.dir =3D=3D XFRM_DEV_OFFLOAD_IN) { rx_ft_put_policy(pol_entry->ipsec, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c b/drivers/net/= ethernet/mellanox/mlx5/core/en_tc.c index 1bc7b9019124..70195fcddfc8 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c @@ -4811,14 +4811,14 @@ static bool is_flow_rule_duplicate_allowed(struct n= et_device *dev, return netif_is_lag_port(dev) && rpriv && rpriv->rep->vport !=3D MLX5_VPO= RT_UPLINK; } =20 -/* As IPsec and TC order is not aligned between software and hardware-offl= oad, - * either IPsec offload or TC offload, not both, is allowed for a specific= interface. +/* TC offload and accel protocols can overwrite each other's flow_tag with + * steering rules and they cannot simultaneously operate on the same inter= face. + * Additionally, as IPsec and TC order is not aligned between software and + * hardware-offload, only one is allowed for a specific interface. */ -static bool is_tc_ipsec_order_check_needed(struct net_device *filter, stru= ct mlx5e_priv *priv) +static bool is_tc_accel_check_needed(struct net_device *filter, + struct mlx5e_priv *priv) { - if (!IS_ENABLED(CONFIG_MLX5_EN_IPSEC)) - return false; - if (filter !=3D priv->netdev) return false; =20 @@ -4828,27 +4828,35 @@ static bool is_tc_ipsec_order_check_needed(struct n= et_device *filter, struct mlx return true; } =20 -static int mlx5e_tc_block_ipsec_offload(struct net_device *filter, struct = mlx5e_priv *priv) +static int mlx5e_tc_block_accel_offload(struct net_device *filter, + struct mlx5e_priv *priv) { struct mlx5_core_dev *mdev =3D priv->mdev; + int ret =3D 0; =20 - if (!is_tc_ipsec_order_check_needed(filter, priv)) + if (!is_tc_accel_check_needed(filter, priv)) return 0; =20 - if (mdev->num_block_tc) - return -EBUSY; - - mdev->num_block_ipsec++; + mutex_lock(&mdev->offload_block.lock); + if (mdev->offload_block.num_tc) + ret =3D -EBUSY; + else + mdev->offload_block.num_accel++; + mutex_unlock(&mdev->offload_block.lock); =20 - return 0; + return ret; } =20 -static void mlx5e_tc_unblock_ipsec_offload(struct net_device *filter, stru= ct mlx5e_priv *priv) +static void mlx5e_tc_unblock_accel_offload(struct net_device *filter, + struct mlx5e_priv *priv) { - if (!is_tc_ipsec_order_check_needed(filter, priv)) + if (!is_tc_accel_check_needed(filter, priv)) return; =20 - priv->mdev->num_block_ipsec--; + mutex_lock(&priv->mdev->offload_block.lock); + if (!WARN_ON_ONCE(!priv->mdev->offload_block.num_accel)) + priv->mdev->offload_block.num_accel--; + mutex_unlock(&priv->mdev->offload_block.lock); } =20 int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv, @@ -4863,7 +4871,7 @@ int mlx5e_configure_flower(struct net_device *dev, st= ruct mlx5e_priv *priv, if (!mlx5_esw_hold(priv->mdev)) return -EBUSY; =20 - err =3D mlx5e_tc_block_ipsec_offload(dev, priv); + err =3D mlx5e_tc_block_accel_offload(dev, priv); if (err) goto esw_release; =20 @@ -4912,7 +4920,7 @@ int mlx5e_configure_flower(struct net_device *dev, st= ruct mlx5e_priv *priv, err_free: mlx5e_flow_put(priv, flow); out: - mlx5e_tc_unblock_ipsec_offload(dev, priv); + mlx5e_tc_unblock_accel_offload(dev, priv); mlx5_esw_put(priv->mdev); esw_release: mlx5_esw_release(priv->mdev); @@ -4955,7 +4963,7 @@ int mlx5e_delete_flower(struct net_device *dev, struc= t mlx5e_priv *priv, trace_mlx5e_delete_flower(f); mlx5e_flow_put(priv, flow); =20 - mlx5e_tc_unblock_ipsec_offload(dev, priv); + mlx5e_tc_unblock_accel_offload(dev, priv); mlx5_esw_put(priv->mdev); return 0; =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/e= thernet/mellanox/mlx5/core/main.c index 643b4aac2033..406c0f7e63d8 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/main.c @@ -1810,6 +1810,7 @@ int mlx5_mdev_init(struct mlx5_core_dev *dev, int pro= file_idx) lockdep_register_key(&dev->lock_key); mutex_init(&dev->intf_state_mutex); lockdep_set_class(&dev->intf_state_mutex, &dev->lock_key); + mutex_init(&dev->offload_block.lock); mutex_init(&dev->mlx5e_res.uplink_netdev_lock); mutex_init(&dev->wc_state_lock); =20 @@ -1898,6 +1899,7 @@ int mlx5_mdev_init(struct mlx5_core_dev *dev, int pro= file_idx) mutex_destroy(&priv->alloc_mutex); mutex_destroy(&priv->bfregs.wc_head.lock); mutex_destroy(&priv->bfregs.reg_head.lock); + mutex_destroy(&dev->offload_block.lock); mutex_destroy(&dev->intf_state_mutex); lockdep_unregister_key(&dev->lock_key); return err; @@ -1925,6 +1927,7 @@ void mlx5_mdev_uninit(struct mlx5_core_dev *dev) mutex_destroy(&priv->bfregs.reg_head.lock); mutex_destroy(&dev->wc_state_lock); mutex_destroy(&dev->mlx5e_res.uplink_netdev_lock); + mutex_destroy(&dev->offload_block.lock); mutex_destroy(&dev->intf_state_mutex); lockdep_unregister_key(&dev->lock_key); } diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h index b1871c0821d0..2d9bc752e431 100644 --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h @@ -788,8 +788,11 @@ struct mlx5_core_dev { u32 vsc_addr; struct mlx5_hv_vhca *hv_vhca; struct mlx5_hwmon *hwmon; - u64 num_block_tc; - u64 num_block_ipsec; + struct { + struct mutex lock; + u64 num_tc; + u64 num_accel; + } offload_block; #ifdef CONFIG_MLX5_MACSEC struct mlx5_macsec_fs *macsec_fs; /* MACsec notifier chain to sync MACsec core and IB database */ --=20 2.44.0 From nobody Fri Oct 2 06:58:27 2026 Received: from SN4PR0501CU005.outbound.protection.outlook.com (mail-southcentralusazon11011005.outbound.protection.outlook.com [40.93.194.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D0A9643B6CB; Tue, 4 Aug 2026 08:37:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.194.5 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785832642; cv=fail; b=j9Q2ztAIwAwJkNGR4nkGn1Wm2TL8ybLwEvXkOaoq554XHd7G4PrRKvlmuNjXDoW8NmzbraJvRWFD0Z6JwEFrxNDkSSrZN6J35PsTfJ4biuVhO9pinrxsBN70tZ01vgAZSNuHSh3ja0ywyRVatP3Uf2C2mVT9F6U10IPLvMWVakg= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785832642; c=relaxed/simple; bh=/yVgWGQ5i6NhfGrZNZkTvdeFQCeJzczJgmXlUGs1q4k=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=VCBZjxkq4Jpn8rL2YFP16GAZ7A6QxJdIjNVdsQNDdS1c9cYko5SdKVafSTOYvkK/Klbf1l2Q/sqvMWQVC6+w+qPirsn1p88k86al6R6kiWSIGHvUt3fO83V3g0hgufq/0VIE55Xl7saq5ldALVtea9QeZL+0Cn+vEKdDcfVReT4= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=rCWJgKzT; arc=fail smtp.client-ip=40.93.194.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="rCWJgKzT" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=IcTixgLYP30vAcLscsr2wFc/qucmhfNfnxdxtDBaAgUSUqutyDH1y9wjHtnbqB2Ar1rOpyQkFX520UNGSsHA4pgTvZJyHSuSKsfFKCRlaNerqGd4RBG59SxJeb8D6QfLolIa8O/eXq+JmyM+Reaa7LCpV89JJqUgveV9mds9N9n5tmsTpKo1AC0CG7MHOyoNIGxHbJixEYHgnNl2TUAvoY4ATLpR8qaKka31Hnhv5FfT3HG/xZdybITBFQzW1qCp6n12bh7SQcAziJvIcAejfaxxayk6NPKttJiNBeN5VzVxEMDk1bATk/k7Sd6meCSrIl+2nAdROe8kC2H+RuCziQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=NwjGJcrgwcc2qsyZSD1f+yo29MHX3+7gcnDlCIyfrWc=; b=uCx1ibajfeB9roiliAZR87R7mZfDKDbBMB6pf7OkXTo97eSONgZtFJa/tEg8+rS0Gm+iVjzB1hYhiQw2aFnYy+KDTuv2DnL9tN981Z4wPsgx2hzgkDNsKC4z4Wtvo+uOlrTU8Z0S9C3p7BZbVsUvxl3RSLiO5BHUWGC19jNjtEvS+zowNjyyH9fUlmKPB17QeU2aq8dAIniwXQ2lO8JBaAmC5XYbXCrCUsFeVahML1EWXRgrXb9wGw6LMERXFOKLtoCYR0YPKR0TCtR66ztyixEl7ngRsuwkHs1UCt6KLr6RZo/ZRfpUqDMsG/6u1hsJGQBWOx8Cxa8dlQCtDAMLSg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=lunn.ch smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=NwjGJcrgwcc2qsyZSD1f+yo29MHX3+7gcnDlCIyfrWc=; b=rCWJgKzT5b2h7LV/D7/caPwEb3/bjahWUIqmMNT/FjhqMqJ5Ckv5TibKTV/OwNuMnxdwxyYHlS+/aGlRRkRi3ViFVR4/tyB4Q4YKCg8Z/IUjQ6PZTn00bc+q9IlRuwXRaOGobLpU7LqFb/TSIN9NHS6anBx1Dw64s0vlogl+B9grUytXlYBikwdVPhxUr5JrACAHLPDE+jxexeSH4ca3I0hXWz3hEzg+BkwyzZ30RTrQBd4bkB/zsjTW1SgJnTYvljuTZNUupqGlxG3r0eoAmlYdh95Nl/dqT4D8KPplThqH/OAePL3TE8g6G96DVYlDZUXbsYWJikZFaV+E0ach5Q== Received: from CH5PR02CA0020.namprd02.prod.outlook.com (2603:10b6:610:1ed::25) by PH7PR12MB6956.namprd12.prod.outlook.com (2603:10b6:510:1b9::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.270.18; Tue, 4 Aug 2026 08:37:13 +0000 Received: from CH1PEPF0000AD7B.namprd04.prod.outlook.com (2603:10b6:610:1ed:cafe::3a) by CH5PR02CA0020.outlook.office365.com (2603:10b6:610:1ed::25) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.292.15 via Frontend Transport; Tue, 4 Aug 2026 08:37:13 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by CH1PEPF0000AD7B.mail.protection.outlook.com (10.167.244.58) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.292.8 via Frontend Transport; Tue, 4 Aug 2026 08:37:13 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Tue, 4 Aug 2026 01:37:02 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 4 Aug 2026 01:37:01 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Tue, 4 Aug 2026 01:36:54 -0700 From: Tariq Toukan To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , , Paolo Abeni , Sabrina Dubroca CC: Aleksandr Loktionov , Alexei Lazar , Boris Pismenny , Carolina Jubran , Chris Mi , Cosmin Ratiu , Daniel Zahka , Doruk Tan Ozturk , Dragos Tatulea , Gal Pressman , Jacob Keller , Jianbo Liu , Kees Cook , Lama Kayal , Leon Romanovsky , , , , Mark Bloch , "Patrisious Haddad" , Raed Salem , Rahul Rameshbabu , Saeed Mahameed , Shuah Khan , Shuah Khan , Simon Horman , Stanislav Fomichev , Stanislav Fomichev , Tariq Toukan Subject: [PATCH net-next V2 02/13] net/mlx5e: ipsec: Block TC offload when IPsec is enabled Date: Tue, 4 Aug 2026 11:35:24 +0300 Message-ID: <20260804083535.2946459-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260804083535.2946459-1-tariqt@nvidia.com> References: <20260804083535.2946459-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7B:EE_|PH7PR12MB6956:EE_ X-MS-Office365-Filtering-Correlation-Id: eeac12c1-0d0a-4f4a-b73f-08def2039529 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|7416014|36860700016|376014|23010399003|22082099003|18002099003|11063799006|56012099006|10067099003; X-Microsoft-Antispam-Message-Info: OkUWIKIJ9GqaTB1oGfgPOuxAOe6jVBP83Z82zRLYe42XplcuO6rw6zdrtkGrMJZTcRZ5LRzxChEiv+K0UzuO0itQn+nqGBnvKjflDOZPZXf6pVoNvfup9ZjW+jj+/YpLU8JafuD+jLwbE9QDeFeBP0nnFPWujy48DnnA+t5zk6sTfmMkaOTfFpBQ+wfET/1n51Ym4G92oTRDMFM8inB7dVZikFI+sJ37D+Hb6157qdIfbg9qhAaCp7TLfPMiGyqegri8xOVbXQIHtkjyKem08iDLCCyjfLuZ7kQD7SHhS/uLWaHEJjmlozr3VbAHxSv1hllCDaschMul8ULPff95fSKhMD4he37wXFKwCcnNeWABQXOcEJ6V9sGv/SixAhm/cu7hzGqFimQiwpfM1qsifvyjr+SQIhPe93EL+lN8EhHL/QpRecZdUq6wcYEcLT/BJSWD5lYvRULze11mWaCvs0+wE5VNW50uIZN14mjfQrSfzGLWOUennr0XKGkdueV1n1vJyihNKpbMx2PVPnkhnN8iIbIZARFUDOaOM7FMnwqa6eQkk1sDscxdEnBXCFmL/HAibx6cr2hWFFpjumXRcG/dzSqlzz9rbL5uxCXQGzCtioCIcOU6B6Baojn4LoRCYRHULhVsLa84Zy/KlBP48TVO013z2FWfXx96sAYcNRHF2tAyijPz4X42iFMMkhpUQlGYzXjNWyvuPXtW/U2nEA== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(7416014)(36860700016)(376014)(23010399003)(22082099003)(18002099003)(11063799006)(56012099006)(10067099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: EqqdTTqqmrxABOtC0GlRXHoD9EaFix9SRIaAHQfEoI+Spdx85A5GPu4obyPBrAPTRL44g7FRgp2JIfAu2dZ1t2lCnJRlU/pm9S4OwN5YiA5LMlrh/vBWkU5dMfr1nQzPsivq7lkK0JvQSihr7ciganbJYNeI6qqpisbhLn3rAI+jde8Y2p3xwV3uoIhLZhZmoZ2qsmC+OwPoiilTG6YmjQHCRdJBt1dop8RR+kQ2igH0l97UoFLPP8/rlZcHhHk/ySHoKhk/oT7qjiPBax0Wh5nGXiOABbZZqbyb0uF/yyeqh7t12BRgXPVO1Gjn6si/sheB50ty9jrWlfPZPexssZZnU1Y4oFI1XPKdvAX9trUpOjRGCr7O/tdOkiPoIRWWevLJ9+aECaQa9SkTJObXhx55OKyMsQrmjMnfLtBSGgx6tGV9aAR/uyMar0bPScyo X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Aug 2026 08:37:13.3299 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eeac12c1-0d0a-4f4a-b73f-08def2039529 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7B.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6956 Content-Type: text/plain; charset="utf-8" From: Cosmin Ratiu Currently the mutual exclusion mechanism is only used in packet offload mode. But with the upcoming changes to flow_tag, all RX IPsec flows need to block TC offload, so do that with the help of a small helper. Signed-off-by: Cosmin Ratiu Reviewed-by: Dragos Tatulea Reviewed-by: Carolina Jubran Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c b/= drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c index 74e0aa5b6133..f236672d3a2a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c @@ -2575,11 +2575,18 @@ void mlx5e_accel_ipsec_fs_read_stats(struct mlx5e_p= riv *priv, void *ipsec_stats) } } =20 +static bool accel_ipsec_should_block_tc(struct mlx5e_ipsec_sa_entry *sa_en= try) +{ + return sa_entry->attrs.type =3D=3D XFRM_DEV_OFFLOAD_PACKET || + sa_entry->attrs.dir =3D=3D XFRM_DEV_OFFLOAD_IN; +} + int mlx5e_accel_ipsec_fs_add_rule(struct mlx5e_ipsec_sa_entry *sa_entry) { + bool block_tc =3D accel_ipsec_should_block_tc(sa_entry); int err; =20 - if (sa_entry->attrs.type =3D=3D XFRM_DEV_OFFLOAD_PACKET) { + if (block_tc) { err =3D mlx5e_accel_block_tc_offload(sa_entry->ipsec->mdev); if (err) return err; @@ -2596,7 +2603,7 @@ int mlx5e_accel_ipsec_fs_add_rule(struct mlx5e_ipsec_= sa_entry *sa_entry) return 0; =20 err_out: - if (sa_entry->attrs.type =3D=3D XFRM_DEV_OFFLOAD_PACKET) + if (block_tc) mlx5e_accel_unblock_tc_offload(sa_entry->ipsec->mdev); return err; } @@ -2611,7 +2618,7 @@ void mlx5e_accel_ipsec_fs_del_rule(struct mlx5e_ipsec= _sa_entry *sa_entry) if (ipsec_rule->pkt_reformat) mlx5_packet_reformat_dealloc(mdev, ipsec_rule->pkt_reformat); =20 - if (sa_entry->attrs.type =3D=3D XFRM_DEV_OFFLOAD_PACKET) + if (accel_ipsec_should_block_tc(sa_entry)) mlx5e_accel_unblock_tc_offload(mdev); =20 if (sa_entry->attrs.dir =3D=3D XFRM_DEV_OFFLOAD_OUT) { --=20 2.44.0 From nobody Fri Oct 2 06:58:27 2026 Received: from BN1PR04CU002.outbound.protection.outlook.com (mail-eastus2azon11010039.outbound.protection.outlook.com [52.101.56.39]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 28AA843B495; Tue, 4 Aug 2026 08:37:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.56.39 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785832652; cv=fail; b=Pug+mRUNn6RrLx3ytq+JsDOPb/Y0mqe75Q/tCODAc4Go3d5y5ihu+WjAeG6ldSw/RnISMcvxZ0xMNWn3PhdzMKTTStBDGHTo2uzhyOJqK6zoayMGBH3Ns5kqmIRkg8KADLU3oIOZXmLubA3m5+TkgdPF/leJPJGcYQkpiCejZ+w= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785832652; c=relaxed/simple; bh=wHTUVtPo4Jc9ZFTJCwRVRrAkEYPn7TM6phZvvpMts3E=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=U2Bs0udSoyfkh6Xv0SzWytKadiSRtDhQyH63Al2lTEMHRUXhZfmPQLQoTSnANS3HNTpxKAL1rx+PmtyZdR/Z7i00dug8sUJMInIOs+/WUMLzGSIKRENdYJB9RayJG1f/ArF6D9Yu4e0bNKls/PUqt+LLgxfiEIkh2G5fvvcT2AE= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=fprSJ8k2; arc=fail smtp.client-ip=52.101.56.39 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="fprSJ8k2" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Y7MKfsTOFR3pfYbcWn9CpPZ1q+Er108d4qR15i2OwewDJco64F3BoNjDJ83j2H4b/3KRa1yRaWic7FoF3eiMezJ9lmJ/iSP9rWxlpALC2puqeh1RJaJmA+oV2VPdL20IH0PyCh1U4U/K1WKbO4j24mdDSVdiPt8KR9fwV21jXQBSVPqJxRWOO0ajvX2I5+IJiJ5+xug7pS+Z0lohRYDo+UrZX/+AIKizBUeWoq245ruyH7kGoIZSp1r6rF7F5T/3SxyxYZHUmkZGFrnC4siwiRpVSZ0EY+nJ9m7TCUNeZnrsmGlNbuAiFVyYUQoK59A/rQ4uRPdVpKJzenSxGfSyxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=BCuJWh8FE2mADeozQy7CgEIWrLF7bl42mZ2Ft+F3Lt0=; b=kJGawJEhzFJpEmnfPdHLZOZ+rwFceesZrSqtjQPrGLj20+QH38EJthF4ynhmVsJvbDf4nKUjn9bPU5UqOsAlZCDISNIPyqDP7sywjjup5+OhxCGfT2IBZsuRgKGHxaDyg1l2OjwuFTpc16w/aLT2AyrfPyA88/5Wn5V7LZ7Whq9eCsaWF2QiPb/03z2co2K33CIBB1A4zmz/rm66GYMbc5t3h55AUWhkZqL62QtuZPxVG2rMM0cNhDTH8jebOaOJnDt6rcOIsfPelndRkJNBw/IyQU3hkdBk9Ra5MY1Vau/f2TpAZUydHuzeBu6pQH9XeNT2R8AygnMCO29SlnQm+g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=lunn.ch smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=BCuJWh8FE2mADeozQy7CgEIWrLF7bl42mZ2Ft+F3Lt0=; b=fprSJ8k2ZZnWZQP/OoWhoK3ixNr8FEKOPlnwfsgXbt3TyyLSYrQEWvhLlYe8dYxHT/rmunqmx005kfPgSPHLaCVBLEYVwIlaurAA67lj/xOqROOjNJ6HHyAlQSUctneANtHGBezGDXxUEJSwYDBfsr1yT3LqHpUwva/71hCt757XTbzF+VpnW6ivxcT6p61ZyQXMGkk4YfoH/nxcHj96oCN24FAvqFOWvPpi+JTHWg93YTmMb/QxMuxJ5DKUqHQacs2eRHsk2b7/5gcDv01EdT8OJdKQkHSMrODDEjBunIRkGHpI/FuWr0QSNsCLUBnhu998ZaE2dWAtEo26+Ijm2A== Received: from CH0PR04CA0028.namprd04.prod.outlook.com (2603:10b6:610:76::33) by PH7PR12MB5687.namprd12.prod.outlook.com (2603:10b6:510:13e::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.270.15; Tue, 4 Aug 2026 08:37:24 +0000 Received: from CH1PEPF0000AD78.namprd04.prod.outlook.com (2603:10b6:610:76:cafe::72) by CH0PR04CA0028.outlook.office365.com (2603:10b6:610:76::33) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.292.15 via Frontend Transport; Tue, 4 Aug 2026 08:37:24 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by CH1PEPF0000AD78.mail.protection.outlook.com (10.167.244.56) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.292.8 via Frontend Transport; Tue, 4 Aug 2026 08:37:23 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Tue, 4 Aug 2026 01:37:10 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 4 Aug 2026 01:37:09 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Tue, 4 Aug 2026 01:37:02 -0700 From: Tariq Toukan To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , , Paolo Abeni , Sabrina Dubroca CC: Aleksandr Loktionov , Alexei Lazar , Boris Pismenny , Carolina Jubran , Chris Mi , Cosmin Ratiu , Daniel Zahka , Doruk Tan Ozturk , Dragos Tatulea , Gal Pressman , Jacob Keller , Jianbo Liu , Kees Cook , Lama Kayal , Leon Romanovsky , , , , Mark Bloch , "Patrisious Haddad" , Raed Salem , Rahul Rameshbabu , Saeed Mahameed , Shuah Khan , Shuah Khan , Simon Horman , Stanislav Fomichev , Stanislav Fomichev , Tariq Toukan Subject: [PATCH net-next V2 03/13] net/mlx5e: psp: Block TC offload when PSP is enabled Date: Tue, 4 Aug 2026 11:35:25 +0300 Message-ID: <20260804083535.2946459-4-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260804083535.2946459-1-tariqt@nvidia.com> References: <20260804083535.2946459-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD78:EE_|PH7PR12MB5687:EE_ X-MS-Office365-Filtering-Correlation-Id: 55837398-4c21-4f93-ec00-08def2039b39 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|376014|7416014|23010399003|1800799024|82310400026|56012099006|10067099003|11063799006|22082099003|18002099003|3023799007; X-Microsoft-Antispam-Message-Info: oV5S0OX0r/GtC41jwgl0/rI8oW3+GSrulhz65QtQ+m+b5H7E+yXDLvwLhjMi8ijCc2dfV+HC6SADF2Gg1LiKyE/yAy/iAxoXXhFnp6Vp9d6gVF+FUFQLDeALYSP9puRZa5EXvHZYydb0YVggQlNapYtDTVG8904BQmOCdbrbXxrf86AzyZLNyDB2luCVz79Sd7zMZjEhIm25Vk8V/B0g6JhOLBdZT9vTOjQpI6ygXyf5gyK2ZDYHXUNHRBLmRy5vaW9OOTs0Y5WZesQdfJQQR7Dz3T/hPd1RmnyDnNknJ5TBcs5UFiU7iHBm4XyTaJiSIBSnIjDFlVoqIjiAXaXJcGKGgOIb9QD5fmPRctqHVFeGyS3FMFm0t9Nkpgg7JPB5xGtt3lbIZcGLrBysv9/rRrGsVr1zntnk/Pi4IxzfOmDg6/P3kxDGUZr/BS8clZ3l8C/ZxFvXdmM4yVyTs7EoE+tEYltLQmj6A+8Pe8xfsZY/IXIYF/bxKL3dslIlcdcHHfpgmjYJrPRZRujeNUoWmZUThcD5og53iDTTrFRcKYOsWO0d96hzkcPHwo8v8zQZguMo9KZE7sNm6M/Rs5RHqDff9Ps4FLdywSnGRNoi0DxuDhXDqn31EVGp+w3lLNo9AwaywYHoCfnhccZiI6/XYXZ/yCNj2PR1GxgvQHmc1+oZld7+HJd8dZTf9euAUETYQpJQO+4UWPG64cbFUnqDOw== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(376014)(7416014)(23010399003)(1800799024)(82310400026)(56012099006)(10067099003)(11063799006)(22082099003)(18002099003)(3023799007);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: BfIyEFQAO3FJYNogV8M07i/nIg9fmonNHHHqPofbJDYfHzCAsdVdLxcIvDVH7LS5WZh/GrxF7p+5JtCNJKwZTyymo06YQgMFXuiV3mYMRPitZFXON0U+3LWAZ527sutCwoBvyjd5ozImsuAGs/DFmbYicYGAR6kWZv0gbZvC8PuJpzOU4zHmNHDqGfQKtjXrnmdrTLoZ2/A6hdEhb4b4CwGe+QhOwOpJL13pOdbtejgK4E7mlmUZad6QpfhHZkmFMLbW59L78OJp7OVt2Xb0TyqhJVXFO+QBveOIUL7KwwbewRKWocEbiBZNv14g7i1V4ugyUe5Wvmn2QZQ7WnMXutZNP3YkJs3E59om8v6aGmb0E2O14e4FrcTNDFkAxZGHgJw4Uwe0G8DFok6jx9rivVRhCTMrTl4S/Fn1BH8gCRWMWpw5gKa0lZLVBouYsJV8 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Aug 2026 08:37:23.4768 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 55837398-4c21-4f93-ec00-08def2039b39 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD78.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5687 Content-Type: text/plain; charset="utf-8" From: Cosmin Ratiu Make use of the mutual exclusion mechanism from the previous patch to make sure only PSP or TC offload is active on a device. Later in the series, the PSP protocol marker will move to the flow_tag, which is also used by TC offload. Signed-off-by: Cosmin Ratiu Reviewed-by: Dragos Tatulea Reviewed-by: Carolina Jubran Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/en_accel/psp.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/psp.c b/drive= rs/net/ethernet/mellanox/mlx5/core/en_accel/psp.c index 73b232379263..6cc4b9d54f6e 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/psp.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/psp.c @@ -6,6 +6,7 @@ #include "mlx5_core.h" #include "psp.h" #include "lib/crypto.h" +#include "en_accel/en_accel.h" #include "en_accel/psp.h" #include "fs_core.h" =20 @@ -526,6 +527,7 @@ accel_psp_fs_rx_decrypt_ft_create(struct mlx5e_psp_fs *= fs, static void accel_psp_fs_rx_destroy(struct mlx5e_psp_fs *fs) { struct mlx5_ttc_table *ttc =3D mlx5e_fs_get_ttc(fs->fs, false); + bool tc_blocked =3D fs->rx.ft; int i; =20 /* disconnect */ @@ -535,6 +537,8 @@ static void accel_psp_fs_rx_destroy(struct mlx5e_psp_fs= *fs) } accel_psp_fs_rx_check_ft_destroy(&fs->check); accel_psp_fs_rx_ft_destroy(&fs->rx); + if (tc_blocked) + mlx5e_accel_unblock_tc_offload(fs->mdev); } =20 static int accel_psp_fs_rx_create(struct mlx5e_psp_fs *fs, @@ -543,10 +547,16 @@ static int accel_psp_fs_rx_create(struct mlx5e_psp_fs= *fs, struct mlx5_ttc_table *ttc =3D mlx5e_fs_get_ttc(fs->fs, false); int i, err; =20 + err =3D mlx5e_accel_block_tc_offload(fs->mdev); + if (err) { + NL_SET_ERR_MSG(extack, "TC offload active, cannot enable PSP"); + return err; + } + err =3D accel_psp_fs_rx_ft_create(fs, &fs->rx); if (err) { NL_SET_ERR_MSG(extack, "Failed creating RX steering table"); - return err; + goto err_unblock_tc; } =20 err =3D accel_psp_fs_rx_check_ft_create(fs, &fs->check); @@ -583,6 +593,8 @@ static int accel_psp_fs_rx_create(struct mlx5e_psp_fs *= fs, accel_psp_fs_rx_check_ft_destroy(&fs->check); err_ft: accel_psp_fs_rx_ft_destroy(&fs->rx); +err_unblock_tc: + mlx5e_accel_unblock_tc_offload(fs->mdev); return err; } =20 --=20 2.44.0 From nobody Fri Oct 2 06:58:27 2026 Received: from BYAPR05CU005.outbound.protection.outlook.com (mail-westusazon11010031.outbound.protection.outlook.com [52.101.85.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E1BD43B495; Tue, 4 Aug 2026 08:37:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.85.31 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785832659; cv=fail; b=L/R9beqS14ANKSHfNtM8jha3IemZp6ewqf7c6et0M3da0wI1CxPFpPylPUioJdSTwd+ArevuifcZVuoMHUxClwmVIV5/4a8gi0WvVCutnXJwlXtaRyHiS03q125FmJPEX7UQbgIQjkWkoMauCBeradSRbhgxdwWXbZYgqxzEgXQ= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785832659; c=relaxed/simple; bh=qeFRiCic+mGtSPAV57nx6XrXVLjcTWxDab3n49sOJaw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=go0vCxJecR9mmwp9EcHzcqRkOFQ0UcimnVqcY1cUbX8s1wplNosfOzFqGAWG9SdTVt721NXPsJegsRzCUR0frtM+rSIQeym/uDmHJ6ftIxqmTG3t9AcXeD+jejUZdWuXHQLshh5YKEuUqNfbOlTyCAHyRQ+DhJ/X57zj/np/njw= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=A0FxRHa4; arc=fail smtp.client-ip=52.101.85.31 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="A0FxRHa4" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=m/k+Pk5mXJYl7joxgHoUa/N+RwNDPEFJYGsj6TdN0qAa0SOvt70KlRI6fRL8t8r4k+odWOneq3Y1dGDbDlI9cNwZ2UyEPfnz2dGWVba2KfFwZvKjSriJLxWs4YyArsUcQ0aBu/AG792ICu+MKzVy4YmPitvmGJXvWOdhDMjfmN34fobf56i0FnlSzR32pEgDhR9CFoAalysC9ihh3VNtSIVQYDnNacaLhpWjZuBHkyt60c3GTduXtrzLKqcONHOxQywNjpSLi1oIAt018SZCWIKLOAc/eN13wobezceltpj+PIB9OHUxQIaQmGOqhQ57F4ABpvPSYow3I5hQNaXSUQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=XgenrtbmBM7uKo18CtVEVQeizlrtxMYTw6HIT8pCGDk=; b=c0NMQ46MQOnlLDCe7tpRZtyPBVlKnlqZ55SXaOEMTYeRGkOu8p+qHIjfhSVpi0zMyah2gKq3IOMHGmuC91lWElM3dAsD3Yqb37HKZrG3OfSGFUiwTHIv7yyXQfPNeny0iSSc3RDi28n9FRSc/hWvB34bmJpL9vSRantGSlqhmk5EJeuNyUWTTDPZX90VQ4kikjdh50/DQ1soclMwnxmgMkEPohMJy4uQ34p/gGh2CoB3QEXN1cf5jLBT6+uHAxBVeIwzCxE8G+0/SCDOns8ChUJte6pdEl4Wohnc+DRgJYYa9J6rbP/3XAkJ34HID07pqOnBJq9EgwqMVrGQ/mqPaw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=lunn.ch smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=XgenrtbmBM7uKo18CtVEVQeizlrtxMYTw6HIT8pCGDk=; b=A0FxRHa4xBsetCvqvFjEVSOs0CfzuMEZOFHCOGHAOwendmF4FSd7yYoMgJ/7rhwpfhWOyQJYu58maKXhAjSafoSOvuheNVyOA7eHUhpMAC9xPc1L8qPHQgjw0SnFsMvrFp6kKU7AEgTCr9nXVbTgs20S5ebC3NpcNT+NAmdudpwi3KZFNS4rxoMO51pMkzO/lHyDZ5Qr4UhG4Nj+xMkrUYdtTN9qfBgYMRTveCvF+7PDV/uWR7hDS1S6b+5KcPu9drElvWoO0Mtp8hvboKuR8lqdzUe0EbiL5bSJiKHU4NlGj2J0ikj2lNeDywx0zX/8iEkZf55W1GDdNttjrYCaTQ== Received: from BLAPR03CA0137.namprd03.prod.outlook.com (2603:10b6:208:32e::22) by DS2PR12MB9568.namprd12.prod.outlook.com (2603:10b6:8:27c::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.292.15; Tue, 4 Aug 2026 08:37:32 +0000 Received: from BL6PEPF00020E5F.namprd04.prod.outlook.com (2603:10b6:208:32e:cafe::43) by BLAPR03CA0137.outlook.office365.com (2603:10b6:208:32e::22) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.270.18 via Frontend Transport; Tue, 4 Aug 2026 08:37:32 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by BL6PEPF00020E5F.mail.protection.outlook.com (10.167.249.20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.292.8 via Frontend Transport; Tue, 4 Aug 2026 08:37:32 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 4 Aug 2026 01:37:18 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 4 Aug 2026 01:37:18 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Tue, 4 Aug 2026 01:37:10 -0700 From: Tariq Toukan To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , , Paolo Abeni , Sabrina Dubroca CC: Aleksandr Loktionov , Alexei Lazar , Boris Pismenny , Carolina Jubran , Chris Mi , Cosmin Ratiu , Daniel Zahka , Doruk Tan Ozturk , Dragos Tatulea , Gal Pressman , Jacob Keller , Jianbo Liu , Kees Cook , Lama Kayal , Leon Romanovsky , , , , Mark Bloch , "Patrisious Haddad" , Raed Salem , Rahul Rameshbabu , Saeed Mahameed , Shuah Khan , Shuah Khan , Simon Horman , Stanislav Fomichev , Stanislav Fomichev , Tariq Toukan Subject: [PATCH net-next V2 04/13] net/mlx5e: macsec: Block TC offload when MACsec is enabled Date: Tue, 4 Aug 2026 11:35:26 +0300 Message-ID: <20260804083535.2946459-5-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260804083535.2946459-1-tariqt@nvidia.com> References: <20260804083535.2946459-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00020E5F:EE_|DS2PR12MB9568:EE_ X-MS-Office365-Filtering-Correlation-Id: 8fe8a22f-c520-492c-2e0e-08def203a0a6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|23010399003|376014|7416014|1800799024|82310400026|10067099003|56012099006|22082099003|18002099003|3023799007|11063799006; X-Microsoft-Antispam-Message-Info: +ee8YEvCmelo9f8GanzEghvh7/O9BTLxpgUZzpR9mhAmETa2D80aOSx0wORWHc/Qm8ZRca9JqVl2TvXHrg3/kfrMH7Qgv/sTQzQuJOy2Ji2JJ1rXeNmdeINKGaS+k7RSzPMCCFLQ4bgy50v+EzwogGKqVwdOhLNoHvHdmsjD6axpPznJfRrvH2+JOpTFr28IcsUyXhb6zsQ7FOP/mMblYgH8qK1dm1abS4XGrapQ+I9ZSKAvuImmQf16+8/L5ExJLfPDkLov4X30+dJqvcwsCaUtagKuvUFDaOpefpFX0b6aa6QbxEPk+y4IfY3q3QLqET2hRQ+CExMEr5AyeHrXxLKpNSJ1cfa/E7/5pZVsF9xuAocsyQREp3RJqU9o0dH+vkSRqRUVJ4KC3Rj1u5XJXcDKod2W+XkW+S77wRP18xKnl6RLzHiDtIRu1Df0errpjfTViLki/cqkFmJkcPsu7cPyNPm4EQfu7XdZR6JexN3XoLZ7qDkLx7XdVAaxu8Ul+W5bH9FdcmPH8chzw3p4+tMaXSrh+hRfH+FZnjOlYYOGABk8fZK2xto7XXcpHnuf9zgBvCqepioZVjoSFRE85gcWVJ+JZRLWoEjo/7IAoSa0np2v+8NzH4pzIM/PezET/ZR2TVERRfbM5hkp74RMOThJnfJ/X5KhnxOVJmyMkeIUfVM08dcNXOoVttbot7c8R6ulrMQ8okWs5Ik+9JD5Fw== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(23010399003)(376014)(7416014)(1800799024)(82310400026)(10067099003)(56012099006)(22082099003)(18002099003)(3023799007)(11063799006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: BFHCP+mPa//2k75xtH1y3RDE8jz2B6lBJKTnPMzNuG4E0Tzz6oP2gjjeBjmI4FadPAx+qqsGeEdoVZ3BEit87Dg0SX3lqzC6r30Rl23weFzPHo4mrK2aAgO3L5vrg37awXS368nRoLmAVCw+xxzBjeuOyOWq+yFu4cjA4ADZWlIk97WdYI7fz3P8Vh69IpPK0kniuEUvFvGFQtTNOIR44g1Cj6nTVIHC4jdptWFq/K5F9AofTgVQsWmMLd+ZDguX4yY4TMyK0n+X68I2t8H/nk26Qpt39nXqtqDa9bL/slrkzIKIlvzsip++iaYlqZ8nZ7AKBvNrWTHZ/9vqxxt4VwjNcmQDPpoghO4nW2p5jukgYC6qN3Vet7ueJFP9zZwiLViHZOWplXh5mZkYE/33r7ZNWAu8uZ3cbBM378hx/KEKBtrtbl0EtYLRAau3BIwI X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Aug 2026 08:37:32.5279 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8fe8a22f-c520-492c-2e0e-08def203a0a6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E5F.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS2PR12MB9568 Content-Type: text/plain; charset="utf-8" From: Cosmin Ratiu The MACsec protocol marker will soon move to flow_tag and that will make TC offload unusable at the same time as MACsec on the same device. This patch makes use of the mutual exclusion mechanism to make sure that TC and MACsec cannot be both active at the same time. One extra bit of logic is in macsec_upd_secy_hw_address(), where existing macsec rules are drained then readded. During the two loops it's possible a mistimed TC filter add to throw a wrench into things and prevent the 2nd loop from adding anything, since accel rules are now blocked. Fix that by keeping a best-effort TC block across the entire operation. Signed-off-by: Cosmin Ratiu Reviewed-by: Dragos Tatulea Reviewed-by: Carolina Jubran Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/en_accel/macsec.c | 28 +++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c b/dr= ivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c index daff53ba7d09..a15a0aff292f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c @@ -10,6 +10,7 @@ #include "en.h" #include "lib/aso.h" #include "lib/crypto.h" +#include "en_accel/en_accel.h" #include "en_accel/macsec.h" =20 #define MLX5_MACSEC_EPN_SCOPE_MID 0x80000000L @@ -324,6 +325,8 @@ static void mlx5e_macsec_cleanup_sa_fs(struct mlx5e_mac= sec *macsec, mlx5_macsec_fs_del_rule(macsec->mdev->macsec_fs, sa->macsec_rule, action,= netdev, fs_id); sa->macsec_rule =3D NULL; + if (!is_tx) + mlx5e_accel_unblock_tc_offload(macsec->mdev); } =20 static void mlx5e_macsec_cleanup_sa(struct mlx5e_macsec *macsec, @@ -343,6 +346,7 @@ static int mlx5e_macsec_init_sa_fs(struct macsec_contex= t *ctx, const struct macsec_tx_sc *tx_sc =3D &ctx->secy->tx_sc; struct mlx5_macsec_rule_attrs rule_attrs; union mlx5_macsec_rule *macsec_rule; + int err =3D 0; =20 if (is_tx && tx_sc->encoding_sa !=3D sa->assoc_num) return 0; @@ -353,13 +357,26 @@ static int mlx5e_macsec_init_sa_fs(struct macsec_cont= ext *ctx, rule_attrs.action =3D (is_tx) ? MLX5_ACCEL_MACSEC_ACTION_ENCRYPT : MLX5_ACCEL_MACSEC_ACTION_DECRYPT; =20 + if (!is_tx) { + err =3D mlx5e_accel_block_tc_offload(priv->mdev); + if (err) + return err; + } + macsec_rule =3D mlx5_macsec_fs_add_rule(macsec_fs, ctx, &rule_attrs, fs_i= d); - if (!macsec_rule) - return -ENOMEM; + if (!macsec_rule) { + err =3D -ENOMEM; + goto out_unblock_tc; + } =20 sa->macsec_rule =3D macsec_rule; =20 return 0; + +out_unblock_tc: + if (!is_tx) + mlx5e_accel_unblock_tc_offload(priv->mdev); + return err; } =20 static int mlx5e_macsec_init_sa(struct macsec_context *ctx, @@ -1137,7 +1154,12 @@ static int macsec_upd_secy_hw_address(struct macsec_= context *ctx, struct mlx5e_macsec_sa *rx_sa; struct list_head *list; int i, err =3D 0; + bool block_tc; =20 + /* Best-effort TC block across the operation, to prevent a mistimed TC + * filter add from preventing the 2nd loop from happening. + */ + block_tc =3D mlx5e_accel_block_tc_offload(priv->mdev) =3D=3D 0; =20 list =3D &macsec_device->macsec_rx_sc_list_head; list_for_each_entry_safe(rx_sc, tmp, list, rx_sc_list_element) { @@ -1168,6 +1190,8 @@ static int macsec_upd_secy_hw_address(struct macsec_c= ontext *ctx, =20 memcpy(macsec_device->dev_addr, dev->dev_addr, dev->addr_len); out: + if (block_tc) + mlx5e_accel_unblock_tc_offload(priv->mdev); return err; } =20 --=20 2.44.0 From nobody Fri Oct 2 06:58:27 2026 Received: from CY3PR05CU001.outbound.protection.outlook.com (mail-westcentralusazon11013021.outbound.protection.outlook.com [40.93.201.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 63EE943CE5A; Tue, 4 Aug 2026 08:37:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.201.21 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785832669; cv=fail; b=NZCa0yosSFw+Y9swluoVPugHEKF21qPr/oeXh6I88tryENB4BGktlkQwoLl29x144Uz6Nwk7ly5yh8kU0eVUhXpMJvmR4PczcaWTTc83J1AHGdn/VVFENqcu4SNiY0WyZEopu8Aq55RA77fwDXex2lZcKOSmszaZI2KWyhngw/8= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785832669; c=relaxed/simple; bh=QMQ6SgZtjcAEDVTjNWx0BF7ZyeuPaaJ3iRHfn+zY/zg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=D2wH4+UIAdFW8vZieXWV2dX5C0LYyZSVKYJZLvNRenwuE2GSy64q1Vl4Dl45jWm31vPr/1KeXbW8RN5qKRc1FG8wxrvoP/e+lW+qu5Iu1jg6xK9KM1iogdl4kEGMNRyHBIdMkm34oyjY/b7VoqbjdCFQL508d7idYhc5TSYO3dw= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=ieGHE6wu; arc=fail smtp.client-ip=40.93.201.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="ieGHE6wu" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=YsydT5zFjvMNCKdHfRwzODwDtzNdGTHzR6FsYV0SbvvsvpsvPxnCCPTAjcGzqNr4XWE2jG6gQLtSLss9TJ0+yZyPU5WAdD7OsJ7r/o4SlyRwcfyL1pgWR2X1tqA8ar/geDUy8YL9SyEvmMrRDmTRpaEkrDa9IBNwuNBQ9HD1MDN2IwWgvkwtx6meWEnBQce+SOQ7vbdl80/Vhv+bHqcXSPMNzg44prM+mlDNEom6CckrqKmhAJ0xNwga9v4gtO6s6ieW9WYNZtk2NiI9i92NOyW/1t/nU33ZrYOXUAFN3bogYlJACOBlBkmvV4BaP0D8T0bonjmGa0BjCK7BceV5NQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=0T3kHu5Dxp8P1gSH1YIztIlTioNvLdwxtGqJt+SeVos=; b=m14T7Tg1LsZPtuDctX+v5h7vh2D2sqO5DZHfZsYW9RLNFMU0QgdhyGMBr52MyYZNvuOaSCuLaXgqu5yzffr2MsmzHtpGKS5/avlGmtcFdzkty4ZxrNsQypRdIHztBVNZfu/0h9TtpIxVPAzFlhRJ1U82s46pZ4RZ3mRtn26DIc0Ev+bH5GIAdqhgvRB/bvc6ueox63URyoMj+mfFVWC2LigB29CuMxd2izLlGDqbdSp7M9GjvjQiG6oD9TdWYtFYbZ8OB/i1k5YIyMziTx8l6xi4h5o5wORz2l9W0qhqIDwvCP8Ks2Erlxsv6SOA9mby03h0JjbDy8WqRhIm5wOHRA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=lunn.ch smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=0T3kHu5Dxp8P1gSH1YIztIlTioNvLdwxtGqJt+SeVos=; b=ieGHE6wu5Knb0RHwKW/Cm9L8A0rdMd0UxsQpazbj9DZSCfzf/e4gHFlCTdOEHWWWz4x2zob6s6UInQkLG0USW6tbTLAVKViJuSjzmR4LJKC996VvnoWRxiYoYW7tNefGtQdrxJl4VDDyJFW4X4XjGzReFnpJQM6XEk/P9e+fDyyvtw7GdqtHiyCOeG5CdynpQcUMZsG7RxMVvcBvI4vvTwCWd7RgY035YV1PU4rKwZyF5aaRrtg6MV6neLZUimu0M2H1XzAbxZYd+0PDPPdf77CMxvbuVdzou93u1q0SzB2IfqBjkGAbYhUstA1k1vgmMFJ2mJsdZTLwfri34CWNeQ== Received: from BL1PR13CA0378.namprd13.prod.outlook.com (2603:10b6:208:2c0::23) by SA1PR12MB8163.namprd12.prod.outlook.com (2603:10b6:806:332::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.270.18; Tue, 4 Aug 2026 08:37:40 +0000 Received: from BL6PEPF00020E65.namprd04.prod.outlook.com (2603:10b6:208:2c0:cafe::73) by BL1PR13CA0378.outlook.office365.com (2603:10b6:208:2c0::23) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.292.13 via Frontend Transport; Tue, 4 Aug 2026 08:37:40 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by BL6PEPF00020E65.mail.protection.outlook.com (10.167.249.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.292.8 via Frontend Transport; Tue, 4 Aug 2026 08:37:40 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 4 Aug 2026 01:37:26 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 4 Aug 2026 01:37:26 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Tue, 4 Aug 2026 01:37:18 -0700 From: Tariq Toukan To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , , Paolo Abeni , Sabrina Dubroca CC: Aleksandr Loktionov , Alexei Lazar , Boris Pismenny , Carolina Jubran , Chris Mi , Cosmin Ratiu , Daniel Zahka , Doruk Tan Ozturk , Dragos Tatulea , Gal Pressman , Jacob Keller , Jianbo Liu , Kees Cook , Lama Kayal , Leon Romanovsky , , , , Mark Bloch , "Patrisious Haddad" , Raed Salem , Rahul Rameshbabu , Saeed Mahameed , Shuah Khan , Shuah Khan , Simon Horman , Stanislav Fomichev , Stanislav Fomichev , Tariq Toukan Subject: [PATCH net-next V2 05/13] net/mlx5e: psp: Move RX marker from ft_metadata to flow_tag Date: Tue, 4 Aug 2026 11:35:27 +0300 Message-ID: <20260804083535.2946459-6-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260804083535.2946459-1-tariqt@nvidia.com> References: <20260804083535.2946459-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00020E65:EE_|SA1PR12MB8163:EE_ X-MS-Office365-Filtering-Correlation-Id: cb68771e-6e9e-4e94-490b-08def203a535 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700016|23010399003|376014|7416014|18002099003|22082099003|11063799006|56012099006|3023799007|10067099003; X-Microsoft-Antispam-Message-Info: Ts2MAj/5lJwBu8CVboPEccMHaGI34/gL9+UsPyMqrbyyU0dz+utxonvq2vTS1I9EfLjbqrfoq3RkImA6HQAPgwryNIxAIqhr2s5y9KEoGb43Ac7vCqmsRjE5qSzqmq4j0cqzyQaZ8A+qwmpHGVMxFNVNUZZlyEzgEOeb+GCcq0sUqFpjAk3AvcbGAInVNiyMt8eNVagkSDg4XG+dd5HiDThFjKMYLrF2JESmjIzaLShX/80LVAbUSRMkUVsVxBaG0lN5OEJOCh6AGSm899+xB2flANRCv8O44pbK4fO6050WmUsM7HqxPZpBeiHByByBvKLXEXNzmkWRoWzsWqGRXCIwVXOPX7vrSjgnz4w24C7raHCqqMdAEe0rQ22YjuJ/dQEML0ZzwPSCJzq6oq8j6shCtGsE/X97zaDBjDCQoVBs0v30ZFc24JHBjAJqHC4WEnMatHjemMaf328uBQA5Gjgo7h/aeDBUAHk9ECXw2rro5WaEMWhHOoXi05uAJRab4Mo0xgGe/CfijiKHSiGbMmaSulblOOdpXc5kiyLzw1s5quVRdnXiq2INcAvYFjyak8yKnfI+o7ZGQ9ZmoSn9kwFqVP/nBIw8py4CLkq5Qf8MxptcR2xZ3+ZN70WOdjX/GHkHbqYn4iVZw5PiB+sfojEKETJm/76yNKLEdKf+pmQwKK7FgMXtuwnGRP7mRi1sLhgaxuHui8lSue/QQIXOeA== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700016)(23010399003)(376014)(7416014)(18002099003)(22082099003)(11063799006)(56012099006)(3023799007)(10067099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ED2hA1gh8TiNrJ7ThARuSIKyIssl3AsPYY9U2DyguQMd2tVg6HOKdZu6gM8fKk0wIMsZngBU2p/sCDErQuUueGgUn8fp1++jWt2E8E1QPZWlORunqwIe7fjv/LbJu6B6mUZ7f7Q4t3LlfcIiEPXBWvCtJkIuntmaTmBpjO7vK3zxbO51fORYCcZB7Cj83eRVx38JG/lmYthcDXXA5a9KMI61iQArgHJm2ivx09DKZk9yqr9X5DAb9C1w7Y7r+MQGI22Qe5mlHryDeFjFuJCcM8ve+XR7SmUE1EXwG//vqptYhZ0PsrcgW+o9kwGPRVxtpd6wChNTm+Hy+C8XFcSRCvzR5kao4smPKiN4gw1gWwwd+aOxZLseDxekVfNWqgokmiuL0sMNJh7Fa/ECqh0SnO2fFUb29RBmSq+NEEFkAmUmehYGc9PGFLek+hPZsY4S X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Aug 2026 08:37:40.1844 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cb68771e-6e9e-4e94-490b-08def203a535 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E65.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8163 Content-Type: text/plain; charset="utf-8" From: Cosmin Ratiu Move PSP RX marker from ft_metadata (set via modify_hdr action) to flow_tag (set via flow_context). This frees ft_metadata for storing SPI for future decapsulated PSP packets. All mlx5e accel protos have to move to avoid misinterpreting packets with high bits of ft_metadata as IPsec or Macsec. This patch is the first step, defining a new header, bit layout and macros. Signed-off-by: Cosmin Ratiu Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/en_accel/flow_tag.h | 35 +++++++++++++++++++ .../mellanox/mlx5/core/en_accel/psp.c | 34 ++++-------------- .../mellanox/mlx5/core/en_accel/psp_rxtx.h | 10 +++--- 3 files changed, 47 insertions(+), 32 deletions(-) create mode 100644 drivers/net/ethernet/mellanox/mlx5/core/en_accel/flow_t= ag.h diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/flow_tag.h b/= drivers/net/ethernet/mellanox/mlx5/core/en_accel/flow_tag.h new file mode 100644 index 000000000000..67f048ff7afe --- /dev/null +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/flow_tag.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ +/* Copyright (c) 2026, NVIDIA CORPORATION & AFFILIATES. All rights reserve= d. */ + +#ifndef __MLX5E_FLOW_TAG_H__ +#define __MLX5E_FLOW_TAG_H__ + +#include +#include +#include +#include + +/* Unified accel flow_tag layout in CQE sop_drop_qpn [23:0]: + * + * [23:21] =3D protocol ID (3 bits): + * 0 =3D none (default) + * 3 =3D PSP (HW decrypted, PSP header present) + * 1,2,4-7 =3D reserved + * [20:16] =3D reserved + * [15:0] =3D used by other subsystems (e.g. TC). + */ +#define MLX5E_ACCEL_FLOW_TAG_PROTO_MASK GENMASK(23, 21) +#define MLX5E_ACCEL_FLOW_TAG_PROTO_NONE (0 << 21) +#define MLX5E_ACCEL_FLOW_TAG_PROTO_PSP (3 << 21) + +static inline u32 mlx5e_accel_flow_tag(struct mlx5_cqe64 *cqe) +{ + return be32_to_cpu(cqe->sop_drop_qpn) & 0xFFFFFF; +} + +static inline u32 mlx5e_accel_flow_tag_proto(struct mlx5_cqe64 *cqe) +{ + return mlx5e_accel_flow_tag(cqe) & MLX5E_ACCEL_FLOW_TAG_PROTO_MASK; +} + +#endif /* __MLX5E_FLOW_TAG_H__ */ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/psp.c b/drive= rs/net/ethernet/mellanox/mlx5/core/en_accel/psp.c index 6cc4b9d54f6e..ca5bb60f6d16 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/psp.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/psp.c @@ -8,6 +8,7 @@ #include "lib/crypto.h" #include "en_accel/en_accel.h" #include "en_accel/psp.h" +#include "en_accel/psp_rxtx.h" #include "fs_core.h" =20 enum accel_fs_psp_type { @@ -42,7 +43,6 @@ struct mlx5e_psp_rx_decrypt_table { struct mlx5_flow_table *ft; struct mlx5_flow_group *miss_group; struct mlx5_flow_handle *miss_rule; - struct mlx5_modify_hdr *rx_modify_hdr; struct mlx5_flow_handle *rule; }; =20 @@ -408,10 +408,6 @@ accel_psp_fs_rx_decrypt_ft_destroy(struct mlx5e_psp_fs= *fs, struct mlx5e_psp_rx_decrypt_table *decrypt) { accel_psp_fs_del_flow_rule(&decrypt->rule); - if (decrypt->rx_modify_hdr) { - mlx5_modify_header_dealloc(fs->mdev, decrypt->rx_modify_hdr); - decrypt->rx_modify_hdr =3D NULL; - } accel_psp_fs_del_flow_rule(&decrypt->miss_rule); accel_psp_fs_destroy_flow_group(&decrypt->miss_group); accel_psp_fs_destroy_ft(&decrypt->ft); @@ -431,8 +427,6 @@ accel_psp_fs_rx_decrypt_ft_create(struct mlx5e_psp_fs *= fs, struct mlx5e_psp_rx_decrypt_table *decrypt, struct mlx5_flow_destination *default_dest) { - u8 action[MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)] =3D {}; - struct mlx5_modify_hdr *modify_hdr =3D NULL; struct mlx5_flow_table_attr ft_attr =3D {}; struct mlx5_flow_destination dest =3D {}; struct mlx5_core_dev *mdev =3D fs->mdev; @@ -482,28 +476,14 @@ accel_psp_fs_rx_decrypt_ft_create(struct mlx5e_psp_fs= *fs, =20 /* Add PSP RX decrypt rule */ setup_fte_udp_psp(spec, PSP_DEFAULT_UDP_PORT); - flow_act.crypto.type =3D MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_PSP; - /* Set bit[31, 30] PSP marker */ -#define MLX5E_PSP_MARKER_BIT (BIT(30) | BIT(31)) - MLX5_SET(set_action_in, action, action_type, MLX5_ACTION_TYPE_SET); - MLX5_SET(set_action_in, action, field, MLX5_ACTION_IN_FIELD_METADATA_REG_= B); - MLX5_SET(set_action_in, action, data, MLX5E_PSP_MARKER_BIT); - MLX5_SET(set_action_in, action, offset, 0); - MLX5_SET(set_action_in, action, length, 32); - - modify_hdr =3D mlx5_modify_header_alloc(mdev, MLX5_FLOW_NAMESPACE_KERNEL,= 1, action); - if (IS_ERR(modify_hdr)) { - err =3D PTR_ERR(modify_hdr); - mlx5_core_err(mdev, "fail to alloc psp set modify_header_id err=3D%d\n",= err); - modify_hdr =3D NULL; - goto out_err; - } - decrypt->rx_modify_hdr =3D modify_hdr; =20 + /* Set PSP marker via flow_tag */ + spec->flow_context.flags =3D FLOW_CONTEXT_HAS_TAG; + spec->flow_context.flow_tag =3D MLX5E_ACCEL_FLOW_TAG_PROTO_PSP; + + flow_act.crypto.type =3D MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_PSP; flow_act.action =3D MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | - MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT | - MLX5_FLOW_CONTEXT_ACTION_MOD_HDR; - flow_act.modify_hdr =3D modify_hdr; + MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT; dest.type =3D MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE; dest.ft =3D fs->check.ft; rule =3D mlx5_add_flow_rules(decrypt->ft, spec, &flow_act, &dest, 1); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/psp_rxtx.h b/= drivers/net/ethernet/mellanox/mlx5/core/en_accel/psp_rxtx.h index 2b080c39cc37..a26faf7cfc27 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/psp_rxtx.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/psp_rxtx.h @@ -9,10 +9,7 @@ #include #include "en.h" #include "en/txrx.h" - -/* Bit30: PSP marker, Bit22-0: PSP obj id */ -#define MLX5_PSP_METADATA_MARKER(metadata) ((((metadata) >> 30) & 0x3) = =3D=3D 0x3) -#define MLX5_PSP_METADATA_HANDLE(metadata) ((metadata) & GENMASK(22, 0)) +#include "en_accel/flow_tag.h" =20 struct mlx5e_accel_tx_psp_state { u32 tailen; @@ -82,7 +79,10 @@ static inline unsigned int mlx5e_psp_tx_ids_len(struct m= lx5e_accel_tx_psp_state =20 static inline bool mlx5e_psp_is_rx_flow(struct mlx5_cqe64 *cqe) { - return MLX5_PSP_METADATA_MARKER(be32_to_cpu(cqe->ft_metadata)); + u32 proto =3D mlx5e_accel_flow_tag_proto(cqe); + + return proto =3D=3D MLX5E_ACCEL_FLOW_TAG_PROTO_PSP; + } =20 bool mlx5e_psp_offload_handle_rx_skb(struct net_device *netdev, struct sk_= buff *skb, --=20 2.44.0 From nobody Fri Oct 2 06:58:27 2026 Received: from MW6PR02CU001.outbound.protection.outlook.com (mail-westus2azon11012061.outbound.protection.outlook.com [52.101.48.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB29A43F0A2; Tue, 4 Aug 2026 08:37:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.48.61 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785832672; cv=fail; b=VL0NXdOFJMxVp5JDJYPFlVRI/oJ2VpIMaeZQ+wKrWiSuocivEs6r4rUFQVlnvURVlR8NQ1gf6bXKv6E/SPaACSOhN+X5Mn+BAfKyWXQORmHH3DLllDfqRuj7T77tuGRwTuBlT+NqWgqCWAIo72deVIJr8PT+Pkk7yu/aRmM8yOQ= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785832672; c=relaxed/simple; bh=iTXGvFPY4pfd9ioud/hs3HFb60fPoeKTgcA64diBHgI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=pu4vzeJK2ZdXE3jlUaJyymrDKBnoyrpwWQ3fAfXFp7CTURGDJ9pcbW6cig1cm+E9ejMvHumZzlG0uY6uk1A2Q9yFxc+tMP36hJjatWlbsQms5hEZCSnc0uuiI4Jx8ol0R8Ht+eNF2J0BHrzWjBbC6Pmu3pabLZE0YNJk0LnjzYg= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=ZIgM0kdw; arc=fail smtp.client-ip=52.101.48.61 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="ZIgM0kdw" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=PhlV94ututl34kX5vzmRFu5l0Z8q1WyzCjLSmgPfSuHGrUjBfi0J7+PFkwNNdHVwpDcjXegFW3ayLvFgIrxWmv6i8kBqDY+8ILbqCGbcicgdpOKo13qwJ2wOU+HUaV5jTncpyyUXqvqG0iT5svxnpavjrfu3zDKh9uJd96J+YDkUcu63/adnhXu2+Px6cdYpEaYdOl02r/MCSzzmUGBbouryoHpwEAD0ARPEs3yM2XbiflK/q0QbcUf3d2R3paJJIPtIG+T8Ne0N8jP30mjrv8ewz4lllxhRc/HWTpjide+1nOFo8LgdwKeFfRGh7V+NHv2YhORv4idZTf+EzUBtIg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=svE5la3NzrcnVi5xhNIJXanR8uk+OS8Uz3eYI8eLJw0=; b=ul+BYdjNoPPq+rPHAWlgCwNOflF+JRpashIFGPLlT7WhSEcISvHQ40qFk8IPYmAWZaAvdcWs702G5EbsMeQy8EPSsiBKXvq7aB/CF2YULnliy1qLe+KOrEpH83Hw0sSUUApVzt7K6ykUxu+Nquebep2iSCFR/vTmJKQF6jvwpf6i8Q2lIwTegQGiraK4sn0p9/Ia6eYEGwiMIsTSkQKSnzY4uzHF90OTHWRR0mXRBbDqeN/RhHvEo/JUA78AotVVWp7IvwWUbWlIax7wmFUPtXHU8bMOWypG4GqGKx0B5hFJINV9ofW3CYSYGKvPoJ11+gEChfzQqpf9VqnSCq16xw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=lunn.ch smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=svE5la3NzrcnVi5xhNIJXanR8uk+OS8Uz3eYI8eLJw0=; b=ZIgM0kdw+1vMjhguXdCwGCbZhsZd3qZ5/3QOIxqXtzZRPH3+GAWTI7G5yIWD1LExM9SAZdTKlA2tMzDNP0Q7yNwwQTSx2Cl8YXuFszUobSTkY4IkFNdt0rgwf02q5xwBkzRCMVCWbAo69jpajcduVzHdoVLNmEZv+m/EJdho1vTLr2e3w1SDtzegJ9yye33b2h1+Fp2lau1y5zKCuV5dLYImurRsqefqcE5W69sLws/60Jz/AxFO4Wy4GvNe5/LrN+7lKkK1r8WstP66aRS21FG57mIr52aV26qhKbuI/FqD7Rnf3qy4Oa0SDARbduh6RfUitjwwHhFhl+nWc05iJg== Received: from BL1PR13CA0125.namprd13.prod.outlook.com (2603:10b6:208:2bb::10) by CY3PR12MB9656.namprd12.prod.outlook.com (2603:10b6:930:101::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.270.18; Tue, 4 Aug 2026 08:37:45 +0000 Received: from BL6PEPF00020E60.namprd04.prod.outlook.com (2603:10b6:208:2bb:cafe::12) by BL1PR13CA0125.outlook.office365.com (2603:10b6:208:2bb::10) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.292.15 via Frontend Transport; Tue, 4 Aug 2026 08:37:44 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by BL6PEPF00020E60.mail.protection.outlook.com (10.167.249.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.292.8 via Frontend Transport; Tue, 4 Aug 2026 08:37:44 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 4 Aug 2026 01:37:35 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 4 Aug 2026 01:37:34 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Tue, 4 Aug 2026 01:37:26 -0700 From: Tariq Toukan To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , , Paolo Abeni , Sabrina Dubroca CC: Aleksandr Loktionov , Alexei Lazar , Boris Pismenny , Carolina Jubran , Chris Mi , Cosmin Ratiu , Daniel Zahka , Doruk Tan Ozturk , Dragos Tatulea , Gal Pressman , Jacob Keller , Jianbo Liu , Kees Cook , Lama Kayal , Leon Romanovsky , , , , Mark Bloch , "Patrisious Haddad" , Raed Salem , Rahul Rameshbabu , Saeed Mahameed , Shuah Khan , Shuah Khan , Simon Horman , Stanislav Fomichev , Stanislav Fomichev , Tariq Toukan Subject: [PATCH net-next V2 06/13] net/mlx5e: ipsec: Move RX marker from ft_metadata to flow_tag Date: Tue, 4 Aug 2026 11:35:28 +0300 Message-ID: <20260804083535.2946459-7-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260804083535.2946459-1-tariqt@nvidia.com> References: <20260804083535.2946459-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00020E60:EE_|CY3PR12MB9656:EE_ X-MS-Office365-Filtering-Correlation-Id: d5154110-e9ce-4901-3a3a-08def203a7d3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700016|23010399003|7416014|376014|6133799003|56012099006|11063799006|10067099003|3023799007|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: VAfJdv36InQxyMZ69hbjeFE7fohGzgsFyQPiaSzOrOu4zIdAW2d9rh70FlLkr3QZcM+XIYRYQFHvmVbRWTrfo3T/ZDY/cWKqmfsK1M/RLuPtFUqVo5olcv8we1JXRDKRXwPc0td1ZNtWsnlMZF9ShPWkUP9EiX54KneEYlqYNl9xSzXdyAAnmvMLvzYECHOEGFaeISA5cRQwEPNBQsE3EOwZwkp3RATuOmOK8FVJQ02+Gmy7EqYKu8aGaxB9kEIZlNLVi+etP3U/BoCO6RUTZ13eEUIDo1wVWbyPjYcuvCemy86znZxT27SyeyHi0GMYeqyDOXUUo8qJik/YFkgUxJ1rNExsQ0v7QRQ4LDaLC/WC0MuxZS3uXDBUUT+xGMgmPcabaE0Rg3lXNtaRm7sYfAnPxx0Akxvr0pYIYthfCVXc2Bv22mAR6fkSl7GWafhJ/AvaDu+eOyPCZDsrDu4GVg+nxI+5kTlkpQRxEW0EaPqfBM0CEIdNKoXv3BxLTuFH8HQ8cbVr3zmn18oGFVloYg13JAzJiGoA7B+S7CjtaNkXwB4IvDm7dRTUie9hVTXRLcj9GDL0cXp5O28FjaH+goI1B7qbQeLCVfjNOJnTsWAHKhw/X/PPAsog7RxE3QFvgSL9jTdsp3ID0aWG5BPp8/L+mYm8qZLYZ+pDtNoIjzgOiwWyLDEJp+8K49u6uc/4jPRfh06KoM3UI+pJA4nkKw== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700016)(23010399003)(7416014)(376014)(6133799003)(56012099006)(11063799006)(10067099003)(3023799007)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Je7PNuQ3oT5E8keSIjU38mIqAz9VvyaBs6hZVx3hwBOGKAo4AtTk5E6hAN9h/cWi/yJQXHpDa6mxjvQObYK7RxGtfr9QCg15Q3JKOTUAitPAnVnoJZe9k6M+idgHeUe8suZfgRekDZcna/40MErWVt53NeOjwPlBxxCbuht/00OuZzhONA1e6xwNt5xRB3EMwOYW7Sfn7xXSZ+P/IP/OeBAXU9skSbD6BolEclH6BvTepCOfwuzOZJ8DaXbFOzHAm1pm65QtH+03gln+UlfLXvcACF1TlyVsziCHc98cvp+otNtq9mNzpsqCPUhn0tfQfZc5U8IjFi1/25JxnfGsaNDsftXlT2wpmxZj4U2eGNpnMRl5qv6NRsrO3OFwbRa08Vz6sq0dI+OcRissw6XBhaxNvcQJVKycdPoLeAZyj6TGkwJ7/Bj1p7FWDJCMortm X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Aug 2026 08:37:44.5465 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d5154110-e9ce-4901-3a3a-08def203a7d3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E60.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY3PR12MB9656 Content-Type: text/plain; charset="utf-8" From: Cosmin Ratiu IPsec used BIT(31) in cqe.ft_metadata as a marker for ingress IPsec-decrypted packets. This will conflict with PSP which stores SPI in ft_metadata - an SPI with bit 31 set would falsely trigger mlx5_ipsec_is_rx_flow(). Define a new marker for IPsec in flow_tag and use it in steering rules. The obj_id stays in ft_metadata bits[23:0]. Remove the unused MARKER and SYNDROM (sic) macros. This is only done for IPsec NIC RX flows. The esw path uses a different mechanism and is unaffected: RX handling in mlx5e_rep_tc_receive() makes use of a few bits in ft_metadata to detect and hand off IPsec packets to mlx5e_ipsec_offload_handle_rx_skb(). An additional complication is that mlx5e_cqe_regb_chain() used the high order bits of ft_metadata to differentiate between TC chains and protocol markers. With the IPSec marker moving to flow_tag, this would falsely trigger mlx5e_cqe_regb_chain() to believe the chain is set, when in fact, ft_metadata is something completely different. Solve that by requiring that the new flow_tag proto is NONE, since only those packets can carry a chain id in ft_metadata. Signed-off-by: Cosmin Ratiu Reviewed-by: Dragos Tatulea Reviewed-by: Carolina Jubran Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/en_accel/flow_tag.h | 4 +++- .../net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c | 9 +++++++-- .../ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.h | 9 +++++---- drivers/net/ethernet/mellanox/mlx5/core/en_tc.h | 7 +++++-- 4 files changed, 20 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/flow_tag.h b/= drivers/net/ethernet/mellanox/mlx5/core/en_accel/flow_tag.h index 67f048ff7afe..8a02e8e9713d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/flow_tag.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/flow_tag.h @@ -13,13 +13,15 @@ * * [23:21] =3D protocol ID (3 bits): * 0 =3D none (default) + * 1 =3D IPsec * 3 =3D PSP (HW decrypted, PSP header present) - * 1,2,4-7 =3D reserved + * 2,4-7 =3D reserved * [20:16] =3D reserved * [15:0] =3D used by other subsystems (e.g. TC). */ #define MLX5E_ACCEL_FLOW_TAG_PROTO_MASK GENMASK(23, 21) #define MLX5E_ACCEL_FLOW_TAG_PROTO_NONE (0 << 21) +#define MLX5E_ACCEL_FLOW_TAG_PROTO_IPSEC (1 << 21) #define MLX5E_ACCEL_FLOW_TAG_PROTO_PSP (3 << 21) =20 static inline u32 mlx5e_accel_flow_tag(struct mlx5_cqe64 *cqe) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c b/= drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c index f236672d3a2a..081cb2f31be0 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c @@ -5,6 +5,7 @@ #include "en.h" #include "en/fs.h" #include "en_accel/en_accel.h" +#include "en_accel/flow_tag.h" #include "eswitch.h" #include "ipsec.h" #include "fs_core.h" @@ -190,7 +191,7 @@ static void ipsec_rx_rule_add_match_obj(struct mlx5e_ip= sec_sa_entry *sa_entry, misc_parameters_2.metadata_reg_c_2); MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_c_2, - sa_entry->ipsec_obj_id | BIT(31)); + sa_entry->ipsec_obj_id); =20 spec->match_criteria_enable |=3D MLX5_MATCH_MISC_PARAMETERS_2; } @@ -2066,7 +2067,7 @@ static int rx_add_rule(struct mlx5e_ipsec_sa_entry *s= a_entry) if (!attrs->drop) { if (rx !=3D ipsec->rx_esw) err =3D setup_modify_header(ipsec, attrs->type, - sa_entry->ipsec_obj_id | BIT(31), + sa_entry->ipsec_obj_id, XFRM_DEV_OFFLOAD_IN, &flow_act); else err =3D mlx5_esw_ipsec_rx_setup_modify_header(sa_entry, &flow_act); @@ -2099,6 +2100,10 @@ static int rx_add_rule(struct mlx5e_ipsec_sa_entry *= sa_entry) flow_act.action |=3D MLX5_FLOW_CONTEXT_ACTION_DROP; else flow_act.action |=3D MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; + if (!attrs->drop && rx !=3D ipsec->rx_esw) { + spec->flow_context.flags |=3D FLOW_CONTEXT_HAS_TAG; + spec->flow_context.flow_tag =3D MLX5E_ACCEL_FLOW_TAG_PROTO_IPSEC; + } dest[0].type =3D MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE; dest[0].ft =3D rx->ft.status; dest[1].type =3D MLX5_FLOW_DESTINATION_TYPE_COUNTER; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.h = b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.h index 45b0d19e735c..6dea5978a40e 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.h @@ -38,10 +38,9 @@ #include #include "en.h" #include "en/txrx.h" +#include "en_accel/flow_tag.h" =20 -/* Bit31: IPsec marker, Bit30: reserved, Bit29-24: IPsec syndrome, Bit23-0= : IPsec obj id */ -#define MLX5_IPSEC_METADATA_MARKER(metadata) ((((metadata) >> 30) & 0x3) = =3D=3D 0x2) -#define MLX5_IPSEC_METADATA_SYNDROM(metadata) (((metadata) >> 24) & GENMAS= K(5, 0)) +/* IPsec obj id in ft_metadata bits[23:0] */ #define MLX5_IPSEC_METADATA_HANDLE(metadata) ((metadata) & GENMASK(23, 0)) =20 struct mlx5e_accel_tx_ipsec_state { @@ -74,7 +73,9 @@ static inline unsigned int mlx5e_ipsec_tx_ids_len(struct = mlx5e_accel_tx_ipsec_st =20 static inline bool mlx5_ipsec_is_rx_flow(struct mlx5_cqe64 *cqe) { - return MLX5_IPSEC_METADATA_MARKER(be32_to_cpu(cqe->ft_metadata)); + u32 proto =3D mlx5e_accel_flow_tag_proto(cqe); + + return proto =3D=3D MLX5E_ACCEL_FLOW_TAG_PROTO_IPSEC; } =20 static inline bool mlx5e_ipsec_eseg_meta(struct mlx5_wqe_eth_seg *eseg) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.h b/drivers/net/= ethernet/mellanox/mlx5/core/en_tc.h index e1b8cb78369f..53b6043e33d2 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.h @@ -36,6 +36,7 @@ #include #include "en.h" #include "eswitch.h" +#include "en_accel/flow_tag.h" #include "en/tc_ct.h" #include "en/tc_tun.h" #include "en/tc/int_port.h" @@ -370,11 +371,13 @@ struct mlx5e_tc_table *mlx5e_tc_table_alloc(void); void mlx5e_tc_table_free(struct mlx5e_tc_table *tc); static inline bool mlx5e_cqe_regb_chain(struct mlx5_cqe64 *cqe) { - u32 chain, reg_b; + u32 flow_tag, reg_b, chain; =20 + flow_tag =3D mlx5e_accel_flow_tag_proto(cqe); reg_b =3D be32_to_cpu(cqe->ft_metadata); =20 - if (reg_b >> (MLX5E_TC_TABLE_CHAIN_TAG_BITS + ESW_ZONE_ID_BITS)) + if (flow_tag !=3D MLX5E_ACCEL_FLOW_TAG_PROTO_NONE || + (reg_b >> (MLX5E_TC_TABLE_CHAIN_TAG_BITS + ESW_ZONE_ID_BITS))) return false; =20 chain =3D reg_b & MLX5E_TC_TABLE_CHAIN_TAG_MASK; --=20 2.44.0 From nobody Fri Oct 2 06:58:27 2026 Received: from CY3PR05CU001.outbound.protection.outlook.com (mail-westcentralusazon11013018.outbound.protection.outlook.com [40.93.201.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D0E9440A3D; Tue, 4 Aug 2026 08:38:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.201.18 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785832689; cv=fail; b=hJNyV7xNgpaQJOx+6eELii+HfzLFuNr9qxho6d1HWMETeqDTl8bGuvFlo5ExPpuxsR9Bzc4mvHphnoTBs1sfnT+g0P7zobXRVxOZP3lvnZcpPEZP2UQpFMVF4vP+7ytwFjtsavmlWwvhSTJfvi/2izWdJMzIKNjllrwK9v9DXfI= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785832689; c=relaxed/simple; bh=K79ghD/WIanBDVAeeC3TkunkpIzvj/UNEO5YRFhGcmw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=AgAJn1WAVn8bxn43rENFW4HPCch5gO5JYRKpO9lLGRvylZR85/6V3JBIim+ckdccqiRfb8Hc8aXpaVQL9Zg+SfV8eWtl7F4l/XjdHL0D3vJFL1aMgXpbwlzaTx9n/FCC2YC7aJEsF3dRritx8rJMZrMnVKQ4OOWj2kj5GnaczIY= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=Cz9aqwib; arc=fail smtp.client-ip=40.93.201.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="Cz9aqwib" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=ClluUomfGWy9b+s0kBOpC+KtCGIvufS5PJ4yeDnO3++7QQ9dhFDupvTxfkp5e4+Ui5BErZ9DyxAXhA7qpPmv1OS/fUvbXhcKMhpqXcCckrF1xQDgt9/HnTRLnJI1bOocDdjEHk/wklJxvVdvk/Ngf6bCq0UIE+hZwjXAJ0wy1VPtFKKUTFEC+8buVa2gOcyTzDpX6tEh75F3a4/QCq2RUQC7cP2il2CtBMNIAm3LuzekaTeV/Mz5XaLYEqq+qeMfZLG8lA8AQsdnSTUBMJAYPilRp6kYtgHuDazd2fSp2vHta9GvrJC7dk8UL/JdRWUDaWc1Bgc5OMmnXKu/PCye6A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=YosucmlZe95ViftRsSyssVpiiEvpUvQqrcmejy+CgiU=; b=G4NG0uo2vS3MfQlaVX+gpnmwsnZCQ6UWAx1TtidyfxFDmPIMMwtcj12MeYzkiEW4x0vWNOm6JeBdZQZQX85wmBcPwSeCYa/5tOG9roUmNRiakXOn6ZfUKpZ2Kyay4adQipL8CE648X509dq8vnB+xYAFjDtykiES8Tjc5JPcmcSQba3YFIyypWQF8XW7VceK5CHfsj/mXmvN4iFLph6p9RG8czpEL993JQQiO+709k0yTLeZe9hCF+3T123txx3kkHDULMZXDxg4bfMWVSyQ2hSsPwGfUeKn239U968R5yKQAAmrXS/l0fWajeaJ16w6uZXD67Di/+ryxfc/WK81ZQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=lunn.ch smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=YosucmlZe95ViftRsSyssVpiiEvpUvQqrcmejy+CgiU=; b=Cz9aqwibcW/Cf+f2bBHZhXaUv8U75x5tV2zAfqqloKJrll80r7IclpLdUKjCxqZNLUgnCZv20zoor4gxnVdcwMqUWijc7kpbADInOPWizpO/f1wj9E2lNM3grlHQJGa4GiVNXeuUEkrUMy3QcsRocIPcmjjPGFHTbDLtDLQA+ZbFKGbRbHE013zBSCzVr7TsEJWFnPq5AGjjbZ9e8uui9eAnfLhjnUZQT+YTA6v6w1+LR0E1FtZhVvbWFFuSJ5rgEx5baUA3/U5qzr5UPOVnKL4iEG4zT0FqNpXGw7jzMtNgoNb5wpPXlBO0FyIKY/p5QipcNdhIcU32dXMJb2cqGQ== Received: from SA0PR11CA0171.namprd11.prod.outlook.com (2603:10b6:806:1bb::26) by LV2PR12MB5871.namprd12.prod.outlook.com (2603:10b6:408:174::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.292.15; Tue, 4 Aug 2026 08:38:00 +0000 Received: from SN1PEPF000252A1.namprd05.prod.outlook.com (2603:10b6:806:1bb:cafe::81) by SA0PR11CA0171.outlook.office365.com (2603:10b6:806:1bb::26) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.292.15 via Frontend Transport; Tue, 4 Aug 2026 08:38:00 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by SN1PEPF000252A1.mail.protection.outlook.com (10.167.242.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.292.8 via Frontend Transport; Tue, 4 Aug 2026 08:37:59 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Tue, 4 Aug 2026 01:37:43 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 4 Aug 2026 01:37:42 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Tue, 4 Aug 2026 01:37:35 -0700 From: Tariq Toukan To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , , Paolo Abeni , Sabrina Dubroca CC: Aleksandr Loktionov , Alexei Lazar , Boris Pismenny , Carolina Jubran , Chris Mi , Cosmin Ratiu , Daniel Zahka , Doruk Tan Ozturk , Dragos Tatulea , Gal Pressman , Jacob Keller , Jianbo Liu , Kees Cook , Lama Kayal , Leon Romanovsky , , , , Mark Bloch , "Patrisious Haddad" , Raed Salem , Rahul Rameshbabu , Saeed Mahameed , Shuah Khan , Shuah Khan , Simon Horman , Stanislav Fomichev , Stanislav Fomichev , Tariq Toukan Subject: [PATCH net-next V2 07/13] net/mlx5e: macsec: Move RX marker from ft_metadata to flow_tag Date: Tue, 4 Aug 2026 11:35:29 +0300 Message-ID: <20260804083535.2946459-8-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260804083535.2946459-1-tariqt@nvidia.com> References: <20260804083535.2946459-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A1:EE_|LV2PR12MB5871:EE_ X-MS-Office365-Filtering-Correlation-Id: 1fd16a49-28e4-487e-2669-08def203b07e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|1800799024|7416014|376014|82310400026|36860700016|10067099003|11063799006|6133799003|56012099006|3023799007|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: oDBXaU0zL7WIWVEb2NeIwNwx4oo8dLEoBB2qDCj1e1ggs62TDiui20XM8QlK2+FoBweBmiXiLjZ5Q7tyq7aObUcgjO7Tou9ixvrRBiqXPFHYxa82moubDu1WeKbwEDMpQY5aYFlq6yGTg9nV3X9lZbk3zFaMIMRuPINmwGKOWUClejd7W7oJ0J90vMV42/wRFvVvfafr24/IIArkDY00zMLCPsPPGY0zpEGCAp9AbOTLkiVB+APOZzzbNsjj4M3/lA1r3Z+Uv81L6AHZ/Bhc5Uph6maB18b8kyMhSz6Ktfr97DyI1esASZ8w2JV2tq7skq86gbacmawgn2kOKJqnBwestMl1mc/SOQbyYenra4q3XJtGWSZ+RC56f18LvfH11ob5CwE3WBAMrb5AFOKnlkblMO1OnNBOMDYGN5wPvRC31joLzRcFAxJiER0MfWKkKprS3jf7mfmRiKTe5Oi0fyPwahHBPVLmZRvkveyi0SycZkoYT8UqUxA+FU1htPJc9a3Q1jmv2hv/J/bLf1KFDhL2liQDtSF7blF/X5NoiDRXtYujwjX/d19Fa9f2M2VD7nlQrFVDY1vi7QMjqT4fZIX/2gye2xSeIeMIDZJcVgI/6T4ZS/ySdE8RmT4jgNA1ohJIo2SgLfNIWJl+spWMtd/3AclylggegnRuGdP4Ku9swcZdqlRnvgZOZHZH+rKsByrAOyhev9nb5qfw+QXQtA== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(23010399003)(1800799024)(7416014)(376014)(82310400026)(36860700016)(10067099003)(11063799006)(6133799003)(56012099006)(3023799007)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 9pTEo76NfS4wjwtYOXxFqeF6cn1dQ0Q5pXoXWplG2BNLg31XsSr/iA6a9x3KS/N9hWZDIhpMyHh3uhRyt72CKZqxOnSaK6vgPbxwRIBbbVCjYCGJlELVc9QI0vV/tG/IMoD2nuwLzdzBqTm3mNYOCjXgdL2mR5WOACLqs+Ty4BGElVZCIj3+tHuWPmfQnkG8c4QYY3xJgsG5zvgigv/NpplUhKcdEUP8Rn5hVwIUCTsqe8a7/YJ3HBoPT0nLg/9cSg5RRbOGbFoZk/MxxXlK6NNa25IcYR0Cua6QLU1jGShriOwfAfGet2mQh6sor09lqfU0+xfa2wuK4gLOf/gajZQDG32PfBs9NSMauZZx9lnMSTBzlQd536PAtBcvvSqwghE28hTKU4NCfcerMOs3Pdr+PUllNC9g4NG5dK7oER5PBhBdBq5ExjveNZIhYKcZ X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Aug 2026 08:37:59.1776 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1fd16a49-28e4-487e-2669-08def203b07e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5871 Content-Type: text/plain; charset="utf-8" From: Cosmin Ratiu MACsec uses BIT(30) in cqe.ft_metadata as a marker to identify MACsec-decrypted packets. This will conflict with PSP SPI values with bit 30 set, which would falsely trigger mlx5e_macsec_is_rx_flow(). Define a new marker for MACsec in flow_tag and use it in steering rules. The fs_id stays in ft_metadata bits[15:0]. Correct typos of MLX5_MACSEC_RX_METADAT_HANDLE and MLX5_MACEC_RX_FS_ID_MAX while touching this. Delete the METADATA_MARKER macro. Set flow_tag on both with-SCI and without-SCI crypto rules. Signed-off-by: Cosmin Ratiu Reviewed-by: Dragos Tatulea Reviewed-by: Carolina Jubran Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/en_accel/flow_tag.h | 4 +++- .../mellanox/mlx5/core/en_accel/macsec.c | 6 +++--- .../mellanox/mlx5/core/en_accel/macsec.h | 5 ++++- .../ethernet/mellanox/mlx5/core/lib/macsec_fs.c | 17 ++++++++++------- .../ethernet/mellanox/mlx5/core/lib/macsec_fs.h | 9 ++++----- 5 files changed, 24 insertions(+), 17 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/flow_tag.h b/= drivers/net/ethernet/mellanox/mlx5/core/en_accel/flow_tag.h index 8a02e8e9713d..28b4470bc91f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/flow_tag.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/flow_tag.h @@ -14,14 +14,16 @@ * [23:21] =3D protocol ID (3 bits): * 0 =3D none (default) * 1 =3D IPsec + * 2 =3D MACsec * 3 =3D PSP (HW decrypted, PSP header present) - * 2,4-7 =3D reserved + * 4-7 =3D reserved * [20:16] =3D reserved * [15:0] =3D used by other subsystems (e.g. TC). */ #define MLX5E_ACCEL_FLOW_TAG_PROTO_MASK GENMASK(23, 21) #define MLX5E_ACCEL_FLOW_TAG_PROTO_NONE (0 << 21) #define MLX5E_ACCEL_FLOW_TAG_PROTO_IPSEC (1 << 21) +#define MLX5E_ACCEL_FLOW_TAG_PROTO_MACSEC (2 << 21) #define MLX5E_ACCEL_FLOW_TAG_PROTO_PSP (3 << 21) =20 static inline u32 mlx5e_accel_flow_tag(struct mlx5_cqe64 *cqe) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c b/dr= ivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c index a15a0aff292f..aa7a28954861 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c @@ -752,12 +752,12 @@ static int mlx5e_macsec_add_rxsc(struct macsec_contex= t *ctx) * a non-NULL md_dst with uninitialised contents. */ err =3D xa_alloc(&macsec->sc_xarray, &sc_xarray_element->fs_id, sc_xarray= _element, - XA_LIMIT(1, MLX5_MACEC_RX_FS_ID_MAX), GFP_KERNEL); + XA_LIMIT(1, MLX5_MACSEC_RX_FS_ID_MAX), GFP_KERNEL); if (err) { if (err =3D=3D -EBUSY) netdev_err(ctx->netdev, "MACsec offload: unable to create entry for RX SC (%d Rx SCs alread= y allocated)\n", - MLX5_MACEC_RX_FS_ID_MAX); + MLX5_MACSEC_RX_FS_ID_MAX); goto destroy_md_dst; } =20 @@ -1724,7 +1724,7 @@ void mlx5e_macsec_offload_handle_rx_skb(struct net_de= vice *netdev, if (!macsec) return; =20 - fs_id =3D MLX5_MACSEC_RX_METADAT_HANDLE(macsec_meta_data); + fs_id =3D MLX5_MACSEC_RX_METADATA_HANDLE(macsec_meta_data); =20 rcu_read_lock(); sc_xarray_element =3D xa_load(&macsec->sc_xarray, fs_id); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.h b/dr= ivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.h index 27df72e23106..571624f2db15 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.h @@ -9,6 +9,7 @@ #include #include #include +#include "en_accel/flow_tag.h" #include "lib/macsec_fs.h" =20 struct mlx5e_priv; @@ -31,7 +32,9 @@ static inline bool mlx5e_macsec_skb_is_offload(struct sk_= buff *skb) =20 static inline bool mlx5e_macsec_is_rx_flow(struct mlx5_cqe64 *cqe) { - return MLX5_MACSEC_METADATA_MARKER(be32_to_cpu(cqe->ft_metadata)); + u32 proto =3D mlx5e_accel_flow_tag_proto(cqe); + + return proto =3D=3D MLX5E_ACCEL_FLOW_TAG_PROTO_MACSEC; } =20 void mlx5e_macsec_offload_handle_rx_skb(struct net_device *netdev, struct = sk_buff *skb, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.c b/driv= ers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.c index efc5167493c1..b8e9021027e9 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.c @@ -8,6 +8,7 @@ #include #include "fs_core.h" #include "lib/macsec_fs.h" +#include "en_accel/flow_tag.h" #include "mlx5_core.h" =20 /* MACsec TX flow steering */ @@ -45,9 +46,6 @@ #define MLX5_SECTAG_HEADER_SIZE_WITHOUT_SCI 0x8 #define MLX5_SECTAG_HEADER_SIZE_WITH_SCI (MLX5_SECTAG_HEADER_SIZE_WITHOUT_= SCI + MACSEC_SCI_LEN) =20 -/* MACsec fs_id handling for steering */ -#define macsec_fs_set_rx_fs_id(fs_id) ((fs_id) | BIT(30)) - struct mlx5_sectag_header { __be16 ethertype; u8 tci_an; @@ -1757,11 +1755,10 @@ macsec_fs_rx_add_rule(struct mlx5_macsec_fs *macsec= _fs, rx_tables =3D &rx_fs->tables; ft_crypto =3D &rx_tables->ft_crypto; =20 - /* Set bit[31 - 30] macsec marker - 0x01 */ /* Set bit[15-0] fs id */ MLX5_SET(set_action_in, action, action_type, MLX5_ACTION_TYPE_SET); MLX5_SET(set_action_in, action, field, MLX5_ACTION_IN_FIELD_METADATA_REG_= B); - MLX5_SET(set_action_in, action, data, macsec_fs_set_rx_fs_id(fs_id)); + MLX5_SET(set_action_in, action, data, fs_id); MLX5_SET(set_action_in, action, offset, 0); MLX5_SET(set_action_in, action, length, 32); =20 @@ -1778,6 +1775,9 @@ macsec_fs_rx_add_rule(struct mlx5_macsec_fs *macsec_f= s, /* Rx crypto table with SCI rule */ macsec_fs_rx_setup_fte(spec, &flow_act, attrs, true); =20 + spec->flow_context.flags |=3D FLOW_CONTEXT_HAS_TAG; + spec->flow_context.flow_tag =3D MLX5E_ACCEL_FLOW_TAG_PROTO_MACSEC; + flow_act.modify_hdr =3D modify_hdr; flow_act.action =3D MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT | @@ -1803,6 +1803,9 @@ macsec_fs_rx_add_rule(struct mlx5_macsec_fs *macsec_f= s, =20 macsec_fs_rx_setup_fte(spec, &flow_act, attrs, false); =20 + spec->flow_context.flags |=3D FLOW_CONTEXT_HAS_TAG; + spec->flow_context.flow_tag =3D MLX5E_ACCEL_FLOW_TAG_PROTO_MACSEC; + flow_act.modify_hdr =3D modify_hdr; flow_act.action =3D MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT | @@ -2160,8 +2163,8 @@ static int mlx5_macsec_fs_add_roce_rule_rx(struct mlx= 5_macsec_fs *macsec_fs, u32 =20 spec->match_criteria_enable |=3D MLX5_MATCH_MISC_PARAMETERS_2; MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, misc_parameters_2= .metadata_reg_c_5); - MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_r= eg_c_5, - macsec_fs_set_rx_fs_id(fs_id)); + MLX5_SET(fte_match_param, spec->match_value, + misc_parameters_2.metadata_reg_c_5, fs_id); flow_act.action =3D MLX5_FLOW_CONTEXT_ACTION_ALLOW; new_rule =3D mlx5_add_flow_rules(rx_fs->roce.ft_macsec_op_check, spec, &f= low_act, NULL, 0); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.h b/driv= ers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.h index 15acaff43641..b8b8b412d5c3 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/macsec_fs.h @@ -6,11 +6,10 @@ =20 #ifdef CONFIG_MLX5_MACSEC =20 -/* Bit31 - 30: MACsec marker, Bit15-0: MACsec id */ -#define MLX5_MACEC_RX_FS_ID_MAX USHRT_MAX /* Must be power of two */ -#define MLX5_MACSEC_RX_FS_ID_MASK MLX5_MACEC_RX_FS_ID_MAX -#define MLX5_MACSEC_METADATA_MARKER(metadata) ((((metadata) >> 30) & 0x3)= =3D=3D 0x1) -#define MLX5_MACSEC_RX_METADAT_HANDLE(metadata) ((metadata) & MLX5_MACSEC= _RX_FS_ID_MASK) +/* MACsec fs_id in ft_metadata bits[15:0] */ +#define MLX5_MACSEC_RX_FS_ID_MAX USHRT_MAX /* Must be power of two */ +#define MLX5_MACSEC_RX_FS_ID_MASK MLX5_MACSEC_RX_FS_ID_MAX +#define MLX5_MACSEC_RX_METADATA_HANDLE(metadata) ((metadata) & MLX5_MACSE= C_RX_FS_ID_MASK) =20 /* MACsec TX flow steering */ #define MLX5_ETH_WQE_FT_META_MACSEC_MASK \ --=20 2.44.0 From nobody Fri Oct 2 06:58:27 2026 Received: from CY3PR05CU001.outbound.protection.outlook.com (mail-westcentralusazon11013000.outbound.protection.outlook.com [40.93.201.0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9F581367F2F; Tue, 4 Aug 2026 08:38:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.201.0 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785832700; cv=fail; b=cM1dba5iuwSuAwkPCSnd/ncyMDUYleVyb1sJpwc54XZaK9K4xT/L74TubHPMbL692WLG6WtzcJx8V2fieesosJWkiVOUjTDotf+vskPT3OIcM2mm2TtOk0+9BvRCGosgp7Ule1tD7IBeGaxIumKBU4JRrRRp/Nel2Ve9it3EHzg= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785832700; c=relaxed/simple; bh=kxOTU8L/4Bz2Ih2+a2ZPHMGlLL+Qch0TMoTytc2oE4M=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=oNmJRcfxm3OsR9TwhGkoEU9p/XXhMnUTl/OOw7ZuFOH2CI+evYNQ60+4MPJKBeCvWLkK5e9ylybN0LZTQ8MGJm8uJ8+YzUrqnoFwA6wiTLUsLn6EId31ssgxJX60QtbgizOjN4QAT1fzXlYBO8B6FG7vV+0w8fVCb14mSYamRS4= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=Iu9uML/a; arc=fail smtp.client-ip=40.93.201.0 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="Iu9uML/a" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=broHAvgyA9K+Mk2vvBgFgrkhLtRYODt3jHchbM/lv/2cC31bFJfO60PhmO6y3NvZoPOi1/+JAYXTcD5FGmeQ2MHvfXYI90IHucg8wrpBHXDxDwLivGNVu8YWctyHw+AxhdU2ODa0Vlt4odljmj7nkf1mmI+yGqpsg3YaauiZlzleAC4/XuqSoVYHQoU6F3UHgE05JSbopdKr5tdOKjniVc9wDbNGGfNo/Su79O7OUAmgOoSwfKgIOnNo1uC6u8WEzVKvB94qEbIP179NBm/XXYFYye5n09/WWRmrj+6iZl8Y5ejP/Ek1+wCLprGzjNlTdMXcZUdtOlSbL60WXV6G9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=9hyHIL5NdCQ/KTN89/w1LSOcDEnoZkaPUlpEIL7mPgA=; b=n3B3TxP9SQRwv84VXDakputKhpHU/lqmAtxVvRlAbwXGXcjacGeeFLEx2G2ClqoERgPmC9EMAPTSfLEpoAZ5PUUx94Ax698Sp8umLhwjGHGmQjhZ4tdk1m4iiJa9OKqf8PFIC4Tr4uFGBF6TWi0C0byaWML7i7DcqeF2IabDy9kpv3D/ub4OHeQZj4yMf/wk7oasCuM4jy05FNLYFPuv61pH3aKrZQQ5KNgJxWVziKSMBE9ULXHFC3jdAD2+Hucv68plDroTRIvxWmvNPsfkNdOgyCvhWzlixyYnk/XlLcNko32qlTSn7iz6vbpsy3DLeJYJIo+aOTL3EX73ag78hw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=lunn.ch smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=9hyHIL5NdCQ/KTN89/w1LSOcDEnoZkaPUlpEIL7mPgA=; b=Iu9uML/aog5JRFvsj2DbUEH6WdFn3/WwpwqFxYa7hWhNBAvnKU+ePSeQG4SEMPfxpXAh6m8aMmrwLWoYdzb0tMvhlefvfWem8/BQg2kb3fh43Gskn6ZF88kxerxw/uBFJ51FIsnRsfaszq6Zt7khcen6swmJgjUY0yy9jzQgVGTUIQEtr/XfZTrCgpH0U7XsUNaDaYNIo7TtFCnPch6ozY5W8ncVPF5bdXxz8kteYomyUEJwQVQy/67ppkhvxTfRveYQNjJ/dYLKN//h0k1/WZl5LPnCyHOU1v8jT/oQiZd/4mzBHAaK20QByyIk1cqRPPjqkEBdAv9QSm+0HLVqDw== Received: from BL1PR13CA0108.namprd13.prod.outlook.com (2603:10b6:208:2b9::23) by BY5PR12MB4324.namprd12.prod.outlook.com (2603:10b6:a03:209::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.292.15; Tue, 4 Aug 2026 08:38:10 +0000 Received: from BL6PEPF00020E63.namprd04.prod.outlook.com (2603:10b6:208:2b9:cafe::1c) by BL1PR13CA0108.outlook.office365.com (2603:10b6:208:2b9::23) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.292.15 via Frontend Transport; Tue, 4 Aug 2026 08:38:10 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by BL6PEPF00020E63.mail.protection.outlook.com (10.167.249.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.292.8 via Frontend Transport; Tue, 4 Aug 2026 08:38:09 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 4 Aug 2026 01:37:51 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 4 Aug 2026 01:37:51 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Tue, 4 Aug 2026 01:37:43 -0700 From: Tariq Toukan To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , , Paolo Abeni , Sabrina Dubroca CC: Aleksandr Loktionov , Alexei Lazar , Boris Pismenny , Carolina Jubran , Chris Mi , Cosmin Ratiu , Daniel Zahka , Doruk Tan Ozturk , Dragos Tatulea , Gal Pressman , Jacob Keller , Jianbo Liu , Kees Cook , Lama Kayal , Leon Romanovsky , , , , Mark Bloch , "Patrisious Haddad" , Raed Salem , Rahul Rameshbabu , Saeed Mahameed , Shuah Khan , Shuah Khan , Simon Horman , Stanislav Fomichev , Stanislav Fomichev , Tariq Toukan Subject: [PATCH net-next V2 08/13] net/mlx5e: psp: Handle HW-decapsulated RX PSP packets Date: Tue, 4 Aug 2026 11:35:30 +0300 Message-ID: <20260804083535.2946459-9-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260804083535.2946459-1-tariqt@nvidia.com> References: <20260804083535.2946459-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00020E63:EE_|BY5PR12MB4324:EE_ X-MS-Office365-Filtering-Correlation-Id: 84212470-6c95-4a96-6ba8-08def203b68a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|23010399003|376014|7416014|1800799024|82310400026|10067099003|11063799006|56012099006|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: JqFbr2jWjt4H6hdk17RqPXeEM9uiLsIvRKXD+Sg+k3I9QwN1/z+fKYcFXzs3NTO5JZ6SBIkdfgMyVn4QvR9Z69XOs1ilSkcjjQu/DX59VLYf6s3d7n7U5Ug80M/Z0KVgZ36Dt4bdqVBR+NaCA/++2m84zOGwuR/GiuHIrSkPwUq+Pzv1CFAbh7gXtuRNuWDLEq01GXMr4lWS/O3qWh+7JmTkSXsxwVAsWtoF+cTC+0OfgrhDS35Cgi7eiPze6Hs0hkUMtCqjTbKOk8O1EqL2XLAw/rwsdHfK6Io8zP9Qk9ju+Ezvp2/nMYN0FzBtuSEIK15c22S9o3g7dqEGi1k0T1GTOoOXF5iPA0HojW4UUhrNA5rC4qhY8Ck2iFZOEL4yyNR9mMVTsYmGAn478jwqlzaueRS8BxXSmbKEfhhGKGUEd39n+KpknQpttaKO/qPyCrXq9XMMdRzzRDxRSW8jnqeUVc9vwre6yTiQQbRXivAA4haIhv0nbRitM+9sX6W6w/pAQFyMu1djbE1CTwE+DKWP4fRREPr07rr9hTKCDJMKGlrnlK9egMjnUV09BUbLivX3a47Pso6dclyT95gJifQPxljcN+HDRustW8yDNYm/NViBCsq8jOSElEgVRT/lFqGmfpZe8+OR0uWD+v1NQMz3lj5JE47iVQo5DUPb9ufTwCRmIuX8lYxM9MyrZ05klLUx3EhqsNI7QfslAf2WfQ== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(23010399003)(376014)(7416014)(1800799024)(82310400026)(10067099003)(11063799006)(56012099006)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: xkXTdbgUlqxo0eGjYkIbp/saHHWQtFDdQnHuVKllKyoVuTH50oGnpLmBwyZz6yDIzL9p1IXIrYieyplc6Gji8THR0A46thhkVwuOVRmBSnhvR7+jQHcM8wW3jgKIbu1a5CmE/XOCyMVFLvEY35gcd89NW/mSyswbYs0REXcqtCdw4xrAJLGaKADrdI0l/BN60L71Y6lceNIrcY11N3N+QzWXFJ/5f2dVJVabGc6NN+XU0dVEKkZcgncbAHWtiSmbtb/s9Bqo9LohrpJ2zDZyFoXt0wqybDwsZ8KQbxMyQ2ZmTQ5DRMGAeJAjbzbrAaA9XxTRxHcGavI/MJG7WmjawesfmUH8axOBK47SfOyQcKw0//G+UlaRol1Y0Pc7W6meOllAjv2IHnzeD1RvkJLy022aAG0V718QWEyHkEdenyMXtaYikieA9ioWMt79ACUE X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Aug 2026 08:38:09.2456 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 84212470-6c95-4a96-6ba8-08def203b68a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E63.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4324 Content-Type: text/plain; charset="utf-8" From: Cosmin Ratiu mlx5e_psp_offload_handle_rx_skb() handles RX PSP packets. Add an additional flow tag marker and helpers for decapsulated PSP packets and extend the handler to construct the PSP skb extension from the CQE fields (SPI in ft_metadata and PSP version in flow_tag). Signed-off-by: Cosmin Ratiu Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/en_accel/flow_tag.h | 10 ++++-- .../mellanox/mlx5/core/en_accel/psp_rxtx.c | 21 +++++++++-- .../mellanox/mlx5/core/en_accel/psp_rxtx.h | 36 ++++++++++++++++++- 3 files changed, 61 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/flow_tag.h b/= drivers/net/ethernet/mellanox/mlx5/core/en_accel/flow_tag.h index 28b4470bc91f..d422f96ffced 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/flow_tag.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/flow_tag.h @@ -16,8 +16,10 @@ * 1 =3D IPsec * 2 =3D MACsec * 3 =3D PSP (HW decrypted, PSP header present) - * 4-7 =3D reserved - * [20:16] =3D reserved + * 4 =3D PSP decap (HW decrypted & decapsulated) + * 5-7 =3D reserved + * [20:17] =3D PSP version (4 bits, valid when proto =3D=3D PSP decap) + * 16 =3D reserved * [15:0] =3D used by other subsystems (e.g. TC). */ #define MLX5E_ACCEL_FLOW_TAG_PROTO_MASK GENMASK(23, 21) @@ -25,6 +27,10 @@ #define MLX5E_ACCEL_FLOW_TAG_PROTO_IPSEC (1 << 21) #define MLX5E_ACCEL_FLOW_TAG_PROTO_MACSEC (2 << 21) #define MLX5E_ACCEL_FLOW_TAG_PROTO_PSP (3 << 21) +#define MLX5E_ACCEL_FLOW_TAG_PROTO_PSP_DECAP (4 << 21) + +#define MLX5E_ACCEL_FLOW_TAG_PSP_VER_SHIFT 17 +#define MLX5E_ACCEL_FLOW_TAG_PSP_VER_MASK (0xF << MLX5E_ACCEL_FLOW_TAG_PSP= _VER_SHIFT) =20 static inline u32 mlx5e_accel_flow_tag(struct mlx5_cqe64 *cqe) { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/psp_rxtx.c b/= drivers/net/ethernet/mellanox/mlx5/core/en_accel/psp_rxtx.c index 348fd7a96261..2beffee14278 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/psp_rxtx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/psp_rxtx.c @@ -118,10 +118,25 @@ bool mlx5e_psp_offload_handle_rx_skb(struct net_devic= e *netdev, struct sk_buff * { struct mlx5e_priv *priv =3D netdev_priv(netdev); u16 dev_id =3D priv->psp->psd->id; - bool strip_icv =3D true; - u8 generation =3D 0; + struct psp_skb_ext *pse; + + if (mlx5e_psp_is_decap(cqe)) { + /* UDP + PSP headers and PSP trailer removed by HW. + * Construct the PSP extension from CQE metadata. + */ + pse =3D skb_ext_add(skb, SKB_EXT_PSP); + if (unlikely(!pse)) + goto drop; + + pse->spi =3D mlx5e_psp_get_spi(cqe); + pse->version =3D mlx5e_psp_get_version(cqe); + pse->dev_id =3D dev_id; + pse->generation =3D 0; + skb->decrypted =3D 1; + return false; + } =20 - if (psp_dev_rcv(skb, dev_id, generation, strip_icv)) + if (psp_dev_rcv(skb, dev_id, 0, true)) goto drop; =20 skb->decrypted =3D 1; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/psp_rxtx.h b/= drivers/net/ethernet/mellanox/mlx5/core/en_accel/psp_rxtx.h index a26faf7cfc27..41b60259b3bc 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/psp_rxtx.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/psp_rxtx.h @@ -81,10 +81,29 @@ static inline bool mlx5e_psp_is_rx_flow(struct mlx5_cqe= 64 *cqe) { u32 proto =3D mlx5e_accel_flow_tag_proto(cqe); =20 - return proto =3D=3D MLX5E_ACCEL_FLOW_TAG_PROTO_PSP; + return proto =3D=3D MLX5E_ACCEL_FLOW_TAG_PROTO_PSP || + proto =3D=3D MLX5E_ACCEL_FLOW_TAG_PROTO_PSP_DECAP; =20 } =20 +static inline bool mlx5e_psp_is_decap(struct mlx5_cqe64 *cqe) +{ + u32 proto =3D mlx5e_accel_flow_tag_proto(cqe); + + return proto =3D=3D MLX5E_ACCEL_FLOW_TAG_PROTO_PSP_DECAP; +} + +static inline u8 mlx5e_psp_get_version(struct mlx5_cqe64 *cqe) +{ + return (mlx5e_accel_flow_tag(cqe) & MLX5E_ACCEL_FLOW_TAG_PSP_VER_MASK) >> + MLX5E_ACCEL_FLOW_TAG_PSP_VER_SHIFT; +} + +static inline __be32 mlx5e_psp_get_spi(struct mlx5_cqe64 *cqe) +{ + return cqe->ft_metadata; +} + bool mlx5e_psp_offload_handle_rx_skb(struct net_device *netdev, struct sk_= buff *skb, struct mlx5_cqe64 *cqe); #else @@ -110,6 +129,21 @@ static inline bool mlx5e_psp_is_rx_flow(struct mlx5_cq= e64 *cqe) return false; } =20 +static inline bool mlx5e_psp_is_decap(struct mlx5_cqe64 *cqe) +{ + return false; +} + +static inline u8 mlx5e_psp_get_version(struct mlx5_cqe64 *cqe) +{ + return 0; +} + +static inline __be32 mlx5e_psp_get_spi(struct mlx5_cqe64 *cqe) +{ + return 0; +} + static inline bool mlx5e_psp_offload_handle_rx_skb(struct net_device *netd= ev, struct sk_buff *skb, struct mlx5_cqe64 *cqe) --=20 2.44.0 From nobody Fri Oct 2 06:58:27 2026 Received: from DM1PR04CU001.outbound.protection.outlook.com (mail-centralusazon11010022.outbound.protection.outlook.com [52.101.61.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7992843E071; Tue, 4 Aug 2026 08:38:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.61.22 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785832705; cv=fail; b=b8odGGynVZTjBFp44K9zKorG23oJSup4ZAxcuDjJ0vGdq3tKQNeW5pmyBlQAHDDCsW/+cvjJuPoUL4c97sxghhfzkLft/Tl8aa9AxmzmcXwKOwKOYX5x6iYzAuFtH1OTo/PSYAvECE2uCmMEiBUc7FQNHXMKIhzl8T8whqi2ugI= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785832705; c=relaxed/simple; bh=Bl+WsP8q4BRLKNZkViHEBR1mzZ+4eacieCYs3IDyVPM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=dCkBG5W6ejKvURWOk4njginBlfCWj9L34BvGrLUS4nQ3sNSh6sGFFKVyZItLTJSGjIUoE7ndcZ8o9VIAgnr8sSQrfKTjB12pKoKBH+/AJqJfgF/U0n3lJFDaxCmzd9WuGQxi0JpGjZFFE0By5ImRA/1Gb8brnEtjXK3h6qm0D+E= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=Bx3bQE4r; arc=fail smtp.client-ip=52.101.61.22 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="Bx3bQE4r" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=OJkdzKVH9tZfwagKq/mFeF7cTdxCzJ9zg8V5nJykOiqhFVU4sZD34MER/XsLaJBJf0JS6vsfLaUVz5suDg4AP8tW/Gi3dVftNjPqKNhHPk7HgoOkqXj3aeYPEJxAsgPTIFyhAUHBY7UEE+oOhw/K7FoBFcBxPfjW3JN678mq1VKmT+BecQEbWm/y15zVjGoWUQfCVB+9LvxwZa+RGQ5/M+bEOhgqUII9MmCTliCmnqmWmFbdsB2v6gleESyM6pmHCOB5SFTgBSsi9+UhAzkILcScqYIJcv4K2zbZaynWJMs2BlY97LNr0+tUdoPVMXMMCPnG58Nwe14UcpomG7iqzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=uPMRtkzFawjP4/3R06oqVTAaRF+cZP0xecLVt55A0MA=; b=yfngfAPexu8HV7ZMTZk6QL90Tm9UoBjeLOIiKex2Z19h056qQWP1TsO2O2szrRrvEylxOgldjWMRF4nTqpJGJ3K/t9PIRteqGi0fNHbd4oP9oxLmawgcZyGGu3xqbgn/14KBlcJWYAy0unccE4dPlewEPyMunTseMooY8IEgL9Dp6SIbwRcHzHJtRmB75LslzeAsYFzVYYQu0Vi/wCYSK5Jf9Nj+rWmurDvorMr//MZeYl564tre6fPGdMfG/onMxdUQjvpGisLr23G1+x/i6GanyasuHwCbGlTCLmw5Wr/iuzkW+Rlvn64SaiCO2V+iuMJeHDbo6CE/3Bf/NdpRUg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=lunn.ch smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=uPMRtkzFawjP4/3R06oqVTAaRF+cZP0xecLVt55A0MA=; b=Bx3bQE4r51HEaV5oDM443asRx+7xyEjZpYqbqD9wfYh9kEyQ/F8K1GcXC8NA2t012FFNCujhsGGp0dy2TyegYU5wRQX7WII+ITq/iJ6G3olFxxx0bx2TdMbpcFsCeX+Am2emJfw54PCyLoLhtZ9o4U/C95HWRnDLmQwXvYzN/diiOc+A/uK4pj01ko1VnwI2j8oOhakzZ2c5zY31OWvFz/AwePn4EFvq7OfxgxnAU+4jzac7m49CZGH73fEuvNCBAdtLy4lvUszUNmDU1H3CNUCJCHq7A/ff4YdYaUJVos1vzObrs2rv+vuQqL6Fagjl8qj/wCbE4bYhXRT4s4Xoyw== Received: from PH8PR20CA0020.namprd20.prod.outlook.com (2603:10b6:510:23c::21) by IA1PR12MB6092.namprd12.prod.outlook.com (2603:10b6:208:3ec::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.292.15; Tue, 4 Aug 2026 08:38:13 +0000 Received: from SN1PEPF000252A4.namprd05.prod.outlook.com (2603:10b6:510:23c:cafe::77) by PH8PR20CA0020.outlook.office365.com (2603:10b6:510:23c::21) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.292.15 via Frontend Transport; Tue, 4 Aug 2026 08:38:12 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by SN1PEPF000252A4.mail.protection.outlook.com (10.167.242.11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.292.8 via Frontend Transport; Tue, 4 Aug 2026 08:38:12 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Tue, 4 Aug 2026 01:38:00 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 4 Aug 2026 01:37:59 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Tue, 4 Aug 2026 01:37:51 -0700 From: Tariq Toukan To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , , Paolo Abeni , Sabrina Dubroca CC: Aleksandr Loktionov , Alexei Lazar , Boris Pismenny , Carolina Jubran , Chris Mi , Cosmin Ratiu , Daniel Zahka , Doruk Tan Ozturk , Dragos Tatulea , Gal Pressman , Jacob Keller , Jianbo Liu , Kees Cook , Lama Kayal , Leon Romanovsky , , , , Mark Bloch , "Patrisious Haddad" , Raed Salem , Rahul Rameshbabu , Saeed Mahameed , Shuah Khan , Shuah Khan , Simon Horman , Stanislav Fomichev , Stanislav Fomichev , Tariq Toukan Subject: [PATCH net-next V2 09/13] net/mlx5e: psp: Add an rx_decap steering table Date: Tue, 4 Aug 2026 11:35:31 +0300 Message-ID: <20260804083535.2946459-10-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260804083535.2946459-1-tariqt@nvidia.com> References: <20260804083535.2946459-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A4:EE_|IA1PR12MB6092:EE_ X-MS-Office365-Filtering-Correlation-Id: c219bfaa-4029-4448-3e30-08def203b869 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|82310400026|23010399003|36860700016|6133799003|56012099006|5023799004|11063799006|10067099003|3023799007|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: blh21KIEGXPp6Z/zb3mRGiaiV9ZS14gooyTLqcRDdTkWgbTtYfREZcWzOK+QCbZZdi4iB6j3emREscrxV0CLw1Rs7GyKZqrHlvOUEyD0qQjupy0iLZ9Ee5G5Hm+B7ziZBzD451zhv+cZRjmdQTYniT0F55IVKnYnZNWhB+K4ooCrscVwfxItHhqgRWb9pF1XHLDFj65OoC0aEwnthwjXpc5NybQzSeq6WvLQzgcfnwhS+mwkxAcdWTc623P8p2y4BCgu1wEWBnmb91TpS4JsWocaDqryh6r30dSR8lJv5UQHJ7UlqFdLuLYMcnSBvChQfg77lJ6VaY6RCh/RNUPllzypfTzZHmYCHcayiOE1t45QbuVhn6AbigDkOmJiIzol7X0ftuHOopdqn72fWDy0WttDLV70braFAO6cJLeZD2SAfIPSL+KMG/tSESYc9WaTOuhgWtyDF6LrEeczqhZxri7ZwgYuSo6Xg1IkUqZlTAf9xE6FOGknPoiV2G/UMB5n9ZqFdmDlV4FfHSDKhQHXxItp7L6EOBOFP6ndYFkShkyq/wRYnXs4ZGhOeqc9n8rWmnIKHbRWsCrOx4cNQD6Wgglrog8c3Uafz5+yeZyuyvvcH+sqCHWx6aIunsVMtrab+TwN0+Ea5YFZZO72PAOvEys4VG3y9CF3KUxV2VyX9mB93+8iWUA70oAFLh/COc6Io357KRjw0FEAehVTq4EJng== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(1800799024)(82310400026)(23010399003)(36860700016)(6133799003)(56012099006)(5023799004)(11063799006)(10067099003)(3023799007)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: HmlxC0Yl0EAS8owjXP0yN5HKqO+/bu5kanUSCOHztSpVtQBtiZH8Q1AcJIMs/Mg5Y6DdagKJnVIrGOp8veeTMsBBL0/uBPQeqpBZtAuP+Fx9dlMV/Q/xAG8PblED49Vag9Hh9Y8LbLqnlC+iBlgk/Gqg7jWiqaAjucEgfgf7CvzCRgMt4i+uff1VH3sFzS14CQK8+W6mi4vmPp53Bed9KqN0jQ5PSs6jSuNwjc2lkg44UMKzfzMaIja6YbBqaFjFbXddSDARJj2UrXXpsR79QixG3ue6/MUvAZ3ysL0eSyKoNh8y7yHbohEVG7Znd1lm89x+MUTe6q3P28ztgbuzq/GbIs4gQgfUSnhQ1utYqE/ctc0yTg4boTiojvaO8u+GwQCnv44hsbbKq9n7Uup/2iAKx6fNt7l54+J324TgjsiAHahw9KnuMVqbT9XQyUca X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Aug 2026 08:38:12.4849 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c219bfaa-4029-4448-3e30-08def203b869 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A4.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6092 Content-Type: text/plain; charset="utf-8" From: Cosmin Ratiu Introduce an additional steering table for PSP transport mode decapsulation, containing: - one rule per supported PSP version which does: - transport mode decap (removes UDP+PSP headers and PSP trailer) - recomputes iph->tot_len - recomputes IP checksum - reparses packet headers - copy SPI into reg_b (which ends up as cqe.ft_metadata) - set a decap marker and the PSP version in the flow_tag, so the RX handler can make sense of the packet - default drop rule for unsupported PSP versions (per PSP spec). Packets are forwarded to the previously added rx table, where: - one rule forwards UDP traffic to the UDP default destination. - default rule forwards traffic to the TTC table. The reason is to avoid steering loops. If packets were to be injected into the TTC directly after rx_decap, it may be possible to create a steering loop with RX packets of the form IP|UDP|PSP|UDP|PSP... The rx flow table guarantees that packets go through PSP steering at most once. The steering mode is saved in a new field 'fs.decap_enabled'. Updating the mode is done through accel_psp_fs_rx_reconfigure(), which creates the decap steering table if needed and possible. It then uses an atomic rule update to redirect traffic to the new table. This is now invoked with decap_wanted =3D=3D false. The intention is for failures creating the new table to not block feature reconfig. A message is logged when table creation failed and PSP for HW GRO will not work in that case. Nothing happens on HW without the ability to decapsulate PSP transport. An upcoming patch will add dynamic reconfiguration of PSP steering based on HW GRO. Signed-off-by: Cosmin Ratiu Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/en/fs.h | 1 + .../mellanox/mlx5/core/en_accel/psp.c | 254 +++++++++++++++++- 2 files changed, 253 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/fs.h b/drivers/net/= ethernet/mellanox/mlx5/core/en/fs.h index 4973fb473ff0..a802f80d90be 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/fs.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/fs.h @@ -98,6 +98,7 @@ enum { #if defined(CONFIG_MLX5_EN_PSP) MLX5E_ACCEL_FS_PSP_FT_LEVEL =3D MLX5E_INNER_TTC_FT_LEVEL + 1, MLX5E_ACCEL_FS_PSP_ERR_FT_LEVEL, + MLX5E_ACCEL_FS_PSP_DECAP_FT_LEVEL, MLX5E_ACCEL_FS_PSP_RX_FT_LEVEL, #endif }; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/psp.c b/drive= rs/net/ethernet/mellanox/mlx5/core/en_accel/psp.c index ca5bb60f6d16..37635be7346b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/psp.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/psp.c @@ -23,6 +23,13 @@ enum accel_psp_syndrome { PSP_BAD_TRAILER, }; =20 +static const u8 psp_supported_versions[] =3D { + PSP_VERSION_HDR0_AES_GCM_128, + PSP_VERSION_HDR0_AES_GCM_256, +}; + +#define MLX5E_PSP_NUM_SUPPORTED_VERSIONS ARRAY_SIZE(psp_supported_versions) + struct mlx5e_psp_tx_table { struct mlx5_flow_namespace *ns; struct mlx5_flow_table *ft; @@ -43,6 +50,7 @@ struct mlx5e_psp_rx_decrypt_table { struct mlx5_flow_table *ft; struct mlx5_flow_group *miss_group; struct mlx5_flow_handle *miss_rule; + struct mlx5_modify_hdr *modify_hdr; struct mlx5_flow_handle *rule; }; =20 @@ -53,6 +61,15 @@ struct mlx5e_psp_rx_table { struct mlx5_flow_handle *udp_rules[ACCEL_FS_PSP_NUM_TYPES]; }; =20 +struct mlx5e_psp_rx_decap_table { + struct mlx5_flow_table *ft; + struct mlx5_flow_group *drop_group; + struct mlx5_modify_hdr *modify_hdr; + struct mlx5_pkt_reformat *reformat; + struct mlx5_flow_handle *rule[MLX5E_PSP_NUM_SUPPORTED_VERSIONS]; + struct mlx5_flow_handle *unsupported_rule; +}; + struct mlx5e_psp_fs { struct mlx5_core_dev *mdev; struct mlx5_fc *tx_counter; @@ -64,9 +81,14 @@ struct mlx5e_psp_fs { struct mlx5_fc *rx_auth_fail_counter; struct mlx5_fc *rx_err_counter; struct mlx5_fc *rx_bad_counter; + /* When set, steering is configured to decapsulate PSP (remove UDP+PSP + * headers and PSP trailer) and hand off the SPI in cqe.ft_metadata. + */ + bool decap_enabled; =20 struct mlx5e_psp_rx_decrypt_table decrypt[ACCEL_FS_PSP_NUM_TYPES]; struct mlx5e_psp_rx_check_table check; + struct mlx5e_psp_rx_decap_table decap; struct mlx5e_psp_rx_table rx; }; =20 @@ -111,6 +133,15 @@ static void accel_psp_fs_del_flow_rule(struct mlx5_flo= w_handle **rule) } } =20 +static void accel_psp_fs_dealloc_modify_hdr(struct mlx5_core_dev *dev, + struct mlx5_modify_hdr **modhdr) +{ + if (*modhdr) { + mlx5_modify_header_dealloc(dev, *modhdr); + *modhdr =3D NULL; + } +} + static int accel_psp_fs_create_miss_group(struct mlx5_flow_table *ft, struct mlx5_flow_group **group) { @@ -403,11 +434,161 @@ int accel_psp_fs_rx_check_ft_create(struct mlx5e_psp= _fs *fs, return err; } =20 +static +void accel_psp_fs_rx_decap_ft_destroy(struct mlx5e_psp_fs *fs, + struct mlx5e_psp_rx_decap_table *decap) +{ + int i; + + accel_psp_fs_del_flow_rule(&decap->unsupported_rule); + for (i =3D 0; i < MLX5E_PSP_NUM_SUPPORTED_VERSIONS; i++) + accel_psp_fs_del_flow_rule(&decap->rule[i]); + if (decap->reformat) { + mlx5_packet_reformat_dealloc(fs->mdev, decap->reformat); + decap->reformat =3D NULL; + } + accel_psp_fs_dealloc_modify_hdr(fs->mdev, &decap->modify_hdr); + accel_psp_fs_destroy_flow_group(&decap->drop_group); + accel_psp_fs_destroy_ft(&decap->ft); +} + +static void setup_fte_psp_version(struct mlx5_flow_spec *spec, u8 version) +{ + void *misc_params_6; + + memset(spec, 0, sizeof(*spec)); + spec->match_criteria_enable |=3D MLX5_MATCH_MISC_PARAMETERS_6; + misc_params_6 =3D MLX5_ADDR_OF(fte_match_param, spec->match_criteria, + misc_parameters_6); + MLX5_SET_TO_ONES(fte_match_set_misc6, misc_params_6, psp_version); + misc_params_6 =3D MLX5_ADDR_OF(fte_match_param, spec->match_value, + misc_parameters_6); + MLX5_SET(fte_match_set_misc6, misc_params_6, psp_version, version); +} + +static +int accel_psp_fs_rx_decap_ft_create(struct mlx5e_psp_fs *fs, + struct mlx5e_psp_rx_decap_table *decap) +{ + u8 action[MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)] =3D {}; + struct mlx5_pkt_reformat_params reformat_params =3D {}; + struct mlx5_flow_table_attr ft_attr =3D {}; + struct mlx5_flow_destination dest =3D {}; + struct mlx5_core_dev *mdev =3D fs->mdev; + struct mlx5_pkt_reformat *reformat; + struct mlx5_modify_hdr *modify_hdr; + struct mlx5_flow_handle *rule; + struct mlx5_flow_spec *spec; + int i, err =3D 0; + + spec =3D kvzalloc_obj(*spec); + if (!spec) + return -ENOMEM; + + /* Create FT */ + ft_attr.max_fte =3D 1 + MLX5E_PSP_NUM_SUPPORTED_VERSIONS; + ft_attr.level =3D MLX5E_ACCEL_FS_PSP_DECAP_FT_LEVEL; + ft_attr.prio =3D MLX5E_NIC_PRIO; + ft_attr.autogroup.num_reserved_entries =3D 1; + err =3D accel_psp_fs_create_ft(fs, &ft_attr, &decap->ft); + if (err) { + mlx5_core_err(mdev, "fail to create psp decap rx ft err=3D%d\n", + err); + goto out_spec; + } + + /* Create drop group */ + err =3D accel_psp_fs_create_miss_group(decap->ft, &decap->drop_group); + if (err) { + mlx5_core_err(mdev, + "fail to create psp decap rx drop_group err=3D%d\n", + err); + goto out_err; + } + + /* Add default drop rule */ + err =3D accel_psp_add_drop_rule(decap->ft, NULL, fs->rx_bad_counter, + &decap->unsupported_rule); + if (err) { + mlx5_core_err(mdev, + "fail to create psp decap unsupported versions drop rule err=3D%d= \n", + err); + goto out_err; + } + + /* modify_hdr: copy SPI from REG_C_0 to REG_B */ + MLX5_SET(copy_action_in, action, action_type, MLX5_ACTION_TYPE_COPY); + MLX5_SET(copy_action_in, action, src_field, + MLX5_ACTION_IN_FIELD_METADATA_REG_C_0); + MLX5_SET(copy_action_in, action, src_offset, 0); + MLX5_SET(copy_action_in, action, length, 0); /* 0 =3D 32 bits */ + MLX5_SET(copy_action_in, action, dst_field, + MLX5_ACTION_IN_FIELD_METADATA_REG_B); + MLX5_SET(copy_action_in, action, dst_offset, 0); + + modify_hdr =3D mlx5_modify_header_alloc(mdev, MLX5_FLOW_NAMESPACE_KERNEL, + 1, action); + if (IS_ERR(modify_hdr)) { + err =3D PTR_ERR(modify_hdr); + goto out_err; + } + decap->modify_hdr =3D modify_hdr; + + /* pkt_reformat: decap PSP transport */ + reformat_params.type =3D MLX5_REFORMAT_TYPE_REMOVE_PSP_TRANSPORT; + reformat =3D mlx5_packet_reformat_alloc(mdev, &reformat_params, + MLX5_FLOW_NAMESPACE_KERNEL); + if (IS_ERR(reformat)) { + err =3D PTR_ERR(reformat); + goto out_err; + } + decap->reformat =3D reformat; + + for (i =3D 0; i < MLX5E_PSP_NUM_SUPPORTED_VERSIONS; i++) { + u8 version =3D psp_supported_versions[i]; + struct mlx5_flow_act flow_act =3D {}; + + /* match(version) =3D> decap, copy SPI, fwd to rx FT */ + setup_fte_psp_version(spec, version); + + /* + * Override the flow tag set in the decrypt table with + * the decap PSP marker and version. + */ + spec->flow_context.flags =3D FLOW_CONTEXT_HAS_TAG; + spec->flow_context.flow_tag =3D MLX5E_ACCEL_FLOW_TAG_PROTO_PSP_DECAP | + ((u32)version << MLX5E_ACCEL_FLOW_TAG_PSP_VER_SHIFT); + + flow_act.action =3D MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT | + MLX5_FLOW_CONTEXT_ACTION_MOD_HDR | + MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; + flow_act.pkt_reformat =3D reformat; + flow_act.modify_hdr =3D modify_hdr; + dest.type =3D MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE; + dest.ft =3D fs->rx.ft; + + rule =3D mlx5_add_flow_rules(decap->ft, spec, &flow_act, &dest, 1); + if (IS_ERR(rule)) { + err =3D PTR_ERR(rule); + goto out_err; + } + decap->rule[i] =3D rule; + } + goto out_spec; + +out_err: + accel_psp_fs_rx_decap_ft_destroy(fs, decap); +out_spec: + kvfree(spec); + return err; +} + static void accel_psp_fs_rx_decrypt_ft_destroy(struct mlx5e_psp_fs *fs, struct mlx5e_psp_rx_decrypt_table *decrypt) { accel_psp_fs_del_flow_rule(&decrypt->rule); + accel_psp_fs_dealloc_modify_hdr(fs->mdev, &decrypt->modify_hdr); accel_psp_fs_del_flow_rule(&decrypt->miss_rule); accel_psp_fs_destroy_flow_group(&decrypt->miss_group); accel_psp_fs_destroy_ft(&decrypt->ft); @@ -427,10 +608,12 @@ accel_psp_fs_rx_decrypt_ft_create(struct mlx5e_psp_fs= *fs, struct mlx5e_psp_rx_decrypt_table *decrypt, struct mlx5_flow_destination *default_dest) { + u8 action[MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)] =3D {}; struct mlx5_flow_table_attr ft_attr =3D {}; struct mlx5_flow_destination dest =3D {}; struct mlx5_core_dev *mdev =3D fs->mdev; MLX5_DECLARE_FLOW_ACT(flow_act); + struct mlx5_modify_hdr *modhdr; struct mlx5_flow_handle *rule; struct mlx5_flow_spec *spec; int err =3D 0; @@ -474,6 +657,24 @@ accel_psp_fs_rx_decrypt_ft_create(struct mlx5e_psp_fs = *fs, } decrypt->miss_rule =3D rule; =20 + /* Create modify_hdr to copy SPI to REG_C_0 */ + MLX5_SET(copy_action_in, action, action_type, MLX5_ACTION_TYPE_COPY); + MLX5_SET(copy_action_in, action, src_field, + MLX5_ACTION_IN_FIELD_PSP_HEADER_1); + MLX5_SET(copy_action_in, action, src_offset, 0); + MLX5_SET(copy_action_in, action, length, 0); /* 0 =3D 32 bits */ + MLX5_SET(copy_action_in, action, dst_field, + MLX5_ACTION_IN_FIELD_METADATA_REG_C_0); + MLX5_SET(copy_action_in, action, dst_offset, 0); + + modhdr =3D mlx5_modify_header_alloc(mdev, MLX5_FLOW_NAMESPACE_KERNEL, 1, + action); + if (IS_ERR(modhdr)) { + err =3D PTR_ERR(modhdr); + goto out_err; + } + decrypt->modify_hdr =3D modhdr; + /* Add PSP RX decrypt rule */ setup_fte_udp_psp(spec, PSP_DEFAULT_UDP_PORT); =20 @@ -482,8 +683,10 @@ accel_psp_fs_rx_decrypt_ft_create(struct mlx5e_psp_fs = *fs, spec->flow_context.flow_tag =3D MLX5E_ACCEL_FLOW_TAG_PROTO_PSP; =20 flow_act.crypto.type =3D MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_PSP; - flow_act.action =3D MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | - MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT; + flow_act.action =3D MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT | + MLX5_FLOW_CONTEXT_ACTION_MOD_HDR | + MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; + flow_act.modify_hdr =3D modhdr; dest.type =3D MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE; dest.ft =3D fs->check.ft; rule =3D mlx5_add_flow_rules(decrypt->ft, spec, &flow_act, &dest, 1); @@ -504,6 +707,46 @@ accel_psp_fs_rx_decrypt_ft_create(struct mlx5e_psp_fs = *fs, return err; } =20 +static int accel_psp_fs_rx_reconfigure(struct mlx5e_psp_fs *fs, + bool decap_wanted) +{ + bool decap_supported =3D + MLX5_CAP_FLOWTABLE(fs->mdev, + flow_table_properties_nic_receive.reformat_del_psp_transport); + bool decap_enable =3D decap_wanted && decap_supported; + struct mlx5_flow_destination dest =3D {}; + int err; + + /* Create the decap table if needed. */ + if (decap_enable && !fs->decap.ft) { + err =3D accel_psp_fs_rx_decap_ft_create(fs, &fs->decap); + if (err) { + mlx5_core_warn(fs->mdev, + "Failed to create PSP decapsulation rules (err %d), HW GRO for = PSP unavailable", + err); + decap_enable =3D false; + } + } + if (decap_enable =3D=3D fs->decap_enabled) + return 0; + + /* Redirect traffic to the correct table. */ + dest.type =3D MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE; + dest.ft =3D decap_enable ? fs->decap.ft : fs->rx.ft; + err =3D mlx5_modify_rule_destination(fs->check.rule, &dest, NULL); + if (err) + goto out_destroy_ft; + + fs->decap_enabled =3D decap_enable; + + return 0; + +out_destroy_ft: + if (decap_enable) + accel_psp_fs_rx_decap_ft_destroy(fs, &fs->decap); + return err; +} + static void accel_psp_fs_rx_destroy(struct mlx5e_psp_fs *fs) { struct mlx5_ttc_table *ttc =3D mlx5e_fs_get_ttc(fs->fs, false); @@ -516,6 +759,7 @@ static void accel_psp_fs_rx_destroy(struct mlx5e_psp_fs= *fs) accel_psp_fs_rx_decrypt_ft_destroy(fs, &fs->decrypt[i]); } accel_psp_fs_rx_check_ft_destroy(&fs->check); + accel_psp_fs_rx_decap_ft_destroy(fs, &fs->decap); accel_psp_fs_rx_ft_destroy(&fs->rx); if (tc_blocked) mlx5e_accel_unblock_tc_offload(fs->mdev); @@ -563,6 +807,12 @@ static int accel_psp_fs_rx_create(struct mlx5e_psp_fs = *fs, mlx5_ttc_fwd_dest(ttc, fs_psp2tt(i), &dest); } =20 + err =3D accel_psp_fs_rx_reconfigure(fs, false); + if (err) { + NL_SET_ERR_MSG(extack, "Failed RX steering config for HW GRO"); + goto err_decrypt_ft; + } + return 0; =20 err_decrypt_ft: --=20 2.44.0 From nobody Fri Oct 2 06:58:27 2026 Received: from CH5PR02CU005.outbound.protection.outlook.com (mail-northcentralusazon11012011.outbound.protection.outlook.com [40.107.200.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D9D5A43BDA4; Tue, 4 Aug 2026 08:38:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.200.11 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785832714; cv=fail; b=MIGhBGS/joXkDCrBAGlzzv01tOK0+f4vKB0DbNQ9UYqfNJBPqYI95s5V0ezEUNfBpEwAbu12lMtiQJfRxJIqM0Lmvv0x8GSwBANJnUujhBJhB2DyiAHFisoHefDi7lDddtWNu9aTT+B3QtRmMNq9dxDXTr4rUr4Alt2tyiTFeXQ= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785832714; c=relaxed/simple; bh=bfQNML775xZLqEJn4AMYO8JSu4/oE1+GqAuSjn22hSY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mWGXv7e77KD6/57nMYwUrpVcszJCeckeZWP1nHjOIIszLZx2YgoKA7VOG48C8tEJYeFkKqotdu7iVWBL2+OVE5tWL63+dTaoG2K61Xc/2UR46Aish7ifzWYSy/AqZklFjgp8Wo5woJJrELuj2eITix/abwCQpDmj78x3qS7rchg= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=md36TKyt; arc=fail smtp.client-ip=40.107.200.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="md36TKyt" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=nnn/5omlmjBV1dfTAfaWBpfv6budyD1UBZzYVNLINAwq7ALumn1rwYlX5nh/pNMt9Za8HymBkySC9R2s228WWUPSuvYWpDCDW4yd4Kut9Jzo0J19y6lUgg41LUZlCBT7nS6eWuw1urbs+Ghq64PijrYROd11hoY11uC5oc48CTcudc5bmZTxpwQRIed/xgOHRnYxTrYmh4oN5P6chz7+0xz4wp5sukE8ytYkIdXKYfdtVEBOvXMhFkTgf2Wm9/tMGSwhNCU4ltpCo8TvEaxSZHHB/Ojbe2REvFmr/HNno+qY3iEAcCSH0T+uCiawVniqlmzMpH1hCSmRGlDxlAJ1dA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=7FfU6jR0F/JKdkyoTFATa1lhB9OBmyV3xWJnz4QGDs0=; b=RgDXEyiaGUUkBmIQJgV2OcU0prXzx2UT0UzGIxENLawrXDMXoU8p7LAA21/P/rzTj6k5l21GTbtoTDDCXZiqCbi9RnVDKMms7FzBCFUqh+2tUBoVBj8NFZiNM7B1GsdeM4LrnZY0C/P36aWrFBNapluTc/eaQeEUKBk0vS2CiZLVoGGEUQj7Ee+eCEUxOOdq4zpmn/5vJRrNjSkjj2aMIm1RU+cZ1/GU4VVcCLC/3efjZEnlUfVWqVd1/ivzDA4r/oF20UZbj4LRBErBgodmsYe6elaP0HdZE666Wuw0nnfGsO2Rg9Oc2nDg6OloRbZow/lRkJqkBnlerMuzuCjqrA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=lunn.ch smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=7FfU6jR0F/JKdkyoTFATa1lhB9OBmyV3xWJnz4QGDs0=; b=md36TKytpaDuvIzyhY/LReAjpywreudcjkR1dTsn4uhtXLNWnMgzlQKgQ2QcJNEtxCoxjG4t/WdgwzqWrjF9ve0+akjK57SMOTdl9tGndFsqu0LqFvNOzTRy/fXV3y2/QrEvdvRHjxvhIA6nFivMXn8TSYtFtcOOwv2Ib02waQsqHl6QVwQKEGKmBm0Eogo/qJBexfvco1zOkjKdfXdQA5PGkxMIj80xEbCvNe6EG/4FFH/tyTHCGy2KS5mYKAQpEDGPdsPHXnT0EA3zsUlFGYGyPKQA0zwlQ0i2JjeWOMGDK95zrJ4H79dNMnuRmVEGVwW76TUDf2AXNMLNuqgwHA== Received: from SA9PR10CA0016.namprd10.prod.outlook.com (2603:10b6:806:a7::21) by BY5PR12MB4097.namprd12.prod.outlook.com (2603:10b6:a03:213::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.292.15; Tue, 4 Aug 2026 08:38:24 +0000 Received: from SN1PEPF000252A2.namprd05.prod.outlook.com (2603:10b6:806:a7:cafe::27) by SA9PR10CA0016.outlook.office365.com (2603:10b6:806:a7::21) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.270.17 via Frontend Transport; Tue, 4 Aug 2026 08:38:24 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by SN1PEPF000252A2.mail.protection.outlook.com (10.167.242.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.292.8 via Frontend Transport; Tue, 4 Aug 2026 08:38:23 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Tue, 4 Aug 2026 01:38:08 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 4 Aug 2026 01:38:07 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Tue, 4 Aug 2026 01:38:00 -0700 From: Tariq Toukan To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , , Paolo Abeni , Sabrina Dubroca CC: Aleksandr Loktionov , Alexei Lazar , Boris Pismenny , Carolina Jubran , Chris Mi , Cosmin Ratiu , Daniel Zahka , Doruk Tan Ozturk , Dragos Tatulea , Gal Pressman , Jacob Keller , Jianbo Liu , Kees Cook , Lama Kayal , Leon Romanovsky , , , , Mark Bloch , "Patrisious Haddad" , Raed Salem , Rahul Rameshbabu , Saeed Mahameed , Shuah Khan , Shuah Khan , Simon Horman , Stanislav Fomichev , Stanislav Fomichev , Tariq Toukan Subject: [PATCH net-next V2 10/13] net/mlx5e: shampo: Flush session on PSP mismatch Date: Tue, 4 Aug 2026 11:35:32 +0300 Message-ID: <20260804083535.2946459-11-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260804083535.2946459-1-tariqt@nvidia.com> References: <20260804083535.2946459-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A2:EE_|BY5PR12MB4097:EE_ X-MS-Office365-Filtering-Correlation-Id: a1bfcaa8-1486-47c2-cd9f-08def203bf0c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|82310400026|1800799024|36860700016|23010399003|3023799007|18002099003|22082099003|11063799006|56012099006|10067099003; X-Microsoft-Antispam-Message-Info: gorABt3QXyUi+1MLCJi61KD46cdzItwBD+qdcWwW0vZ4BSQX3c/F4khrLvYznW8H92bOUDpx9rHm72sXbbVG1vp+7KWHfW5+eUuE8V8QL9ydm4iumAGErGLl6egQKt4WaVWmhNmnMUI64GMA1kVPObcIfrM8wbrOKv8LAtZlo837r61G3Km95+h0iRKQZ49sPHlPjva67MsOlDmCN+ckm5KsDlmIJr8b36oYv4/9RBkeVIMhaHXI/qfF4n0ZCxKvOSoKHkRdBbSPnIrt+NwyIv75To7fRnpiCanp9TpIVzN27Fk7bPhg7inoIiolBOEc3mwVZT9rHcR6liL0t1gWKAAsTRYX/+kEO16RR7OMCaPumjzoQSdOgpyeV3U51RheaCipd1711ptLmDJTm6Ksis8tIytvgDvZmELzzhOPK8q6cnmcm1Y184HVJG7ZeunL1R/deZaX9l6bINAPJrwwNisN3YTzvWORl46m1+jtEayAPycv47kYj7nwXrsHj3veyEp1pAUZJ3dqWcU1rdwhK0vWeniUhj2lI0HIdywyDLNAHeVRSnWnStJR4ziLffB16/JNHdKqsIHpb017cBBsXBwuL9GlFoWwMVT4+s+YpHvG0+BbOVa5VVOjIsqroPerf6SUNUgzr2GKzL58FsXHaeJEeIx1mOdvFVXBeZmkxfYW8ZYKPHu9uxsW3kC1zGDFCFn82cESYMIwQuQS6+XQTA== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(82310400026)(1800799024)(36860700016)(23010399003)(3023799007)(18002099003)(22082099003)(11063799006)(56012099006)(10067099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: GyEqlHqpzwVixXPrdrAj0hebgTaWeyQgVAeV1SDIMwyabpmoC1BfoVfaRK+I1lT8xFFtrH4+edGiucAuf3S+LiPziaBe2j3MMq2eub3hD6yYKL3ii73H4aag+UBTkKYf5laUnveN/YF/jnWB8ysFly4aK3QQ5rZ1ALpYG99uZNJHeRz7+D+dr6ZllMr8aq+4N6mFxQKtdj/IIoBMlCymPnJ1d6fiGnhcrrBDZQ2JXeAlSC/uDlHV8RF5ZYVLwaL4+hdYBJL3HYKJ6CeR0Yw0k3vcpkFR/6sh7sgoPyGZF86QLLss855qQ2Zui2Mcr3Fp2reuqfu4BI7TXhIZaC1yYSj9BJwxbkuzuGPE/nuyZ0PVjcDm/rB4cUCMfzzs8ocC0RHQFL8dTb+/NmYsZ/kaonsGvroZhKd2CThplfNQ49q9reIs/v92kKbyGdPGAaH8 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Aug 2026 08:38:23.5953 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a1bfcaa8-1486-47c2-cd9f-08def203bf0c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4097 Content-Type: text/plain; charset="utf-8" From: Cosmin Ratiu Flush SHAMPO session on PSP status change (no PSP -> PSP or vice-versa) or on SPI/version mismatch. HW aggregates by 5-tuple but is unaware of PSP fields, so sessions must be terminated when security parameters change to avoid mixing packets from different PSP associations. The session is also forcefully flushed if non-decapsulated packets are received. This could happen if, for example, the decap table could not be created so HW GRO is active but there's no decapsulation. Signed-off-by: Cosmin Ratiu Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/en_rx.c | 32 +++++++++++++++++-- 1 file changed, 30 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c b/drivers/net/= ethernet/mellanox/mlx5/core/en_rx.c index fb7110b1b683..c7eaab3f7967 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c @@ -2221,6 +2221,33 @@ static bool mlx5e_hw_gro_skb_has_enough_space(struct= sk_buff *skb, return page_size * nr_frags + data_bcnt <=3D GRO_LEGACY_MAX_SIZE; } =20 +static bool mlx5e_hw_gro_psp_match(struct sk_buff *skb, struct mlx5_cqe64 = *cqe) +{ +#ifdef CONFIG_MLX5_EN_PSP + struct psp_skb_ext *pse =3D skb_ext_find(skb, SKB_EXT_PSP); + bool is_psp =3D mlx5e_psp_is_rx_flow(cqe); + + if (likely(!is_psp && !pse)) + return true; + + /* No match on PSP status change (no crypto -> crypto or vice-versa). */ + if (unlikely(is_psp !=3D !!pse)) + return false; + + /* SPI and version are only available in CQE metadata for decap flows. + * Non-decap PSP cannot be matched here, force a flush. + */ + if (unlikely(!mlx5e_psp_is_decap(cqe))) + return false; + + /* No match on security parameters change. */ + return pse->spi =3D=3D mlx5e_psp_get_spi(cqe) && + pse->version =3D=3D mlx5e_psp_get_version(cqe); +#else + return true; +#endif +} + static void mlx5e_handle_rx_cqe_mpwrq_shampo(struct mlx5e_rq *rq, struct m= lx5_cqe64 *cqe) { u16 data_bcnt =3D mpwrq_get_cqe_byte_cnt(cqe) - cqe->shampo.header_size; @@ -2258,8 +2285,9 @@ static void mlx5e_handle_rx_cqe_mpwrq_shampo(struct m= lx5e_rq *rq, struct mlx5_cq data_offset =3D wqe_offset & (page_size - 1); page_idx =3D wqe_offset >> rq->mpwqe.page_shift; if (*skb && - !(match && mlx5e_hw_gro_skb_has_enough_space(*skb, data_bcnt, - page_size))) { + !(match && + mlx5e_hw_gro_skb_has_enough_space(*skb, data_bcnt, page_size) && + mlx5e_hw_gro_psp_match(*skb, cqe))) { match =3D false; mlx5e_shampo_flush_skb(rq, cqe, match); } --=20 2.44.0 From nobody Fri Oct 2 06:58:27 2026 Received: from MW6PR02CU001.outbound.protection.outlook.com (mail-westus2azon11012026.outbound.protection.outlook.com [52.101.48.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C43AD442B07; Tue, 4 Aug 2026 08:38:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.48.26 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785832721; cv=fail; b=MDWQ7DIqSAsxwcqOIvWOmknOyeUjhXvFT+izgCdkttuMHNA0QPJ1aX5fJPERIC4x32lzEGDIqZvKE2FV3LbDL10ztWN7k9HRzSOlJl6RasnM6I/svk0tB6HwJwv9VMwDK2v2/R0IOfawYaoQ9qojvo/8qOGGj66+E1PqrDsOFuQ= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785832721; c=relaxed/simple; bh=ri0NZ/oP0WLmD58TRrAZQL2y84HAeMjOXAvqLeScg4U=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=MJXmvzNbCh2Wwaka+ksMGjApaFK8fyL1ul0BA7EMozMWrcKQo2N7qNveK+se2hI0i3x08bqaw5YQL22AeU+ECPbted2QdFVax9qyUSMtrwuXQ29QGel8tGbInrsi72EeUGcWfy2j1SxuySLCaBfMqwspO4Djcai/K3yis26wlQs= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=dVbxQbSj; arc=fail smtp.client-ip=52.101.48.26 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="dVbxQbSj" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=VopCDr9vmU2dfN2BsLRFAlLqvlzr5vAep+FzBEhaL9mV/xUEQn/nKWOef6rKLC3Vwnb3YQELaz75wB/yARLyVa34/LTagRkBGKV9HKjhU3zrl4zKGg9rLzBmstPEw0mPk3ui+koUtSs7sffcvCHcYcD/kin8guAHjlt8zVREPHkVQIRsVe8h9o9GMa/R4VT6nzayHbmXFIRkhz/t2lJtXLMo+JWuT9O6tiEkA39BfWy4Q+bB5RKM4h4tn5Sx+q+BN9lGGcI7UbS2QtDmYB+0TjT/BsM554whkCeFysU4ySfe9ch8mwScBGmi0Ws7t7qnPoU0cEYjY72L5a8vg64N+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=VBACNLZYKBPceRl2Mwzb9g0F3IhZY/Q3yRssXECEbQU=; b=oK5I29OIOEuyqYCiXShqL8beZzuSBQDhjilKE/GXKWbiPNVSO9bel9ijJPzvjgJb3xQ9HfjyQFsYyylZ3YTf/Ct1sD7eu0wWV+b4cwHNFbsLU0QeTAVLIFdDPN8VBGrLieI0jLHjLfca6CWMKyHN42U+pgmuF9B/Cwtcsdw8DRGXNJ8IKnU8QQWnJJ9xnLm9pL4waga2WeuiUICxH/uD1SWA4plcWpOM8wNugSvzInSJ8lo5blDw1jTJow2uMlGGL4ic4m4vy47fXCx5diH5YE7qwWejdQqWuTn52mC0uw7ZAp1P5Y6jeCr+UR80Fkv2ywu0+f+gsHlYgZt5GcJOWg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=lunn.ch smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=VBACNLZYKBPceRl2Mwzb9g0F3IhZY/Q3yRssXECEbQU=; b=dVbxQbSjyWQQTe8sb87DydigbvMzetI8wnVt43yxWnzz3Hhqu5cBITcPfxz32IcKTsGf6Ef81Yk9/hIn/lZ7SybIhjreBbjYja4vjAMkh5o+LgNFLVHbSXsONbY8FXgyGPMOOgHIV/WCb/647g4Oum2UiAZXg5dmtH+CYiApkOlK2m5Ik5MfGDzJwUbU1Ab6VN7xuVLjcutbkJ5jLJ6UjoAWYvcMzL2K8c6Jp9i/8hsMBBR7viVGdewEyW8Juhwpa+kXwDa7WRmjqbfx3d49UtxEwNV5yqVybitLO3eCE+qqOHXG23adcEXT+mUjDiiMND8G6cMLgfyo73rG/9Bmhg== Received: from PH8PR20CA0008.namprd20.prod.outlook.com (2603:10b6:510:23c::18) by SJ5PPF01781787B.namprd12.prod.outlook.com (2603:10b6:a0f:fc02::986) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.292.15; Tue, 4 Aug 2026 08:38:29 +0000 Received: from SN1PEPF000252A4.namprd05.prod.outlook.com (2603:10b6:510:23c:cafe::11) by PH8PR20CA0008.outlook.office365.com (2603:10b6:510:23c::18) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.292.15 via Frontend Transport; Tue, 4 Aug 2026 08:38:29 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by SN1PEPF000252A4.mail.protection.outlook.com (10.167.242.11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.292.8 via Frontend Transport; Tue, 4 Aug 2026 08:38:29 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Tue, 4 Aug 2026 01:38:16 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 4 Aug 2026 01:38:15 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Tue, 4 Aug 2026 01:38:08 -0700 From: Tariq Toukan To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , , Paolo Abeni , Sabrina Dubroca CC: Aleksandr Loktionov , Alexei Lazar , Boris Pismenny , Carolina Jubran , Chris Mi , Cosmin Ratiu , Daniel Zahka , Doruk Tan Ozturk , Dragos Tatulea , Gal Pressman , Jacob Keller , Jianbo Liu , Kees Cook , Lama Kayal , Leon Romanovsky , , , , Mark Bloch , "Patrisious Haddad" , Raed Salem , Rahul Rameshbabu , Saeed Mahameed , Shuah Khan , Shuah Khan , Simon Horman , Stanislav Fomichev , Stanislav Fomichev , Tariq Toukan Subject: [PATCH net-next V2 11/13] net/mlx5e: psp: Dynamically reconfigure based on SHAMPO mode Date: Tue, 4 Aug 2026 11:35:33 +0300 Message-ID: <20260804083535.2946459-12-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260804083535.2946459-1-tariqt@nvidia.com> References: <20260804083535.2946459-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A4:EE_|SJ5PPF01781787B:EE_ X-MS-Office365-Filtering-Correlation-Id: fe98bdf3-2aca-4793-0b23-08def203c278 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|82310400026|36860700016|23010399003|376014|1800799024|56012099006|11063799006|10067099003|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: 5lHatwGlpvIdEDZgQiPRar4B+wQ/LEY5y05U+C7hH7c4t72H7Al8fnGVYYJ2QRSjBL8qsITXx5RgzdXo+zi3MyiVMiGi8TCufsM5GQLzZrCKTthNNJMzeUT0MIJww3oJM986B39RTunimyfgLmb7/kXspf85RYGPJkIet8JTs5PuBfyfELMGLKKyzb/rfEdR7QxWrd8yMjI+ci0In+n07Ut4GQVHsN9RRL87x5X/wPfbqTUUKX6oAZMiJKYPPl6+9dN8FmmBHrZzKPctP23hDkGg6AFO6iuEX5LCIUJAdhcz1dNKoh7M//VOvBpTIKwss+azfwJ1Gi+LxgwTBb/oO+ban9nU+jeAeCw5LzqI/tFdeHL/uVpiqyORW+inWqpurE9eHmDsiSp/KAXPzsaXB9rEjvBqpqlRNJLn9HpUQ8keNqqFG0Zgp0PpEJXloTdvK35q+K+m+RUMMQiO50xGR2lO46MabuCLtPrT8ejMng5uC96pAkQ2yfGam4J4xDn4Og+D4pO9pda2Dl9DsfHmdtICMsMZqNfuPh2Te3/dOPhbfGwlJeXtmW7pfyvCzCQoJFQB1111oirS4IOdYoZMODCLOnB204lqKI0Kc8ChweMGyPe9mADhyMTVS8e3KlCyYe/u0o3LLVesn7vz6ZSf6fTZSHOz1a0GnHf6ulysnxm78KaZlx8xScNb1V+8m3hOuLm8T0q/HXt3ZYB9nAwpLw== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(82310400026)(36860700016)(23010399003)(376014)(1800799024)(56012099006)(11063799006)(10067099003)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: VumWMBx0z3wZZLiHzyh4PewhPtZsL0Ap1JgOqGY1ALcPUMRJfGgbs/rYANs5K85VIpAtU7zOOZO0mDngTiCl9mWzOzLnPdpVbrkB2hvjBOCDdZ4UBSZmDaKGj7rftR4L9CBxan36zThGm2JAEfMfqzxA/UI6spCLm2MWfHV8UztwAbAYC/Wee05hHJPfbgyVxE69X1fuKz1I980EwGY32FwwGTK0CjCni6EJ0TpLDRkb5yXOK3ikVxKLM4yXPdOj7AWriuuHA0uAA1jE3bo2vq6vI2r95K3z1g2fCxIUM2M5/SC6IBa5lZBfKaxIk/3mPdbxqeL79m8ejXPmwKVBsAaqKrud7pjUIeJ1UGKzuT/vgztIGUJq6s+hmOhntb1qEeVCt/3/krYpw/9qSP3rPdRCTbp4Prjz5XW+3HUBtLKW6DEUZoxcpF+yvp4bt+tf X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Aug 2026 08:38:29.3300 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fe98bdf3-2aca-4793-0b23-08def203c278 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A4.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ5PPF01781787B Content-Type: text/plain; charset="utf-8" From: Cosmin Ratiu Add an mlx5e_update_nic_rx() -> mlx5e_psp_update_rx() hook. This allows PSP steering to reconfigure when netdev features change. When this signal is received, toggle PSP between standard and decap modes when SHAMPO mode changes, optionally creating the decap steering table. The toggling of traffic is atomic (a single steering rule update), so no packets should get eaten/lost. It is probable though that the rxhash will change, and decapsulated packets will be received by a different core than before. Established PSP connections receiving traffic might experience reordering/retransmits as a result. Also enable decap when configuring the device if the mode indicates it. Signed-off-by: Cosmin Ratiu Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/en_accel/en_accel.h | 9 ++++++++ .../mellanox/mlx5/core/en_accel/psp.c | 23 +++++++++++++++++-- .../mellanox/mlx5/core/en_accel/psp.h | 2 ++ .../net/ethernet/mellanox/mlx5/core/en_main.c | 8 ++++++- 4 files changed, 39 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h b/= drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h index 8a2ea7616440..a0bb19cc956d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h @@ -251,6 +251,15 @@ static inline void mlx5e_accel_cleanup_rx(struct mlx5e= _priv *priv) mlx5_accel_psp_fs_cleanup_rx_tables(priv); } =20 +static inline int mlx5e_accel_update_rx(struct mlx5e_priv *priv) +{ +#ifdef CONFIG_MLX5_EN_PSP + return mlx5e_psp_update_rx(priv); +#else + return 0; +#endif +} + static inline int mlx5e_accel_init_tx(struct mlx5e_priv *priv) { return mlx5e_ktls_init_tx(priv); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/psp.c b/drive= rs/net/ethernet/mellanox/mlx5/core/en_accel/psp.c index 37635be7346b..ad8dbd8c2f27 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/psp.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/psp.c @@ -92,6 +92,12 @@ struct mlx5e_psp_fs { struct mlx5e_psp_rx_table rx; }; =20 +static bool shampo_enabled(struct mlx5e_priv *priv) +{ + return priv->channels.params.packet_merge.type =3D=3D + MLX5E_PACKET_MERGE_SHAMPO; +} + /* PSP RX flow steering */ static enum mlx5_traffic_types fs_psp2tt(enum accel_fs_psp_type i) { @@ -766,6 +772,7 @@ static void accel_psp_fs_rx_destroy(struct mlx5e_psp_fs= *fs) } =20 static int accel_psp_fs_rx_create(struct mlx5e_psp_fs *fs, + bool decap_enable, struct netlink_ext_ack *extack) { struct mlx5_ttc_table *ttc =3D mlx5e_fs_get_ttc(fs->fs, false); @@ -807,7 +814,7 @@ static int accel_psp_fs_rx_create(struct mlx5e_psp_fs *= fs, mlx5_ttc_fwd_dest(ttc, fs_psp2tt(i), &dest); } =20 - err =3D accel_psp_fs_rx_reconfigure(fs, false); + err =3D accel_psp_fs_rx_reconfigure(fs, decap_enable); if (err) { NL_SET_ERR_MSG(extack, "Failed RX steering config for HW GRO"); goto err_decrypt_ft; @@ -1081,7 +1088,8 @@ static int accel_psp_fs_create(struct mlx5e_priv *pri= v, { int err; =20 - err =3D accel_psp_fs_rx_create(priv->psp->fs, extack); + err =3D accel_psp_fs_rx_create(priv->psp->fs, shampo_enabled(priv), + extack); if (err) return err; =20 @@ -1358,3 +1366,14 @@ void mlx5e_psp_cleanup(struct mlx5e_priv *priv) priv->psp =3D NULL; kfree(psp); } + +int mlx5e_psp_update_rx(struct mlx5e_priv *priv) +{ + struct mlx5e_psp *psp =3D priv->psp; + + netdev_assert_locked(priv->netdev); + if (!psp || !psp->fs->check.ft) + return 0; + + return accel_psp_fs_rx_reconfigure(psp->fs, shampo_enabled(priv)); +} diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/psp.h b/drive= rs/net/ethernet/mellanox/mlx5/core/en_accel/psp.h index 3f441e7dd55a..76f6c69de0e9 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/psp.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/psp.h @@ -49,6 +49,7 @@ int mlx5e_psp_register(struct mlx5e_priv *priv); void mlx5e_psp_unregister(struct mlx5e_priv *priv); int mlx5e_psp_init(struct mlx5e_priv *priv); void mlx5e_psp_cleanup(struct mlx5e_priv *priv); +int mlx5e_psp_update_rx(struct mlx5e_priv *priv); #else static inline void mlx5_accel_psp_fs_cleanup_rx_tables(struct mlx5e_priv *= priv) { } static inline void mlx5_accel_psp_fs_cleanup_tx_tables(struct mlx5e_priv *= priv) { } @@ -61,5 +62,6 @@ static inline int mlx5e_psp_register(struct mlx5e_priv *p= riv) { return 0; } static inline void mlx5e_psp_unregister(struct mlx5e_priv *priv) { } static inline int mlx5e_psp_init(struct mlx5e_priv *priv) { return 0; } static inline void mlx5e_psp_cleanup(struct mlx5e_priv *priv) { } +static inline int mlx5e_psp_update_rx(struct mlx5e_priv *priv) { return 0;= } #endif /* CONFIG_MLX5_EN_PSP */ #endif /* __MLX5E_ACCEL_PSP_H__ */ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index 3b9d42c7e9c2..3c6ef500d0fb 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -6286,7 +6286,13 @@ static void mlx5e_nic_disable(struct mlx5e_priv *pri= v) =20 static int mlx5e_update_nic_rx(struct mlx5e_priv *priv) { - return mlx5e_refresh_tirs(priv->mdev, false, false); + int err; + + err =3D mlx5e_refresh_tirs(priv->mdev, false, false); + if (err) + return err; + + return mlx5e_accel_update_rx(priv); } =20 static const struct mlx5e_profile mlx5e_nic_profile =3D { --=20 2.44.0 From nobody Fri Oct 2 06:58:27 2026 Received: from CO1PR03CU002.outbound.protection.outlook.com (mail-westus2azon11010059.outbound.protection.outlook.com [52.101.46.59]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6548F442FC7; Tue, 4 Aug 2026 08:38:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.46.59 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785832725; cv=fail; b=QqRGHRH8jZAkudDRdJEuuLyakpLoIFkGdVm917SY5OoEJveBd6jz0R4lnoEHq7hQ1lyLiHIeGfIxxhEksuerM84ou54nt/Vo2m9bepBHh0F36aYk6Qm7geGc/Ao9bhpqMPNOG+7Wet9qZsRlzQtVFJH7fIa9IaR7PZyaVu3G4h8= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785832725; c=relaxed/simple; bh=Om/YphdYx0xEwrwDgR3s0UyhvuNAAcT/GzEd9IlnAn4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ERc2wSBVC3MWhITUWbYFeKhoQRZO0bMD7egOdMUyyZqn1CKIj/rou6z5GM3pHR+r6X8ylCdPavzBDQly8Z/P07wsoNuRUz0alzTjjIQ7ab2CE92inqc1sM6V+PA+NN8qSkn4s7+LjYejvbZzo50IESt2v30P/rWasfkLU2jigmk= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=tw99U7vc; arc=fail smtp.client-ip=52.101.46.59 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="tw99U7vc" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=acm7Bo758xCNdmC1ApmPfi+VyXj+XrPlS68Z6Bf9jU8GEbOs5v8PgEw8Kcg2pkP/1e6BQkX2ccBo6iC9eLfclfvD8lOXPgxY2bKqvJbJpqcXxf+EqrMV0gJ3vpOQaKgVb5BOfkyZtl7k6uOK+zIzRKSjlztTaQhZrszPbEL7ksuhvCKfKeIGbEfFXy752eBt3MHwH9eW66pixdkTeXo5M+H83/LvpJIFot5lSl5nujnQUm88jpWbSDhAP3xzzxl7+n/ZBcoPiHzMEhqpChNtoZxgLcOHVsqUn2A2aoxodQ9/9fv45ZB5AmZuM7KEoO72hYfANGXC1s9CShNoyl4lqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=h8aLoDLh/xjeos60Zcl7Q6zQLEhbNz0l8bfyG81LOIk=; b=eyH/CzU+fme4mVBIY6UV0kxWNGpohxDkSMJIxHPb2tIe2DLL2lvkz9SIE99GjaEbZPkkn0uvO5icFVlvxTngQE1l3jsR5Sd1mxpm6y1wGGTtTeFvfp77ol2y/JMZFL8efUAuXmKAf/oCwFrGaAHdilMUBk8Ru8fE48QoOxgeUlEZWJgPanr+O0Yu+LyXpdoPBprgw9ZDaezGqAapUnQErmPLvC0qLnJUrKEhgjkov5tVLvgcY8MwELWcW+GF0XOsnAEWg0PiA+NPvzkG31Q1h6Ylh24ez6hE4Adum556K1x3cfCNofwW80Cjnwi+dV8B3SHWaUqWkWYCMGGmibwDsQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=lunn.ch smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=h8aLoDLh/xjeos60Zcl7Q6zQLEhbNz0l8bfyG81LOIk=; b=tw99U7vcQz+hDZKZ8T1vUIshIlGgStx77WJ6bZXW5HI70XcELgVun1jT950+kZne0CIbsy0uttxa7JoNzTYQ/XB4HhJQWoz7BzdXQHd+WkpL74dLIKf4Y4+z1VBARb+QdoQNDMNI37y52Ki2W4XDqJWCmg0xbg4pi61K9DyHXl/qhgaoQP/nV029TbffF/uStxY75r4X46mbOrhRP0badX6XAWmVitKvfp3VPAjN2GhD6Wt+46F3TxM4f1bvNMwTXY3tWpFZkUZIcGIFo+MBRcD5hBVAtSat492OEoUydjNGiDBO5jEJWYq1/5CvL/Ghi5pqHFRw3UcENt4tLh3ogg== Received: from PH0P220CA0013.NAMP220.PROD.OUTLOOK.COM (2603:10b6:510:d3::11) by CY3PR12MB9555.namprd12.prod.outlook.com (2603:10b6:930:10a::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.270.18; Tue, 4 Aug 2026 08:38:38 +0000 Received: from SN1PEPF000252A0.namprd05.prod.outlook.com (2603:10b6:510:d3::4) by PH0P220CA0013.outlook.office365.com (2603:10b6:510:d3::11) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.292.16 via Frontend Transport; Tue, 4 Aug 2026 08:38:38 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by SN1PEPF000252A0.mail.protection.outlook.com (10.167.242.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.292.8 via Frontend Transport; Tue, 4 Aug 2026 08:38:37 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Tue, 4 Aug 2026 01:38:24 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 4 Aug 2026 01:38:24 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Tue, 4 Aug 2026 01:38:16 -0700 From: Tariq Toukan To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , , Paolo Abeni , Sabrina Dubroca CC: Aleksandr Loktionov , Alexei Lazar , Boris Pismenny , Carolina Jubran , Chris Mi , Cosmin Ratiu , Daniel Zahka , Doruk Tan Ozturk , Dragos Tatulea , Gal Pressman , Jacob Keller , Jianbo Liu , Kees Cook , Lama Kayal , Leon Romanovsky , , , , Mark Bloch , "Patrisious Haddad" , Raed Salem , Rahul Rameshbabu , Saeed Mahameed , Shuah Khan , Shuah Khan , Simon Horman , Stanislav Fomichev , Stanislav Fomichev , Tariq Toukan Subject: [PATCH net-next V2 12/13] selftests: drv-net: psp: Fix responder parsing Date: Tue, 4 Aug 2026 11:35:34 +0300 Message-ID: <20260804083535.2946459-13-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260804083535.2946459-1-tariqt@nvidia.com> References: <20260804083535.2946459-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A0:EE_|CY3PR12MB9555:EE_ X-MS-Office365-Filtering-Correlation-Id: d9323689-dd8c-4d14-b5f9-08def203c796 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|23010399003|376014|7416014|1800799024|6133799003|56012099006|11063799006|10067099003|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: LgIj3tJeLTmHicdQzHZGQK3TkjY4fKXvq6yOCoflSExb9uIPu5h7vz6BeZdlEI4bFJfZoanfTPAWIJGkIe0buUvWDlBt9UradYrYXHQVytLfsW6HtaJDw9/PdGU/6QgwKs/K5W/ZfzEDT92h5HIFYXW6621lqp8XEHjXw6UJmzvytlDlFj2pdt/2Tu9mzTvTskNzPjowT9sslfiBNgYvhwwsrfS0kuZcTt8A3E5w5nf27cy5mWeoju8TAxWm3BOvmY1xdcirFYvwnJW7Sie87/zshUv3gZhgI248NbxOuHZqYSuvd5++0Ti8KJY7dypN76c5/6GPlvsQy20S+7SLRRiPl7jrH5+7vcscV8MOF0Q+BYdX8E4JjTRxDAA6n6sK9Url3LinBqDnKpXJ7E+E+OW85CKcng71gDuaNY4jrim2y6zi//FNvvu41NGpQmORur76Co3XEJNdqr6c2ZXHGGxWoRhi1DxQ8yBCsTFdQv4UW2tUtkwEn3zqdX9UkoW01KRw+MdPBsl5/yqP4Ami8EC7qffNzm/YamUuYu4MCxkis9BVe7FDnpZ10VtILvj/2XVORfIcpRcqu86+AtjbfKLRlrIyLHqBZHjw6gcavBQbsazxXtAVjUQwENE3WRhYSgndbG0ddteR3SI4qFkXzOSC3GRSz/FqgnByuaNPeSK77sHFwmrpYsnAphsSRl/5sPk0Y4i6kL99tcQjv3M5LA== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(82310400026)(23010399003)(376014)(7416014)(1800799024)(6133799003)(56012099006)(11063799006)(10067099003)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: RqNV7jyqF8TptyQiJnCav6QV1RdJxKii5kOdQrYtT/9HWtmPxYlcb6T1nQn+wwsOU1zmp9slswwo+7Wmf7gKT39k/l55asN6YFBAq/rxKhz38/k0k5uCRpLEqQwgCOsGu6GIcSEbmuSMzA5TQHBgpeK1jSPK7xc+3OHKTixdrI514BJfwAvWt2f+Ae0jwXfD6EoWmuCVMcT5WiPxCNq3+hMjq9jsZy89k0kZXYL2ywGJ3/svZvgi1uvBx5mG1EMP+B9LUXlmfwbNo2b1IIlFyP8cuuDbNnO7lkiPwT8BCHGjW/V1aZCW5UU/aUYmaMfv5bLPkxllrPR3TINkECH0OI1N83jLqIeJTTcpTOrDv1Vahf8wzYuL3y6yeD5CtIpLuKQSxN8990CZeDmbS9AvUpIHRNl3gInl+uMvwh/Bytf95QX8R5wwr6dAtIOS9PFs X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Aug 2026 08:38:37.9215 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d9323689-dd8c-4d14-b5f9-08def203c796 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A0.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY3PR12MB9555 Content-Type: text/plain; charset="utf-8" From: Cosmin Ratiu The psp_responder accumulates received data in a buffer and parses received messages from it, but a message that's split in two across command and argument (e.g. "psp conn" and "1") will permanently choke the parser, because the stand-alone arg is never parsed after discarding the command. This is mostly a theoretical issue since a sent TCP segment from psp.py of the form "psp conn 1" will arrive in one piece to psp_responder, but the AI tools complain about the possibility that it might get split, so fix it now before another command with an argument is added in the next patch. Signed-off-by: Cosmin Ratiu Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- .../selftests/drivers/net/psp_responder.c | 38 +++++++++---------- 1 file changed, 17 insertions(+), 21 deletions(-) diff --git a/tools/testing/selftests/drivers/net/psp_responder.c b/tools/te= sting/selftests/drivers/net/psp_responder.c index a26e7628bbb1..985161eb482b 100644 --- a/tools/testing/selftests/drivers/net/psp_responder.c +++ b/tools/testing/selftests/drivers/net/psp_responder.c @@ -185,22 +185,22 @@ run_session(struct ynl_sock *ys, struct opts *opts, } =20 off +=3D n; - n =3D off; =20 #define __consume(sz) \ ({ \ - if (n =3D=3D (sz)) { \ - off =3D 0; \ - } else { \ - off -=3D (sz); \ - memmove(buf, &buf[(sz)], off); \ - } \ + off -=3D (sz); \ + memmove(buf, &buf[(sz)], off); \ }) =20 -#define cmd(_name) \ +/* Only match once the command and its _extra_sz byte payload are both + * buffered, otherwise a split read would consume the name and strand + * the payload, desynchronizing the parser for good. + */ +#define cmd(_name, _extra_sz) \ ({ \ ssize_t sz =3D sizeof(_name); \ - bool match =3D n >=3D sz && !memcmp(buf, _name, sz); \ + bool match =3D off >=3D sz + (_extra_sz) && \ + !memcmp(buf, _name, sz); \ \ if (match) { \ dbg("command: " _name "\n"); \ @@ -213,10 +213,10 @@ run_session(struct ynl_sock *ys, struct opts *opts, do { consumed =3D false; =20 - if (cmd("read len")) + if (cmd("read len", 0)) send_str(comm_sock, data_read); =20 - if (cmd("data echo")) { + if (cmd("data echo", 0)) { if (data_sock >=3D 0) send(data_sock, "echo", 5, MSG_WAITALL); @@ -224,7 +224,7 @@ run_session(struct ynl_sock *ys, struct opts *opts, fprintf(stderr, "WARN: echo but no data sock\n"); send_ack(comm_sock); } - if (cmd("data close")) { + if (cmd("data close", 0)) { if (data_sock >=3D 0) { close(data_sock); data_sock =3D -1; @@ -233,26 +233,22 @@ run_session(struct ynl_sock *ys, struct opts *opts, race_close =3D true; } } - if (cmd("conn psp")) { + if (cmd("conn psp", 2)) { if (accept_cfg !=3D ACCEPT_CFG_NONE) fprintf(stderr, "WARN: old conn config still set!\n"); accept_cfg =3D ACCEPT_CFG_PSP; send_ack(comm_sock); /* next two bytes are versions */ - if (off >=3D 2) { - memcpy(&psp_vers, buf, 2); - __consume(2); - } else { - fprintf(stderr, "WARN: short conn psp command!\n"); - } + memcpy(&psp_vers, buf, 2); + __consume(2); } - if (cmd("conn clr")) { + if (cmd("conn clr", 0)) { if (accept_cfg !=3D ACCEPT_CFG_NONE) fprintf(stderr, "WARN: old conn config still set!\n"); accept_cfg =3D ACCEPT_CFG_CLEAR; send_ack(comm_sock); } - if (cmd("exit")) + if (cmd("exit", 0)) should_quit =3D true; #undef cmd =20 --=20 2.44.0 From nobody Fri Oct 2 06:58:27 2026 Received: from PH0PR06CU001.outbound.protection.outlook.com (mail-westus3azon11011047.outbound.protection.outlook.com [40.107.208.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2B58841D12F; Tue, 4 Aug 2026 08:38:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.208.47 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785832733; cv=fail; b=XymEOLYk9XHrAY0JBcRC2L7WogU3qPb2cs6+5IkcX7FfUs4FT53+heAd4vXG7tjEmA2GjImsMESHu3gZnCgFQZW2JbzErs6Eaap+d83uianZzrI8NJsDxSVQDjymXD70HVxhUP+prhplB7oCghq8TulcNge56eTe2z1IhTaq6Qg= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785832733; c=relaxed/simple; bh=pRs1d7exX2CTZlgQ/pQ4DdKwUwkL1yUWWvs3KMhSRpg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=nAhKAecda2HiYRjfz6mvhR6OX0UTXAVVHJzWu0Upd31lQCG+O0Nr4jTpHYceS0zH+3NB+HtvSyVwWikXTu34e5HWm/pRfLRgS2Bp0ZyMyuWJqm95Q8FZ9M2y9QJsxUKnpzwT3D9BEpUrZ3rJVBgaBTbyVJ5htNfSoXmGxvOxkx4= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=EGhFCs/M; arc=fail smtp.client-ip=40.107.208.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="EGhFCs/M" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=f8JschJPzRQMsntPPYDBCdDEMjY1AybNVyYjEL8AYXyWMdHpHtF1BEP8/0/aKje7f0nfQ3LGX99seFCotts4uJIkJR0EbYT9SI6E0Imkiox3PKpesP4+d8xL/3W3Hrmevgcoy0Lufzo58ZpzYxJ3MCKdNOLBM2zufIurkUNuz9lxhQKZ97T6vkdbUc/t9ya+IcmrzfnibwvS0s3mu/0PDicdaVHnLhGR7rfA2u8d8lvgzQI4Nm8zhCWAwv+tU6FJNbFSidhCZW+PWmEFq/b6yBPLafm27QgiSNLO9QDLCnNEkPP0I66m1TPHWLsyqvOqbksqLtEtyxrheTvqUNQiBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=mMrLY0yInKU641Hd5nGGp2MRkxOi+pLr/UbL3QBlHJk=; b=R9TtO6+g6IFVccR3IHaIRO/GX+3mWQlttiXeRGFLeT9ehM03AEKEJV/zMW44F0IqPgWG+s2wt/G8+HY6UpUN+caBvAtIM8xdaoEP9cvVOXL67/bqI1rFawPng7Ygsg0iuuKbApvgcn7GJaTS/jAb5X9ckmHvMeY/6QGHk+1wipr3hvTd2rBScNRbhEla1+f9ELLnmX58w2I06pNemQ21Nr1/IEhPxvaBd1YjK7Bc16B/TIzQ1i5PteVf5xwaYx2BMpjiI3kMbWBQMsLRADyDQWyZgBtohtw1JawJhU/nQlQU87+5ZaMXKK7n2qkMpN0yb73mH25fT4K6R1Ssj1vV8w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=lunn.ch smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=mMrLY0yInKU641Hd5nGGp2MRkxOi+pLr/UbL3QBlHJk=; b=EGhFCs/McuApkt35bZPbTfC3U6eF/KEd0PhsflogSNeWh9Xcy/PqenTxkJbDf+2Rd/20OBMXWWdv4d08Oz3a34ZqA7E+kVHtoy6CYTJXVl6hOzazWOoEgCrZ6N5w/FLtgjZKm2IUD1Vwadqi3+FJxg6xu1dfyDFeJHsCT2TNjbddu2j5XcmR2KbAlcJ5St68TwvcGET7AVfcTNqUbLhUvIziCgLxyAufRQgoJIaZfuEuDmEqam1HroSLahf4F6XcCcVkiKL8TT0/hWcyNpTk1QcNWcHYLpUiRDpWzxPVVSDNO/egZjWDDTSeOIc20yazlXf9QdVUf+ABdOw82w/z2w== Received: from PH0P220CA0015.NAMP220.PROD.OUTLOOK.COM (2603:10b6:510:d3::26) by SA1PR12MB9469.namprd12.prod.outlook.com (2603:10b6:806:45a::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.270.17; Tue, 4 Aug 2026 08:38:46 +0000 Received: from SN1PEPF000252A0.namprd05.prod.outlook.com (2603:10b6:510:d3:cafe::80) by PH0P220CA0015.outlook.office365.com (2603:10b6:510:d3::26) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.292.15 via Frontend Transport; Tue, 4 Aug 2026 08:38:45 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by SN1PEPF000252A0.mail.protection.outlook.com (10.167.242.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.292.8 via Frontend Transport; Tue, 4 Aug 2026 08:38:45 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Tue, 4 Aug 2026 01:38:33 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 4 Aug 2026 01:38:32 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Tue, 4 Aug 2026 01:38:24 -0700 From: Tariq Toukan To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , , Paolo Abeni , Sabrina Dubroca CC: Aleksandr Loktionov , Alexei Lazar , Boris Pismenny , Carolina Jubran , Chris Mi , Cosmin Ratiu , Daniel Zahka , Doruk Tan Ozturk , Dragos Tatulea , Gal Pressman , Jacob Keller , Jianbo Liu , Kees Cook , Lama Kayal , Leon Romanovsky , , , , Mark Bloch , "Patrisious Haddad" , Raed Salem , Rahul Rameshbabu , Saeed Mahameed , Shuah Khan , Shuah Khan , Simon Horman , Stanislav Fomichev , Stanislav Fomichev , Tariq Toukan Subject: [PATCH net-next V2 13/13] selftests: drv-net: psp: Add a test for PSP with HW-GRO Date: Tue, 4 Aug 2026 11:35:35 +0300 Message-ID: <20260804083535.2946459-14-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260804083535.2946459-1-tariqt@nvidia.com> References: <20260804083535.2946459-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A0:EE_|SA1PR12MB9469:EE_ X-MS-Office365-Filtering-Correlation-Id: 3983d18d-4884-4f0d-6e7d-08def203cc40 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|7416014|376014|23010399003|1800799024|82310400026|6133799003|56012099006|10067099003|11063799006|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: YCZzEntMZrlgpCwzJ+Jvpkt7+Nd2DMXyI14wVgPPf+iUaeiu9FtDkDByq9AdlvjYCiDbEtxFTP5zVFgO2nf5uqh5O+jJhtVQwyAJ7CED3jtLIV8p1ycOFGPh1pJoILbHNTmTueIj5KZX2MO7xeXLcTJFHyyFMBXXqZRCBRVx//CvY3OtGyRTIY01q7yy8djKz70VWnK1gvvgE2t3QGlobaKZYp3lLEbM498vKQszmulIEL/oQ+QWi2JLwsVKq+uveqhs9W73Z8RkeppWS+ha+wS+r6ykVEqT9gToG8WI7bSFK+1OWX7K+cqCIYNpJLL/Y4jeA3F5dvLmzcrHVraK9660cEnaDxbAIVKZ4w25VXP7/LVTXZL0Ee9bLRC1hyagc7famQSKFdY0kC1Ex50YiYW5Uqa05xvzf0i/j/F9bIxjZfcrc8Rksf4D7Wjmfx+Rj/Sdj68FDVQR3Phn+Ss839LB2GAUsBx7PEF8kQ+qTj4x+Qmx7TMDjwr9LyilEcOC6RIVsdh5B0FvXBiS7szjdGkxih4z7WXVARihXMsk2gkU5yFX9vWr41Ms2F/9xGRvVu79vlVRLWeIgt5iprGiU8X3Xwrh+OrAMNaMAuC6O1SUP50WFA3SJR89VeANv2/b73kN0Zps3y8o41Rp3CO5xfJ5DLavwJh5cWUuk/isvh5u97YIpinc6l6zmC+VdNIj8MNun+yntANBPnSgeIyvEw== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(7416014)(376014)(23010399003)(1800799024)(82310400026)(6133799003)(56012099006)(10067099003)(11063799006)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Fzbk+FikZBiUJ1fxKh8ZVoRs2uvXxCP6lE9++QbQWqa4MD88lU6l5cdv2ILsBcZUDLw0Fz9a+nLrl/Q+F3aH2uH/VXOXlnv2DvYJBgrRvyrPpF3TUTlAomn1YEY695ksnshwlLUzBTPol0cg6XcqtWShbxyeAIsauUURbEzxEwBkL5jlu01CwpTqECbP3lW5e7gFwreulqnPJjwNrnpiOh/UEkPODFwTj14L7YaRTGQe7vvEJIXmz9NgSnEhhbvIlQWhw50mHrzEFmXG6Y2DPC9b8JfDRe0YWWLsMCi4T2KUcHTW6nhDry36pzkYyvpr7qGg73pgtUTmdodacqOEyvf0ABNIKLWKXiR2EeniYO+WqYTrCXd0LxA3U90Sp3qlo5OlY1rqM3uetdYJZfIu9vuI7I8ckKIAusCR9I0xpDDiI6fDdfxykux+xhozOq+v X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Aug 2026 08:38:45.7184 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3983d18d-4884-4f0d-6e7d-08def203cc40 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A0.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB9469 Content-Type: text/plain; charset="utf-8" From: Cosmin Ratiu Add a test case which attempts to send several 64K chunks over PSP, which is more than MTU, and thus trigger GSO on the TX side and HW GRO on the RX side. Verify HW GRO counters increase. This required the addition of a new command in the psp responder, so it sends the data in order to get it reassembled on the local (DUT) side. Signed-off-by: Cosmin Ratiu Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- tools/testing/selftests/drivers/net/psp.py | 131 ++++++++++++++++-- .../selftests/drivers/net/psp_responder.c | 49 +++++++ 2 files changed, 171 insertions(+), 9 deletions(-) diff --git a/tools/testing/selftests/drivers/net/psp.py b/tools/testing/sel= ftests/drivers/net/psp.py index 315648a770d0..9b899723a635 100755 --- a/tools/testing/selftests/drivers/net/psp.py +++ b/tools/testing/selftests/drivers/net/psp.py @@ -16,11 +16,12 @@ from lib.py import ksft_run, ksft_exit, ksft_pr from lib.py import ksft_true, ksft_eq, ksft_ne, ksft_gt, ksft_raises from lib.py import ksft_not_none from lib.py import ksft_variants, KsftNamedVariant -from lib.py import KsftSkipEx, KsftFailEx +from lib.py import KsftSkipEx, KsftFailEx, KsftXfailEx from lib.py import NetDrvEpEnv, NetDrvContEnv -from lib.py import Netlink, NlError, PSPFamily, RtnlFamily +from lib.py import Netlink, NlError, NetdevFamily, PSPFamily, RtnlFamily from lib.py import NetNSEnter from lib.py import bkg, rand_port, wait_port_listen +from lib.py import bkg, ethtool, rand_port, wait_port_listen, CmdExitFailu= re from lib.py import ip =20 =20 @@ -30,15 +31,25 @@ def _get_outq(s): return struct.unpack("I", outq)[0] =20 =20 +def _recv_exact(sock, n): + buf =3D b'' + while len(buf) < n: + chunk =3D sock.recv(n - len(buf)) + if not chunk: + break + buf +=3D chunk + return buf + + def _send_with_ack(cfg, msg): - cfg.comm_sock.send(msg) - response =3D cfg.comm_sock.recv(4) + cfg.comm_sock.sendall(msg) + response =3D _recv_exact(cfg.comm_sock, 4) if response !=3D b'ack\0': raise RuntimeError("Unexpected server response", response) =20 =20 def _remote_read_len(cfg): - cfg.comm_sock.send(b'read len\0') + cfg.comm_sock.sendall(b'read len\0') return int(cfg.comm_sock.recv(1024)[:-1].decode('utf-8')) =20 =20 @@ -97,7 +108,7 @@ def _send_careful(cfg, s, rounds): def _check_data_rx(cfg, exp_len): read_len =3D -1 for _ in range(30): - cfg.comm_sock.send(b'read len\0') + cfg.comm_sock.sendall(b'read len\0') read_len =3D int(cfg.comm_sock.recv(1024)[:-1].decode('utf-8')) if read_len =3D=3D exp_len: break @@ -583,6 +594,108 @@ def _get_psp_ver_ip_variants(): for ipv in ("4", "6"): yield KsftNamedVariant(f"v{ver}_ip{ipv}", ver, ipv) =20 +def _enable_local_hw_gro(cfg): + cfg.require_cmd("ethtool") + feat =3D ethtool(f"-k {cfg.ifname}", json=3DTrue)[0] + gro =3D feat.get("rx-gro-hw") + if not gro or "active" not in gro or "fixed" not in gro: + raise KsftSkipEx("HW GRO feature not reported by ethtool") + if gro["fixed"] and not gro["active"]: + raise KsftXfailEx("HW GRO not supported by device") + if not gro["active"]: + try: + ethtool(f"-K {cfg.ifname} rx-gro-hw on") + except CmdExitFailure as e: + raise KsftSkipEx("Cannot enable HW GRO via ethtool") from e + defer(ethtool, f"-K {cfg.ifname} rx-gro-hw off") + feat =3D ethtool(f"-k {cfg.ifname}", json=3DTrue)[0] + gro =3D feat.get("rx-gro-hw", {}) + if not gro.get("active"): + raise KsftSkipEx("HW GRO failed to activate") + + +def _remote_send(cfg, size): + cfg.comm_sock.sendall(b'data send\0' + struct.pack('!I', size)) + response =3D _recv_exact(cfg.comm_sock, 4) + if response !=3D b'ack\0': + raise RuntimeError("Unexpected server response to data send", resp= onse) + + +def _recv_all(s, expected, timeout=3D20): + s.settimeout(timeout) + total =3D 0 + try: + while total < expected: + data =3D s.recv(min(65536, expected - total)) + if not data: + break + total +=3D len(data) + except socket.timeout: + raise RuntimeError( + f"Timed out receiving data: got {total}/{expected} bytes " + f"(responder may have failed to send)") + if total < expected: + raise RuntimeError( + f"Short read: got {total}/{expected} bytes " + f"(responder connection closed early)") + return total + + +def _data_hw_gro(cfg, version, ipver): + """ Test PSP data transfer with HW GRO enabled """ + _init_psp_dev(cfg) + # Version 0 is required by spec, don't let it skip + if version: + name =3D cfg.pspnl.consts["version"].entries_by_val[version].name + if name not in cfg.psp_info['psp-versions-cap']: + raise KsftSkipEx("PSP version not supported", name) + + _enable_local_hw_gro(cfg) + + s =3D _make_psp_conn(cfg, version, ipver) + try: + rx_assoc =3D cfg.pspnl.rx_assoc({"version": version, + "dev-id": cfg.psp_dev_id, + "sock-fd": s.fileno()}) + rx =3D rx_assoc['rx-key'] + tx =3D _spi_xchg(s, rx) + cfg.pspnl.tx_assoc({"dev-id": cfg.psp_dev_id, + "version": version, + "tx-key": tx, + "sock-fd": s.fileno()}) + + try: + before =3D cfg.netnl.qstats_get({"ifindex": cfg.ifindex}, dump= =3DTrue)[0] + except NlError as e: + if e.error =3D=3D errno.EOPNOTSUPP: + raise KsftSkipEx("qstats not supported by the device") fro= m e + raise + if ('rx-hw-gro-packets' not in before or + 'rx-hw-gro-wire-packets' not in before): + raise KsftSkipEx("rx-hw-gro-packets counter not available") + + # Remote sends data in 8KB chunks; GSO on remote TX segments them, + # HW GRO reassembles on local RX + data_len =3D 10 * 65536 + _remote_send(cfg, data_len) + recv_len =3D _recv_all(s, data_len) + ksft_eq(recv_len, data_len) + + cfg.wait_hw_stats_settle() + after =3D cfg.netnl.qstats_get({"ifindex": cfg.ifindex}, dump=3DTr= ue)[0] + ksft_gt(after['rx-hw-gro-packets'], + before['rx-hw-gro-packets']) + ksft_gt(after['rx-hw-gro-wire-packets'], + before['rx-hw-gro-wire-packets']) + finally: + _close_psp_conn(cfg, s) + +@ksft_variants(_get_psp_ver_ip_variants()) +def data_hw_gro(cfg, version, ipver): + """ Test PSP data transfer with HW GRO enabled """ + cfg.require_ipver(ipver) + _data_hw_gro(cfg, version, ipver) + =20 def _get_ip_variants(): for ipv in ("4", "6"): @@ -937,7 +1050,6 @@ def _setup_psp_attributes(cfg): cfg.psp_dev_peer_nsid =3D _get_nsid(cfg.netns.name) =20 =20 - def main() -> None: """ Ksft boiler plate main """ =20 @@ -954,6 +1066,7 @@ def main() -> None: =20 with env as cfg: cfg.pspnl =3D PSPFamily() + cfg.netnl =3D NetdevFamily() =20 if has_cont: _setup_psp_attributes(cfg) @@ -973,7 +1086,7 @@ def main() -> None: cfg.comm_port), timeout=3D1) =20 - cases =3D [data_basic_send, data_mss_adjust] + cases =3D [data_basic_send, data_hw_gro, data_mss_adjust] =20 if has_cont: cases +=3D [ @@ -990,7 +1103,7 @@ def main() -> None: case_pfx=3D{"dev_", "data_", "assoc_", "removal_"= }, args=3D(cfg, )) =20 - cfg.comm_sock.send(b"exit\0") + cfg.comm_sock.sendall(b"exit\0") cfg.comm_sock.close() finally: if srv and (srv.stdout or srv.stderr): diff --git a/tools/testing/selftests/drivers/net/psp_responder.c b/tools/te= sting/selftests/drivers/net/psp_responder.c index 985161eb482b..9a675bf449f5 100644 --- a/tools/testing/selftests/drivers/net/psp_responder.c +++ b/tools/testing/selftests/drivers/net/psp_responder.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 =20 +#include #include #include #include @@ -118,6 +119,34 @@ static void send_str(int sock, int value) send(sock, buf, ret + 1, MSG_WAITALL); } =20 +static int send_data(int sock, size_t len) +{ + char sbuf[8192] =3D {0}; + ssize_t sent; + + while (len > 0) { + size_t chunk =3D len; + + if (chunk > sizeof(sbuf)) + chunk =3D sizeof(sbuf); + + sent =3D send(sock, sbuf, chunk, MSG_NOSIGNAL); + if (sent < 0) { + if (errno =3D=3D EINTR) + continue; + fprintf(stderr, "ERR: %s: %s\n", __func__, + strerror(errno)); + return -1; + } + if (sent =3D=3D 0) { + fprintf(stderr, "ERR: %s: peer closed\n", __func__); + return -1; + } + len -=3D sent; + } + return 0; +} + static void run_session(struct ynl_sock *ys, struct opts *opts, int server_sock, int comm_sock) @@ -224,6 +253,26 @@ run_session(struct ynl_sock *ys, struct opts *opts, fprintf(stderr, "WARN: echo but no data sock\n"); send_ack(comm_sock); } + if (cmd("data send", 4)) { + __u32 len; + + memcpy(&len, buf, sizeof(len)); + __consume(sizeof(len)); + len =3D ntohl(len); + + if (data_sock < 0) { + fprintf(stderr, + "WARN: send but no data sock\n"); + send_err(comm_sock); + continue; + } + + send_ack(comm_sock); + if (send_data(data_sock, len)) + fprintf(stderr, + "WARN: send incomplete for %u bytes\n", + len); + } if (cmd("data close", 0)) { if (data_sock >=3D 0) { close(data_sock); --=20 2.44.0