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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260804-blackwell-fixes-v4-1-ac858b6a1935@nvidia.com> References: <20260804-blackwell-fixes-v4-0-ac858b6a1935@nvidia.com> In-Reply-To: <20260804-blackwell-fixes-v4-0-ac858b6a1935@nvidia.com> To: Danilo Krummrich , Alexandre Courbot , Alice Ryhl , David Airlie , Simona Vetter , Benno Lossin , Gary Guo Cc: John Hubbard , Alistair Popple , Timur Tabi , nova-gpu@lists.linux.dev, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org, Eliot Courtney X-Mailer: b4 0.15.2 X-ClientProxiedBy: TY4PR01CA0073.jpnprd01.prod.outlook.com (2603:1096:405:36c::9) To BL0PR12MB2353.namprd12.prod.outlook.com (2603:10b6:207:4c::31) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL0PR12MB2353:EE_|PH7PR12MB6418:EE_ X-MS-Office365-Filtering-Correlation-Id: 512cf7a2-9a75-4789-97d8-08def1eb77b7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|10070799003|23010399003|366016|18002099003|22082099003|3023799007|56012099006|11063799006|10067099003; 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The layout actually looks like this: | non-wpr heap | WPR2 .. FRTS | PMU reserved | ... | VGA workspace | It's just by coincidence + generous alignment that the values happened to match. Instead, define a per-architecture reserved size at the end of the framebuffer and use this plus the PMU reserved size to calculate the frts vidmem offset. Fixes: d317e4585fa3 ("gpu: nova-core: Hopper/Blackwell: add FSP Chain of Tr= ust boot") Signed-off-by: Eliot Courtney --- drivers/gpu/nova-core/fb/hal/gb100.rs | 1 + drivers/gpu/nova-core/fb/hal/gb202.rs | 1 + drivers/gpu/nova-core/fsp.rs | 27 +++++++++++++++++++-------- drivers/gpu/nova-core/fsp/hal.rs | 4 ++++ drivers/gpu/nova-core/fsp/hal/gb100.rs | 6 ++++++ drivers/gpu/nova-core/fsp/hal/gb202.rs | 9 ++++++++- drivers/gpu/nova-core/fsp/hal/gh100.rs | 9 ++++++++- 7 files changed, 47 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/nova-core/fb/hal/gb100.rs b/drivers/gpu/nova-core/= fb/hal/gb100.rs index ec55ec3fc7e1..7e5b0e3ffc67 100644 --- a/drivers/gpu/nova-core/fb/hal/gb100.rs +++ b/drivers/gpu/nova-core/fb/hal/gb100.rs @@ -80,6 +80,7 @@ fn write_sysmem_flush_page_gb100(bar: Bar0<'_>, addr: Bou= nded) { ); } =20 +// This PMU reservation size is r570-specific. pub(super) const fn pmu_reserved_size_gb100() -> u32 { usize_into_u32::<{ const_align_up(SZ_8M + SZ_16M + SZ_4K, Alignment::n= ew::()).unwrap() }>( ) diff --git a/drivers/gpu/nova-core/fb/hal/gb202.rs b/drivers/gpu/nova-core/= fb/hal/gb202.rs index 69ba35d2ea08..c590e5b1269c 100644 --- a/drivers/gpu/nova-core/fb/hal/gb202.rs +++ b/drivers/gpu/nova-core/fb/hal/gb202.rs @@ -73,6 +73,7 @@ fn pmu_reserved_size(&self) -> u32 { =20 fn non_wpr_heap_size(&self) -> u32 { // Non-WPR heap for GB20x (see Open RM: kgspGetNonWprHeapSize, GB2= 02+). + // This size is r570-specific. u32::SZ_2M + u32::SZ_128K } =20 diff --git a/drivers/gpu/nova-core/fsp.rs b/drivers/gpu/nova-core/fsp.rs index ba4544210e40..a81b51028282 100644 --- a/drivers/gpu/nova-core/fsp.rs +++ b/drivers/gpu/nova-core/fsp.rs @@ -251,20 +251,31 @@ struct FspCotMessage { } =20 impl FspCotMessage { + /// Computes the FRTS vidmem offset for the Chain-of-Trust message. It= is measured backwards + /// from the end of the framebuffer. + fn frts_vidmem_offset(hal: &dyn hal::FspHal, fb_layout: &FbLayout) -> = Result { + let mut offset =3D u64::from(hal.fb_end_reserved_size()); + + if fb_layout.pmu_reserved_size !=3D 0 { + offset =3D (offset + u64::from(fb_layout.pmu_reserved_size)) + // The 2 MiB alignment is r570-specific. + .align_up(Alignment::new::()) + .ok_or(EINVAL)?; + } + + Ok(offset) + } + /// Returns an in-place initializer for [`FspCotMessage`]. fn new<'a>( fb_layout: &FbLayout, fsp_fw: &'a FspFirmware, args: &'a FmcBootArgs<'_>, ) -> Result + 'a> { - // frts_vidmem_offset is measured from the end of FB, so FRTS sits= at - // (end of FB) - frts_vidmem_offset. - let frts_vidmem_offset =3D if !args.resume { - let frts_reserved_size =3D fb_layout.heap.len() + u64::from(fb= _layout.pmu_reserved_size); + let hal =3D hal::fsp_hal(args.chipset).ok_or(ENOTSUPP)?; =20 - frts_reserved_size - .align_up(Alignment::new::()) - .ok_or(EINVAL)? + let frts_vidmem_offset =3D if !args.resume { + Self::frts_vidmem_offset(hal, fb_layout)? } else { 0 }; @@ -275,7 +286,7 @@ fn new<'a>( 0 }; =20 - let version =3D hal::fsp_hal(args.chipset).ok_or(ENOTSUPP)?.cot_ve= rsion(); + let version =3D hal.cot_version(); let size =3D num::usize_into_u16::<{ core::mem::size_of::() }>(); =20 Ok(init!(Self { diff --git a/drivers/gpu/nova-core/fsp/hal.rs b/drivers/gpu/nova-core/fsp/h= al.rs index b6f2624bb13d..aa2f8bda59d2 100644 --- a/drivers/gpu/nova-core/fsp/hal.rs +++ b/drivers/gpu/nova-core/fsp/hal.rs @@ -19,6 +19,10 @@ pub(super) trait FspHal { =20 /// Returns the FSP Chain of Trust protocol version this chipset adver= tises. fn cot_version(&self) -> u16; + + // TODO: consider moving this into the TLV firmware metadata when ready + /// Returns the size reserved at the end of the framebuffer, in bytes. + fn fb_end_reserved_size(&self) -> u32; } =20 /// Returns the FSP HAL, or `None` if the architecture doesn't support FSP. diff --git a/drivers/gpu/nova-core/fsp/hal/gb100.rs b/drivers/gpu/nova-core= /fsp/hal/gb100.rs index 42f5ecfc6400..f601b5d7bf61 100644 --- a/drivers/gpu/nova-core/fsp/hal/gb100.rs +++ b/drivers/gpu/nova-core/fsp/hal/gb100.rs @@ -1,6 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 // SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIA= TES. All rights reserved. =20 +use kernel::sizes::SizeConstants; + use crate::{ driver::Bar0, fsp::hal::FspHal, // @@ -17,6 +19,10 @@ fn fsp_boot_status(&self, bar: Bar0<'_>) -> u32 { fn cot_version(&self) -> u16 { 2 } + + fn fb_end_reserved_size(&self) -> u32 { + u32::SZ_2M + u32::SZ_128K + } } =20 const GB100: Gb100 =3D Gb100; diff --git a/drivers/gpu/nova-core/fsp/hal/gb202.rs b/drivers/gpu/nova-core= /fsp/hal/gb202.rs index 1091b169a645..b022d298195a 100644 --- a/drivers/gpu/nova-core/fsp/hal/gb202.rs +++ b/drivers/gpu/nova-core/fsp/hal/gb202.rs @@ -1,7 +1,10 @@ // SPDX-License-Identifier: GPL-2.0 // SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIA= TES. All rights reserved. =20 -use kernel::io::Io; +use kernel::{ + io::Io, + sizes::SizeConstants, // +}; =20 use crate::{ driver::Bar0, @@ -21,6 +24,10 @@ fn fsp_boot_status(&self, bar: Bar0<'_>) -> u32 { fn cot_version(&self) -> u16 { 2 } + + fn fb_end_reserved_size(&self) -> u32 { + u32::SZ_2M + u32::SZ_128K + } } =20 const GB202: Gb202 =3D Gb202; diff --git a/drivers/gpu/nova-core/fsp/hal/gh100.rs b/drivers/gpu/nova-core= /fsp/hal/gh100.rs index 291acaf2845a..002f7ccdca3e 100644 --- a/drivers/gpu/nova-core/fsp/hal/gh100.rs +++ b/drivers/gpu/nova-core/fsp/hal/gh100.rs @@ -1,7 +1,10 @@ // SPDX-License-Identifier: GPL-2.0 // SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIA= TES. 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Unify the name to make it more obvious which heap it is. Signed-off-by: Eliot Courtney --- drivers/gpu/nova-core/fb.rs | 10 +++++----- drivers/gpu/nova-core/gsp/fw.rs | 6 +++--- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/nova-core/fb.rs b/drivers/gpu/nova-core/fb.rs index 9e475efb1150..4a1be29cf5fb 100644 --- a/drivers/gpu/nova-core/fb.rs +++ b/drivers/gpu/nova-core/fb.rs @@ -164,7 +164,7 @@ pub(crate) struct FbLayout { pub(crate) wpr2_heap: FbRange, /// WPR2 region range, starting with an instance of `GspFwWprMeta`. pub(crate) wpr2: FbRange, - pub(crate) heap: FbRange, + pub(crate) non_wpr_heap: FbRange, pub(crate) vf_partition_count: u8, /// PMU reserved memory size, in bytes. pub(crate) pmu_reserved_size: u32, @@ -270,9 +270,9 @@ pub(crate) fn new( FbRange(wpr2_addr..frts.end) }; =20 - let heap =3D { - let heap_size =3D u64::from(hal.non_wpr_heap_size()); - FbRange(wpr2.start - heap_size..wpr2.start) + let non_wpr_heap =3D { + let non_wpr_heap_size =3D u64::from(hal.non_wpr_heap_size()); + FbRange(wpr2.start - non_wpr_heap_size..wpr2.start) }; =20 Ok(Self { @@ -283,7 +283,7 @@ pub(crate) fn new( elf, wpr2_heap, wpr2, - heap, + non_wpr_heap, vf_partition_count, pmu_reserved_size: hal.pmu_reserved_size(), }) diff --git a/drivers/gpu/nova-core/gsp/fw.rs b/drivers/gpu/nova-core/gsp/fw= .rs index 6e8e7d822ef1..a7637bf3f3df 100644 --- a/drivers/gpu/nova-core/gsp/fw.rs +++ b/drivers/gpu/nova-core/gsp/fw.rs @@ -196,9 +196,9 @@ pub(crate) fn new<'a>( sizeOfSignature: u64::from_safe_cast(gsp_firmware.sign= atures.size()), }, }, - gspFwRsvdStart: fb_layout.heap.start, - nonWprHeapOffset: fb_layout.heap.start, - nonWprHeapSize: fb_layout.heap.end - fb_layout.heap.start, + gspFwRsvdStart: fb_layout.non_wpr_heap.start, + nonWprHeapOffset: fb_layout.non_wpr_heap.start, + nonWprHeapSize: fb_layout.non_wpr_heap.end - fb_layout.non_wpr= _heap.start, gspFwWprStart: fb_layout.wpr2.start, gspFwHeapOffset: fb_layout.wpr2_heap.start, gspFwHeapSize: fb_layout.wpr2_heap.end - fb_layout.wpr2_heap.s= tart, --=20 2.55.0 From nobody Fri Oct 2 07:46:13 2026 Received: from CH1PR05CU001.outbound.protection.outlook.com (mail-northcentralusazon11010023.outbound.protection.outlook.com [52.101.193.23]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 199213B2FFE; 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Signed-off-by: Eliot Courtney --- drivers/gpu/nova-core/fb.rs | 2 +- drivers/gpu/nova-core/fb/hal.rs | 2 +- drivers/gpu/nova-core/fb/hal/ga100.rs | 2 +- drivers/gpu/nova-core/fb/hal/ga102.rs | 2 +- drivers/gpu/nova-core/fb/hal/gb100.rs | 4 ++-- drivers/gpu/nova-core/fb/hal/gb202.rs | 4 ++-- drivers/gpu/nova-core/fb/hal/gh100.rs | 4 ++-- drivers/gpu/nova-core/fb/hal/tu102.rs | 6 +++--- 8 files changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/nova-core/fb.rs b/drivers/gpu/nova-core/fb.rs index 4a1be29cf5fb..86d2bdaab7f9 100644 --- a/drivers/gpu/nova-core/fb.rs +++ b/drivers/gpu/nova-core/fb.rs @@ -271,7 +271,7 @@ pub(crate) fn new( }; =20 let non_wpr_heap =3D { - let non_wpr_heap_size =3D u64::from(hal.non_wpr_heap_size()); + let non_wpr_heap_size =3D hal.non_wpr_heap_size(); FbRange(wpr2.start - non_wpr_heap_size..wpr2.start) }; =20 diff --git a/drivers/gpu/nova-core/fb/hal.rs b/drivers/gpu/nova-core/fb/hal= .rs index 714f0b51cd8f..99363cfb116b 100644 --- a/drivers/gpu/nova-core/fb/hal.rs +++ b/drivers/gpu/nova-core/fb/hal.rs @@ -37,7 +37,7 @@ pub(crate) trait FbHal { fn pmu_reserved_size(&self) -> u32; =20 /// Returns the non-WPR heap size for this chipset, in bytes. - fn non_wpr_heap_size(&self) -> u32; + fn non_wpr_heap_size(&self) -> u64; =20 /// Returns the FRTS size, in bytes. fn frts_size(&self) -> u64; diff --git a/drivers/gpu/nova-core/fb/hal/ga100.rs b/drivers/gpu/nova-core/= fb/hal/ga100.rs index d13c9a826eef..a81b3e42ae41 100644 --- a/drivers/gpu/nova-core/fb/hal/ga100.rs +++ b/drivers/gpu/nova-core/fb/hal/ga100.rs @@ -74,7 +74,7 @@ fn pmu_reserved_size(&self) -> u32 { super::tu102::pmu_reserved_size_tu102() } =20 - fn non_wpr_heap_size(&self) -> u32 { + fn non_wpr_heap_size(&self) -> u64 { super::tu102::non_wpr_heap_size_tu102() } =20 diff --git a/drivers/gpu/nova-core/fb/hal/ga102.rs b/drivers/gpu/nova-core/= fb/hal/ga102.rs index 44a2cf8a00f1..a5eeddb8a1ae 100644 --- a/drivers/gpu/nova-core/fb/hal/ga102.rs +++ b/drivers/gpu/nova-core/fb/hal/ga102.rs @@ -41,7 +41,7 @@ fn pmu_reserved_size(&self) -> u32 { super::tu102::pmu_reserved_size_tu102() } =20 - fn non_wpr_heap_size(&self) -> u32 { + fn non_wpr_heap_size(&self) -> u64 { super::tu102::non_wpr_heap_size_tu102() } =20 diff --git a/drivers/gpu/nova-core/fb/hal/gb100.rs b/drivers/gpu/nova-core/= fb/hal/gb100.rs index 7e5b0e3ffc67..d9e4d62ae632 100644 --- a/drivers/gpu/nova-core/fb/hal/gb100.rs +++ b/drivers/gpu/nova-core/fb/hal/gb100.rs @@ -111,9 +111,9 @@ fn pmu_reserved_size(&self) -> u32 { pmu_reserved_size_gb100() } =20 - fn non_wpr_heap_size(&self) -> u32 { + fn non_wpr_heap_size(&self) -> u64 { // Non-WPR heap for GB10x (see Open RM: kgspGetNonWprHeapSize, GB1= 00/GB102). - u32::SZ_2M + u64::SZ_2M } =20 fn frts_size(&self) -> u64 { diff --git a/drivers/gpu/nova-core/fb/hal/gb202.rs b/drivers/gpu/nova-core/= fb/hal/gb202.rs index c590e5b1269c..4341ecf36188 100644 --- a/drivers/gpu/nova-core/fb/hal/gb202.rs +++ b/drivers/gpu/nova-core/fb/hal/gb202.rs @@ -71,10 +71,10 @@ fn pmu_reserved_size(&self) -> u32 { super::gb100::pmu_reserved_size_gb100() } =20 - fn non_wpr_heap_size(&self) -> u32 { + fn non_wpr_heap_size(&self) -> u64 { // Non-WPR heap for GB20x (see Open RM: kgspGetNonWprHeapSize, GB2= 02+). // This size is r570-specific. - u32::SZ_2M + u32::SZ_128K + u64::SZ_2M + u64::SZ_128K } =20 fn frts_size(&self) -> u64 { diff --git a/drivers/gpu/nova-core/fb/hal/gh100.rs b/drivers/gpu/nova-core/= fb/hal/gh100.rs index 2867ae058d0a..cf8e6403ef98 100644 --- a/drivers/gpu/nova-core/fb/hal/gh100.rs +++ b/drivers/gpu/nova-core/fb/hal/gh100.rs @@ -63,9 +63,9 @@ fn pmu_reserved_size(&self) -> u32 { super::tu102::pmu_reserved_size_tu102() } =20 - fn non_wpr_heap_size(&self) -> u32 { + fn non_wpr_heap_size(&self) -> u64 { // Non-WPR heap for Hopper (see Open RM: kgspCalculateFbLayout_GH1= 00). - u32::SZ_2M + u64::SZ_2M } =20 fn frts_size(&self) -> u64 { diff --git a/drivers/gpu/nova-core/fb/hal/tu102.rs b/drivers/gpu/nova-core/= fb/hal/tu102.rs index 541f163b52d3..bf5967cbffd3 100644 --- a/drivers/gpu/nova-core/fb/hal/tu102.rs +++ b/drivers/gpu/nova-core/fb/hal/tu102.rs @@ -46,8 +46,8 @@ pub(super) const fn pmu_reserved_size_tu102() -> u32 { 0 } =20 -pub(super) const fn non_wpr_heap_size_tu102() -> u32 { - u32::SZ_1M +pub(super) const fn non_wpr_heap_size_tu102() -> u64 { + u64::SZ_1M } =20 pub(super) const fn frts_size_tu102() -> u64 { @@ -77,7 +77,7 @@ fn pmu_reserved_size(&self) -> u32 { pmu_reserved_size_tu102() } =20 - fn non_wpr_heap_size(&self) -> u32 { + fn non_wpr_heap_size(&self) -> u64 { non_wpr_heap_size_tu102() } =20 --=20 2.55.0 From nobody Fri Oct 2 07:46:13 2026 Received: from BL0PR03CU003.outbound.protection.outlook.com (mail-eastusazon11012034.outbound.protection.outlook.com [52.101.53.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B303E3F4DC7; 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It contains ranges for each region of framebuffer, but on post FSP architectures, only the size is actually used. The region locations are decided by ACR, which runs as part of the GSP-FMC, not by the driver. The driver only provides the sizes. So, for post FSP architectures `FbLayout` contains essentially guesses for the offsets. Instead, make separate types so that we only store the information that's actually needed, rather than keeping around offsets that may not be correct. Signed-off-by: Eliot Courtney --- drivers/gpu/nova-core/fb.rs | 65 ++++++++++++++++++++------ drivers/gpu/nova-core/fsp.rs | 21 ++++----- drivers/gpu/nova-core/gsp/boot.rs | 28 ++++------- drivers/gpu/nova-core/gsp/fw.rs | 85 ++++++++++++++++++++++++++----= ---- drivers/gpu/nova-core/gsp/hal.rs | 12 ++--- drivers/gpu/nova-core/gsp/hal/gh100.rs | 17 ++++--- drivers/gpu/nova-core/gsp/hal/tu102.rs | 32 ++++++++----- 7 files changed, 170 insertions(+), 90 deletions(-) diff --git a/drivers/gpu/nova-core/fb.rs b/drivers/gpu/nova-core/fb.rs index 86d2bdaab7f9..77447a6567a4 100644 --- a/drivers/gpu/nova-core/fb.rs +++ b/drivers/gpu/nova-core/fb.rs @@ -149,7 +149,7 @@ fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Resul= t { /// /// Contains ranges of GPU memory reserved for a given purpose during the = GSP boot process. #[derive(Debug)] -pub(crate) struct FbLayout { +pub(crate) struct FbRanges { /// Range of the framebuffer. Starts at `0`. pub(crate) fb: FbRange, /// VGA workspace, small area of reserved memory at the end of the fra= mebuffer. @@ -164,14 +164,16 @@ pub(crate) struct FbLayout { pub(crate) wpr2_heap: FbRange, /// WPR2 region range, starting with an instance of `GspFwWprMeta`. pub(crate) wpr2: FbRange, + /// Non-WPR heap, located just below WPR2. pub(crate) non_wpr_heap: FbRange, + /// Number of VF partitions. pub(crate) vf_partition_count: u8, /// PMU reserved memory size, in bytes. pub(crate) pmu_reserved_size: u32, } =20 -impl FbLayout { - /// Computes the FB layout for `chipset` required to run the `gsp_fw` = GSP firmware. +impl FbRanges { + /// Computes concrete framebuffer ranges required on non-FSP booting a= rchitectures. pub(crate) fn new( chipset: Chipset, bar: Bar0<'_>, @@ -240,16 +242,7 @@ pub(crate) fn new( FbRange(elf_addr..elf_addr + elf_size) }; =20 - let (vf_partition_count, wpr2_heap_size) =3D match vgpu_state { - VgpuState::Disabled =3D> ( - 0, - gsp::LibosParams::from_chipset(chipset).wpr_heap_size(chip= set, fb.end)?, - ), - VgpuState::Enabled { total_vfs } =3D> ( - u8::try_from(total_vfs.get()).map_err(|_| EINVAL)?, - gsp::LibosParams::vgpu_wpr_heap_size(), - ), - }; + let (vf_partition_count, wpr2_heap_size) =3D wpr2_heap_params(chip= set, vgpu_state, fb.end)?; =20 let wpr2_heap =3D { const WPR2_HEAP_DOWN_ALIGN: Alignment =3D Alignment::new::(); @@ -303,3 +296,49 @@ pub(crate) fn wpr2_range(bar: Bar0<'_>) -> Option> { =20 Some(wpr2_lo.lower_bound()..wpr2_hi.higher_bound()) } + +/// Computes the number of VF partitions and the WPR2 heap size from the v= GPU state. +fn wpr2_heap_params(chipset: Chipset, vgpu_state: VgpuState, fb_size: u64)= -> Result<(u8, u64)> { + Ok(match vgpu_state { + VgpuState::Disabled =3D> ( + 0, + gsp::LibosParams::from_chipset(chipset).wpr_heap_size(chipset,= fb_size)?, + ), + VgpuState::Enabled { total_vfs } =3D> ( + u8::try_from(total_vfs.get()).map_err(|_| EINVAL)?, + gsp::LibosParams::vgpu_wpr_heap_size(), + ), + }) +} + +/// Framebuffer region sizes needed for GSP-FMC boot. +#[derive(Debug)] +pub(crate) struct FbSizes { + /// FRTS size, in bytes. + pub(crate) frts_size: u64, + /// WPR2 heap size, in bytes. + pub(crate) wpr2_heap_size: u64, + /// Non-WPR heap size, in bytes. + pub(crate) non_wpr_heap_size: u64, + /// PMU reserved memory size, in bytes. + pub(crate) pmu_reserved_size: u32, + /// Number of VF partitions. + pub(crate) vf_partition_count: u8, +} + +impl FbSizes { + /// Computes the framebuffer region sizes for GSP-FMC boot. + pub(crate) fn new(chipset: Chipset, bar: Bar0<'_>, vgpu_state: VgpuSta= te) -> Result { + let hal =3D hal::fb_hal(chipset); + let fb_size =3D hal.vidmem_size(bar); + let (vf_partition_count, wpr2_heap_size) =3D wpr2_heap_params(chip= set, vgpu_state, fb_size)?; + + Ok(Self { + frts_size: hal.frts_size(), + wpr2_heap_size, + non_wpr_heap_size: hal.non_wpr_heap_size(), + pmu_reserved_size: hal.pmu_reserved_size(), + vf_partition_count, + }) + } +} diff --git a/drivers/gpu/nova-core/fsp.rs b/drivers/gpu/nova-core/fsp.rs index a81b51028282..9add62736892 100644 --- a/drivers/gpu/nova-core/fsp.rs +++ b/drivers/gpu/nova-core/fsp.rs @@ -31,7 +31,7 @@ fsp::Fsp as FspEngine, Falcon, // }, - fb::FbLayout, + fb::FbSizes, firmware::{ fsp::{ FmcSignatures, @@ -253,11 +253,11 @@ struct FspCotMessage { impl FspCotMessage { /// Computes the FRTS vidmem offset for the Chain-of-Trust message. It= is measured backwards /// from the end of the framebuffer. - fn frts_vidmem_offset(hal: &dyn hal::FspHal, fb_layout: &FbLayout) -> = Result { + fn frts_vidmem_offset(hal: &dyn hal::FspHal, fb_info: &FbSizes) -> Res= ult { let mut offset =3D u64::from(hal.fb_end_reserved_size()); =20 - if fb_layout.pmu_reserved_size !=3D 0 { - offset =3D (offset + u64::from(fb_layout.pmu_reserved_size)) + if fb_info.pmu_reserved_size !=3D 0 { + offset =3D (offset + u64::from(fb_info.pmu_reserved_size)) // The 2 MiB alignment is r570-specific. .align_up(Alignment::new::()) .ok_or(EINVAL)?; @@ -268,20 +268,20 @@ fn frts_vidmem_offset(hal: &dyn hal::FspHal, fb_layou= t: &FbLayout) -> Result( - fb_layout: &FbLayout, + fb_info: &FbSizes, fsp_fw: &'a FspFirmware, args: &'a FmcBootArgs<'_>, ) -> Result + 'a> { let hal =3D hal::fsp_hal(args.chipset).ok_or(ENOTSUPP)?; =20 let frts_vidmem_offset =3D if !args.resume { - Self::frts_vidmem_offset(hal, fb_layout)? + Self::frts_vidmem_offset(hal, fb_info)? } else { 0 }; =20 let frts_size: u32 =3D if !args.resume { - fb_layout.frts.len().try_into()? + fb_info.frts_size.try_into()? } else { 0 }; @@ -537,15 +537,12 @@ pub(crate) fn read_vgpu_mode( pub(crate) fn boot_fmc( &mut self, dev: &device::Device, - fb_layout: &FbLayout, + fb_info: &FbSizes, args: &FmcBootArgs<'_>, ) -> Result { dev_dbg!(dev, "Starting FSP boot sequence for {}\n", args.chipset); =20 - let msg =3D KBox::init( - FspCotMessage::new(fb_layout, &self.fsp_fw, args)?, - GFP_KERNEL, - )?; + let msg =3D KBox::init(FspCotMessage::new(fb_info, &self.fsp_fw, a= rgs)?, GFP_KERNEL)?; =20 let _response_buf =3D self.send_sync_fsp(dev, &*msg)?; =20 diff --git a/drivers/gpu/nova-core/gsp/boot.rs b/drivers/gpu/nova-core/gsp/= boot.rs index 727b8ae4bcb7..97f6e7ef4ead 100644 --- a/drivers/gpu/nova-core/gsp/boot.rs +++ b/drivers/gpu/nova-core/gsp/boot.rs @@ -3,7 +3,6 @@ =20 use kernel::{ bits, - dma::Coherent, io::poll::read_poll_timeout, prelude::*, time::Delta, @@ -16,15 +15,13 @@ gsp::Gsp, Falcon, // }, - fb::FbLayout, firmware::{ gsp::GspFirmware, FIRMWARE_VERSION, // }, gsp::{ cmdq::Cmdq, - commands, - GspFwWprMeta, // + commands, // }, }; =20 @@ -50,23 +47,16 @@ pub(crate) fn boot( =20 let gsp_fw =3D KBox::pin_init(GspFirmware::new(dev, chipset, FIRMW= ARE_VERSION), GFP_KERNEL)?; =20 - let fb_layout =3D FbLayout::new(chipset, bar, &gsp_fw, ctx.vgpu.st= ate())?; - dev_dbg!(dev, "{:#x?}\n", fb_layout); - - let wpr_meta =3D Coherent::init(dev, GFP_KERNEL, GspFwWprMeta::new= (&gsp_fw, &fb_layout))?; - // Perform the chipset-specific boot sequence, and retrieve the un= load bundle. - let unload_bundle =3D hal - .boot(&self, &mut ctx, &fb_layout, &wpr_meta)? - .or_else(|| { - dev_warn!(dev, "The GSP won't be able to unload properly o= n unbind.\n"); - dev_warn!( - dev, - "The GPU will need to be reset before the driver can b= ind again.\n" - ); + let unload_bundle =3D hal.boot(&self, &mut ctx, &gsp_fw)?.or_else(= || { + dev_warn!(dev, "The GSP won't be able to unload properly on un= bind.\n"); + dev_warn!( + dev, + "The GPU will need to be reset before the driver can bind = again.\n" + ); =20 - None - }); + None + }); =20 let mut unload_guard =3D ScopeGuard::new_with_data((ctx, unload_bundle), |(ctx, unload_= bundle)| { diff --git a/drivers/gpu/nova-core/gsp/fw.rs b/drivers/gpu/nova-core/gsp/fw= .rs index a7637bf3f3df..998293656794 100644 --- a/drivers/gpu/nova-core/gsp/fw.rs +++ b/drivers/gpu/nova-core/gsp/fw.rs @@ -36,7 +36,10 @@ }; =20 use crate::{ - fb::FbLayout, + fb::{ + FbRanges, + FbSizes, // + }, firmware::gsp::GspFirmware, gpu::{ Architecture, @@ -174,10 +177,10 @@ unsafe impl FromBytes for GspFwWprMeta {} =20 impl GspFwWprMeta { /// Returns an initializer for a `GspFwWprMeta` suitable for booting `= gsp_firmware` using the - /// `fb_layout` layout. - pub(crate) fn new<'a>( + /// framebuffer ranges `ranges`. + pub(crate) fn from_ranges<'a>( gsp_firmware: &'a GspFirmware, - fb_layout: &'a FbLayout, + ranges: &'a FbRanges, ) -> impl Init + 'a { let init_inner =3D init!(bindings::GspFwWprMeta { // CAST: we want to store the bits of `GSP_FW_WPR_META_MAGIC` = unmodified. @@ -196,25 +199,67 @@ pub(crate) fn new<'a>( sizeOfSignature: u64::from_safe_cast(gsp_firmware.sign= atures.size()), }, }, - gspFwRsvdStart: fb_layout.non_wpr_heap.start, - nonWprHeapOffset: fb_layout.non_wpr_heap.start, - nonWprHeapSize: fb_layout.non_wpr_heap.end - fb_layout.non_wpr= _heap.start, - gspFwWprStart: fb_layout.wpr2.start, - gspFwHeapOffset: fb_layout.wpr2_heap.start, - gspFwHeapSize: fb_layout.wpr2_heap.end - fb_layout.wpr2_heap.s= tart, - gspFwOffset: fb_layout.elf.start, - bootBinOffset: fb_layout.boot.start, - frtsOffset: fb_layout.frts.start, - frtsSize: fb_layout.frts.end - fb_layout.frts.start, - gspFwWprEnd: fb_layout + gspFwRsvdStart: ranges.non_wpr_heap.start, + nonWprHeapOffset: ranges.non_wpr_heap.start, + nonWprHeapSize: ranges.non_wpr_heap.len(), + gspFwWprStart: ranges.wpr2.start, + gspFwHeapOffset: ranges.wpr2_heap.start, + gspFwHeapSize: ranges.wpr2_heap.len(), + gspFwOffset: ranges.elf.start, + bootBinOffset: ranges.boot.start, + frtsOffset: ranges.frts.start, + frtsSize: ranges.frts.len(), + gspFwWprEnd: ranges .vga_workspace .start .align_down(Alignment::new::()), - gspFwHeapVfPartitionCount: fb_layout.vf_partition_count, - fbSize: fb_layout.fb.end - fb_layout.fb.start, - vgaWorkspaceOffset: fb_layout.vga_workspace.start, - vgaWorkspaceSize: fb_layout.vga_workspace.end - fb_layout.vga_= workspace.start, - pmuReservedSize: fb_layout.pmu_reserved_size, + gspFwHeapVfPartitionCount: ranges.vf_partition_count, + fbSize: ranges.fb.len(), + vgaWorkspaceOffset: ranges.vga_workspace.start, + vgaWorkspaceSize: ranges.vga_workspace.len(), + pmuReservedSize: ranges.pmu_reserved_size, + ..Zeroable::init_zeroed() + }); + + init!(GspFwWprMeta { + inner <- init_inner, + }) + } + + /// Returns an initializer for a `GspFwWprMeta` suitable for booting `= gsp_firmware` using the + /// framebuffer region sizes `sizes`. + /// + /// The region offsets are left at zero: the ACR ucode computes them w= hen it sets up WPR2. + pub(crate) fn from_sizes<'a>( + gsp_firmware: &'a GspFirmware, + sizes: &'a FbSizes, + ) -> impl Init + 'a { + /// VGA workspace size to reserve at the end of the framebuffer, i= n bytes. + const VGA_WORKSPACE_SIZE: u64 =3D u64::SZ_128K; + + let init_inner =3D init!(bindings::GspFwWprMeta { + // CAST: we want to store the bits of `GSP_FW_WPR_META_MAGIC` = unmodified. + magic: bindings::GSP_FW_WPR_META_MAGIC as u64, + revision: u64::from(bindings::GSP_FW_WPR_META_REVISION), + sysmemAddrOfRadix3Elf: gsp_firmware.radix3_dma_handle(), + sizeOfRadix3Elf: u64::from_safe_cast(gsp_firmware.size), + sysmemAddrOfBootloader: gsp_firmware.bootloader.ucode.dma_hand= le(), + sizeOfBootloader: u64::from_safe_cast(gsp_firmware.bootloader.= ucode.size()), + bootloaderCodeOffset: u64::from(gsp_firmware.bootloader.code_o= ffset), + bootloaderDataOffset: u64::from(gsp_firmware.bootloader.data_o= ffset), + bootloaderManifestOffset: u64::from(gsp_firmware.bootloader.ma= nifest_offset), + __bindgen_anon_1: GspFwWprMetaBootResumeInfo { + __bindgen_anon_1: GspFwWprMetaBootInfo { + sysmemAddrOfSignature: gsp_firmware.signatures.dma_han= dle(), + sizeOfSignature: u64::from_safe_cast(gsp_firmware.sign= atures.size()), + }, + }, + nonWprHeapSize: sizes.non_wpr_heap_size, + gspFwHeapSize: sizes.wpr2_heap_size, + frtsSize: sizes.frts_size, + gspFwHeapVfPartitionCount: sizes.vf_partition_count, + vgaWorkspaceSize: VGA_WORKSPACE_SIZE, + pmuReservedSize: sizes.pmu_reserved_size, ..Zeroable::init_zeroed() }); =20 diff --git a/drivers/gpu/nova-core/gsp/hal.rs b/drivers/gpu/nova-core/gsp/h= al.rs index 34b4bb82a999..11e436651a69 100644 --- a/drivers/gpu/nova-core/gsp/hal.rs +++ b/drivers/gpu/nova-core/gsp/hal.rs @@ -5,13 +5,9 @@ mod gh100; mod tu102; =20 -use kernel::{ - dma::Coherent, - prelude::*, // -}; +use kernel::prelude::*; =20 use crate::{ - fb::FbLayout, firmware::gsp::GspFirmware, gpu::{ Architecture, @@ -19,8 +15,7 @@ }, gsp::{ Gsp, - GspBootContext, - GspFwWprMeta, // + GspBootContext, // }, }; =20 @@ -44,8 +39,7 @@ fn boot( &self, gsp: &Gsp, ctx: &mut GspBootContext<'_, '_>, - fb_layout: &FbLayout, - wpr_meta: &Coherent, + gsp_fw: &GspFirmware, ) -> Result>; =20 /// Performs HAL-specific post-GSP boot tasks. diff --git a/drivers/gpu/nova-core/gsp/hal/gh100.rs b/drivers/gpu/nova-core= /gsp/hal/gh100.rs index 22b60f9233de..be10d278f567 100644 --- a/drivers/gpu/nova-core/gsp/hal/gh100.rs +++ b/drivers/gpu/nova-core/gsp/hal/gh100.rs @@ -16,7 +16,8 @@ gsp::Gsp as GspEngine, Falcon, // }, - fb::FbLayout, + fb::FbSizes, + firmware::gsp::GspFirmware, fsp::FmcBootArgs, gsp::{ hal::{ @@ -144,19 +145,23 @@ fn boot( &self, gsp: &Gsp, ctx: &mut GspBootContext<'_, '_>, - fb_layout: &FbLayout, - wpr_meta: &Coherent, + gsp_fw: &GspFirmware, ) -> Result> { let dev =3D ctx.dev(); let chipset =3D ctx.chipset; let gsp_falcon =3D ctx.gsp_falcon; =20 + let fb_sizes =3D FbSizes::new(chipset, ctx.bar, ctx.vgpu.state())?; + dev_dbg!(dev, "{:#x?}\n", fb_sizes); + + let wpr_meta =3D + Coherent::init(dev, GFP_KERNEL, GspFwWprMeta::from_sizes(gsp_f= w, &fb_sizes))?; + let args =3D FmcBootArgs::new(dev, chipset, &wpr_meta, &gsp.libos,= false)?; + let unload_bundle =3D crate::gsp::UnloadBundle( KBox::new(FspUnloadBundle, GFP_KERNEL)? as KBox ); =20 - let args =3D FmcBootArgs::new(dev, chipset, wpr_meta, &gsp.libos, = false)?; - // Wait for the GSP RISC-V core to halt in case of error. We creat= e this guard after `args` // to make sure that boot args are kept alive until halt, in case = they are still being // accessed. @@ -167,7 +172,7 @@ fn boot( =20 let fsp =3D unload_guard.1.fsp.as_mut().ok_or(ENODEV)?; =20 - fsp.boot_fmc(dev, fb_layout, &args)?; + fsp.boot_fmc(dev, &fb_sizes, &args)?; =20 // Wait for GSP-FMC to release the GSP lockdown, indicating that `= args` is not accessed // anymore. diff --git a/drivers/gpu/nova-core/gsp/hal/tu102.rs b/drivers/gpu/nova-core= /gsp/hal/tu102.rs index 03133f723faf..e3c365cf4a68 100644 --- a/drivers/gpu/nova-core/gsp/hal/tu102.rs +++ b/drivers/gpu/nova-core/gsp/hal/tu102.rs @@ -19,7 +19,7 @@ }, fb::{ wpr2_range, - FbLayout, // + FbRanges, // }, firmware::{ booter::{ @@ -143,7 +143,7 @@ fn run_fwsec_frts( falcon: &Falcon<'_, GspEngine>, bar: Bar0<'_>, bios: &Vbios, - fb_layout: &FbLayout, + fb_ranges: &FbRanges, ) -> Result { // Check that the WPR2 region does not already exist - if it does,= we cannot run // FWSEC-FRTS until the GPU is reset. @@ -161,8 +161,8 @@ fn run_fwsec_frts( falcon, bios, FwsecCommand::Frts { - frts_addr: fb_layout.frts.start, - frts_size: fb_layout.frts.len(), + frts_addr: fb_ranges.frts.start, + frts_size: fb_ranges.frts.len(), }, )?; =20 @@ -196,12 +196,12 @@ fn run_fwsec_frts( return Err(EIO); }; =20 - if wpr2_range.start !=3D fb_layout.frts.start { + if wpr2_range.start !=3D fb_ranges.frts.start { dev_err!( dev, "WPR2 region created at unexpected address {:#x}; expected= {:#x}\n", wpr2_range.start, - fb_layout.frts.start, + fb_ranges.frts.start, ); =20 return Err(EIO); @@ -253,8 +253,7 @@ fn boot( &self, gsp: &Gsp, ctx: &mut GspBootContext<'_, '_>, - fb_layout: &FbLayout, - wpr_meta: &Coherent, + gsp_fw: &GspFirmware, ) -> Result> { let dev =3D ctx.dev(); let bar =3D ctx.bar; @@ -262,6 +261,17 @@ fn boot( let gsp_falcon =3D ctx.gsp_falcon; let sec2_falcon =3D ctx.sec2_falcon; =20 + let fb_ranges =3D FbRanges::new(chipset, bar, gsp_fw, ctx.vgpu.sta= te())?; + dev_dbg!(dev, "{:#x?}\n", fb_ranges); + + // Declared before the unload guard so that if Booter fails while = running, SEC2 is reset + // by the guard before this allocation is freed. + let wpr_meta =3D Coherent::init( + dev, + GFP_KERNEL, + GspFwWprMeta::from_ranges(gsp_fw, &fb_ranges), + )?; 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Signed-off-by: Eliot Courtney --- drivers/gpu/nova-core/fsp.rs | 4 ++-- drivers/gpu/nova-core/gsp/hal/gh100.rs | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/nova-core/fsp.rs b/drivers/gpu/nova-core/fsp.rs index 9add62736892..90212ecd6110 100644 --- a/drivers/gpu/nova-core/fsp.rs +++ b/drivers/gpu/nova-core/fsp.rs @@ -350,7 +350,7 @@ pub(crate) struct FmcBootArgs<'a> { fmc_boot_params: Coherent, resume: bool, // Additional dependencies required to be kept alive for FMC boot. - _wpr_meta: &'a Coherent, + _wpr_meta: Coherent, _libos: &'a Coherent<[LibosMemoryRegionInitArgument]>, } =20 @@ -360,7 +360,7 @@ impl<'a> FmcBootArgs<'a> { pub(crate) fn new( dev: &device::Device, chipset: Chipset, - wpr_meta: &'a Coherent, + wpr_meta: Coherent, libos: &'a Coherent<[LibosMemoryRegionInitArgument]>, resume: bool, ) -> Result { diff --git a/drivers/gpu/nova-core/gsp/hal/gh100.rs b/drivers/gpu/nova-core= /gsp/hal/gh100.rs index be10d278f567..b16c2f6f82a0 100644 --- a/drivers/gpu/nova-core/gsp/hal/gh100.rs +++ b/drivers/gpu/nova-core/gsp/hal/gh100.rs @@ -156,15 +156,15 @@ fn boot( =20 let wpr_meta =3D Coherent::init(dev, GFP_KERNEL, GspFwWprMeta::from_sizes(gsp_f= w, &fb_sizes))?; - let args =3D FmcBootArgs::new(dev, chipset, &wpr_meta, &gsp.libos,= false)?; + let args =3D FmcBootArgs::new(dev, chipset, wpr_meta, &gsp.libos, = false)?; =20 let unload_bundle =3D crate::gsp::UnloadBundle( KBox::new(FspUnloadBundle, GFP_KERNEL)? as KBox ); =20 // Wait for the GSP RISC-V core to halt in case of error. We creat= e this guard after `args` - // to make sure that boot args are kept alive until halt, in case = they are still being - // accessed. + // to make sure that the boot args and the WPR metadata they own a= re kept alive until halt, + // in case they are still being accessed. let mut unload_guard =3D ScopeGuard::new_with_data((unload_bundle, ctx), |(unload_bundl= e, ctx)| { let _ =3D unload_bundle.0.run(ctx); --=20 2.55.0