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Mon, 03 Aug 2026 15:35:43 -0700 (PDT) Received: from ryzen.lan ([2601:644:8000:7a86::e35]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84edc2d4473sm4186790b3a.40.2026.08.03.15.35.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 15:35:42 -0700 (PDT) From: Rosen Penev To: linux-gpio@vger.kernel.org Cc: Madhavan Srinivasan , Michael Ellerman , Nicholas Piggin , "Christophe Leroy (CS GROUP)" , Linus Walleij , Bartosz Golaszewski , linuxppc-dev@lists.ozlabs.org (open list:LINUX FOR POWERPC (32-BIT AND 64-BIT)), linux-kernel@vger.kernel.org (open list) Subject: [PATCHv2 1/8] gpio: move ppc4xx gpio driver from arch/powerpc to drivers/gpio Date: Mon, 3 Aug 2026 15:35:32 -0700 Message-ID: <20260803223539.86303-2-rosenp@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803223539.86303-1-rosenp@gmail.com> References: <20260803223539.86303-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move the ppc4xx gpio driver out of arch/powerpc/platforms/44x/ into drivers/gpio/gpio-ppc44x.c. The driver has no architecture-specific dependencies and follows the same pattern as other PowerPC GPIO drivers already in drivers/gpio/ (e.g. gpio-mpc8xxx, gpio-mpc5200). - Renamed Kconfig symbol from PPC4xx_GPIO to GPIO_PPC44X - Updated ppc44x_defconfig and warp_defconfig to use the new symbol - Marked the new option as tristate (was bool) since the driver supports module build via module_platform_driver() Assisted-by: opencode:big-pickle Signed-off-by: Rosen Penev Reviewed-by: Linus Walleij --- arch/powerpc/configs/44x/warp_defconfig | 2 +- arch/powerpc/configs/ppc44x_defconfig | 2 +- arch/powerpc/platforms/44x/Kconfig | 7 ------- arch/powerpc/platforms/44x/Makefile | 2 +- drivers/gpio/Kconfig | 7 +++++++ drivers/gpio/Makefile | 1 + .../platforms/44x/gpio.c =3D> drivers/gpio/gpio-ppc44x.c | 0 7 files changed, 11 insertions(+), 10 deletions(-) rename arch/powerpc/platforms/44x/gpio.c =3D> drivers/gpio/gpio-ppc44x.c (= 100%) diff --git a/arch/powerpc/configs/44x/warp_defconfig b/arch/powerpc/configs= /44x/warp_defconfig index 5757625469c4..d6014b9c5708 100644 --- a/arch/powerpc/configs/44x/warp_defconfig +++ b/arch/powerpc/configs/44x/warp_defconfig @@ -12,7 +12,7 @@ CONFIG_MODULE_UNLOAD=3Dy # CONFIG_BLK_DEV_BSG is not set # CONFIG_EBONY is not set CONFIG_WARP=3Dy -CONFIG_PPC4xx_GPIO=3Dy +CONFIG_GPIO_PPC44X=3Dy CONFIG_HZ_1000=3Dy CONFIG_CMDLINE=3D"ip=3Don" # CONFIG_PCI is not set diff --git a/arch/powerpc/configs/ppc44x_defconfig b/arch/powerpc/configs/p= pc44x_defconfig index 0dc537f6aff3..d351551e266f 100644 --- a/arch/powerpc/configs/ppc44x_defconfig +++ b/arch/powerpc/configs/ppc44x_defconfig @@ -22,7 +22,7 @@ CONFIG_GLACIER=3Dy CONFIG_REDWOOD=3Dy CONFIG_EIGER=3Dy CONFIG_YOSEMITE=3Dy -CONFIG_PPC4xx_GPIO=3Dy +CONFIG_GPIO_PPC44X=3Dy CONFIG_MATH_EMULATION=3Dy CONFIG_NET=3Dy CONFIG_PACKET=3Dy diff --git a/arch/powerpc/platforms/44x/Kconfig b/arch/powerpc/platforms/44= x/Kconfig index fc79f8466933..150813cea945 100644 --- a/arch/powerpc/platforms/44x/Kconfig +++ b/arch/powerpc/platforms/44x/Kconfig @@ -227,13 +227,6 @@ config PPC44x_SIMPLE help This option enables the simple PowerPC 44x platform support. =20 -config PPC4xx_GPIO - bool "PPC4xx GPIO support" - depends on 44x - select GPIOLIB - help - Enable gpiolib support for ppc440 based boards - # 44x specific CPU modules, selected based on the board above. config 440EP bool diff --git a/arch/powerpc/platforms/44x/Makefile b/arch/powerpc/platforms/4= 4x/Makefile index ca7b1bb442d9..4598d8b89bf4 100644 --- a/arch/powerpc/platforms/44x/Makefile +++ b/arch/powerpc/platforms/44x/Makefile @@ -15,4 +15,4 @@ obj-$(CONFIG_FSP2) +=3D fsp2.o obj-$(CONFIG_PCI) +=3D pci.o obj-$(CONFIG_PPC4xx_HSTA_MSI) +=3D hsta_msi.o obj-$(CONFIG_PPC4xx_CPM) +=3D cpm.o -obj-$(CONFIG_PPC4xx_GPIO) +=3D gpio.o + diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index af84285ed1bd..15fd5874f4ea 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -593,6 +593,13 @@ config GPIO_POLARFIRE_SOC help Say yes here to support the GPIO controllers on Microchip FPGAs. =20 +config GPIO_PPC44X + tristate "PPC44x GPIO support" + depends on 44x + select GPIO_GENERIC + help + Enable gpiolib support for ppc440 based boards. + config GPIO_PXA bool "PXA GPIO support" depends on ARCH_PXA || ARCH_MMP || COMPILE_TEST diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index fa14581e3995..dc9e6d643b5b 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -147,6 +147,7 @@ obj-$(CONFIG_GPIO_PCIE_IDIO_24) +=3D gpio-pcie-idio-24= .o obj-$(CONFIG_GPIO_PCI_IDIO_16) +=3D gpio-pci-idio-16.o obj-$(CONFIG_GPIO_PISOSR) +=3D gpio-pisosr.o obj-$(CONFIG_GPIO_PL061) +=3D gpio-pl061.o +obj-$(CONFIG_GPIO_PPC44X) +=3D gpio-ppc44x.o obj-$(CONFIG_GPIO_PMIC_EIC_SPRD) +=3D gpio-pmic-eic-sprd.o obj-$(CONFIG_GPIO_POLARFIRE_SOC) +=3D gpio-mpfs.o obj-$(CONFIG_GPIO_PXA) +=3D gpio-pxa.o diff --git a/arch/powerpc/platforms/44x/gpio.c b/drivers/gpio/gpio-ppc44x.c similarity index 100% rename from arch/powerpc/platforms/44x/gpio.c rename to drivers/gpio/gpio-ppc44x.c --=20 2.55.0 From nobody Fri Oct 2 07:45:31 2026 Received: from mail-pf1-f177.google.com (mail-pf1-f177.google.com [209.85.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C10EF3515FB for ; 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Mon, 03 Aug 2026 15:35:45 -0700 (PDT) Received: from ryzen.lan ([2601:644:8000:7a86::e35]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84edc2d4473sm4186790b3a.40.2026.08.03.15.35.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 15:35:44 -0700 (PDT) From: Rosen Penev To: linux-gpio@vger.kernel.org Cc: Madhavan Srinivasan , Michael Ellerman , Nicholas Piggin , "Christophe Leroy (CS GROUP)" , Linus Walleij , Bartosz Golaszewski , linuxppc-dev@lists.ozlabs.org (open list:LINUX FOR POWERPC (32-BIT AND 64-BIT)), linux-kernel@vger.kernel.org (open list) Subject: [PATCHv2 2/8] gpio: ppc44x: update all 4xx to 44x Date: Mon, 3 Aug 2026 15:35:33 -0700 Message-ID: <20260803223539.86303-3-rosenp@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803223539.86303-1-rosenp@gmail.com> References: <20260803223539.86303-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The kernel lost support for 4xx platforms and now only supports 44x. Since this driver is being moved to drivers/gpio/ , take the opportunity to modernize the name. Signed-off-by: Rosen Penev Reviewed-by: Linus Walleij --- drivers/gpio/gpio-ppc44x.c | 68 +++++++++++++++++++------------------- 1 file changed, 34 insertions(+), 34 deletions(-) diff --git a/drivers/gpio/gpio-ppc44x.c b/drivers/gpio/gpio-ppc44x.c index 4413a94cf7a6..9b874ff8b124 100644 --- a/drivers/gpio/gpio-ppc44x.c +++ b/drivers/gpio/gpio-ppc44x.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * PPC4xx gpio driver + * PPC44x gpio driver * * Copyright (c) 2008 Harris Corporation * Copyright (c) 2008 Sascha Hauer , Pengutronix @@ -23,7 +23,7 @@ #define GPIO_MASK2(gpio) (0xc0000000 >> ((gpio) * 2)) =20 /* Physical GPIO register layout */ -struct ppc4xx_gpio { +struct ppc44x_gpio { __be32 or; __be32 tcr; __be32 osrl; @@ -44,7 +44,7 @@ struct ppc4xx_gpio { __be32 isr3h; }; =20 -struct ppc4xx_gpio_chip { +struct ppc44x_gpio_chip { struct gpio_chip gc; void __iomem *regs; spinlock_t lock; @@ -56,19 +56,19 @@ struct ppc4xx_gpio_chip { * There are a maximum of 32 gpios in each gpio controller. */ =20 -static int ppc4xx_gpio_get(struct gpio_chip *gc, unsigned int gpio) +static int ppc44x_gpio_get(struct gpio_chip *gc, unsigned int gpio) { - struct ppc4xx_gpio_chip *chip =3D gpiochip_get_data(gc); - struct ppc4xx_gpio __iomem *regs =3D chip->regs; + struct ppc44x_gpio_chip *chip =3D gpiochip_get_data(gc); + struct ppc44x_gpio __iomem *regs =3D chip->regs; =20 return !!(in_be32(®s->ir) & GPIO_MASK(gpio)); } =20 static inline void -__ppc4xx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) +__ppc44x_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) { - struct ppc4xx_gpio_chip *chip =3D gpiochip_get_data(gc); - struct ppc4xx_gpio __iomem *regs =3D chip->regs; + struct ppc44x_gpio_chip *chip =3D gpiochip_get_data(gc); + struct ppc44x_gpio __iomem *regs =3D chip->regs; =20 if (val) setbits32(®s->or, GPIO_MASK(gpio)); @@ -76,14 +76,14 @@ __ppc4xx_gpio_set(struct gpio_chip *gc, unsigned int gp= io, int val) clrbits32(®s->or, GPIO_MASK(gpio)); } =20 -static int ppc4xx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int va= l) +static int ppc44x_gpio_set(struct gpio_chip *gc, unsigned int gpio, int va= l) { - struct ppc4xx_gpio_chip *chip =3D gpiochip_get_data(gc); + struct ppc44x_gpio_chip *chip =3D gpiochip_get_data(gc); unsigned long flags; =20 spin_lock_irqsave(&chip->lock, flags); =20 - __ppc4xx_gpio_set(gc, gpio, val); + __ppc44x_gpio_set(gc, gpio, val); =20 spin_unlock_irqrestore(&chip->lock, flags); =20 @@ -92,10 +92,10 @@ static int ppc4xx_gpio_set(struct gpio_chip *gc, unsign= ed int gpio, int val) return 0; } =20 -static int ppc4xx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio) +static int ppc44x_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio) { - struct ppc4xx_gpio_chip *chip =3D gpiochip_get_data(gc); - struct ppc4xx_gpio __iomem *regs =3D chip->regs; + struct ppc44x_gpio_chip *chip =3D gpiochip_get_data(gc); + struct ppc44x_gpio __iomem *regs =3D chip->regs; unsigned long flags; =20 spin_lock_irqsave(&chip->lock, flags); @@ -121,16 +121,16 @@ static int ppc4xx_gpio_dir_in(struct gpio_chip *gc, u= nsigned int gpio) } =20 static int -ppc4xx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) +ppc44x_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) { - struct ppc4xx_gpio_chip *chip =3D gpiochip_get_data(gc); - struct ppc4xx_gpio __iomem *regs =3D chip->regs; + struct ppc44x_gpio_chip *chip =3D gpiochip_get_data(gc); + struct ppc44x_gpio __iomem *regs =3D chip->regs; unsigned long flags; =20 spin_lock_irqsave(&chip->lock, flags); =20 /* First set initial value */ - __ppc4xx_gpio_set(gc, gpio, val); + __ppc44x_gpio_set(gc, gpio, val); =20 /* Disable open-drain function */ clrbits32(®s->odr, GPIO_MASK(gpio)); @@ -154,11 +154,11 @@ ppc4xx_gpio_dir_out(struct gpio_chip *gc, unsigned in= t gpio, int val) return 0; } =20 -static int ppc4xx_gpio_probe(struct platform_device *ofdev) +static int ppc44x_gpio_probe(struct platform_device *ofdev) { struct device *dev =3D &ofdev->dev; struct device_node *np =3D dev->of_node; - struct ppc4xx_gpio_chip *chip; + struct ppc44x_gpio_chip *chip; struct gpio_chip *gc; =20 chip =3D devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); @@ -172,10 +172,10 @@ static int ppc4xx_gpio_probe(struct platform_device *= ofdev) gc->parent =3D dev; gc->base =3D -1; gc->ngpio =3D 32; - gc->direction_input =3D ppc4xx_gpio_dir_in; - gc->direction_output =3D ppc4xx_gpio_dir_out; - gc->get =3D ppc4xx_gpio_get; - gc->set =3D ppc4xx_gpio_set; + gc->direction_input =3D ppc44x_gpio_dir_in; + gc->direction_output =3D ppc44x_gpio_dir_out; + gc->get =3D ppc44x_gpio_get; + gc->set =3D ppc44x_gpio_set; =20 gc->label =3D devm_kasprintf(dev, GFP_KERNEL, "%pOF", np); if (!gc->label) @@ -188,24 +188,24 @@ static int ppc4xx_gpio_probe(struct platform_device *= ofdev) return devm_gpiochip_add_data(dev, gc, chip); } =20 -static const struct of_device_id ppc4xx_gpio_match[] =3D { +static const struct of_device_id ppc44x_gpio_match[] =3D { { .compatible =3D "ibm,ppc4xx-gpio", }, {}, }; -MODULE_DEVICE_TABLE(of, ppc4xx_gpio_match); +MODULE_DEVICE_TABLE(of, ppc44x_gpio_match); =20 -static struct platform_driver ppc4xx_gpio_driver =3D { - .probe =3D ppc4xx_gpio_probe, +static struct platform_driver ppc44x_gpio_driver =3D { + .probe =3D ppc44x_gpio_probe, .driver =3D { - .name =3D "ppc4xx-gpio", - .of_match_table =3D ppc4xx_gpio_match, + .name =3D "ppc44x-gpio", + .of_match_table =3D ppc44x_gpio_match, }, }; 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charset="utf-8" Replace the open-coded arch initcall registration with module_platform_driver(). The initcall level changes from arch_initcall to device_initcall, which is safe since the driver no longer needs architecture-specific ordering. Added MODULE info as a result, otherwise these warnings appear ERROR: modpost: missing MODULE_LICENSE() in drivers/gpio/gpio-ppc4xx.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/gpio/gpio-ppc4xx.o Assisted-by: Codex:GPT-5.5 Signed-off-by: Rosen Penev Reviewed-by: Linus Walleij --- drivers/gpio/gpio-ppc44x.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpio/gpio-ppc44x.c b/drivers/gpio/gpio-ppc44x.c index 9b874ff8b124..99fb11cd7966 100644 --- a/drivers/gpio/gpio-ppc44x.c +++ b/drivers/gpio/gpio-ppc44x.c @@ -204,8 +204,7 @@ static struct platform_driver ppc44x_gpio_driver =3D { }, }; =20 -static int __init ppc44x_gpio_init(void) -{ - return platform_driver_register(&ppc44x_gpio_driver); -} -arch_initcall(ppc44x_gpio_init); +MODULE_DESCRIPTION("PPC44x gpio driver"); +MODULE_LICENSE("GPL"); + +module_platform_driver(ppc44x_gpio_driver); --=20 2.55.0 From nobody Fri Oct 2 07:45:31 2026 Received: from mail-pf1-f169.google.com (mail-pf1-f169.google.com [209.85.210.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 32CB727A92D for ; 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Mon, 03 Aug 2026 15:35:48 -0700 (PDT) Received: from ryzen.lan ([2601:644:8000:7a86::e35]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84edc2d4473sm4186790b3a.40.2026.08.03.15.35.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 15:35:47 -0700 (PDT) From: Rosen Penev To: linux-gpio@vger.kernel.org Cc: Madhavan Srinivasan , Michael Ellerman , Nicholas Piggin , "Christophe Leroy (CS GROUP)" , Linus Walleij , Bartosz Golaszewski , linuxppc-dev@lists.ozlabs.org (open list:LINUX FOR POWERPC (32-BIT AND 64-BIT)), linux-kernel@vger.kernel.org (open list) Subject: [PATCHv2 4/8] gpio: ppc44x: Use platform resource helper for GPIO MMIO Date: Mon, 3 Aug 2026 15:35:35 -0700 Message-ID: <20260803223539.86303-5-rosenp@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803223539.86303-1-rosenp@gmail.com> References: <20260803223539.86303-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Map the PPC44x GPIO register block through the platform device resource instead of reparsing the firmware node directly. The GPIO node now probes as a platform device, so use the platform helper to keep resource handling aligned with the converted driver model and to report mapping failures with the platform device context. Move ioremap up in order to avoid doing extra work in case of -EPROBE_DEFER. Assisted-by: Codex:GPT-5.5 Signed-off-by: Rosen Penev Reviewed-by: Linus Walleij --- drivers/gpio/gpio-ppc44x.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpio/gpio-ppc44x.c b/drivers/gpio/gpio-ppc44x.c index 99fb11cd7966..5db5217c0225 100644 --- a/drivers/gpio/gpio-ppc44x.c +++ b/drivers/gpio/gpio-ppc44x.c @@ -158,13 +158,20 @@ static int ppc44x_gpio_probe(struct platform_device *= ofdev) { struct device *dev =3D &ofdev->dev; struct device_node *np =3D dev->of_node; + struct ppc44x_gpio __iomem *regs; struct ppc44x_gpio_chip *chip; struct gpio_chip *gc; =20 + regs =3D devm_platform_ioremap_resource(ofdev, 0); + if (IS_ERR(regs)) + return PTR_ERR(regs); + chip =3D devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); if (!chip) return -ENOMEM; =20 + chip->regs =3D regs; + spin_lock_init(&chip->lock); =20 gc =3D &chip->gc; @@ -181,10 +188,6 @@ static int ppc44x_gpio_probe(struct platform_device *o= fdev) if (!gc->label) return -ENOMEM; =20 - chip->regs =3D devm_of_iomap(dev, np, 0, NULL); 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Mon, 03 Aug 2026 15:35:49 -0700 (PDT) Received: from ryzen.lan ([2601:644:8000:7a86::e35]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84edc2d4473sm4186790b3a.40.2026.08.03.15.35.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 15:35:49 -0700 (PDT) From: Rosen Penev To: linux-gpio@vger.kernel.org Cc: Madhavan Srinivasan , Michael Ellerman , Nicholas Piggin , "Christophe Leroy (CS GROUP)" , Linus Walleij , Bartosz Golaszewski , linuxppc-dev@lists.ozlabs.org (open list:LINUX FOR POWERPC (32-BIT AND 64-BIT)), linux-kernel@vger.kernel.org (open list) Subject: [PATCHv2 5/8] gpio: ppc44x: Convert GPIO to generic MMIO Date: Mon, 3 Aug 2026 15:35:36 -0700 Message-ID: <20260803223539.86303-6-rosenp@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803223539.86303-1-rosenp@gmail.com> References: <20260803223539.86303-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use gpio_generic_chip_init() to set up the PPC44x GPIO chip instead of open-coding the basic get, set, locking and state handling. Keep the PPC44x-specific direction callbacks because they still need to program ODR and the OSR/TSR registers around the generic data and direction registers. Assisted-by: Codex:GPT-5.5 Signed-off-by: Rosen Penev Reviewed-by: Linus Walleij --- drivers/gpio/gpio-ppc44x.c | 75 +++++++++++++++----------------------- 1 file changed, 29 insertions(+), 46 deletions(-) diff --git a/drivers/gpio/gpio-ppc44x.c b/drivers/gpio/gpio-ppc44x.c index 5db5217c0225..d9048452162a 100644 --- a/drivers/gpio/gpio-ppc44x.c +++ b/drivers/gpio/gpio-ppc44x.c @@ -11,10 +11,9 @@ =20 #include #include -#include #include #include -#include +#include #include #include #include @@ -45,9 +44,8 @@ struct ppc44x_gpio { }; =20 struct ppc44x_gpio_chip { - struct gpio_chip gc; + struct gpio_generic_chip chip; void __iomem *regs; - spinlock_t lock; }; =20 /* @@ -56,55 +54,34 @@ struct ppc44x_gpio_chip { * There are a maximum of 32 gpios in each gpio controller. */ =20 -static int ppc44x_gpio_get(struct gpio_chip *gc, unsigned int gpio) -{ - struct ppc44x_gpio_chip *chip =3D gpiochip_get_data(gc); - struct ppc44x_gpio __iomem *regs =3D chip->regs; - - return !!(in_be32(®s->ir) & GPIO_MASK(gpio)); -} - static inline void __ppc44x_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) { struct ppc44x_gpio_chip *chip =3D gpiochip_get_data(gc); - struct ppc44x_gpio __iomem *regs =3D chip->regs; + struct gpio_generic_chip *gen_gc =3D &chip->chip; =20 if (val) - setbits32(®s->or, GPIO_MASK(gpio)); + gen_gc->sdata |=3D GPIO_MASK(gpio); else - clrbits32(®s->or, GPIO_MASK(gpio)); -} - -static int ppc44x_gpio_set(struct gpio_chip *gc, unsigned int gpio, int va= l) -{ - struct ppc44x_gpio_chip *chip =3D gpiochip_get_data(gc); - unsigned long flags; + gen_gc->sdata &=3D ~GPIO_MASK(gpio); =20 - spin_lock_irqsave(&chip->lock, flags); - - __ppc44x_gpio_set(gc, gpio, val); - - spin_unlock_irqrestore(&chip->lock, flags); - - pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val); - - return 0; + gpio_generic_write_reg(gen_gc, gen_gc->reg_set, gen_gc->sdata); } =20 static int ppc44x_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio) { struct ppc44x_gpio_chip *chip =3D gpiochip_get_data(gc); + struct gpio_generic_chip *gen_gc =3D &chip->chip; struct ppc44x_gpio __iomem *regs =3D chip->regs; - unsigned long flags; =20 - spin_lock_irqsave(&chip->lock, flags); + guard(gpio_generic_lock_irqsave)(gen_gc); =20 /* Disable open-drain function */ clrbits32(®s->odr, GPIO_MASK(gpio)); =20 /* Float the pin */ clrbits32(®s->tcr, GPIO_MASK(gpio)); + gen_gc->sdir &=3D ~GPIO_MASK(gpio); =20 /* Bits 0-15 use TSRL/OSRL, bits 16-31 use TSRH/OSRH */ if (gpio < 16) { @@ -115,8 +92,6 @@ static int ppc44x_gpio_dir_in(struct gpio_chip *gc, unsi= gned int gpio) clrbits32(®s->tsrh, GPIO_MASK2(gpio)); } =20 - spin_unlock_irqrestore(&chip->lock, flags); - return 0; } =20 @@ -124,10 +99,10 @@ static int ppc44x_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) { struct ppc44x_gpio_chip *chip =3D gpiochip_get_data(gc); + struct gpio_generic_chip *gen_gc =3D &chip->chip; struct ppc44x_gpio __iomem *regs =3D chip->regs; - unsigned long flags; =20 - spin_lock_irqsave(&chip->lock, flags); + guard(gpio_generic_lock_irqsave)(gen_gc); =20 /* First set initial value */ __ppc44x_gpio_set(gc, gpio, val); @@ -137,6 +112,7 @@ ppc44x_gpio_dir_out(struct gpio_chip *gc, unsigned int = gpio, int val) =20 /* Drive the pin */ setbits32(®s->tcr, GPIO_MASK(gpio)); + gen_gc->sdir |=3D GPIO_MASK(gpio); =20 /* Bits 0-15 use TSRL, bits 16-31 use TSRH */ if (gpio < 16) { @@ -147,8 +123,6 @@ ppc44x_gpio_dir_out(struct gpio_chip *gc, unsigned int = gpio, int val) clrbits32(®s->tsrh, GPIO_MASK2(gpio)); } =20 - spin_unlock_irqrestore(&chip->lock, flags); - pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val); =20 return 0; @@ -160,7 +134,9 @@ static int ppc44x_gpio_probe(struct platform_device *of= dev) struct device_node *np =3D dev->of_node; struct ppc44x_gpio __iomem *regs; struct ppc44x_gpio_chip *chip; + struct gpio_generic_chip_config config; struct gpio_chip *gc; + int ret; =20 regs =3D devm_platform_ioremap_resource(ofdev, 0); if (IS_ERR(regs)) @@ -172,17 +148,24 @@ static int ppc44x_gpio_probe(struct platform_device *= ofdev) =20 chip->regs =3D regs; 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Mon, 03 Aug 2026 15:35:52 -0700 (PDT) Received: from ryzen.lan ([2601:644:8000:7a86::e35]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84edc2d4473sm4186790b3a.40.2026.08.03.15.35.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 15:35:52 -0700 (PDT) From: Rosen Penev To: linux-gpio@vger.kernel.org Cc: Madhavan Srinivasan , Michael Ellerman , Nicholas Piggin , "Christophe Leroy (CS GROUP)" , Linus Walleij , Bartosz Golaszewski , linuxppc-dev@lists.ozlabs.org (open list:LINUX FOR POWERPC (32-BIT AND 64-BIT)), linux-kernel@vger.kernel.org (open list) Subject: [PATCHv2 6/8] gpio: ppc44x: drop PPC-specific IO helpers Date: Mon, 3 Aug 2026 15:35:37 -0700 Message-ID: <20260803223539.86303-7-rosenp@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803223539.86303-1-rosenp@gmail.com> References: <20260803223539.86303-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Replace PPC-specific clrbits32()/setbits32() with local helpers using ioread32be()/iowrite32be() which are equivalent on PPC since commit 894fa235eb4c ("powerpc: inline iomap accessors"). Add COMPILE_TEST as a result to increase compile coverage. Assisted-by: opencode:big-pickle Signed-off-by: Rosen Penev Reviewed-by: Linus Walleij --- drivers/gpio/Kconfig | 2 +- drivers/gpio/gpio-ppc44x.c | 40 ++++++++++++++++++++++++++------------ 2 files changed, 29 insertions(+), 13 deletions(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 15fd5874f4ea..0e021af4e81e 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -595,7 +595,7 @@ config GPIO_POLARFIRE_SOC =20 config GPIO_PPC44X tristate "PPC44x GPIO support" - depends on 44x + depends on 44x || COMPILE_TEST select GPIO_GENERIC help Enable gpiolib support for ppc440 based boards. diff --git a/drivers/gpio/gpio-ppc44x.c b/drivers/gpio/gpio-ppc44x.c index d9048452162a..fd543fbb959a 100644 --- a/drivers/gpio/gpio-ppc44x.c +++ b/drivers/gpio/gpio-ppc44x.c @@ -48,6 +48,22 @@ struct ppc44x_gpio_chip { void __iomem *regs; }; =20 +static inline void ppc44x_clrbits32(void __iomem *addr, u32 mask) +{ + u32 val =3D ioread32be(addr); + + val &=3D ~mask; + iowrite32be(val, addr); +} + +static inline void ppc44x_setbits32(void __iomem *addr, u32 mask) +{ + u32 val =3D ioread32be(addr); + + val |=3D mask; + iowrite32be(val, addr); +} + /* * GPIO LIB API implementation for GPIOs * @@ -77,19 +93,19 @@ static int ppc44x_gpio_dir_in(struct gpio_chip *gc, uns= igned int gpio) guard(gpio_generic_lock_irqsave)(gen_gc); =20 /* Disable open-drain function */ - clrbits32(®s->odr, GPIO_MASK(gpio)); + ppc44x_clrbits32(®s->odr, GPIO_MASK(gpio)); =20 /* Float the pin */ - clrbits32(®s->tcr, GPIO_MASK(gpio)); + ppc44x_clrbits32(®s->tcr, GPIO_MASK(gpio)); gen_gc->sdir &=3D ~GPIO_MASK(gpio); =20 /* Bits 0-15 use TSRL/OSRL, bits 16-31 use TSRH/OSRH */ if (gpio < 16) { - clrbits32(®s->osrl, GPIO_MASK2(gpio)); - clrbits32(®s->tsrl, GPIO_MASK2(gpio)); + ppc44x_clrbits32(®s->osrl, GPIO_MASK2(gpio)); + ppc44x_clrbits32(®s->tsrl, GPIO_MASK2(gpio)); } else { - clrbits32(®s->osrh, GPIO_MASK2(gpio)); - clrbits32(®s->tsrh, GPIO_MASK2(gpio)); + ppc44x_clrbits32(®s->osrh, GPIO_MASK2(gpio)); + ppc44x_clrbits32(®s->tsrh, GPIO_MASK2(gpio)); } =20 return 0; @@ -108,19 +124,19 @@ ppc44x_gpio_dir_out(struct gpio_chip *gc, unsigned in= t gpio, int val) __ppc44x_gpio_set(gc, gpio, val); =20 /* Disable open-drain function */ - clrbits32(®s->odr, GPIO_MASK(gpio)); + ppc44x_clrbits32(®s->odr, GPIO_MASK(gpio)); =20 /* Drive the pin */ - setbits32(®s->tcr, GPIO_MASK(gpio)); + ppc44x_setbits32(®s->tcr, GPIO_MASK(gpio)); gen_gc->sdir |=3D GPIO_MASK(gpio); =20 /* Bits 0-15 use TSRL, bits 16-31 use TSRH */ if (gpio < 16) { - clrbits32(®s->osrl, GPIO_MASK2(gpio)); - clrbits32(®s->tsrl, GPIO_MASK2(gpio)); + ppc44x_clrbits32(®s->osrl, GPIO_MASK2(gpio)); + ppc44x_clrbits32(®s->tsrl, GPIO_MASK2(gpio)); } else { - clrbits32(®s->osrh, GPIO_MASK2(gpio)); - clrbits32(®s->tsrh, GPIO_MASK2(gpio)); + ppc44x_clrbits32(®s->osrh, GPIO_MASK2(gpio)); + ppc44x_clrbits32(®s->tsrh, GPIO_MASK2(gpio)); } =20 pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val); --=20 2.55.0 From nobody Fri Oct 2 07:45:31 2026 Received: from mail-pf1-f175.google.com (mail-pf1-f175.google.com [209.85.210.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 326FA35AC37 for ; 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Mon, 03 Aug 2026 15:35:54 -0700 (PDT) Received: from ryzen.lan ([2601:644:8000:7a86::e35]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84edc2d4473sm4186790b3a.40.2026.08.03.15.35.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 15:35:53 -0700 (PDT) From: Rosen Penev To: linux-gpio@vger.kernel.org Cc: Madhavan Srinivasan , Michael Ellerman , Nicholas Piggin , "Christophe Leroy (CS GROUP)" , Linus Walleij , Bartosz Golaszewski , linuxppc-dev@lists.ozlabs.org (open list:LINUX FOR POWERPC (32-BIT AND 64-BIT)), linux-kernel@vger.kernel.org (open list) Subject: [PATCHv2 7/8] gpio: ppc44x: fix undefined behavior in GPIO_MASK2 macro Date: Mon, 3 Aug 2026 15:35:38 -0700 Message-ID: <20260803223539.86303-8-rosenp@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803223539.86303-1-rosenp@gmail.com> References: <20260803223539.86303-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Shifting a 32-bit unsigned integer by 32 or more places is undefined behavior in C. GPIO_MASK2 computes its shift amount as (gpio) * 2, and for pins 16-31 in the OSRH/TSRH bank this yields shifts of 32-62. While this happens to work on PowerPC because slw masks the shift count to the low 5 bits, compilers performing value-range propagation may assume the else branch is unreachable and optimize it away, or may evaluate the shift as zero on other architectures via COMPILE_TEST. Mask gpio to the 16-pin bank index so the shift stays within [0, 30]. The registers are banked (OSRL/TSRL for gpio 0-15, OSRH/TSRH for gpio 16-31) with an identical 2-bit-per-pin layout from MSB to LSB, so masking to the within-bank index preserves the intended behavior. Assisted-by: opencode:big-pickle Signed-off-by: Rosen Penev Reviewed-by: Linus Walleij --- drivers/gpio/gpio-ppc44x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-ppc44x.c b/drivers/gpio/gpio-ppc44x.c index fd543fbb959a..9fdc84e922f4 100644 --- a/drivers/gpio/gpio-ppc44x.c +++ b/drivers/gpio/gpio-ppc44x.c @@ -19,7 +19,7 @@ #include =20 #define GPIO_MASK(gpio) (0x80000000 >> (gpio)) -#define GPIO_MASK2(gpio) (0xc0000000 >> ((gpio) * 2)) +#define GPIO_MASK2(gpio) (0xc0000000 >> (((gpio) % 16) * 2)) =20 /* Physical GPIO register layout */ struct ppc44x_gpio { --=20 2.55.0 From nobody Fri Oct 2 07:45:31 2026 Received: from mail-pf1-f177.google.com (mail-pf1-f177.google.com [209.85.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 93D6A35E955 for ; Mon, 3 Aug 2026 22:35:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.177 ARC-Seal: i=1; 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Mon, 03 Aug 2026 15:35:56 -0700 (PDT) Received: from ryzen.lan ([2601:644:8000:7a86::e35]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84edc2d4473sm4186790b3a.40.2026.08.03.15.35.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 15:35:55 -0700 (PDT) From: Rosen Penev To: linux-gpio@vger.kernel.org Cc: Madhavan Srinivasan , Michael Ellerman , Nicholas Piggin , "Christophe Leroy (CS GROUP)" , Linus Walleij , Bartosz Golaszewski , linuxppc-dev@lists.ozlabs.org (open list:LINUX FOR POWERPC (32-BIT AND 64-BIT)), linux-kernel@vger.kernel.org (open list) Subject: [PATCHv2 8/8] gpio: ppc44x: use dev_name() for chip label Date: Mon, 3 Aug 2026 15:35:39 -0700 Message-ID: <20260803223539.86303-9-rosenp@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803223539.86303-1-rosenp@gmail.com> References: <20260803223539.86303-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Replace devm_kasprintf() with dev_name() for the chip label. dev_name() returns a stable pointer to the device name, so the separate allocation and -ENOMEM check can be dropped. Using dev_name() seems to be common for GPIO labels. Signed-off-by: Rosen Penev Reviewed-by: Linus Walleij --- drivers/gpio/gpio-ppc44x.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/gpio/gpio-ppc44x.c b/drivers/gpio/gpio-ppc44x.c index 9fdc84e922f4..189667e0e1ba 100644 --- a/drivers/gpio/gpio-ppc44x.c +++ b/drivers/gpio/gpio-ppc44x.c @@ -147,7 +147,6 @@ ppc44x_gpio_dir_out(struct gpio_chip *gc, unsigned int = gpio, int val) static int ppc44x_gpio_probe(struct platform_device *ofdev) { struct device *dev =3D &ofdev->dev; - struct device_node *np =3D dev->of_node; struct ppc44x_gpio __iomem *regs; struct ppc44x_gpio_chip *chip; struct gpio_generic_chip_config config; @@ -179,14 +178,11 @@ static int ppc44x_gpio_probe(struct platform_device *= ofdev) return ret; =20 gc =3D &chip->chip.gc; + gc->label =3D dev_name(dev); gc->parent =3D dev; gc->direction_input =3D ppc44x_gpio_dir_in; gc->direction_output =3D ppc44x_gpio_dir_out; =20 - gc->label =3D devm_kasprintf(dev, GFP_KERNEL, "%pOF", np); - if (!gc->label) - return -ENOMEM; - return devm_gpiochip_add_data(dev, gc, chip); } =20 --=20 2.55.0