From nobody Fri Oct 2 07:46:57 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 127893B47C4; Mon, 3 Aug 2026 21:05:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785791142; cv=none; b=frKn7EytWnzXeL6G7hNAQQWQWTddt2Uv1vKTM3wXxBtwJbr/QMCJge+zcx7f7MC4S6UuGtPE56JTEKHDXXfpZGLCIWVGFKDYlli7mIqjAePPDBsIg+839uemYXQM7fEvMVrD3mQqAMhSK/ratQx2E+TqqG0iXwSL6ehFI5Or9+k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785791142; c=relaxed/simple; bh=dMB18QgeVAdPqzBMAuUOG2aj6yCR7463Svrc+87yX68=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=fQetaI4pPSgvJWkAVRZ3KZPfNhxuMiCpxRAf9sh+r1osmH6Ls0Lxg/0e8dZaecM5bUoQSABmU+3uwMEu85r4RUWQFbVoKwn9T5DGUm7wYYUwk1hUuE0cLswd4lLqO7lFR9aLq5yIq90vsrpKSxpevTXinbqq63rZDFUsS2iH8kc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=LPnNZk4G; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="LPnNZk4G" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 717121476; Mon, 3 Aug 2026 14:05:36 -0700 (PDT) Received: from e127648.arm.com (unknown [10.57.0.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 3E1923F86F; Mon, 3 Aug 2026 14:05:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1785791140; bh=dMB18QgeVAdPqzBMAuUOG2aj6yCR7463Svrc+87yX68=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LPnNZk4GcTaF6g2j76B+zCTIw2JhUHkcP1dFYvLUaO4L34VBCD3rFOvBkrJDmx4oW 4MD+FX5620yj8ARscQV/tVlxhlSCIQSyQNMn37YKj2mHPMOgYEytKmaeSMae2hy//5 kw/xMTmMEvOMbXQTYpqqlSg/PNlUhUqDAi1wYm+Q= From: Christian Loehle To: "Rafael J . Wysocki" , Viresh Kumar Cc: linux-pm@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, Len Brown , Jie Zhan , Lifeng Zheng , Pierre Gondois , Sumit Gupta , Sudeep Holla , Ionela Voinescu , zhongqiu.han@oss.qualcomm.com, Christian Loehle Subject: [PATCH 1/3] ACPI: CPPC: Avoid unnecessary reads for full-width writes Date: Mon, 3 Aug 2026 22:05:25 +0100 Message-Id: <20260803210527.1285229-2-christian.loehle@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260803210527.1285229-1-christian.loehle@arm.com> References: <20260803210527.1285229-1-christian.loehle@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" SystemMemory GAS entries may describe a field within a wider access unit, so cpc_write() reads the access unit before updating the field to preserve the surrounding bits. It also does this when the field covers the complete access unit. When the bit offset is zero and the register bit width equals the resolved access width, the previous value cannot affect the result. Skip the MMIO read and mask operation in that case. Retain rmw_lock because another entry in the same _CPC package may share the access unit. Signed-off-by: Christian Loehle Reviewed-by: Zhongqiu Han --- drivers/acpi/cppc_acpi.c | 43 ++++++++++++++++++++++++---------------- 1 file changed, 26 insertions(+), 17 deletions(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 53d09ca98f06..9b8d68b44ea9 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1162,25 +1162,34 @@ static int cpc_write(int cpu, struct cpc_register_r= esource *reg_res, u64 val) return -ENODEV; } =20 + /* + * Only partial fields need the previous contents to preserve bits + * outside the field. Keep serializing full-width writes because + * another _CPC entry may share the access unit and require RMW. + */ raw_spin_lock_irqsave(&cpc_desc->rmw_lock, flags); - switch (size) { - case 8: - prev_val =3D readb_relaxed(vaddr); - break; - case 16: - prev_val =3D readw_relaxed(vaddr); - break; - case 32: - prev_val =3D readl_relaxed(vaddr); - break; - case 64: - prev_val =3D readq_relaxed(vaddr); - break; - default: - raw_spin_unlock_irqrestore(&cpc_desc->rmw_lock, flags); - return -EFAULT; + + if (reg->bit_offset || reg->bit_width !=3D size) { + switch (size) { + case 8: + prev_val =3D readb_relaxed(vaddr); + break; + case 16: + prev_val =3D readw_relaxed(vaddr); + break; + case 32: + prev_val =3D readl_relaxed(vaddr); + break; + case 64: + prev_val =3D readq_relaxed(vaddr); + break; + default: + raw_spin_unlock_irqrestore(&cpc_desc->rmw_lock, + flags); + return -EFAULT; + } + val =3D MASK_VAL_WRITE(reg, prev_val, val); } - val =3D MASK_VAL_WRITE(reg, prev_val, val); } =20 switch (size) { --=20 2.34.1 From nobody Fri Oct 2 07:46:57 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BD82B3B71C6; Mon, 3 Aug 2026 21:05:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785791145; cv=none; b=nPLCqE3qfK0Om2bN1C9w+hVrZSH4kc+n87mcRNG0h1TQJdp/1CfvoFUGFkIxxYWvYv55vSHjGOQ5EALbgjvZBGKOwaeQEJqnwSqO6KZXkEeerWUjxRN1oQGqHeItwSzp28wheRG7MxtMzufp0lqUZXp/xbefWVsjwVdTRqZOqbY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785791145; c=relaxed/simple; bh=gq9J1RvWC89pSiDbdZPLorYduWb+4Hbnf2Jhd3DjhiQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=H83zOPNCccbRgjhUAeZTQw5u1XLzCb4QblIUVK0Zu99CF1ljdIbsGsw33FxByCzJT0P1ECCWgk2raymYdgQo/ZZx6qDQlvBSjT3E8pRWL3yDEzaIU9YTWe9mFiE6TvedPcBx2S1E9/ojuueny76/CMD/fFQTpldElRKGOeJR+90= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=q79hImrF; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="q79hImrF" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0B03E143D; Mon, 3 Aug 2026 14:05:39 -0700 (PDT) Received: from e127648.arm.com (unknown [10.57.0.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id CFE803F86F; Mon, 3 Aug 2026 14:05:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1785791143; bh=gq9J1RvWC89pSiDbdZPLorYduWb+4Hbnf2Jhd3DjhiQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=q79hImrFDuwV9ADDuIoiwjGdoSYITlBcVg83GjTBIwbSj88kOzwnjDf1qkPh+4sxf WMPfxFHC+dHHrL74KgxihIcUNzNBdn2qOveHJteQAse6u1t2O9+OY7y0DRQ11H0YsF yEiKaa0MNfX5kpdn9N58HTdeYxNpHudRJKUlqfeM= From: Christian Loehle To: "Rafael J . Wysocki" , Viresh Kumar Cc: linux-pm@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, Len Brown , Jie Zhan , Lifeng Zheng , Pierre Gondois , Sumit Gupta , Sudeep Holla , Ionela Voinescu , zhongqiu.han@oss.qualcomm.com, Christian Loehle Subject: [PATCH 2/3] ACPI: CPPC: Avoid locking standalone full-width registers Date: Mon, 3 Aug 2026 22:05:26 +0100 Message-Id: <20260803210527.1285229-3-christian.loehle@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260803210527.1285229-1-christian.loehle@arm.com> References: <20260803210527.1285229-1-christian.loehle@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" cpc_write() serializes every SystemMemory write with the per-CPU rmw_lock. The lock is required for read-modify-write fields and for registers whose access units overlap, but not for a full-width register in a standalone access unit. The _CPC layout is immutable after it has been parsed. Classify each SystemMemory register at probe time and retain locking for partial fields, invalid access widths, and overlapping access units. Allow standalone full-width registers to bypass the descriptor lookup and spinlock. Store the classification in existing structure padding so that struct cpc_register_resource does not grow. Signed-off-by: Christian Loehle --- drivers/acpi/cppc_acpi.c | 97 ++++++++++++++++++++++++++++++++++------ include/acpi/cppc_acpi.h | 5 ++- 2 files changed, 88 insertions(+), 14 deletions(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 9b8d68b44ea9..2793d6b7d40d 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -200,6 +200,72 @@ show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, = wraparound_time); ((((val) & GENMASK(((reg)->bit_width) - 1, 0)) << (reg)->bit_offset) | \ ((prev_val) & ~(GENMASK(((reg)->bit_width) - 1, 0) << (reg)->bit_offset))= ) \ =20 +static u64 cpc_sysmem_access_size(const struct cpc_register_resource *reg) +{ + const struct cpc_reg *gas =3D ®->cpc_entry.reg; + unsigned int width; + + if (gas->access_width > 4) + return 0; + + width =3D GET_BIT_WIDTH(gas); + + if (width !=3D 8 && width !=3D 16 && width !=3D 32 && width !=3D 64) + return 0; + + return width / 8; +} + +static bool cpc_sysmem_access_units_overlap(const struct cpc_register_reso= urce *a, + const struct cpc_register_resource *b) +{ + const struct cpc_reg *a_gas =3D &a->cpc_entry.reg; + const struct cpc_reg *b_gas =3D &b->cpc_entry.reg; + u64 a_size =3D cpc_sysmem_access_size(a); + u64 b_size =3D cpc_sysmem_access_size(b); + + /* Keep the conservative locking path for malformed access widths. */ + if (!a_size || !b_size) + return true; + + if (a_gas->address < b_gas->address) + return b_gas->address - a_gas->address < a_size; + + return a_gas->address - b_gas->address < b_size; +} + +static void cpc_mark_rmw_lock_users(struct cpc_desc *cpc_desc) +{ + int i, j; + + for (i =3D 0; i < cpc_desc->num_entries - 2; i++) { + struct cpc_register_resource *a =3D &cpc_desc->cpc_regs[i]; + struct cpc_reg *gas; + u64 access_size; + + if (!CPC_SUPPORTED(a) || !CPC_IN_SYSTEM_MEMORY(a)) + continue; + + gas =3D &a->cpc_entry.reg; + access_size =3D cpc_sysmem_access_size(a); + if (gas->bit_offset || !access_size || + gas->bit_width !=3D access_size * 8) + a->cpc_entry.use_rmw_lock =3D true; + + for (j =3D i + 1; j < cpc_desc->num_entries - 2; j++) { + struct cpc_register_resource *b =3D &cpc_desc->cpc_regs[j]; + + if (!CPC_SUPPORTED(b) || !CPC_IN_SYSTEM_MEMORY(b)) + continue; + if (!cpc_sysmem_access_units_overlap(a, b)) + continue; + + a->cpc_entry.use_rmw_lock =3D true; + b->cpc_entry.use_rmw_lock =3D true; + } + } +} + static ssize_t show_feedback_ctrs(struct kobject *kobj, struct kobj_attribute *attr, char *buf) { @@ -904,6 +970,7 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr) =20 /* Store CPU Logical ID */ cpc_ptr->cpu_id =3D pr->id; + cpc_mark_rmw_lock_users(cpc_ptr); raw_spin_lock_init(&cpc_ptr->rmw_lock); =20 /* Parse PSD data for this CPU */ @@ -1123,6 +1190,7 @@ static int cpc_write(int cpu, struct cpc_register_res= ource *reg_res, u64 val) struct cpc_reg *reg =3D ®_res->cpc_entry.reg; struct cpc_desc *cpc_desc; unsigned long flags; + bool locked =3D false; =20 size =3D GET_BIT_WIDTH(reg); =20 @@ -1156,18 +1224,20 @@ static int cpc_write(int cpu, struct cpc_register_r= esource *reg_res, u64 val) val, size); =20 if (reg->space_id =3D=3D ACPI_ADR_SPACE_SYSTEM_MEMORY) { - cpc_desc =3D per_cpu(cpc_desc_ptr, cpu); - if (!cpc_desc) { - pr_debug("No CPC descriptor for CPU:%d\n", cpu); - return -ENODEV; - } - /* - * Only partial fields need the previous contents to preserve bits - * outside the field. Keep serializing full-width writes because - * another _CPC entry may share the access unit and require RMW. + * The _CPC layout is immutable after probe. The precomputed flag + * retains serialization for partial fields or overlapping access + * units; standalone full-width registers avoid the lock. */ - raw_spin_lock_irqsave(&cpc_desc->rmw_lock, flags); + locked =3D reg_res->cpc_entry.use_rmw_lock; + if (locked) { + cpc_desc =3D per_cpu(cpc_desc_ptr, cpu); + if (!cpc_desc) { + pr_debug("No CPC descriptor for CPU:%d\n", cpu); + return -ENODEV; + } + raw_spin_lock_irqsave(&cpc_desc->rmw_lock, flags); + } =20 if (reg->bit_offset || reg->bit_width !=3D size) { switch (size) { @@ -1184,8 +1254,9 @@ static int cpc_write(int cpu, struct cpc_register_res= ource *reg_res, u64 val) prev_val =3D readq_relaxed(vaddr); break; default: - raw_spin_unlock_irqrestore(&cpc_desc->rmw_lock, - flags); + if (locked) + raw_spin_unlock_irqrestore(&cpc_desc->rmw_lock, + flags); return -EFAULT; } val =3D MASK_VAL_WRITE(reg, prev_val, val); @@ -1217,7 +1288,7 @@ static int cpc_write(int cpu, struct cpc_register_res= ource *reg_res, u64 val) break; } =20 - if (reg->space_id =3D=3D ACPI_ADR_SPACE_SYSTEM_MEMORY) + if (locked) raw_spin_unlock_irqrestore(&cpc_desc->rmw_lock, flags); =20 return ret_val; diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index 8c191b9ac18f..19830146c644 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -69,7 +69,10 @@ struct cpc_register_resource { acpi_object_type type; u64 __iomem *sys_mem_vaddr; union { - struct cpc_reg reg; + struct { + struct cpc_reg reg; + bool use_rmw_lock; + }; u64 int_value; } cpc_entry; }; --=20 2.34.1 From nobody Fri Oct 2 07:46:57 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 53B1A2D8795; Mon, 3 Aug 2026 21:05:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785791148; cv=none; b=EXS5xmBERrTQq7I40roPixMUbVttLXqfGDOLg6jBU9ZUvzLw4NPqpvn3QgWfCOPz5VdB8Bg5uOY8QPvWKVSOG2ViUySe0IaPHDEo1oAvP8kaV3ujEmnIbQXmKRRkYkBFAdKFJz++Hba4xfdqgzIXy0RPlYCQMa0xJMK0aE3rQGA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785791148; c=relaxed/simple; bh=eNP5GqOW7zsH2R03Okaf82MSE794/afd4AaWtwVDhXs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=theHeh6AhaXE/44ZZnlod4z4H8aoXapUct5RUyK8txHfHEOQ6Xvosle1etOICkREGTsR/+v2Ce9WfHSKcm1bPQl/gvO3DBUx5mKXBZr8KFx4HM3bepSbHWqPmXIcy+1VDyc61RlkrJeUfD8WAK6LcHpd4S4sU8YG3GFc+N3qlMA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=YQWWQvr/; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="YQWWQvr/" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A2A301476; Mon, 3 Aug 2026 14:05:41 -0700 (PDT) Received: from e127648.arm.com (unknown [10.57.0.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 6FA703F86F; Mon, 3 Aug 2026 14:05:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1785791145; bh=eNP5GqOW7zsH2R03Okaf82MSE794/afd4AaWtwVDhXs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YQWWQvr/f3KrOx5TGL6xHVRegyjjUQo2S1ujWcuSYY7bv+DgtJNVO6+7ZbIhoHruh gOV/WP1hMIe0mi42z+2X+IvRv2Y/ry6xHD6ICNavHRCK2MVJ2GrKhOsQS5m7nqO93K aVNHGC1jmAYclQ+4FlvinrqYeVP+2eU+B2Tdir0g= From: Christian Loehle To: "Rafael J . Wysocki" , Viresh Kumar Cc: linux-pm@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, Len Brown , Jie Zhan , Lifeng Zheng , Pierre Gondois , Sumit Gupta , Sudeep Holla , Ionela Voinescu , zhongqiu.han@oss.qualcomm.com, Christian Loehle Subject: [PATCH 3/3] ACPI: CPPC: Evaluate performance-control PCC use once Date: Mon, 3 Aug 2026 22:05:27 +0100 Message-Id: <20260803210527.1285229-4-christian.loehle@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260803210527.1285229-1-christian.loehle@arm.com> References: <20260803210527.1285229-1-christian.loehle@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" cppc_set_perf() evaluates the same immutable address-space predicates before and after each phase of a performance-control update. This repeats the three-control PCC test three times for every target request. Evaluate the predicate once after resolving the control descriptors and reuse the result throughout the transaction. Signed-off-by: Christian Loehle --- drivers/acpi/cppc_acpi.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 2793d6b7d40d..cd1c4a30eb6f 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -2002,6 +2002,7 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *pe= rf_ctrls) struct cpc_register_resource *desired_reg, *min_perf_reg, *max_perf_reg; int pcc_ss_id =3D per_cpu(cpu_pcc_subspace_idx, cpu); struct cppc_pcc_data *pcc_ss_data =3D NULL; + bool regs_in_pcc; int ret =3D 0; =20 if (!cpc_desc) { @@ -2012,6 +2013,8 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *pe= rf_ctrls) desired_reg =3D &cpc_desc->cpc_regs[DESIRED_PERF]; min_perf_reg =3D &cpc_desc->cpc_regs[MIN_PERF]; max_perf_reg =3D &cpc_desc->cpc_regs[MAX_PERF]; + regs_in_pcc =3D CPC_IN_PCC(desired_reg) || CPC_IN_PCC(min_perf_reg) || + CPC_IN_PCC(max_perf_reg); =20 /* * This is Phase-I where we want to write to CPC registers @@ -2020,7 +2023,7 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *pe= rf_ctrls) * Since read_lock can be acquired by multiple CPUs simultaneously we * achieve that goal here */ - if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max= _perf_reg)) { + if (regs_in_pcc) { if (pcc_ss_id < 0) { pr_debug("Invalid pcc_ss_id\n"); return -ENODEV; @@ -2056,7 +2059,7 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *pe= rf_ctrls) if (perf_ctrls->max_perf && CPC_SUPPORTED(max_perf_reg)) cpc_write(cpu, max_perf_reg, perf_ctrls->max_perf); =20 - if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max= _perf_reg)) + if (regs_in_pcc) up_read(&pcc_ss_data->pcc_lock); /* END Phase-I */ /* * This is Phase-II where we transfer the ownership of PCC to Platform @@ -2104,7 +2107,7 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *pe= rf_ctrls) * case during a CMD_READ and if there are pending writes it delivers * the write command before servicing the read command */ - if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max= _perf_reg)) { + if (regs_in_pcc) { if (down_write_trylock(&pcc_ss_data->pcc_lock)) {/* BEGIN Phase-II */ /* Update only if there are pending write commands */ if (pcc_ss_data->pending_pcc_write_cmd) --=20 2.34.1