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Mon, 03 Aug 2026 11:08:01 -0700 (PDT) From: =?UTF-8?q?Juan=20Manuel=20L=C3=B3pez=20Carrillo?= To: mturquette@baylibre.com, sboyd@kernel.org, wens@kernel.org, jernej.skrabec@gmail.com, samuel@sholland.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: andre.przywara@arm.com, bmasney@redhat.com, linux-clk@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Juan=20Manuel=20L=C3=B3pez=20Carrillo?= Subject: [PATCH v2 1/3] clk: sunxi-ng: add cycle-masking divider (maskdiv) clock type Date: Mon, 3 Aug 2026 20:07:53 +0200 Message-ID: <20260803180755.288793-2-juanmanuellopezcarrillo@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260803180755.288793-1-juanmanuellopezcarrillo@gmail.com> References: <20260803180755.288793-1-juanmanuellopezcarrillo@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Some mod clocks do not divide their parent with a linear M+1 divider: the M factor masks (swallows) M pulses out of every 2^width parent cycles, so the average output rate is rate =3D parent * (2^width - M) / 2^width and the surviving pulses keep the parent period. The A523/T527 GPU clock (GPU_CLK_REG, 0x670) is such a divider: "FACTOR_M: mask M cycles at 16 cycles", GPU_CLK =3D Clock Source * ((16-M)/16) (T527 user manual v0.92, section 2.7.6.58). Modelling these registers with the linear ccu_div type programs a faster clock than requested for every M > 0 (e.g. M=3D1 on a 800 MHz parent yields 750 MHz, not 400 MHz). Add a small ccu type implementing the masking semantics. Because the masked output is not an even pulse train, determine_rate prefers, among the parents that reach the requested rate, the one needing the least masking, and clamps the result to the request's min_rate/max_rate bounds. set_rate_and_parent follows the same ordering rule as clk_composite_set_rate_and_parent() so no intermediate configuration overshoots both the old and the new rate, and honours the CCU_FEATURE_UPDATE_BIT and CCU_FEATURE_KEY_FIELD features, so the type can be reused on registers that need them. CLK_SET_RATE_PARENT is deliberately not supported: the masking factor and a parent rate change are two independent knobs and picking a combination of both is out of scope for this type. Signed-off-by: Juan Manuel L=C3=B3pez Carrillo --- drivers/clk/sunxi-ng/Makefile | 1 + drivers/clk/sunxi-ng/ccu_common.h | 3 + drivers/clk/sunxi-ng/ccu_maskdiv.c | 213 +++++++++++++++++++++++++++++ drivers/clk/sunxi-ng/ccu_maskdiv.h | 76 ++++++++++ drivers/clk/sunxi-ng/ccu_mux.c | 2 - 5 files changed, 293 insertions(+), 2 deletions(-) create mode 100644 drivers/clk/sunxi-ng/ccu_maskdiv.c create mode 100644 drivers/clk/sunxi-ng/ccu_maskdiv.h diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile index a1c4087d7241..26313083c2f8 100644 --- a/drivers/clk/sunxi-ng/Makefile +++ b/drivers/clk/sunxi-ng/Makefile @@ -10,6 +10,7 @@ sunxi-ccu-y +=3D ccu_reset.o # Base clock types sunxi-ccu-y +=3D ccu_div.o sunxi-ccu-y +=3D ccu_frac.o +sunxi-ccu-y +=3D ccu_maskdiv.o sunxi-ccu-y +=3D ccu_gate.o sunxi-ccu-y +=3D ccu_mux.o sunxi-ccu-y +=3D ccu_mult.o diff --git a/drivers/clk/sunxi-ng/ccu_common.h b/drivers/clk/sunxi-ng/ccu_c= ommon.h index d9dc24ad5503..0260af263d05 100644 --- a/drivers/clk/sunxi-ng/ccu_common.h +++ b/drivers/clk/sunxi-ng/ccu_common.h @@ -29,6 +29,9 @@ /* Some clocks need this bit to actually apply register changes */ #define CCU_SUNXI_UPDATE_BIT BIT(27) =20 +/* Key value for clocks with CCU_FEATURE_KEY_FIELD (reads as zero) */ +#define CCU_MUX_KEY_VALUE 0x16aa0000 + struct device_node; =20 struct ccu_common { diff --git a/drivers/clk/sunxi-ng/ccu_maskdiv.c b/drivers/clk/sunxi-ng/ccu_= maskdiv.c new file mode 100644 index 000000000000..4ad49d51405b --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu_maskdiv.c @@ -0,0 +1,213 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2026 Juan Manuel L=C3=B3pez Carrillo + * + * Cycle-masking divider: the M factor masks M pulses out of every + * 2^width parent cycles instead of dividing the parent rate, so + * + * rate =3D parent * (2^width - M) / 2^width + * + * The masked output is not an even pulse train: the surviving pulses + * keep the parent period. Rate selection therefore prefers, among the + * parents that reach the requested rate, the one needing the least + * masking. + */ + +#include +#include +#include + +#include "ccu_gate.h" +#include "ccu_maskdiv.h" + +static unsigned long ccu_maskdiv_calc_rate(unsigned long parent_rate, + unsigned int m, unsigned int width) +{ + unsigned int n =3D 1 << width; + + return div_u64((u64)parent_rate * (n - m), n); +} + +/* + * Smallest M (least masking) whose output does not exceed the requested + * rate; masking everything (M =3D=3D 2^width) is never returned. + */ +static unsigned int ccu_maskdiv_find_m(unsigned long parent_rate, + unsigned long rate, unsigned int width) +{ + unsigned int n =3D 1 << width; + u64 kept; + + if (!parent_rate || rate >=3D parent_rate) + return 0; + + kept =3D div64_ul((u64)rate * n, parent_rate); + if (!kept) + kept =3D 1; + + return n - (unsigned int)kept; +} + +static void ccu_maskdiv_disable(struct clk_hw *hw) +{ + struct ccu_maskdiv *cmd =3D hw_to_ccu_maskdiv(hw); + + return ccu_gate_helper_disable(&cmd->common, cmd->enable); +} + +static int ccu_maskdiv_enable(struct clk_hw *hw) +{ + struct ccu_maskdiv *cmd =3D hw_to_ccu_maskdiv(hw); + + return ccu_gate_helper_enable(&cmd->common, cmd->enable); +} + +static int ccu_maskdiv_is_enabled(struct clk_hw *hw) +{ + struct ccu_maskdiv *cmd =3D hw_to_ccu_maskdiv(hw); + + return ccu_gate_helper_is_enabled(&cmd->common, cmd->enable); +} + +static unsigned long ccu_maskdiv_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct ccu_maskdiv *cmd =3D hw_to_ccu_maskdiv(hw); + unsigned int m; + u32 reg; + + reg =3D readl(cmd->common.base + cmd->common.reg); + m =3D (reg >> cmd->shift) & ((1 << cmd->width) - 1); + + return ccu_maskdiv_calc_rate(parent_rate, m, cmd->width); +} + +static int ccu_maskdiv_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct ccu_maskdiv *cmd =3D hw_to_ccu_maskdiv(hw); + unsigned long best_rate =3D 0, best_parent_rate =3D 0; + struct clk_hw *best_parent =3D NULL; + unsigned int best_m =3D UINT_MAX; + unsigned int i; + + for (i =3D 0; i < clk_hw_get_num_parents(hw); i++) { + struct clk_hw *parent =3D clk_hw_get_parent_by_index(hw, i); + unsigned long parent_rate, new_rate; + unsigned int m; + + if (!parent) + continue; + + parent_rate =3D clk_hw_get_rate(parent); + m =3D ccu_maskdiv_find_m(parent_rate, req->rate, cmd->width); + new_rate =3D ccu_maskdiv_calc_rate(parent_rate, m, cmd->width); + + if (new_rate > req->rate) + continue; + + /* + * Reject rates outside the framework's bounds: a maskdiv + * rounds by masking parent cycles, so it can only produce + * sub-multiples of a parent rate; without this check a + * consumer asking for, say, a tight [max_rate, max_rate] + * window would silently get a smaller rate. + */ + if (new_rate < req->min_rate || new_rate > req->max_rate) + continue; + + /* Closest rate first; on ties, the least masking */ + if (new_rate > best_rate || + (new_rate =3D=3D best_rate && m < best_m)) { + best_rate =3D new_rate; + best_parent_rate =3D parent_rate; + best_parent =3D parent; + best_m =3D m; + } + } + + if (!best_parent) + return -EINVAL; + + req->best_parent_hw =3D best_parent; + req->best_parent_rate =3D best_parent_rate; + req->rate =3D best_rate; + + return 0; +} + +static int ccu_maskdiv_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct ccu_maskdiv *cmd =3D hw_to_ccu_maskdiv(hw); + unsigned int m; + unsigned long flags; + u32 reg; + + m =3D ccu_maskdiv_find_m(parent_rate, rate, cmd->width); + + spin_lock_irqsave(cmd->common.lock, flags); + + reg =3D readl(cmd->common.base + cmd->common.reg); + reg &=3D ~GENMASK(cmd->shift + cmd->width - 1, cmd->shift); + if (cmd->common.features & CCU_FEATURE_KEY_FIELD) + reg |=3D CCU_MUX_KEY_VALUE; + if (cmd->common.features & CCU_FEATURE_UPDATE_BIT) + reg |=3D CCU_SUNXI_UPDATE_BIT; + writel(reg | (m << cmd->shift), cmd->common.base + cmd->common.reg); + + spin_unlock_irqrestore(cmd->common.lock, flags); + + return 0; +} + +static u8 ccu_maskdiv_get_parent(struct clk_hw *hw) +{ + struct ccu_maskdiv *cmd =3D hw_to_ccu_maskdiv(hw); + + return ccu_mux_helper_get_parent(&cmd->common, &cmd->mux); +} + +static int ccu_maskdiv_set_parent(struct clk_hw *hw, u8 index) +{ + struct ccu_maskdiv *cmd =3D hw_to_ccu_maskdiv(hw); + + return ccu_mux_helper_set_parent(&cmd->common, &cmd->mux, index); +} + +static int ccu_maskdiv_set_rate_and_parent(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate, u8 index) +{ + /* + * Same ordering rule as clk_composite_set_rate_and_parent(): if + * switching the mux with the current M would overshoot the + * requested rate, program the divider first, so the + * intermediate rate never exceeds both the old and the new + * rate. + */ + if (ccu_maskdiv_recalc_rate(hw, parent_rate) > rate) { + ccu_maskdiv_set_rate(hw, rate, parent_rate); + ccu_maskdiv_set_parent(hw, index); + } else { + ccu_maskdiv_set_parent(hw, index); + ccu_maskdiv_set_rate(hw, rate, parent_rate); + } + + return 0; +} + +const struct clk_ops ccu_maskdiv_ops =3D { + .disable =3D ccu_maskdiv_disable, + .enable =3D ccu_maskdiv_enable, + .is_enabled =3D ccu_maskdiv_is_enabled, + + .get_parent =3D ccu_maskdiv_get_parent, + .set_parent =3D ccu_maskdiv_set_parent, + + .determine_rate =3D ccu_maskdiv_determine_rate, + .recalc_rate =3D ccu_maskdiv_recalc_rate, + .set_rate =3D ccu_maskdiv_set_rate, + .set_rate_and_parent =3D ccu_maskdiv_set_rate_and_parent, +}; +EXPORT_SYMBOL_NS_GPL(ccu_maskdiv_ops, "SUNXI_CCU"); diff --git a/drivers/clk/sunxi-ng/ccu_maskdiv.h b/drivers/clk/sunxi-ng/ccu_= maskdiv.h new file mode 100644 index 000000000000..e070798f1533 --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu_maskdiv.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2026 Juan Manuel L=C3=B3pez Carrillo + */ + +#ifndef _CCU_MASKDIV_H_ +#define _CCU_MASKDIV_H_ + +#include + +#include "ccu_common.h" +#include "ccu_mux.h" + +/* + * struct ccu_maskdiv - cycle-masking ("fractional") divider + * + * This divider does not divide the parent clock: it masks (swallows) M + * pulses out of every 2^width parent cycles, so the average output rate + * is + * + * rate =3D parent * (2^width - M) / 2^width + * + * with the remaining pulses keeping the parent period. The A523/T527 + * GPU clock (GPU_CLK_REG, 0x670) is such a divider: "FACTOR_M: mask M + * cycles at 16 cycles", GPU_CLK =3D Clock Source * ((16-M)/16) (T527 user + * manual v0.92, section 2.7.6.58). + * + * This type does not support CLK_SET_RATE_PARENT: determine_rate + * evaluates parents at their current rate and does not propagate rate + * requests upstream. If a future user needs parent rate propagation, + * switch to clk_hw_round_rate() in the determine_rate loop. + * + * @shift: shift of the M field in the register + * @width: width of the M field; the mask window is 2^width cycles + */ +struct ccu_maskdiv { + u32 enable; + + u8 shift; + u8 width; + + struct ccu_mux_internal mux; + struct ccu_common common; +}; + +#define SUNXI_CCU_MASKDIV_HW_WITH_MUX_TABLE_GATE(_struct, _name, \ + _parents, _table, \ + _reg, \ + _mshift, _mwidth, \ + _muxshift, _muxwidth, \ + _gate, _flags) \ + struct ccu_maskdiv _struct =3D { \ + .enable =3D _gate, \ + .shift =3D _mshift, \ + .width =3D _mwidth, \ + .mux =3D _SUNXI_CCU_MUX_TABLE(_muxshift, _muxwidth, \ + _table), \ + .common =3D { \ + .reg =3D _reg, \ + .hw.init =3D CLK_HW_INIT_PARENTS_HW(_name, \ + _parents, \ + &ccu_maskdiv_ops, \ + _flags), \ + }, \ + } + +static inline struct ccu_maskdiv *hw_to_ccu_maskdiv(struct clk_hw *hw) +{ + struct ccu_common *common =3D hw_to_ccu_common(hw); + + return container_of(common, struct ccu_maskdiv, common); +} + +extern const struct clk_ops ccu_maskdiv_ops; + +#endif /* _CCU_MASKDIV_H_ */ diff --git a/drivers/clk/sunxi-ng/ccu_mux.c b/drivers/clk/sunxi-ng/ccu_mux.c index 4503c9780c39..fa1f5fd2a1fd 100644 --- a/drivers/clk/sunxi-ng/ccu_mux.c +++ b/drivers/clk/sunxi-ng/ccu_mux.c @@ -12,8 +12,6 @@ #include "ccu_gate.h" #include "ccu_mux.h" =20 -#define CCU_MUX_KEY_VALUE 0x16aa0000 - static u16 ccu_mux_get_prediv(struct ccu_common *common, struct ccu_mux_internal *cm, int parent_index) --=20 2.47.3 From nobody Fri Oct 2 07:46:24 2026 Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D671D43800C for ; Mon, 3 Aug 2026 18:08:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785780488; cv=none; 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Mon, 03 Aug 2026 11:08:03 -0700 (PDT) Received: from localhost.localdomain ([2a0d:3344:2841:7708:a101:2b8a:f76:a00f]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47fd42d91b3sm37950955f8f.14.2026.08.03.11.08.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 11:08:03 -0700 (PDT) From: =?UTF-8?q?Juan=20Manuel=20L=C3=B3pez=20Carrillo?= To: mturquette@baylibre.com, sboyd@kernel.org, wens@kernel.org, jernej.skrabec@gmail.com, samuel@sholland.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: andre.przywara@arm.com, bmasney@redhat.com, linux-clk@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Juan=20Manuel=20L=C3=B3pez=20Carrillo?= Subject: [PATCH v2 2/3] clk: sunxi-ng: sun55i-a523: GPU clock divider is fractional, not linear Date: Mon, 3 Aug 2026 20:07:54 +0200 Message-ID: <20260803180755.288793-3-juanmanuellopezcarrillo@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260803180755.288793-1-juanmanuellopezcarrillo@gmail.com> References: <20260803180755.288793-1-juanmanuellopezcarrillo@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The GPU mod clock (0x670) was modelled as a linear M+1 divider, but the M factor of this register is a cycle-masking divider: GPU_CLK =3D Clock Source * ((16-M)/16) (T527 user manual v0.92, section 2.7.6.58). With the linear model every OPP that needed M > 0 silently ran the GPU faster than requested. Measured on an Orange Pi 4A (T527) with the Mali cycle counter against the programmed register: OPP request programmed real rate 150 MHz 600M, M=3D3 487.5 MHz 200 MHz 800M, M=3D3 650 MHz 300 MHz 600M, M=3D1 562.5 MHz 400 MHz 800M, M=3D1 750 MHz 600 MHz 600M, M=3D0 600 MHz i.e. the "400 MHz" OPP ran the GPU at 750 MHz, 25% above the vendor ceiling of 600 MHz, at the low-OPP voltage. Thermal throttling to "400 MHz" actually overclocked the GPU. Switch the clock to the maskdiv type. With least-masking preference the vendor OPP set now resolves to 600/400/300/200 MHz taken undivided from their periph outputs and 150 MHz =3D pll-periph0-200M * 12/16, all verified exact on hardware with the same cycle-counter method. Drop pll-periph0-800M from the selectable parents (the mux table skips hardware index 1): the vendor BSP removed it from its parent list with the comment "If GPU use pll-peri0-800m, gpu will occur job fault", and with the masking semantics every vendor OPP matches exactly from the 800M parent first, so it would otherwise always be chosen. Also drop CLK_SET_RATE_PARENT: every OPP is reachable from the fixed pll-periph0 outputs, and pll-gpu must never be reprogrammed through this mux. Once the GPU moves off pll-gpu the PLL is no longer prepared, so it loses the rate protection of CLK_SET_RATE_GATE; a propagated rate request would then reprogram the PLL while its gate is off (the lock bit never asserts, 70 ms poll timeout per transition) and switch the running GPU onto it before it locks. Fixes: 6702d17f54a8 ("clk: sunxi-ng: a523: add video mod clocks") Signed-off-by: Juan Manuel L=C3=B3pez Carrillo --- drivers/clk/sunxi-ng/ccu-sun55i-a523.c | 32 +++++++++++++++++++++----- 1 file changed, 26 insertions(+), 6 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c b/drivers/clk/sunxi-ng/= ccu-sun55i-a523.c index 20dad06b37ca..979e53e63522 100644 --- a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c +++ b/drivers/clk/sunxi-ng/ccu-sun55i-a523.c @@ -21,6 +21,7 @@ =20 #include "ccu_div.h" #include "ccu_gate.h" +#include "ccu_maskdiv.h" #include "ccu_mp.h" #include "ccu_mult.h" #include "ccu_nk.h" @@ -442,18 +443,37 @@ static SUNXI_CCU_GATE_HWS(bus_g2d_clk, "bus-g2d", ahb= _hws, 0x63c, BIT(0), 0); =20 static const struct clk_hw *gpu_parents[] =3D { &pll_gpu_clk.common.hw, - &pll_periph0_800M_clk.common.hw, &pll_periph0_600M_clk.hw, &pll_periph0_400M_clk.hw, &pll_periph0_300M_clk.hw, &pll_periph0_200M_clk.hw, }; =20 -static SUNXI_CCU_M_HW_WITH_MUX_GATE(gpu_clk, "gpu", gpu_parents, 0x670, - 0, 4, /* M */ - 24, 3, /* mux */ - BIT(31), /* gate */ - CLK_SET_RATE_PARENT); +/* + * Mux index 1 (pll-periph0-800M) is skipped: the vendor BSP removed it + * from the parent list ("If GPU use pll-peri0-800m, gpu will occur job + * fault"), and with the masking divider every OPP would match exactly + * from it first. + */ +static const u8 gpu_mux_table[] =3D { 0, 2, 3, 4, 5 }; + +/* + * The M factor is a cycle-masking (fractional) divider, not a linear + * one: rate =3D source * (16 - M) / 16 (T527 manual, GPU_CLK_REG). + * + * No CLK_SET_RATE_PARENT: every GPU OPP is reachable from the fixed + * pll-periph0 outputs, and pll-gpu must never be reprogrammed through thi= s mux. + * Once the GPU moves off pll-gpu the PLL is no longer prepared, so it los= es + * the rate protection of CLK_SET_RATE_GATE; a propagated rate request wou= ld + * then reprogram the PLL while its gate is off (the lock bit never assert= s, + * 70 ms timeout) and switch the running GPU onto it before it locks. + */ +static SUNXI_CCU_MASKDIV_HW_WITH_MUX_TABLE_GATE(gpu_clk, "gpu", gpu_parent= s, + gpu_mux_table, 0x670, + 0, 4, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); 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Mon, 03 Aug 2026 11:08:05 -0700 (PDT) From: =?UTF-8?q?Juan=20Manuel=20L=C3=B3pez=20Carrillo?= To: mturquette@baylibre.com, sboyd@kernel.org, wens@kernel.org, jernej.skrabec@gmail.com, samuel@sholland.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: andre.przywara@arm.com, bmasney@redhat.com, linux-clk@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Juan=20Manuel=20L=C3=B3pez=20Carrillo?= Subject: [PATCH v2 3/3] arm64: dts: allwinner: a523: add GPU OPP table Date: Mon, 3 Aug 2026 20:07:55 +0200 Message-ID: <20260803180755.288793-4-juanmanuellopezcarrillo@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260803180755.288793-1-juanmanuellopezcarrillo@gmail.com> References: <20260803180755.288793-1-juanmanuellopezcarrillo@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Add the Mali-G57 operating points from the vendor BSP universal table (150/200/300/400/600 MHz) so panfrost devfreq can scale the GPU instead of running at the boot clock. The table describes the SoC rather than any particular board, so it lives in the .dtsi and is referenced from the GPU node there; every A523/T527 board in tree already provides mali-supply. The BSP universal table specifies 900 mV for all of these operating points, so that is the target and minimum voltage. The maximum is set to 920 mV to also cover boards whose GPU rail is a fixed 920 mV supply (the Orange Pi 4A drives it from AXP717 DCDC2, fixed at 920 mV), where the voltage transitions are then no-ops. The higher speed-bin points of the BSP (648-792 MHz) are not included: they are gated by a SID efuse bin and need pll-gpu as a live parent. Depends on the sun55i-a523 GPU clock divider fix: the OPP rates are only produced correctly with the cycle-masking divider model. Validated on hardware with the Mali cycle counter: 149/199/300/399/597 MHz measured under load, thermal-emulation throttling included. Signed-off-by: Juan Manuel L=C3=B3pez Carrillo --- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun55i-a523.dtsi index 85ef492ffeae..a3164b5dd609 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -85,6 +85,35 @@ osc24M: osc24M-clk { clock-output-names =3D "osc24M"; }; =20 + gpu_opp_table: opp-table-gpu { + compatible =3D "operating-points-v2"; + + opp-150000000 { + opp-hz =3D /bits/ 64 <150000000>; + opp-microvolt =3D <900000 900000 920000>; + }; + + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>; + opp-microvolt =3D <900000 900000 920000>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + opp-microvolt =3D <900000 900000 920000>; + }; + + opp-400000000 { + opp-hz =3D /bits/ 64 <400000000>; + opp-microvolt =3D <900000 900000 920000>; + }; + + opp-600000000 { + opp-hz =3D /bits/ 64 <600000000>; + opp-microvolt =3D <900000 900000 920000>; + }; + }; + pmu { compatible =3D "arm,cortex-a55-pmu"; interrupts =3D ; @@ -121,6 +150,7 @@ gpu: gpu@1800000 { interrupt-names =3D "job", "mmu", "gpu"; clocks =3D <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>; clock-names =3D "core", "bus"; + operating-points-v2 =3D <&gpu_opp_table>; power-domains =3D <&pck600 PD_GPU>; resets =3D <&ccu RST_BUS_GPU>; status =3D "disabled"; --=20 2.47.3