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[14.13.71.96]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38fb30dff2esm4078462a91.13.2026.08.03.07.17.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 07:17:30 -0700 (PDT) From: Akari Tsuyukusa To: Michael Turquette , Stephen Boyd , Brian Masney , Matthias Brugger , AngeloGioacchino Del Regno , Yassine Oudjana , Richard Cochran Cc: Laura Nao , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Chen-Yu Tsai , Akari Tsuyukusa , Bartosz Golaszewski , Danilo Krummrich , Bjorn Helgaas , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Nicolas Frattaroli , Takashi Sakamoto , Haotian Zhang , Kees Cook , Miles Chen , Daniel Golle , Sam Shih , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support), netdev@vger.kernel.org (open list:PTP HARDWARE CLOCK SUPPORT:Keyword:(?:\b|_)ptp(?:\b|_)), stable@vger.kernel.org Subject: [PATCH 01/32] clk: mediatek: mt2712: fix memory leak on module removal Date: Mon, 3 Aug 2026 23:16:28 +0900 Message-ID: <20260803141659.559129-2-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803141659.559129-1-akkun11.open@gmail.com> References: <20260803141659.559129-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" clk_mt2712_apmixed_probe() in clk-mt2712-apmixedsys.c does not call platform_set_drvdata(), but clk_mt2712_apmixed_remove() callback calls platform_get_drvdata(). This results in platform_get_drvdata() returning NULL, which leads to calling kfree(NULL) in mtk_free_clk_data(NULL). This leaves clk_data unreleased, causing a memory leak. Fix this by calling platform_set_drvdata() during probe. Fixes: c6368ce86435 ("clk: mediatek: mt2712-apmixedsys: Add .remove() callb= ack for module build") Cc: stable@vger.kernel.org Signed-off-by: Akari Tsuyukusa Reviewed-by: Brian Masney --- drivers/clk/mediatek/clk-mt2712-apmixedsys.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt2712-apmixedsys.c b/drivers/clk/med= iatek/clk-mt2712-apmixedsys.c index 54b18e9f83f8..087cf574bcdc 100644 --- a/drivers/clk/mediatek/clk-mt2712-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt2712-apmixedsys.c @@ -129,6 +129,8 @@ static int clk_mt2712_apmixed_probe(struct platform_dev= ice *pdev) goto unregister_plls; } =20 + platform_set_drvdata(pdev, clk_data); + return 0; =20 unregister_plls: --=20 2.55.0 From nobody Fri Oct 2 08:24:59 2026 Received: from mail-pj1-f46.google.com (mail-pj1-f46.google.com [209.85.216.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5414540A940 for ; Mon, 3 Aug 2026 14:17:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785766658; cv=none; b=uvakhtBhTedJwPelQivU3LK/c52kxGcEne4d9k2zpG3nWVhP3Op74LyhaKPTlJ6xtoUSCCo3MLWnnb3BF+aOql/yihVB/cUER5z4fun8btSS8DKdWnBnw3LH0CF6M3COjaedy9pNIA5mTax9JJQerinM9qJGZWvkMQx5Sx8L+pg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785766658; c=relaxed/simple; bh=jXMNEPGSmgzb4Ni0tFwqVaC5hDYyBsmFzVyIZbl8eok=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HlNL/Ir2+SM3OVEViXGxkWx/i2T+yGZ+9aM4hUkDhBahs2aLMwQdt2wO9DWZYgf9k4A/bgQ6GlIYKD1nXiU+D6TlocrUE+G+BhagDVDmOukCleVg896lj3FBRLVDIizshwoVs34oZuKiDAvleBGjIrLO6hir77nUpP1gRwKOwU8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=LrEGY7NH; arc=none smtp.client-ip=209.85.216.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="LrEGY7NH" Received: by mail-pj1-f46.google.com with SMTP id 98e67ed59e1d1-383b4a3755fso3309508a91.3 for ; Mon, 03 Aug 2026 07:17:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1785766656; x=1786371456; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=YIV+HU50AEtRbtVbE/kWRl5gYNOX4lr3tpB0iIeyarg=; b=LrEGY7NHH8ULc+ge2eBS13hi56QQRdd/tb+/Z6J++ZCphX5LcEnmEC6zlygG4F7v5I 8Gsj3rkPOaXrdWt710nYv8yzfMcqQ17zQgmjix10HOPNRcYVZDlwniYGTWtZqH48D76O utxhy11jJo1Xlrf3UKIPgXtULASeI1er9So6bfFk+ovguHBHQU3CADigYdSqquMNJJlF VU11fBHTmcfKOJ2F3s+0oozGHGGVzqf2Gtpo2LnbyhUlx19zMK7rGruEIfVatp7kBRFg UcMZAC8dZyU3jgMTrq9XatJTZ84jrfRNfeF54mPFsGpUJWEuj3CJwyFzU9qRLCs722hz aKKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1785766656; x=1786371456; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=YIV+HU50AEtRbtVbE/kWRl5gYNOX4lr3tpB0iIeyarg=; b=cqwyKJ+OSzy3x+/leAgI6mmJBfyUF7xSQgGi7Bf4c7jgloflsTSA8Fd0wzPAeyFfPm eyMCW5//VDMhutxc/z6tk4x/Azv6dbjWFn2T1miZM4uodxu7nQhSoRfSTmpHARNn3Qct MZRyOAEN4BbD2Qwr/Rimndb9N8BvcKS4QDVAinapxY4JoJzENedbE1qM/AvEIEyACTmU y5XUBWawzwVTy9XRo3uqEezH+ops+yGvxk/12kgYCjOyF32XxIYlaRXypEfSp4H1CQk0 hkewWzMuvy/NFcWBDjWyy3Bx+U0+M8Jxpd4U1JDVC90v6FVggYpzt3OdcHZiQQrG3N9m KyXA== X-Forwarded-Encrypted: i=1; AHgh+RrgYcdxuMscHHv30+nrWM4nf4SnM1n2Egpe1RkmM2WwUpRSUgthRMMHTledIApElMian3XN8Se9npnI6hU=@vger.kernel.org X-Gm-Message-State: AOJu0YywgJ47zIJkTAe40Wi7CkvpQ3VCPaxs8h52oyCDok/yi0ghDXZo J5htsKaIYeVNhdUgnSYQuV4Q6tmTtHciurvBiCwSWkWtej6VuZuQyFJY X-Gm-Gg: AR+sD1021d+2AnMnJBLhGIMFxjquapmG2OXZLOZ35jRYIoDU95YPPUpuPOYTtOkPfse yXHNbzaaRQnr2jmtyRvaEzOuXohY4oZ4oE8j1VqhGj0X9OOmiSmspfiZzsWFG1O4GRj9M9wdvzh deoWg4TjfF1ol5z26druiN3GB+kEuYlawUNwWR+YhaZ/Zo9TS4NNOXQInfdOZPxELSKyeciyHwC VQ00ZtvH46IOuywpXCkiUic1J/6mIwrBx5oyWxiLqjscc//03e7WLvU0eDulKQVDXdBEYYbuzYZ yKp3gLRIIxADVa8bmxgMl23sLh6TQ8hDyvR26Ye4WSQRfEtBo3ja9r1itwDPCRuZTi2MZbMdtQu UupvW4f5oXEGVPc4RdiF7YtX513t+9AhkA+uUVw+I4Dq66yJygCcWB0egk32Q9S8Vgy6YZXBrpS RbtSGNNwQTHg9dnAlReY+QELCTDoK/36dDag0q1YG2RhUNxSQ7lNELWNGANxCu0aF7Cc3fVtwbk gQOAhQuUtuLtQ5kzm2V X-Received: by 2002:a17:90b:5690:b0:38d:a8be:a597 with SMTP id 98e67ed59e1d1-38fbc56732bmr9286831a91.37.1785766655662; Mon, 03 Aug 2026 07:17:35 -0700 (PDT) Received: from buffalo-ssd (M014013071096.v4.enabler.ne.jp. [14.13.71.96]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38fb30dff2esm4078462a91.13.2026.08.03.07.17.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 07:17:35 -0700 (PDT) From: Akari Tsuyukusa To: Michael Turquette , Stephen Boyd , Brian Masney , Matthias Brugger , AngeloGioacchino Del Regno , Yassine Oudjana , Richard Cochran Cc: Laura Nao , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Chen-Yu Tsai , Akari Tsuyukusa , Bartosz Golaszewski , Danilo Krummrich , Bjorn Helgaas , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Nicolas Frattaroli , Takashi Sakamoto , Haotian Zhang , Kees Cook , Miles Chen , Daniel Golle , Sam Shih , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support), netdev@vger.kernel.org (open list:PTP HARDWARE CLOCK SUPPORT:Keyword:(?:\b|_)ptp(?:\b|_)), stable@vger.kernel.org Subject: [PATCH 02/32] clk: mediatek: mt6795: fix memory leak on module removal Date: Mon, 3 Aug 2026 23:16:29 +0900 Message-ID: <20260803141659.559129-3-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803141659.559129-1-akkun11.open@gmail.com> References: <20260803141659.559129-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" clk-mt6795-apmixedsys.c, clk-mt6795-infracfg.c and clk-mt6795-pericfg.c do not call platform_set_drvdata() during their driver probe callback, but their remove callback calls platform_get_drvdata(). This results in platform_get_drvdata() returning NULL, which leads to calling kfree(NULL) in mtk_free_clk_data(NULL). This leaves clk_data unreleased, causing a memory leak. Fix this by calling platform_set_drvdata() during probe. Fixes: 0d363282bb0c ("clk: mediatek: Add MediaTek Helio X10 MT6795 clock dr= ivers") Cc: stable@vger.kernel.org Signed-off-by: Akari Tsuyukusa Reviewed-by: Brian Masney --- drivers/clk/mediatek/clk-mt6795-apmixedsys.c | 2 ++ drivers/clk/mediatek/clk-mt6795-infracfg.c | 2 ++ drivers/clk/mediatek/clk-mt6795-pericfg.c | 2 ++ 3 files changed, 6 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt6795-apmixedsys.c b/drivers/clk/med= iatek/clk-mt6795-apmixedsys.c index 123d5d7fea85..239a3f5e1760 100644 --- a/drivers/clk/mediatek/clk-mt6795-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt6795-apmixedsys.c @@ -175,6 +175,8 @@ static int clk_mt6795_apmixed_probe(struct platform_dev= ice *pdev) dev_dbg(dev, "Performing initial setup for MD1\n"); clk_mt6795_apmixed_setup_md1(base); =20 + platform_set_drvdata(pdev, clk_data); + return 0; =20 unregister_ref2usb: diff --git a/drivers/clk/mediatek/clk-mt6795-infracfg.c b/drivers/clk/media= tek/clk-mt6795-infracfg.c index e4559569f5b0..914bb069aa85 100644 --- a/drivers/clk/mediatek/clk-mt6795-infracfg.c +++ b/drivers/clk/mediatek/clk-mt6795-infracfg.c @@ -116,6 +116,8 @@ static int clk_mt6795_infracfg_probe(struct platform_de= vice *pdev) if (ret) goto unregister_cpumuxes; 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[14.13.71.96]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38fb30dff2esm4078462a91.13.2026.08.03.07.17.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 07:17:39 -0700 (PDT) From: Akari Tsuyukusa To: Michael Turquette , Stephen Boyd , Brian Masney , Matthias Brugger , AngeloGioacchino Del Regno , Yassine Oudjana , Richard Cochran Cc: Laura Nao , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Chen-Yu Tsai , Akari Tsuyukusa , Bartosz Golaszewski , Danilo Krummrich , Bjorn Helgaas , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Nicolas Frattaroli , Takashi Sakamoto , Haotian Zhang , Kees Cook , Miles Chen , Daniel Golle , Sam Shih , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support), netdev@vger.kernel.org (open list:PTP HARDWARE CLOCK SUPPORT:Keyword:(?:\b|_)ptp(?:\b|_)), stable@vger.kernel.org Subject: [PATCH 03/32] clk: mediatek: mt7622: fix memory leak on module removal Date: Mon, 3 Aug 2026 23:16:30 +0900 Message-ID: <20260803141659.559129-4-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803141659.559129-1-akkun11.open@gmail.com> References: <20260803141659.559129-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" clk-mt7622-apmixedsys.c and clk-mt7622-infracfg.c do not call platform_set_drvdata() during their driver probe callback, but their remove callback calls platform_get_drvdata(). This results in platform_get_drvdata() returning NULL, which leads to calling kfree(NULL) in mtk_free_clk_data(NULL). This leaves clk_data unreleased, causing a memory leak. Fix this by calling platform_set_drvdata() during probe. Fixes: c50e2ea6507b ("clk: mediatek: mt7622-apmixedsys: Add .remove() callb= ack for module build") Fixes: 838b86331c5e ("clk: mediatek: mt7622: Move infracfg to clk-mt7622-in= fracfg.c") Cc: stable@vger.kernel.org Signed-off-by: Akari Tsuyukusa Reviewed-by: Brian Masney --- drivers/clk/mediatek/clk-mt7622-apmixedsys.c | 2 ++ drivers/clk/mediatek/clk-mt7622-infracfg.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt7622-apmixedsys.c b/drivers/clk/med= iatek/clk-mt7622-apmixedsys.c index 8a29eaab0cfc..fae8abda14b3 100644 --- a/drivers/clk/mediatek/clk-mt7622-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt7622-apmixedsys.c @@ -109,6 +109,8 @@ static int clk_mt7622_apmixed_probe(struct platform_dev= ice *pdev) if (ret) goto unregister_gates; =20 + platform_set_drvdata(pdev, clk_data); + return 0; =20 unregister_gates: diff --git a/drivers/clk/mediatek/clk-mt7622-infracfg.c b/drivers/clk/media= tek/clk-mt7622-infracfg.c index cfdf3b07c3e0..cec19447d637 100644 --- a/drivers/clk/mediatek/clk-mt7622-infracfg.c +++ b/drivers/clk/mediatek/clk-mt7622-infracfg.c @@ -90,6 +90,8 @@ static int clk_mt7622_infracfg_probe(struct platform_devi= ce *pdev) if (ret) goto unregister_cpumuxes; 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[14.13.71.96]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38fb30dff2esm4078462a91.13.2026.08.03.07.17.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 07:17:44 -0700 (PDT) From: Akari Tsuyukusa To: Michael Turquette , Stephen Boyd , Brian Masney , Matthias Brugger , AngeloGioacchino Del Regno , Yassine Oudjana , Richard Cochran Cc: Laura Nao , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Chen-Yu Tsai , Akari Tsuyukusa , Bartosz Golaszewski , Danilo Krummrich , Bjorn Helgaas , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Nicolas Frattaroli , Takashi Sakamoto , Haotian Zhang , Kees Cook , Miles Chen , Daniel Golle , Sam Shih , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support), netdev@vger.kernel.org (open list:PTP HARDWARE CLOCK SUPPORT:Keyword:(?:\b|_)ptp(?:\b|_)), stable@vger.kernel.org Subject: [PATCH 04/32] clk: mediatek: mt8135: fix memory leak on module removal Date: Mon, 3 Aug 2026 23:16:31 +0900 Message-ID: <20260803141659.559129-5-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803141659.559129-1-akkun11.open@gmail.com> References: <20260803141659.559129-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" clk_mt8135_apmixed_probe() in clk-mt8135-apmixedsys.c does not call platform_set_drvdata(), but clk_mt8135_apmixed_remove() callback calls platform_get_drvdata(). This results in platform_get_drvdata() returning NULL, which leads to calling kfree(NULL) in mtk_free_clk_data(NULL). This leaves clk_data unreleased, causing a memory leak. Fix this by calling platform_set_drvdata() during probe. Fixes: 54b7026f011e ("clk: mediatek: mt8135-apmixedsys: Convert to platform= _driver and module") Cc: stable@vger.kernel.org Signed-off-by: Akari Tsuyukusa Reviewed-by: Brian Masney --- drivers/clk/mediatek/clk-mt8135-apmixedsys.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt8135-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8135-apmixedsys.c index 19e4ee489ec3..e3b7dc13b458 100644 --- a/drivers/clk/mediatek/clk-mt8135-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8135-apmixedsys.c @@ -66,6 +66,8 @@ static int clk_mt8135_apmixed_probe(struct platform_devic= e *pdev) if (ret) goto unregister_plls; =20 + platform_set_drvdata(pdev, clk_data); + return 0; =20 unregister_plls: --=20 2.55.0 From nobody Fri Oct 2 08:24:59 2026 Received: from mail-pj1-f49.google.com (mail-pj1-f49.google.com [209.85.216.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21016413791 for ; Mon, 3 Aug 2026 14:17:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785766671; cv=none; b=kfKPH/5t+YStK0ExlDmvBEzXbzIT5ReaIiPFbJfGSQoaco93a3DTkmYuu59YCkMXpEW2EMV64672+I9DM7EoclFbr53pAmt1IkT+foXoQHhXfp3cPcex+rzOEMSrYP6BIXkuom7x1U2qhNffVqfW0mkOdjiwj7kT/b7R2n+ciVM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785766671; c=relaxed/simple; bh=q1Uz+Gm71OPt/zJsTxyArW2pEOjZRyhgf2I4biF/dNg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GYFgk+VjU+rNc5EMHW5zFUeal/w0Q/bAiffDoLuXuRRORReyPjqdn857M0rcj2N6/liAuee1sJbPpTbxtnVl9cwXgfJASpp6kKflg4mq0dIHfRvplzMKOzKcRXPGpzsTgEB1wo07WH7EXRTT6pfaSl9ghI1uNuJuoPjnu5oPLUc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=mGG62n+g; arc=none smtp.client-ip=209.85.216.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="mGG62n+g" Received: by mail-pj1-f49.google.com with SMTP id 98e67ed59e1d1-38e041ea211so3564048a91.0 for ; Mon, 03 Aug 2026 07:17:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1785766669; x=1786371469; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=iWp6MzQC1qDygJL4OCtM1qnllOHL0djYegVbWv/i/KI=; b=mGG62n+gxE57o+8qRAEcvglTLaHHxWqsRO2gbcsY3lopfDIO7ynotl6PvKeHun06CS xC8fGyYSlpPAceQ7AL3qvtDlAGz1dBj5JVgSfaXpyIvFAvakseHsxtYS+2LUHGmmwpLd dl1iqbYxwpPkLt665JTbDu76QziLMQy+HR7I9lBNPTAeiwboxCdKISVzC80kGgP8Qj5h bf81nGvYBRIjyWlACQwsHrbmmAes2Cyo2vFOD9OhiSvfFmDI3l75M0iFy4DJjAB49Sdp o2AY/ke65dcrhEBFzsupDdSYh9m4NOfnpAqeoy3yvCqi39HNu/11DsOTaFzRQ9MNiB2b pn7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1785766669; x=1786371469; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=iWp6MzQC1qDygJL4OCtM1qnllOHL0djYegVbWv/i/KI=; b=kr1C/VySdnDG22GSjpRjRO7GLVFjnxKPcFLmUIPS74jEFeti7AhWcwwy39KN+zxJ0a MoNcbgUAiGQx4nNI1xafc134j1YKRNneObB8D8cJY0Fc/NFIwEb+GOF6Pez+eM3cTj53 RblHAowP8LPUqbbLPsxpK6TdFvdE9XPgVXqkbexEDgRpP0twk0sd2Wch2RXKZl9ojygb y5m1gtjfDahVws9vO4GvOkG3XBwwj0zfIzL/rlYpYK09qZxU4z6b9LI/KVno+Ih1zRIK U7TpxYEtE1qyPLvg/0pepo4b+FRNwze5A0GXnDC+atNzhvi7B7PSyzqs0SkGZVJ6WtXC jNZg== X-Forwarded-Encrypted: i=1; AHgh+Rop3lj+4HiGAM0LD+D2cacp4eVEKydT3+adAO4ITHlqGCjp/bysGkxDkwB+Z+Kks2wiDOXnk/Cax52aEyo=@vger.kernel.org X-Gm-Message-State: AOJu0YyQ7jalBd5RM4SRhldNyPTCRsi0q1E3gYqLmep172mHTw9PIb/q F1M6bi0RQh6oaKY+IYEyVGS6zcGG/VpbECXZ45zZp2poL81KebVUQIBo X-Gm-Gg: AR+sD13Sr78BmziINVyJkXdfa45ztTeRGUfYZhHp9fLiPiH+2q2Z63GphDCtDgpSTmZ AZYamJR/N5TSR2XIRiMdvItqeN1/xZsXSkRvQ7hB1+hzu7Kj30/+LAU5JoHyYfmfvWzoAtV54VT tb2K+WUMsrVq80ueZbC9+RbltMxKCLcjOt8LpQ+JN0+4s+yeOKr771uRP+fC/z2TNPGE4vrW2SZ 7FdTC6qeQS+LEuR5V6zTjJLFWJxFXnEiaef3jY/YI31SolWHOZPuc3NcwE22MB3XRIpBa7CkavG TyFBX1FqOfaucof4rBqFCjbF6YvxZadnDBGa87dMwPUVbiUOa5uN8QUOqWvnbIAvOcR6V45KmuU ulRTQ1mYTklzcDC9pecv3TgrkPnHx3EizyJJW6vI0ZKSEBV3L+AAaWEj6euxgR9OKccCXpB6T/+ qVjW49o2BqFRLNVktwDRxTlIEv1jDFGmOf+ZnNxKN7olCsppMoRH7ON3YTKy0LHDKcuoO2XNetw 7gEFozugGHt70mzsBuJ X-Received: by 2002:a17:90b:528c:b0:37f:9ce1:7364 with SMTP id 98e67ed59e1d1-38fbc4d5e09mr9059524a91.26.1785766669331; Mon, 03 Aug 2026 07:17:49 -0700 (PDT) Received: from buffalo-ssd (M014013071096.v4.enabler.ne.jp. [14.13.71.96]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38fb30dff2esm4078462a91.13.2026.08.03.07.17.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 07:17:49 -0700 (PDT) From: Akari Tsuyukusa To: Michael Turquette , Stephen Boyd , Brian Masney , Matthias Brugger , AngeloGioacchino Del Regno , Yassine Oudjana , Richard Cochran Cc: Laura Nao , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Chen-Yu Tsai , Akari Tsuyukusa , Bartosz Golaszewski , Danilo Krummrich , Bjorn Helgaas , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Nicolas Frattaroli , Takashi Sakamoto , Haotian Zhang , Kees Cook , Miles Chen , Daniel Golle , Sam Shih , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support), netdev@vger.kernel.org (open list:PTP HARDWARE CLOCK SUPPORT:Keyword:(?:\b|_)ptp(?:\b|_)), stable@vger.kernel.org Subject: [PATCH 05/32] clk: mediatek: mt8173: fix memory leak on module removal Date: Mon, 3 Aug 2026 23:16:32 +0900 Message-ID: <20260803141659.559129-6-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803141659.559129-1-akkun11.open@gmail.com> References: <20260803141659.559129-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" clk-mt8173-apmixedsys.c and clk-mt8173-infracfg.c do not call platform_set_drvdata() during their driver probe callback, but their remove callback calls platform_get_drvdata(). This results in platform_get_drvdata() returning NULL, which leads to calling kfree(NULL) in mtk_free_clk_data(NULL). This leaves clk_data unreleased, causing a memory leak. Fix this by calling platform_set_drvdata() during probe. Fixes: 4c02c9af3cb9 ("clk: mediatek: mt8173: Break down clock drivers and a= llow module build") Cc: stable@vger.kernel.org Signed-off-by: Akari Tsuyukusa --- drivers/clk/mediatek/clk-mt8173-apmixedsys.c | 2 ++ drivers/clk/mediatek/clk-mt8173-infracfg.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt8173-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8173-apmixedsys.c index d7d416172ab3..65dc4489a09c 100644 --- a/drivers/clk/mediatek/clk-mt8173-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8173-apmixedsys.c @@ -179,6 +179,8 @@ static int clk_mt8173_apmixed_probe(struct platform_dev= ice *pdev) if (r) goto unregister_ref2usb; =20 + platform_set_drvdata(pdev, clk_data); + return 0; =20 unregister_ref2usb: diff --git a/drivers/clk/mediatek/clk-mt8173-infracfg.c b/drivers/clk/media= tek/clk-mt8173-infracfg.c index fa2d1d557e04..9b8c35897789 100644 --- a/drivers/clk/mediatek/clk-mt8173-infracfg.c +++ b/drivers/clk/mediatek/clk-mt8173-infracfg.c @@ -128,6 +128,8 @@ static int clk_mt8173_infracfg_probe(struct platform_de= vice *pdev) if (r) goto unregister_clk_hw; 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[14.13.71.96]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38fb30dff2esm4078462a91.13.2026.08.03.07.17.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 07:17:53 -0700 (PDT) From: Akari Tsuyukusa To: Michael Turquette , Stephen Boyd , Brian Masney , Matthias Brugger , AngeloGioacchino Del Regno , Yassine Oudjana , Richard Cochran Cc: Laura Nao , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Chen-Yu Tsai , Akari Tsuyukusa , Bartosz Golaszewski , Danilo Krummrich , Bjorn Helgaas , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Nicolas Frattaroli , Takashi Sakamoto , Haotian Zhang , Kees Cook , Miles Chen , Daniel Golle , Sam Shih , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support), netdev@vger.kernel.org (open list:PTP HARDWARE CLOCK SUPPORT:Keyword:(?:\b|_)ptp(?:\b|_)), stable@vger.kernel.org Subject: [PATCH 06/32] clk: mediatek: mt8192: fix memory leak on module removal Date: Mon, 3 Aug 2026 23:16:33 +0900 Message-ID: <20260803141659.559129-7-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803141659.559129-1-akkun11.open@gmail.com> References: <20260803141659.559129-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" clk_mt8192_apmixed_probe() in clk-mt8192-apmixedsys.c does not call platform_set_drvdata(), but clk_mt8192_apmixed_remove() callback calls platform_get_drvdata(). This results in platform_get_drvdata() returning NULL, which leads to calling kfree(NULL) in mtk_free_clk_data(NULL). This leaves clk_data unreleased, causing a memory leak. Fix this by calling platform_set_drvdata() during probe. Fixes: 124294ff468f ("clk: mediatek: mt8192: Move apmixedsys clock driver t= o its own file") Cc: stable@vger.kernel.org Signed-off-by: Akari Tsuyukusa Reviewed-by: Brian Masney --- drivers/clk/mediatek/clk-mt8192-apmixedsys.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt8192-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8192-apmixedsys.c index b0563a285bd6..e6ac40e2f12d 100644 --- a/drivers/clk/mediatek/clk-mt8192-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8192-apmixedsys.c @@ -176,6 +176,8 @@ static int clk_mt8192_apmixed_probe(struct platform_dev= ice *pdev) if (r) goto unregister_gates; =20 + platform_set_drvdata(pdev, clk_data); + return r; =20 unregister_gates: --=20 2.55.0 From nobody Fri Oct 2 08:24:59 2026 Received: from mail-pj1-f46.google.com (mail-pj1-f46.google.com [209.85.216.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 634AA4189A6 for ; Mon, 3 Aug 2026 14:17:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785766680; cv=none; b=iwugEd4vUpwZjUMYUEWzdzapEdEfSmRMOMdeHp8eMfIYD3PlcujMxZ28EPayusCwMYJq4SBMZOnvRT+n96kOJgBYkackkP+LDglqoqwSlNnqIpznUdFSTQsSHmmrIXWtypN5scz1PG5pBRA9uiu6zNupwzWqwnGlBWesiZ+izIM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785766680; c=relaxed/simple; bh=V47oyzd0XPM6qZmTh1BgPQ6mJdcG+FwNvo/fLSmwpXA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=IcsXYzUFdRMWNoSjLAt+b2x+kwO4BxNQ5o6nu840/6Vx5nlNSAAEiG1csh5XNsk4c+McO7ocmGvWJImPrCS/n82hpntbaJkwJXkrfxphS8J9YFILswpiGs/v2m07MqC/WEnvUTun6BbWFgqWUkcTkvs3P3OGGw9rnWiFWa6q2d8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=CvEdjiGz; arc=none smtp.client-ip=209.85.216.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="CvEdjiGz" Received: by mail-pj1-f46.google.com with SMTP id 98e67ed59e1d1-383b4a3755fso3309904a91.3 for ; Mon, 03 Aug 2026 07:17:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1785766678; x=1786371478; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=Wn8DGKA5kSavmCRKRx9MyxFXC5hjjcK6hiv7Zc2G8KI=; b=CvEdjiGzilGV9t82WBz4Okenoo/EZFN+Sohg1SOAgLIOqXiUDj2QhfoY/hBxgzck7f LOrT/aRpFc1bA7TUToX8VkFzechASpKeuQfwQljcI+Q0wnh0jUr4vY/KuYJQ51ju2agb EHl52cBOJvoXo3KwvnR6Q2KSg+7FlsGwUMi4LdAzO6mA/dHFSX5kJlJQnolu9USSXo7x hcf2gKAT/KSSjF8Dxpi5caRujv5uMQIKokoCdMbAYMAOUVNHAtpkooN2xWGsu8sBOBKX qsFYY5Phe1b7x0/QtOqBFg9Qb7NOC6H9O2xgE8Rs8b+rmlqi36xdgDADkGdhenBP16Yv hHnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1785766678; x=1786371478; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=Wn8DGKA5kSavmCRKRx9MyxFXC5hjjcK6hiv7Zc2G8KI=; b=hc/GxjPabn70y7jfVHuItkQiBNReAa5KdEX85bs6X2FR3cH4p7bqpNrJOCQ8sbIwwY a2hyi/kHLGu562Z5y3NTXYGIwt9mWDe7exl/ttHLBwLbnnMU+VQQRTcyTb5Mz/52f3zF CHr2dyfqIKS33e8RDCSI5f3HGUS5bqmJIGnXyVx8ttQcNQnsgntDRoCPOhdyKuxXjQgv UcZ7PdrW5ug1bqeOvSLFtMac5qV4mmdZmCabeBxEpjY9usCle4UTwdbC+tV7uBQoTwuS bn3FXMhmEmPhBgshPhXmcYd3BQeOCSTVjmZopFe9sANHkIj3/dyLc67BRFr2aoOtw00r kTbw== X-Forwarded-Encrypted: i=1; AHgh+Rrkg2NzpTvJ1Lwv8NV1LiX4FIp7Lg/iY7VEft6Q1uAXv/dHjgH91QdasQn+kuR4D3J9XxsHSeVzo0Fna6s=@vger.kernel.org X-Gm-Message-State: AOJu0Yw5n5uKNn626kjhVQMg4v/9vRHI1Z5mCJH8oWmQdHhX1dXVX8Vo DADTmXGnsCRWBZscdnHCFMysrpHuAifpP12twUvMTs2grVPcnvhGu0dr X-Gm-Gg: AR+sD11DZgckmLK6wq16ipusV7PSoKLxf8LpVJmrFJtsrpmjZRfYURS4P3r9Ka55uRg EECajuKRIm3v/m34UlaVNqbGC29cB208t7fWj+gmf0ZrfL/XRV89idrc2RHDinN5BrABNsDXOg6 QaGRPy4EADgeS5z3+WZZxqPXEfXsXG+gHRXgwt4VXSqoNDKGjx+EOp0c2Y4cFxwb3fo7C8g+wzo xDhZVTBcxZCkv4msXP1n1mI6MPzPG/ouFRuVjqmFNOrNuw/ohRS6OJSRMeYtQSpocs9Ougv67vd 3PLAXO5s5mZRjLlapfBBw4VdekaoDfdxgqsX5OrkAlPXF9c+n5r6Ii3fX9N+ujEqxhpeZp+rymR ratFcHAGG8oOxxtHhHBNHtB+B5jPOazGn4Pe9AdFcZt3jq46TI1Ho23ZEdKFtFgJlq+kLVXCEB6 dEWggvpI1FXR0JbnKHhM1FRrpXKPa3WzCTEiTmeDK8TvEYVhuiaPykCA6GMeXFeYScGMDI9gegg xIZiKvusP8Vo9UW4ipAYpWS523k5Xxn X-Received: by 2002:a17:90b:590d:b0:368:af5c:5925 with SMTP id 98e67ed59e1d1-38fbc4d0204mr9749689a91.23.1785766678572; Mon, 03 Aug 2026 07:17:58 -0700 (PDT) Received: from buffalo-ssd (M014013071096.v4.enabler.ne.jp. [14.13.71.96]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38fb30dff2esm4078462a91.13.2026.08.03.07.17.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 07:17:58 -0700 (PDT) From: Akari Tsuyukusa To: Michael Turquette , Stephen Boyd , Brian Masney , Matthias Brugger , AngeloGioacchino Del Regno , Yassine Oudjana , Richard Cochran Cc: Laura Nao , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Chen-Yu Tsai , Akari Tsuyukusa , Bartosz Golaszewski , Danilo Krummrich , Bjorn Helgaas , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Nicolas Frattaroli , Takashi Sakamoto , Haotian Zhang , Kees Cook , Miles Chen , Daniel Golle , Sam Shih , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support), netdev@vger.kernel.org (open list:PTP HARDWARE CLOCK SUPPORT:Keyword:(?:\b|_)ptp(?:\b|_)), stable@vger.kernel.org Subject: [PATCH 07/32] clk: mediatek: mt6735: Add missing MODULE_DEVICE_TABLE() Date: Mon, 3 Aug 2026 23:16:34 +0900 Message-ID: <20260803141659.559129-8-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803141659.559129-1-akkun11.open@gmail.com> References: <20260803141659.559129-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add MODULE_DEVICE_TABLE() to the MT6735 clock drivers (imgsys, mfgcfg, vdecsys, vencsys) to export the Device Tree matching tables. This is required so that the clock drivers can be automatically loaded when built as modules. Fixes: 0bd9b1211f74 ("clk: mediatek: Add drivers for MT6735 syscon clock an= d reset controllers") Cc: stable@vger.kernel.org Signed-off-by: Akari Tsuyukusa --- drivers/clk/mediatek/clk-mt6735-imgsys.c | 1 + drivers/clk/mediatek/clk-mt6735-mfgcfg.c | 1 + drivers/clk/mediatek/clk-mt6735-vdecsys.c | 1 + drivers/clk/mediatek/clk-mt6735-vencsys.c | 1 + 4 files changed, 4 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt6735-imgsys.c b/drivers/clk/mediate= k/clk-mt6735-imgsys.c index c564f8f72432..813241d526cf 100644 --- a/drivers/clk/mediatek/clk-mt6735-imgsys.c +++ b/drivers/clk/mediatek/clk-mt6735-imgsys.c @@ -41,6 +41,7 @@ static const struct of_device_id of_match_mt6735_imgsys[]= =3D { { .compatible =3D "mediatek,mt6735-imgsys", .data =3D &imgsys_clks }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_mt6735_imgsys); =20 static struct platform_driver clk_mt6735_imgsys =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt6735-mfgcfg.c b/drivers/clk/mediate= k/clk-mt6735-mfgcfg.c index 1f5aedddf209..8a18ee244a4d 100644 --- a/drivers/clk/mediatek/clk-mt6735-mfgcfg.c +++ b/drivers/clk/mediatek/clk-mt6735-mfgcfg.c @@ -45,6 +45,7 @@ static const struct of_device_id of_match_mt6735_mfgcfg[]= =3D { { .compatible =3D "mediatek,mt6735-mfgcfg", .data =3D &mfgcfg_clks }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_mt6735_mfgcfg); =20 static struct platform_driver clk_mt6735_mfgcfg =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt6735-vdecsys.c b/drivers/clk/mediat= ek/clk-mt6735-vdecsys.c index 8817085fc1db..d53ebf92e878 100644 --- a/drivers/clk/mediatek/clk-mt6735-vdecsys.c +++ b/drivers/clk/mediatek/clk-mt6735-vdecsys.c @@ -63,6 +63,7 @@ static const struct of_device_id of_match_mt6735_vdecsys[= ] =3D { { .compatible =3D "mediatek,mt6735-vdecsys", .data =3D &vdecsys_clks }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_mt6735_vdecsys); =20 static struct platform_driver clk_mt6735_vdecsys =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt6735-vencsys.c b/drivers/clk/mediat= ek/clk-mt6735-vencsys.c index 8dec7f98492a..64ba9da9fd42 100644 --- a/drivers/clk/mediatek/clk-mt6735-vencsys.c +++ b/drivers/clk/mediatek/clk-mt6735-vencsys.c @@ -37,6 +37,7 @@ static const struct of_device_id of_match_mt6735_vencsys[= ] =3D { { .compatible =3D "mediatek,mt6735-vencsys", .data =3D &vencsys_clks }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_mt6735_vencsys); =20 static struct platform_driver clk_mt6735_vencsys =3D { .probe =3D mtk_clk_simple_probe, --=20 2.55.0 From nobody Fri Oct 2 08:24:59 2026 Received: from mail-pj1-f45.google.com (mail-pj1-f45.google.com [209.85.216.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C43E5419FBD for ; Mon, 3 Aug 2026 14:18:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785766686; cv=none; b=hyEneY3WRk+JSuE5ajGH05qPd6ErQ13ULgCUx4S5v4o4WwfT2lTcaF9v6DxDHk1YbzsTtuYo4i2DZ4nQ4GoexpdrA3eDk4A5+fmNQtcpkMy6s9KM4JLhK/vhu1L53wssSZFuLepAZljyADr1Sf4UnSstK7+h5SybJXeYJBqM6LI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785766686; c=relaxed/simple; bh=7h3J0KJRIBj4TZbgkPIpnUg4BNLSixuEuLBm1vCS7vo=; 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[14.13.71.96]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38fb30dff2esm4078462a91.13.2026.08.03.07.17.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 07:18:02 -0700 (PDT) From: Akari Tsuyukusa To: Michael Turquette , Stephen Boyd , Brian Masney , Matthias Brugger , AngeloGioacchino Del Regno , Yassine Oudjana , Richard Cochran Cc: Laura Nao , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Chen-Yu Tsai , Akari Tsuyukusa , Bartosz Golaszewski , Danilo Krummrich , Bjorn Helgaas , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Nicolas Frattaroli , Takashi Sakamoto , Haotian Zhang , Kees Cook , Miles Chen , Daniel Golle , Sam Shih , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support), netdev@vger.kernel.org (open list:PTP HARDWARE CLOCK SUPPORT:Keyword:(?:\b|_)ptp(?:\b|_)), stable@vger.kernel.org Subject: [PATCH 08/32] clk: mediatek: mt7988-apmixed: Add missing MODULE_DEVICE_TABLE() Date: Mon, 3 Aug 2026 23:16:35 +0900 Message-ID: <20260803141659.559129-9-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803141659.559129-1-akkun11.open@gmail.com> References: <20260803141659.559129-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add MODULE_DEVICE_TABLE() to the MT7988 apmixedsys clock driver to export the Device Tree matching tables. This is required so that the clock drivers can be automatically loaded when built as modules. Fixes: 4b4719437d85 ("clk: mediatek: add drivers for MT7988 SoC") Cc: stable@vger.kernel.org Signed-off-by: Akari Tsuyukusa --- drivers/clk/mediatek/clk-mt7988-apmixed.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/mediatek/clk-mt7988-apmixed.c b/drivers/clk/mediat= ek/clk-mt7988-apmixed.c index 416a4b88d100..24f4e7b87a31 100644 --- a/drivers/clk/mediatek/clk-mt7988-apmixed.c +++ b/drivers/clk/mediatek/clk-mt7988-apmixed.c @@ -75,6 +75,7 @@ static const struct of_device_id of_match_clk_mt7988_apmi= xed[] =3D { { .compatible =3D "mediatek,mt7988-apmixedsys" }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_apmixed); =20 static int clk_mt7988_apmixed_probe(struct platform_device *pdev) { --=20 2.55.0 From nobody Fri Oct 2 08:24:59 2026 Received: from mail-pj1-f48.google.com (mail-pj1-f48.google.com [209.85.216.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5649340BCD8 for ; Mon, 3 Aug 2026 14:18:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785766689; cv=none; b=Wj2bR5xp31cuWuYmqevcMYg0rIjJHHX8t8GyNO4+Z+CZmAzUmohnO1Y0HAL7E7qet+w/e9vGJx0W69y7dzWwjgN78LSm3MDiKF9/6GZtwwPA7TEQCpWf+pU1HXxaktlx96FvMfVqHO/qZsocBynG1CMK2cUBm0vbYw1dkmSlWnI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785766689; c=relaxed/simple; bh=MLI5y678+94kda6BFxWOuNupkCQ3DfRm8M73wi7fZVA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KU8gU0cngcuKwAiq/5XVrvtNsDMWWYI0zGgTt8OCWJlSEDg08D9TNhPjlsUy3EY3sERjUwwJmFlj6tz9TBl7DAy7NsmNXRfBgdtA+Y5zn7sPvSTM/qYZGTwd9tBtlxtEcmzOJy70cAqESvDTjsfrwRz7HUps2r8ojaLOUxS5dCY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=SHbrm+OP; arc=none smtp.client-ip=209.85.216.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="SHbrm+OP" Received: by mail-pj1-f48.google.com with SMTP id 98e67ed59e1d1-38a0c7e841fso4209462a91.2 for ; Mon, 03 Aug 2026 07:18:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1785766688; x=1786371488; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=on4B/LfqkHipeTiwMXYITPpUbegoRxXk89rke8WT6Ak=; b=SHbrm+OPfMbEzCX/XgOR5mtFgQMosray+RYKVaV+UKe+Ew4EViThBKkyqKpNkA92KN l6m2O8d8KHpCVgJc1utgMck7Eju8mqnsshPjNE+7wjA9Herjm9r97FtznHX9O+W066YC hZNAabVft8X82wZj4nUOekdch+FhjxosNpNoPOp004xAzs0rpGiftfx1IuPQS9SdMTjK SYnQqV1ei7h51u32xqcLxEDAla6tHWDy8Bp0zjo7rpbdwRDyLvq5jJVYCvTnoL+rsUtz KmenlESiK4ET+GCquhvP+fBt4df6bQl+ceAsqs79eq7X4KS7m2dk+VIjkzQuTGfd3pQw +ZUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1785766688; x=1786371488; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=on4B/LfqkHipeTiwMXYITPpUbegoRxXk89rke8WT6Ak=; b=KRiLN0CiYB/EKkKf9T9snlmJHFtA4HUu95P/aTmBsVXJUebA0klhbkjVVVv5YXasZ/ /c/fKq7+/5UeMH2pEqumZ05PAPL3Fhf1tFTNHFbZX6L/Sn+91OZDH+f1pR4E0op/LnTr aHyS1WsLRiRp6hxr55vNcn4Rdv4IP96AwRXXqL7KPZch3K9dAPhne9OaC9RTRqwg/TKd Rei0LYQmCll2e6vA2Tz+JrzBJGBvrdz43BOVMHyGLKIsQ5zjFf0t4s22UZeb4P5CbgwO yvYfIg0vl5ZquDSJi4PupVmEr+VF38REWh+E8DQEegxyAiAc/Mz2FTr4B8O++MAveAxr T0uQ== X-Forwarded-Encrypted: i=1; AHgh+Rpec2EqYZaifZN9co4HqJLw349l7PtFCZOSy8zaFJZn8Uy5pJn6S7b/6lIm7NAKZjgGZvt2p4lpqPF1hqE=@vger.kernel.org X-Gm-Message-State: AOJu0YxBqKGtGTwLUvlzZ7H6fQzBMQ82c7ooFHM6G82SHIiwbEIFuH0E SnCbklYgrFcet3aMtyTdia/W1ICI0/Gz+OzLZUr+vu0p/0yO3OzsdUiS X-Gm-Gg: AR+sD10qNLtGD5QpoKJpPA8+F2EH4ZJyo2CeIi68pQ59LOnCw8i4PczNaxWmLeO31nt xDuM4GuU+aKE0Y+6fVisBOg49c7rGtjSsMzihGEWZDiPTf9KjXLjf9eAdBsJ0It7EtawL2xp80e eaGEh5sMvUxNQzKR2ZMRacSJQ3SmEpd2Y/V6mie7HaK7aPHAbvsRubj/3zMzgN+CfRJxE55Osr6 Q9KdaMXkk7THDk4ixbire4F26fYu82DfTZ7eDQRbF40e1+Nf5FE6uALCYcIYYESVEzY+CPxmC09 IFGi7iNFz0ZAAvMX4Y9D1L2AT9ZCikJRMIlY4VK2aTICj6OlCxTsMQQ5h+uZe3YHvZ0AkDTiQrD FL9viNknH0gRIkOWPpHMWB/jcUBDtcRqe+vKHfaPSczmWdqil6pkYRexA92/eI6y0tTvaHJSmW6 TXgGzGbD+RbY9WqeoTGrSpuBCnIMMzv2d5WEtmNUXbJXq4PQLvSlEQ3aclMji+iigU506VmClqL zadBUIcgdtLBjIVQjqm X-Received: by 2002:a17:90b:5643:b0:38e:2f21:3bb5 with SMTP id 98e67ed59e1d1-38fbc4cfde2mr9523866a91.21.1785766687657; Mon, 03 Aug 2026 07:18:07 -0700 (PDT) Received: from buffalo-ssd (M014013071096.v4.enabler.ne.jp. [14.13.71.96]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38fb30dff2esm4078462a91.13.2026.08.03.07.18.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 07:18:07 -0700 (PDT) From: Akari Tsuyukusa To: Michael Turquette , Stephen Boyd , Brian Masney , Matthias Brugger , AngeloGioacchino Del Regno , Yassine Oudjana , Richard Cochran Cc: Laura Nao , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Chen-Yu Tsai , Akari Tsuyukusa , Bartosz Golaszewski , Danilo Krummrich , Bjorn Helgaas , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Nicolas Frattaroli , Takashi Sakamoto , Haotian Zhang , Kees Cook , Miles Chen , Daniel Golle , Sam Shih , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support), netdev@vger.kernel.org (open list:PTP HARDWARE CLOCK SUPPORT:Keyword:(?:\b|_)ptp(?:\b|_)), stable@vger.kernel.org Subject: [PATCH 09/32] clk: mediatek: Add cpumux support to common probe/remove helpers Date: Mon, 3 Aug 2026 23:16:36 +0900 Message-ID: <20260803141659.559129-10-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803141659.559129-1-akkun11.open@gmail.com> References: <20260803141659.559129-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Extend __mtk_clk_simple_probe() and __mtk_clk_simple_remove() to support cpumux clocks. This reduces boilerplate code in drivers for SoCs that require cpumux registration, such as mt6795-infracfg. Signed-off-by: Akari Tsuyukusa Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mtk.c | 18 +++++++++++++++++- drivers/clk/mediatek/clk-mtk.h | 2 ++ 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 3dfdd3a422f8..8148c21e6099 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -19,6 +19,7 @@ #include "clk-mtk.h" #include "clk-gate.h" #include "clk-mux.h" +#include "clk-cpumux.h" =20 const struct mtk_gate_regs cg_regs_dummy =3D { 0, 0, 0 }; EXPORT_SYMBOL_GPL(cg_regs_dummy); @@ -513,6 +514,7 @@ static int __mtk_clk_simple_probe(struct platform_devic= e *pdev, num_clks =3D mcd->num_clks + mcd->num_composite_clks; num_clks +=3D mcd->num_fixed_clks + mcd->num_factor_clks; num_clks +=3D mcd->num_mux_clks + mcd->num_divider_clks; + num_clks +=3D mcd->num_cpumuxes; =20 clk_data =3D mtk_alloc_clk_data(num_clks); if (!clk_data) { @@ -542,6 +544,13 @@ static int __mtk_clk_simple_probe(struct platform_devi= ce *pdev, goto unregister_factors; } =20 + if (mcd->cpumuxes) { + r =3D mtk_clk_register_cpumuxes(&pdev->dev, node, mcd->cpumuxes, + mcd->num_cpumuxes, clk_data); + if (r) + goto unregister_muxes; + } + if (mcd->composite_clks) { /* We don't check composite_lock because it's optional */ r =3D mtk_clk_register_composites(&pdev->dev, @@ -549,7 +558,7 @@ static int __mtk_clk_simple_probe(struct platform_devic= e *pdev, mcd->num_composite_clks, base, mcd->clk_lock, clk_data); if (r) - goto unregister_muxes; + goto unregister_cpumuxes; } =20 if (mcd->divider_clks) { @@ -605,6 +614,10 @@ static int __mtk_clk_simple_probe(struct platform_devi= ce *pdev, if (mcd->composite_clks) mtk_clk_unregister_composites(mcd->composite_clks, mcd->num_composite_clks, clk_data); +unregister_cpumuxes: + if (mcd->cpumuxes) + mtk_clk_unregister_cpumuxes(mcd->cpumuxes, + mcd->num_cpumuxes, clk_data); unregister_muxes: if (mcd->mux_clks) mtk_clk_unregister_muxes(mcd->mux_clks, @@ -643,6 +656,9 @@ static void __mtk_clk_simple_remove(struct platform_dev= ice *pdev, if (mcd->composite_clks) mtk_clk_unregister_composites(mcd->composite_clks, mcd->num_composite_clks, clk_data); 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[14.13.71.96]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38fb30dff2esm4078462a91.13.2026.08.03.07.18.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 07:18:11 -0700 (PDT) From: Akari Tsuyukusa To: Michael Turquette , Stephen Boyd , Brian Masney , Matthias Brugger , AngeloGioacchino Del Regno , Yassine Oudjana , Richard Cochran Cc: Laura Nao , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Chen-Yu Tsai , Akari Tsuyukusa , Bartosz Golaszewski , Danilo Krummrich , Bjorn Helgaas , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Nicolas Frattaroli , Takashi Sakamoto , Haotian Zhang , Kees Cook , Miles Chen , Daniel Golle , Sam Shih , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support), netdev@vger.kernel.org (open list:PTP HARDWARE CLOCK SUPPORT:Keyword:(?:\b|_)ptp(?:\b|_)), stable@vger.kernel.org Subject: [PATCH 10/32] clk: mediatek: Add PLL support to common probe/remove helpers Date: Mon, 3 Aug 2026 23:16:37 +0900 Message-ID: <20260803141659.559129-11-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803141659.559129-1-akkun11.open@gmail.com> References: <20260803141659.559129-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Extend __mtk_clk_simple_probe() and __mtk_clk_simple_remove() to support PLLs. This reduces boilerplate code in apmixedsys drivers. Signed-off-by: Akari Tsuyukusa --- drivers/clk/mediatek/clk-mtk.c | 19 ++++++++++++++++--- drivers/clk/mediatek/clk-mtk.h | 3 +++ 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 8148c21e6099..c3369a04cdec 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -20,6 +20,7 @@ #include "clk-gate.h" #include "clk-mux.h" #include "clk-cpumux.h" +#include "clk-pll.h" =20 const struct mtk_gate_regs cg_regs_dummy =3D { 0, 0, 0 }; EXPORT_SYMBOL_GPL(cg_regs_dummy); @@ -486,7 +487,7 @@ static int __mtk_clk_simple_probe(struct platform_devic= e *pdev, } =20 /* Composite and divider clocks needs us to pass iomem pointer */ - if (mcd->composite_clks || mcd->divider_clks) { + if (mcd->composite_clks || mcd->divider_clks || mcd->plls) { if (!mcd->shared_io) base =3D devm_platform_ioremap_resource(pdev, 0); else @@ -514,7 +515,7 @@ static int __mtk_clk_simple_probe(struct platform_devic= e *pdev, num_clks =3D mcd->num_clks + mcd->num_composite_clks; num_clks +=3D mcd->num_fixed_clks + mcd->num_factor_clks; num_clks +=3D mcd->num_mux_clks + mcd->num_divider_clks; - num_clks +=3D mcd->num_cpumuxes; + num_clks +=3D mcd->num_cpumuxes + mcd->num_plls; =20 clk_data =3D mtk_alloc_clk_data(num_clks); if (!clk_data) { @@ -522,11 +523,18 @@ static int __mtk_clk_simple_probe(struct platform_dev= ice *pdev, goto free_base; } =20 + if (mcd->plls) { + r =3D mtk_clk_register_plls(&pdev->dev, mcd->plls, + mcd->num_plls, clk_data); + if (r) + goto free_data; + } + if (mcd->fixed_clks) { r =3D mtk_clk_register_fixed_clks(mcd->fixed_clks, mcd->num_fixed_clks, clk_data); if (r) - goto free_data; + goto unregister_plls; } =20 if (mcd->factor_clks) { @@ -630,6 +638,9 @@ static int __mtk_clk_simple_probe(struct platform_devic= e *pdev, if (mcd->fixed_clks) mtk_clk_unregister_fixed_clks(mcd->fixed_clks, mcd->num_fixed_clks, clk_data); +unregister_plls: + if (mcd->plls) + mtk_clk_unregister_plls(mcd->plls, mcd->num_plls, clk_data); free_data: mtk_free_clk_data(clk_data); free_base: @@ -668,6 +679,8 @@ static void __mtk_clk_simple_remove(struct platform_dev= ice *pdev, if (mcd->fixed_clks) mtk_clk_unregister_fixed_clks(mcd->fixed_clks, mcd->num_fixed_clks, clk_data); + if (mcd->plls) + mtk_clk_unregister_plls(mcd->plls, mcd->num_plls, clk_data); mtk_free_clk_data(clk_data); } =20 diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index 02fab4b166f2..b6504b3e77ed 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -23,6 +23,7 @@ #define MTK_WAIT_HWV_DONE_US 30 =20 struct platform_device; +struct mtk_pll_data; =20 /* * We need the clock IDs to start from zero but to maintain devicetree @@ -254,6 +255,8 @@ struct mtk_clk_desc { size_t num_mux_clks; const struct mtk_composite *cpumuxes; size_t num_cpumuxes; + const struct mtk_pll_data *plls; + size_t num_plls; const struct mtk_clk_rst_desc *rst_desc; spinlock_t *clk_lock; bool shared_io; --=20 2.55.0 From nobody Fri Oct 2 08:24:59 2026 Received: from mail-pj1-f49.google.com (mail-pj1-f49.google.com [209.85.216.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D0E541D20C for ; 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[14.13.71.96]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38fb30dff2esm4078462a91.13.2026.08.03.07.18.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 07:18:16 -0700 (PDT) From: Akari Tsuyukusa To: Michael Turquette , Stephen Boyd , Brian Masney , Matthias Brugger , AngeloGioacchino Del Regno , Yassine Oudjana , Richard Cochran Cc: Laura Nao , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Chen-Yu Tsai , Akari Tsuyukusa , Bartosz Golaszewski , Danilo Krummrich , Bjorn Helgaas , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Nicolas Frattaroli , Takashi Sakamoto , Haotian Zhang , Kees Cook , Miles Chen , Daniel Golle , Sam Shih , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support), netdev@vger.kernel.org (open list:PTP HARDWARE CLOCK SUPPORT:Keyword:(?:\b|_)ptp(?:\b|_)), stable@vger.kernel.org Subject: [PATCH 11/32] clk: mediatek: Add auto-population of sub-devices support in simple probe Date: Mon, 3 Aug 2026 23:16:38 +0900 Message-ID: <20260803141659.559129-12-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803141659.559129-1-akkun11.open@gmail.com> References: <20260803141659.559129-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" MediaTek audio clock drivers call devm_of_platform_populate() after mtk_clk_simple_probe(). Extend __mtk_clk_simple_probe() to run devm_of_platform_populate() when the new 'populate_children' flag is set, reducing boilerplate. Note that explicit of_platform_depopulate() calls in remove functions are unnecessary because devm_of_platform_populate() is managed by devres and cleans up automatically. Signed-off-by: Akari Tsuyukusa --- drivers/clk/mediatek/clk-mtk.c | 7 +++++++ drivers/clk/mediatek/clk-mtk.h | 1 + 2 files changed, 8 insertions(+) diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index c3369a04cdec..71d70b5a9990 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -609,6 +610,12 @@ static int __mtk_clk_simple_probe(struct platform_devi= ce *pdev, if (mcd->need_runtime_pm) pm_runtime_put(&pdev->dev); =20 + if (mcd->populate_children) { + r =3D devm_of_platform_populate(&pdev->dev); + if (r) + goto unregister_clks; + } + return r; =20 unregister_clks: diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index b6504b3e77ed..11939e3e0b38 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -265,6 +265,7 @@ struct mtk_clk_desc { unsigned int mfg_clk_idx; =20 bool need_runtime_pm; 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[14.13.71.96]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38fb30dff2esm4078462a91.13.2026.08.03.07.18.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 07:18:21 -0700 (PDT) From: Akari Tsuyukusa To: Michael Turquette , Stephen Boyd , Brian Masney , Matthias Brugger , AngeloGioacchino Del Regno , Yassine Oudjana , Richard Cochran Cc: Laura Nao , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Chen-Yu Tsai , Akari Tsuyukusa , Bartosz Golaszewski , Danilo Krummrich , Bjorn Helgaas , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Nicolas Frattaroli , Takashi Sakamoto , Haotian Zhang , Kees Cook , Miles Chen , Daniel Golle , Sam Shih , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support), netdev@vger.kernel.org (open list:PTP HARDWARE CLOCK SUPPORT:Keyword:(?:\b|_)ptp(?:\b|_)), stable@vger.kernel.org Subject: [PATCH 12/32] clk: mediatek: Add pllfh support to common probe/remove helpers Date: Mon, 3 Aug 2026 23:16:39 +0900 Message-ID: <20260803141659.559129-13-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803141659.559129-1-akkun11.open@gmail.com> References: <20260803141659.559129-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Extend __mtk_clk_simple_probe() and __mtk_clk_simple_remove() to support pll freqhoppings. This reduces boilerplate code in apmixedsys drivers with pllfh support. Signed-off-by: Akari Tsuyukusa --- drivers/clk/mediatek/clk-mtk.c | 44 ++++++++++++++++++++++++++++++---- drivers/clk/mediatek/clk-mtk.h | 6 +++++ 2 files changed, 45 insertions(+), 5 deletions(-) diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 71d70b5a9990..e80ae497fadd 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -23,6 +23,10 @@ #include "clk-cpumux.h" #include "clk-pll.h" =20 +#if IS_ENABLED(CONFIG_COMMON_CLK_MEDIATEK_FHCTL) +#include "clk-fhctl.h" +#endif + const struct mtk_gate_regs cg_regs_dummy =3D { 0, 0, 0 }; EXPORT_SYMBOL_GPL(cg_regs_dummy); =20 @@ -525,8 +529,19 @@ static int __mtk_clk_simple_probe(struct platform_devi= ce *pdev, } =20 if (mcd->plls) { - r =3D mtk_clk_register_plls(&pdev->dev, mcd->plls, + if (mcd->fhctl_node) { +#if IS_ENABLED(CONFIG_COMMON_CLK_MEDIATEK_FHCTL) + fhctl_parse_dt(mcd->fhctl_node, mcd->pllfhs, + mcd->num_pllfhs); + r =3D mtk_clk_register_pllfhs(&pdev->dev, mcd->plls, + mcd->num_plls, mcd->pllfhs, + mcd->num_pllfhs, clk_data); +#endif + } else { + r =3D mtk_clk_register_plls(&pdev->dev, mcd->plls, mcd->num_plls, clk_data); + } + if (r) goto free_data; } @@ -646,8 +661,17 @@ static int __mtk_clk_simple_probe(struct platform_devi= ce *pdev, mtk_clk_unregister_fixed_clks(mcd->fixed_clks, mcd->num_fixed_clks, clk_data); unregister_plls: - if (mcd->plls) - mtk_clk_unregister_plls(mcd->plls, mcd->num_plls, clk_data); + if (mcd->plls) { + if (mcd->fhctl_node) +#if IS_ENABLED(CONFIG_COMMON_CLK_MEDIATEK_FHCTL) + mtk_clk_unregister_pllfhs(mcd->plls, mcd->num_plls, + mcd->pllfhs, mcd->num_pllfhs, + clk_data); +#endif + else + mtk_clk_unregister_plls(mcd->plls, mcd->num_plls, + clk_data); + } free_data: mtk_free_clk_data(clk_data); free_base: @@ -686,8 +710,18 @@ static void __mtk_clk_simple_remove(struct platform_de= vice *pdev, if (mcd->fixed_clks) mtk_clk_unregister_fixed_clks(mcd->fixed_clks, mcd->num_fixed_clks, clk_data); - if (mcd->plls) - mtk_clk_unregister_plls(mcd->plls, mcd->num_plls, clk_data); + if (mcd->plls) { + if (mcd->fhctl_node) +#if IS_ENABLED(CONFIG_COMMON_CLK_MEDIATEK_FHCTL) + mtk_clk_unregister_pllfhs(mcd->plls, mcd->num_plls, + mcd->pllfhs, mcd->num_pllfhs, + clk_data); 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[14.13.71.96]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38fb30dff2esm4078462a91.13.2026.08.03.07.18.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 07:18:25 -0700 (PDT) From: Akari Tsuyukusa To: Michael Turquette , Stephen Boyd , Brian Masney , Matthias Brugger , AngeloGioacchino Del Regno , Yassine Oudjana , Richard Cochran Cc: Laura Nao , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Chen-Yu Tsai , Akari Tsuyukusa , Bartosz Golaszewski , Danilo Krummrich , Bjorn Helgaas , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Nicolas Frattaroli , Takashi Sakamoto , Haotian Zhang , Kees Cook , Miles Chen , Daniel Golle , Sam Shih , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support), netdev@vger.kernel.org (open list:PTP HARDWARE CLOCK SUPPORT:Keyword:(?:\b|_)ptp(?:\b|_)), stable@vger.kernel.org Subject: [PATCH 13/32] clk: mediatek: mt2701: Switch to common probe/remove helpers Date: Mon, 3 Aug 2026 23:16:40 +0900 Message-ID: <20260803141659.559129-14-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803141659.559129-1-akkun11.open@gmail.com> References: <20260803141659.559129-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MT2701 clock drivers can use the MediaTek clock framework common initialization sequence. Reduce boilerplate code by creating struct mtk_clk_desc and using the mtk_clk_simple_probe/remove helpers. Drop the CLK_OF_DECLARE_DRIVER early init for infracfg; the kernel's deferred probe mechanism ensures dependent drivers like cpufreq are initialized correctly. Since all MT2701 clock drivers can now be built as modules, change Kconfig settings to "tristate". Signed-off-by: Akari Tsuyukusa --- drivers/clk/mediatek/Kconfig | 18 +- drivers/clk/mediatek/clk-mt2701-aud.c | 35 +--- drivers/clk/mediatek/clk-mt2701.c | 233 ++++++-------------------- 3 files changed, 65 insertions(+), 221 deletions(-) diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 2c09fd729bab..b58656a7e8c3 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -19,7 +19,7 @@ config COMMON_CLK_MEDIATEK_FHCTL spread spectrum clocking features. =20 config COMMON_CLK_MT2701 - bool "Clock driver for MediaTek MT2701" + tristate "Clock driver for MediaTek MT2701" depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST select COMMON_CLK_MEDIATEK default ARCH_MEDIATEK && ARM @@ -27,49 +27,49 @@ config COMMON_CLK_MT2701 This driver supports MediaTek MT2701 basic clocks. =20 config COMMON_CLK_MT2701_MMSYS - bool "Clock driver for MediaTek MT2701 mmsys" + tristate "Clock driver for MediaTek MT2701 mmsys" depends on COMMON_CLK_MT2701 help This driver supports MediaTek MT2701 mmsys clocks. =20 config COMMON_CLK_MT2701_IMGSYS - bool "Clock driver for MediaTek MT2701 imgsys" + tristate "Clock driver for MediaTek MT2701 imgsys" depends on COMMON_CLK_MT2701 help This driver supports MediaTek MT2701 imgsys clocks. =20 config COMMON_CLK_MT2701_VDECSYS - bool "Clock driver for MediaTek MT2701 vdecsys" + tristate "Clock driver for MediaTek MT2701 vdecsys" depends on COMMON_CLK_MT2701 help This driver supports MediaTek MT2701 vdecsys clocks. =20 config COMMON_CLK_MT2701_HIFSYS - bool "Clock driver for MediaTek MT2701 hifsys" + tristate "Clock driver for MediaTek MT2701 hifsys" depends on COMMON_CLK_MT2701 help This driver supports MediaTek MT2701 hifsys clocks. =20 config COMMON_CLK_MT2701_ETHSYS - bool "Clock driver for MediaTek MT2701 ethsys" + tristate "Clock driver for MediaTek MT2701 ethsys" depends on COMMON_CLK_MT2701 help This driver supports MediaTek MT2701 ethsys clocks. =20 config COMMON_CLK_MT2701_BDPSYS - bool "Clock driver for MediaTek MT2701 bdpsys" + tristate "Clock driver for MediaTek MT2701 bdpsys" depends on COMMON_CLK_MT2701 help This driver supports MediaTek MT2701 bdpsys clocks. =20 config COMMON_CLK_MT2701_AUDSYS - bool "Clock driver for Mediatek MT2701 audsys" + tristate "Clock driver for Mediatek MT2701 audsys" depends on COMMON_CLK_MT2701 help This driver supports Mediatek MT2701 audsys clocks. =20 config COMMON_CLK_MT2701_G3DSYS - bool "Clock driver for MediaTek MT2701 g3dsys" + tristate "Clock driver for MediaTek MT2701 g3dsys" depends on COMMON_CLK_MT2701 help This driver supports MediaTek MT2701 g3dsys clocks. diff --git a/drivers/clk/mediatek/clk-mt2701-aud.c b/drivers/clk/mediatek/c= lk-mt2701-aud.c index e103121cf58e..533d35614661 100644 --- a/drivers/clk/mediatek/clk-mt2701-aud.c +++ b/drivers/clk/mediatek/clk-mt2701-aud.c @@ -128,6 +128,7 @@ static const struct mtk_gate audio_clks[] =3D { static const struct mtk_clk_desc audio_desc =3D { .clks =3D audio_clks, .num_clks =3D ARRAY_SIZE(audio_clks), + .populate_children =3D true, }; =20 static const struct of_device_id of_match_clk_mt2701_aud[] =3D { @@ -136,39 +137,9 @@ static const struct of_device_id of_match_clk_mt2701_a= ud[] =3D { }; MODULE_DEVICE_TABLE(of, of_match_clk_mt2701_aud); =20 -static int clk_mt2701_aud_probe(struct platform_device *pdev) -{ - int r; - - r =3D mtk_clk_simple_probe(pdev); - if (r) { - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - return r; - } - - r =3D devm_of_platform_populate(&pdev->dev); - if (r) - goto err_plat_populate; - - return 0; - -err_plat_populate: - mtk_clk_simple_remove(pdev); - return r; -} - -static void clk_mt2701_aud_remove(struct platform_device *pdev) -{ - of_platform_depopulate(&pdev->dev); - mtk_clk_simple_remove(pdev); -} - static struct platform_driver clk_mt2701_aud_drv =3D { - .probe =3D clk_mt2701_aud_probe, - .remove =3D clk_mt2701_aud_remove, + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, .driver =3D { .name =3D "clk-mt2701-aud", .of_match_table =3D of_match_clk_mt2701_aud, diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-m= t2701.c index 710c4f2f9f30..5ea0c4acaf1b 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -6,6 +6,7 @@ =20 #include #include +#include =20 #include "clk-cpumux.h" #include "clk-gate.h" @@ -655,38 +656,19 @@ static const struct mtk_gate top_clks[] =3D { 28), }; =20 -static int mtk_topckgen_init(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - void __iomem *base; - struct device_node *node =3D pdev->dev.of_node; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - clk_data =3D mtk_alloc_clk_data(CLK_TOP_NR); - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), - clk_data); - - mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs), - clk_data); - - mtk_clk_register_composites(&pdev->dev, top_muxes, - ARRAY_SIZE(top_muxes), base, - &mt2701_clk_lock, clk_data); - - mtk_clk_register_dividers(&pdev->dev, top_adj_divs, ARRAY_SIZE(top_adj_di= vs), - base, &mt2701_clk_lock, clk_data); - - mtk_clk_register_gates(&pdev->dev, node, top_clks, - ARRAY_SIZE(top_clks), clk_data); - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -} +static const struct mtk_clk_desc topck_desc =3D { + .clks =3D top_clks, + .num_clks =3D ARRAY_SIZE(top_clks), + .fixed_clks =3D top_fixed_clks, + .num_fixed_clks =3D ARRAY_SIZE(top_fixed_clks), + .factor_clks =3D top_fixed_divs, + .num_factor_clks =3D ARRAY_SIZE(top_fixed_divs), + .composite_clks =3D top_muxes, + .num_composite_clks =3D ARRAY_SIZE(top_muxes), + .divider_clks =3D top_adj_divs, + .num_divider_clks =3D ARRAY_SIZE(top_adj_divs), + .clk_lock =3D &mt2701_clk_lock, +}; =20 static const struct mtk_gate_regs infra_cg_regs =3D { .set_ofs =3D 0x0040, @@ -725,81 +707,21 @@ static const struct mtk_fixed_factor infra_fixed_divs= [] =3D { static u16 infrasys_rst_ofs[] =3D { 0x30, 0x34, }; static u16 pericfg_rst_ofs[] =3D { 0x0, 0x4, }; =20 -static const struct mtk_clk_rst_desc clk_rst_desc[] =3D { - /* infrasys */ - { - .version =3D MTK_RST_SIMPLE, - .rst_bank_ofs =3D infrasys_rst_ofs, - .rst_bank_nr =3D ARRAY_SIZE(infrasys_rst_ofs), - }, - /* pericfg */ - { - .version =3D MTK_RST_SIMPLE, - .rst_bank_ofs =3D pericfg_rst_ofs, - .rst_bank_nr =3D ARRAY_SIZE(pericfg_rst_ofs), - }, +static const struct mtk_clk_rst_desc infra_rst_desc =3D { + .version =3D MTK_RST_SIMPLE, + .rst_bank_ofs =3D infrasys_rst_ofs, + .rst_bank_nr =3D ARRAY_SIZE(infrasys_rst_ofs), }; =20 -static struct clk_hw_onecell_data *infra_clk_data; - -static void __init mtk_infrasys_init_early(struct device_node *node) -{ - int r, i; - - if (!infra_clk_data) { - infra_clk_data =3D mtk_alloc_clk_data(CLK_INFRA_NR); - if (!infra_clk_data) - return; - - for (i =3D 0; i < CLK_INFRA_NR; i++) - infra_clk_data->hws[i] =3D ERR_PTR(-EPROBE_DEFER); - } - - mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs), - infra_clk_data); - - mtk_clk_register_cpumuxes(NULL, node, cpu_muxes, ARRAY_SIZE(cpu_muxes), - infra_clk_data); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, - infra_clk_data); - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); -} -CLK_OF_DECLARE_DRIVER(mtk_infra, "mediatek,mt2701-infracfg", - mtk_infrasys_init_early); - -static int mtk_infrasys_init(struct platform_device *pdev) -{ - int r, i; - struct device_node *node =3D pdev->dev.of_node; - - if (!infra_clk_data) { - infra_clk_data =3D mtk_alloc_clk_data(CLK_INFRA_NR); - if (!infra_clk_data) - return -ENOMEM; - } else { - for (i =3D 0; i < CLK_INFRA_NR; i++) { - if (infra_clk_data->hws[i] =3D=3D ERR_PTR(-EPROBE_DEFER)) - infra_clk_data->hws[i] =3D ERR_PTR(-ENOENT); - } - } - - mtk_clk_register_gates(&pdev->dev, node, infra_clks, - ARRAY_SIZE(infra_clks), infra_clk_data); - mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs), - infra_clk_data); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, - infra_clk_data); - if (r) - return r; - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]); - - return 0; -} +static const struct mtk_clk_desc infracfg_desc =3D { + .clks =3D infra_clks, + .num_clks =3D ARRAY_SIZE(infra_clks), + .factor_clks =3D infra_fixed_divs, + .num_factor_clks =3D ARRAY_SIZE(infra_fixed_divs), + .cpumuxes =3D cpu_muxes, + .num_cpumuxes =3D ARRAY_SIZE(cpu_muxes), + .rst_desc =3D &infra_rst_desc, +}; =20 static const struct mtk_gate_regs peri0_cg_regs =3D { .set_ofs =3D 0x0008, @@ -883,36 +805,20 @@ static const struct mtk_composite peri_muxs[] =3D { 0x40c, 3, 1), }; =20 -static int mtk_pericfg_init(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - void __iomem *base; - int r; - struct device_node *node =3D pdev->dev.of_node; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - clk_data =3D mtk_alloc_clk_data(CLK_PERI_NR); - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_gates(&pdev->dev, node, peri_clks, - ARRAY_SIZE(peri_clks), clk_data); - - mtk_clk_register_composites(&pdev->dev, peri_muxs, - ARRAY_SIZE(peri_muxs), base, - &mt2701_clk_lock, clk_data); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - return r; - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]); +static const struct mtk_clk_rst_desc peri_rst_desc =3D { + .version =3D MTK_RST_SIMPLE, + .rst_bank_ofs =3D pericfg_rst_ofs, + .rst_bank_nr =3D ARRAY_SIZE(pericfg_rst_ofs), +}; =20 - return 0; -} +static const struct mtk_clk_desc pericfg_desc =3D { + .clks =3D peri_clks, + .num_clks =3D ARRAY_SIZE(peri_clks), + .composite_clks =3D peri_muxs, + .num_composite_clks =3D ARRAY_SIZE(peri_muxs), + .rst_desc =3D &peri_rst_desc, + .clk_lock =3D &mt2701_clk_lock, +}; =20 #define MT8590_PLL_FMAX (2000 * MHZ) #define CON0_MT8590_RST_BAR BIT(27) @@ -968,74 +874,41 @@ static const struct mtk_fixed_factor apmixed_fixed_di= vs[] =3D { FACTOR(CLK_APMIXED_HDMI_REF, "hdmi_ref", "tvdpll", 1, 1), }; =20 -static int mtk_apmixedsys_init(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - - clk_data =3D mtk_alloc_clk_data(CLK_APMIXED_NR); - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_plls(&pdev->dev, apmixed_plls, ARRAY_SIZE(apmixed_plls), - clk_data); - mtk_clk_register_factors(apmixed_fixed_divs, ARRAY_SIZE(apmixed_fixed_div= s), - clk_data); - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -} +static const struct mtk_clk_desc apmixedsys_desc =3D { + .plls =3D apmixed_plls, + .num_plls =3D ARRAY_SIZE(apmixed_plls), + .factor_clks =3D apmixed_fixed_divs, + .num_factor_clks =3D ARRAY_SIZE(apmixed_fixed_divs), +}; =20 static const struct of_device_id of_match_clk_mt2701[] =3D { { .compatible =3D "mediatek,mt2701-topckgen", - .data =3D mtk_topckgen_init, + .data =3D &topck_desc, }, { .compatible =3D "mediatek,mt2701-infracfg", - .data =3D mtk_infrasys_init, + .data =3D &infracfg_desc, }, { .compatible =3D "mediatek,mt2701-pericfg", - .data =3D mtk_pericfg_init, + .data =3D &pericfg_desc, }, { .compatible =3D "mediatek,mt2701-apmixedsys", - .data =3D mtk_apmixedsys_init, + .data =3D &apmixedsys_desc, }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, of_match_clk_mt2701); =20 -static int clk_mt2701_probe(struct platform_device *pdev) -{ - int (*clk_init)(struct platform_device *); - int r; - - clk_init =3D of_device_get_match_data(&pdev->dev); - if (!clk_init) - return -EINVAL; - - r =3D clk_init(pdev); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - return r; -} - static struct platform_driver clk_mt2701_drv =3D { - .probe =3D clk_mt2701_probe, .driver =3D { .name =3D "clk-mt2701", .of_match_table =3D of_match_clk_mt2701, }, + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, }; - -static int __init clk_mt2701_init(void) -{ - return platform_driver_register(&clk_mt2701_drv); -} - -arch_initcall(clk_mt2701_init); +module_platform_driver(clk_mt2701_drv); =20 MODULE_DESCRIPTION("MediaTek MT2701 main clocks driver"); MODULE_LICENSE("GPL"); --=20 2.55.0 From nobody Fri Oct 2 08:24:59 2026 Received: from mail-pj1-f44.google.com (mail-pj1-f44.google.com [209.85.216.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 310E0421223 for ; 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[14.13.71.96]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38fb30dff2esm4078462a91.13.2026.08.03.07.18.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 07:18:30 -0700 (PDT) From: Akari Tsuyukusa To: Michael Turquette , Stephen Boyd , Brian Masney , Matthias Brugger , AngeloGioacchino Del Regno , Yassine Oudjana , Richard Cochran Cc: Laura Nao , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Chen-Yu Tsai , Akari Tsuyukusa , Bartosz Golaszewski , Danilo Krummrich , Bjorn Helgaas , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Nicolas Frattaroli , Takashi Sakamoto , Haotian Zhang , Kees Cook , Miles Chen , Daniel Golle , Sam Shih , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support), netdev@vger.kernel.org (open list:PTP HARDWARE CLOCK SUPPORT:Keyword:(?:\b|_)ptp(?:\b|_)), stable@vger.kernel.org Subject: [PATCH 14/32] clk: mediatek: mt2712-apmixedsys: Switch to common probe/remove helpers Date: Mon, 3 Aug 2026 23:16:41 +0900 Message-ID: <20260803141659.559129-15-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803141659.559129-1-akkun11.open@gmail.com> References: <20260803141659.559129-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MT2712 apmixedsys driver can use the MediaTek clock framework common initialization sequence. Reduce boilerplate code by creating struct mtk_clk_desc and using the mtk_clk_simple_probe/remove helpers. Signed-off-by: Akari Tsuyukusa --- drivers/clk/mediatek/clk-mt2712-apmixedsys.c | 50 +++----------------- 1 file changed, 7 insertions(+), 43 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2712-apmixedsys.c b/drivers/clk/med= iatek/clk-mt2712-apmixedsys.c index 087cf574bcdc..1e06f87e71d0 100644 --- a/drivers/clk/mediatek/clk-mt2712-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt2712-apmixedsys.c @@ -109,56 +109,20 @@ static const struct mtk_pll_data plls[] =3D { 0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0), }; =20 -static int clk_mt2712_apmixed_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - int r; - struct device_node *node =3D pdev->dev.of_node; - - clk_data =3D mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); - if (!clk_data) - return -ENOMEM; - - r =3D mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data); - if (r) - goto free_clk_data; - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) { - dev_err(&pdev->dev, "Cannot register clock provider: %d\n", r); - goto unregister_plls; - } - - platform_set_drvdata(pdev, clk_data); - - return 0; - -unregister_plls: - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); -free_clk_data: - mtk_free_clk_data(clk_data); - return r; -} - -static void clk_mt2712_apmixed_remove(struct platform_device *pdev) -{ - struct device_node *node =3D pdev->dev.of_node; - struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); - - of_clk_del_provider(node); - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); - mtk_free_clk_data(clk_data); -} +static const struct mtk_clk_desc apmixed_desc =3D { + .plls =3D plls, + .num_plls =3D ARRAY_SIZE(plls), +}; =20 static const struct of_device_id of_match_clk_mt2712_apmixed[] =3D { - { .compatible =3D "mediatek,mt2712-apmixedsys" }, + { .compatible =3D "mediatek,mt2712-apmixedsys", .data =3D &apmixed_desc }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, of_match_clk_mt2712_apmixed); =20 static struct platform_driver clk_mt2712_apmixed_drv =3D { - .probe =3D clk_mt2712_apmixed_probe, - .remove =3D clk_mt2712_apmixed_remove, + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, .driver =3D { .name =3D "clk-mt2712-apmixed", .of_match_table =3D of_match_clk_mt2712_apmixed, --=20 2.55.0 From nobody Fri Oct 2 08:24:59 2026 Received: from mail-pj1-f44.google.com (mail-pj1-f44.google.com [209.85.216.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B32404218AC for ; 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[14.13.71.96]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38fb30dff2esm4078462a91.13.2026.08.03.07.18.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 07:18:34 -0700 (PDT) From: Akari Tsuyukusa To: Michael Turquette , Stephen Boyd , Brian Masney , Matthias Brugger , AngeloGioacchino Del Regno , Yassine Oudjana , Richard Cochran Cc: Laura Nao , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Chen-Yu Tsai , Akari Tsuyukusa , Bartosz Golaszewski , Danilo Krummrich , Bjorn Helgaas , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Nicolas Frattaroli , Takashi Sakamoto , Haotian Zhang , Kees Cook , Miles Chen , Daniel Golle , Sam Shih , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support), netdev@vger.kernel.org (open list:PTP HARDWARE CLOCK SUPPORT:Keyword:(?:\b|_)ptp(?:\b|_)), stable@vger.kernel.org Subject: [PATCH 15/32] clk: mediatek: mt6735-apmixedsys: Switch to common probe/remove helpers Date: Mon, 3 Aug 2026 23:16:42 +0900 Message-ID: <20260803141659.559129-16-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803141659.559129-1-akkun11.open@gmail.com> References: <20260803141659.559129-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MT6735 apmixedsys driver can use the MediaTek clock framework common initialization sequence. Reduce boilerplate code by creating struct mtk_clk_desc and using the mtk_clk_simple_probe/remove helpers. Signed-off-by: Akari Tsuyukusa --- drivers/clk/mediatek/clk-mt6735-apmixedsys.c | 48 +++----------------- 1 file changed, 7 insertions(+), 41 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt6735-apmixedsys.c b/drivers/clk/med= iatek/clk-mt6735-apmixedsys.c index 9e30c089a209..94cb0bee8bb4 100644 --- a/drivers/clk/mediatek/clk-mt6735-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt6735-apmixedsys.c @@ -77,54 +77,20 @@ static const struct mtk_pll_data apmixedsys_plls[] =3D { PLL(CLK_APMIXED_APLL2, "apll2", APLL2_CON0, APLL2_PWR_CON0, 0x00000001, 0= , APLL2_CON0, 4, APLL2_CON2, AP_PLL_CON_5, 1, APLL2_CON1, 31, 0) }; =20 -static int clk_mt6735_apmixed_probe(struct platform_device *pdev) -{ - void __iomem *base; - struct resource *res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); - struct clk_hw_onecell_data *clk_data; - int ret; - - base =3D devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(base)) - return PTR_ERR(base); - - clk_data =3D mtk_devm_alloc_clk_data(&pdev->dev, ARRAY_SIZE(apmixedsys_pl= ls)); - if (!clk_data) - return -ENOMEM; - platform_set_drvdata(pdev, clk_data); - - ret =3D mtk_clk_register_plls(&pdev->dev, apmixedsys_plls, - ARRAY_SIZE(apmixedsys_plls), clk_data); - if (ret) { - dev_err(&pdev->dev, "Failed to register PLLs: %d\n", ret); - return ret; - } - - ret =3D devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get, - clk_data); - if (ret) - dev_err(&pdev->dev, - "Failed to register clock provider: %d\n", ret); - - return ret; -} - -static void clk_mt6735_apmixed_remove(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); - - mtk_clk_unregister_plls(apmixedsys_plls, ARRAY_SIZE(apmixedsys_plls), clk= _data); -} +static const struct mtk_clk_desc apmixed_desc =3D { + .plls =3D apmixedsys_plls, + .num_plls =3D ARRAY_SIZE(apmixedsys_plls), +}; =20 static const struct of_device_id of_match_mt6735_apmixedsys[] =3D { - { .compatible =3D "mediatek,mt6735-apmixedsys" }, + { .compatible =3D "mediatek,mt6735-apmixedsys", .data =3D &apmixed_desc }, { /* sentinel */ } }; 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[14.13.71.96]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38fb30dff2esm4078462a91.13.2026.08.03.07.18.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 07:18:39 -0700 (PDT) From: Akari Tsuyukusa To: Michael Turquette , Stephen Boyd , Brian Masney , Matthias Brugger , AngeloGioacchino Del Regno , Yassine Oudjana , Richard Cochran Cc: Laura Nao , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Chen-Yu Tsai , Akari Tsuyukusa , Bartosz Golaszewski , Danilo Krummrich , Bjorn Helgaas , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Nicolas Frattaroli , Takashi Sakamoto , Haotian Zhang , Kees Cook , Miles Chen , Daniel Golle , Sam Shih , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support), netdev@vger.kernel.org (open list:PTP HARDWARE CLOCK SUPPORT:Keyword:(?:\b|_)ptp(?:\b|_)), stable@vger.kernel.org Subject: [PATCH 16/32] clk: mediatek: mt6779: Switch to common probe/remove helpers Date: Mon, 3 Aug 2026 23:16:43 +0900 Message-ID: <20260803141659.559129-17-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803141659.559129-1-akkun11.open@gmail.com> References: <20260803141659.559129-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MT6779 main clock driver can use the MediaTek clock framework common initialization sequence. Reduce boilerplate code by creating struct mtk_clk_desc and using the mtk_clk_simple_probe/remove helpers. Additionally, merge the separate infracfg and other drivers into a single platform driver, and add support for the apmixed and topckgen clock controllers using the consolidated of_match_table. Finally, replace the custom arch_initcall() initialization loop with the module_platform_driver() macro. Signed-off-by: Akari Tsuyukusa --- drivers/clk/mediatek/clk-mt6779.c | 124 ++++++------------------------ 1 file changed, 22 insertions(+), 102 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-m= t6779.c index 4b9dcb910b03..a806789ae27c 100644 --- a/drivers/clk/mediatek/clk-mt6779.c +++ b/drivers/clk/mediatek/clk-mt6779.c @@ -808,7 +808,7 @@ static const char * const i2s5_m_ck_parents[] =3D { "aud_2_sel" }; =20 -static const struct mtk_composite top_aud_muxes[] =3D { +static const struct mtk_composite top_aud_muxes_divs[] =3D { MUX(CLK_TOP_I2S0_M_SEL, "i2s0_m_ck_sel", i2s0_m_ck_parents, 0x320, 8, 1), MUX(CLK_TOP_I2S1_M_SEL, "i2s1_m_ck_sel", i2s1_m_ck_parents, @@ -821,9 +821,7 @@ static const struct mtk_composite top_aud_muxes[] =3D { 0x320, 12, 1), MUX(CLK_TOP_I2S5_M_SEL, "i2s5_m_ck_sel", i2s5_m_ck_parents, 0x328, 20, 1), -}; =20 -static struct mtk_composite top_aud_divs[] =3D { DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "i2s0_m_ck_sel", 0x320, 2, 0x324, 8, 0), DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "i2s1_m_ck_sel", @@ -1211,125 +1209,47 @@ static const struct mtk_pll_data plls[] =3D { 0, 0, 32, 8, 0x02D4, 1, 0, 0x14, 1, 0x02D8, 0, 0x02D4), }; =20 -static int clk_mt6779_apmixed_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - - clk_data =3D mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data); - - mtk_clk_register_gates(&pdev->dev, node, apmixed_clks, - ARRAY_SIZE(apmixed_clks), clk_data); - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -} - -static int clk_mt6779_top_probe(struct platform_device *pdev) -{ - void __iomem *base; - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - clk_data =3D mtk_alloc_clk_data(CLK_TOP_NR_CLK); - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), - clk_data); - - mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); - - mtk_clk_register_muxes(&pdev->dev, top_muxes, - ARRAY_SIZE(top_muxes), node, - &mt6779_clk_lock, clk_data); - - mtk_clk_register_composites(&pdev->dev, top_aud_muxes, - ARRAY_SIZE(top_aud_muxes), base, - &mt6779_clk_lock, clk_data); - - mtk_clk_register_composites(&pdev->dev, top_aud_divs, - ARRAY_SIZE(top_aud_divs), base, - &mt6779_clk_lock, clk_data); - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -} - -static const struct of_device_id of_match_clk_mt6779[] =3D { - { - .compatible =3D "mediatek,mt6779-apmixed", - .data =3D clk_mt6779_apmixed_probe, - }, { - .compatible =3D "mediatek,mt6779-topckgen", - .data =3D clk_mt6779_top_probe, - }, { - /* sentinel */ - } +static const struct mtk_clk_desc apmixed_desc =3D { + .clks =3D apmixed_clks, + .num_clks =3D ARRAY_SIZE(apmixed_clks), + .plls =3D plls, + .num_plls =3D ARRAY_SIZE(plls), }; =20 -static int clk_mt6779_probe(struct platform_device *pdev) -{ - int (*clk_probe)(struct platform_device *pdev); - int r; - - clk_probe =3D of_device_get_match_data(&pdev->dev); - if (!clk_probe) - return -EINVAL; - - r =3D clk_probe(pdev); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - return r; -} +static const struct mtk_clk_desc topck_desc =3D { + .fixed_clks =3D top_fixed_clks, + .num_fixed_clks =3D ARRAY_SIZE(top_fixed_clks), + .factor_clks =3D top_divs, + .num_factor_clks =3D ARRAY_SIZE(top_divs), + .mux_clks =3D top_muxes, + .num_mux_clks =3D ARRAY_SIZE(top_muxes), + .composite_clks =3D top_aud_muxes_divs, + .num_composite_clks =3D ARRAY_SIZE(top_aud_muxes_divs), + .clk_lock =3D &mt6779_clk_lock, +}; =20 static const struct mtk_clk_desc infra_desc =3D { .clks =3D infra_clks, .num_clks =3D ARRAY_SIZE(infra_clks), }; =20 -static const struct of_device_id of_match_clk_mt6779_infra[] =3D { +static const struct of_device_id of_match_clk_mt6779[] =3D { + { .compatible =3D "mediatek,mt6779-apmixed", .data =3D &apmixed_desc }, + { .compatible =3D "mediatek,mt6779-topckgen", .data =3D &topck_desc }, { .compatible =3D "mediatek,mt6779-infracfg_ao", .data =3D &infra_desc }, { /* sentinel */ } }; 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[14.13.71.96]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38fb30dff2esm4078462a91.13.2026.08.03.07.18.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 07:18:43 -0700 (PDT) From: Akari Tsuyukusa To: Michael Turquette , Stephen Boyd , Brian Masney , Matthias Brugger , AngeloGioacchino Del Regno , Yassine Oudjana , Richard Cochran Cc: Laura Nao , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Chen-Yu Tsai , Akari Tsuyukusa , Bartosz Golaszewski , Danilo Krummrich , Bjorn Helgaas , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Nicolas Frattaroli , Takashi Sakamoto , Haotian Zhang , Kees Cook , Miles Chen , Daniel Golle , Sam Shih , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support), netdev@vger.kernel.org (open list:PTP HARDWARE CLOCK SUPPORT:Keyword:(?:\b|_)ptp(?:\b|_)), stable@vger.kernel.org Subject: [PATCH 17/32] clk: mediatek: mt6795: Switch to common probe/remove helpers Date: Mon, 3 Aug 2026 23:16:44 +0900 Message-ID: <20260803141659.559129-18-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803141659.559129-1-akkun11.open@gmail.com> References: <20260803141659.559129-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MT6795 infracfg and pericfg drivers can use the MediaTek clock framework common initialization sequence. Reduce boilerplate code by creating struct mtk_clk_desc and using the mtk_clk_simple_probe/remove helpers. Note that the apmixedsys driver is excluded from this conversion because it requires ref2usb_tx clock handling, which is not currently supported by the common simple probe helper. Signed-off-by: Akari Tsuyukusa --- drivers/clk/mediatek/clk-mt6795-infracfg.c | 72 ++++----------------- drivers/clk/mediatek/clk-mt6795-pericfg.c | 73 ++++------------------ 2 files changed, 23 insertions(+), 122 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt6795-infracfg.c b/drivers/clk/media= tek/clk-mt6795-infracfg.c index 914bb069aa85..6aefc577ece5 100644 --- a/drivers/clk/mediatek/clk-mt6795-infracfg.c +++ b/drivers/clk/mediatek/clk-mt6795-infracfg.c @@ -8,7 +8,6 @@ #include #include #include -#include "clk-cpumux.h" #include "clk-gate.h" #include "clk-mtk.h" #include "reset.h" @@ -77,76 +76,27 @@ static const struct mtk_clk_rst_desc clk_rst_desc =3D { .rst_idx_map_nr =3D ARRAY_SIZE(infra_ao_idx_map), }; =20 +static const struct mtk_clk_desc infra_desc =3D { + .clks =3D infra_gates, + .num_clks =3D ARRAY_SIZE(infra_gates), + .cpumuxes =3D cpu_muxes, + .num_cpumuxes =3D ARRAY_SIZE(cpu_muxes), + .rst_desc =3D &clk_rst_desc, +}; + static const struct of_device_id of_match_clk_mt6795_infracfg[] =3D { - { .compatible =3D "mediatek,mt6795-infracfg" }, + { .compatible =3D "mediatek,mt6795-infracfg", .data =3D &infra_desc }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, of_match_clk_mt6795_infracfg); =20 -static int clk_mt6795_infracfg_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - void __iomem *base; - int ret; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - clk_data =3D mtk_alloc_clk_data(CLK_INFRA_NR_CLK); - if (!clk_data) - return -ENOMEM; - - ret =3D mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); - if (ret) - goto free_clk_data; - - ret =3D mtk_clk_register_gates(&pdev->dev, node, infra_gates, - ARRAY_SIZE(infra_gates), clk_data); - if (ret) - goto free_clk_data; - - ret =3D mtk_clk_register_cpumuxes(&pdev->dev, node, cpu_muxes, - ARRAY_SIZE(cpu_muxes), clk_data); - if (ret) - goto unregister_gates; - - ret =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (ret) - goto unregister_cpumuxes; - - platform_set_drvdata(pdev, clk_data); - - return 0; - -unregister_cpumuxes: - mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data); -unregister_gates: - mtk_clk_unregister_gates(infra_gates, ARRAY_SIZE(infra_gates), clk_data); -free_clk_data: - mtk_free_clk_data(clk_data); - return ret; -} - -static void clk_mt6795_infracfg_remove(struct platform_device *pdev) -{ - struct device_node *node =3D pdev->dev.of_node; - struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); - - of_clk_del_provider(node); - mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data); - mtk_clk_unregister_gates(infra_gates, ARRAY_SIZE(infra_gates), clk_data); - mtk_free_clk_data(clk_data); -} - static struct platform_driver clk_mt6795_infracfg_drv =3D { .driver =3D { .name =3D "clk-mt6795-infracfg", .of_match_table =3D of_match_clk_mt6795_infracfg, }, - .probe =3D clk_mt6795_infracfg_probe, - .remove =3D clk_mt6795_infracfg_remove, + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, }; module_platform_driver(clk_mt6795_infracfg_drv); =20 diff --git a/drivers/clk/mediatek/clk-mt6795-pericfg.c b/drivers/clk/mediat= ek/clk-mt6795-pericfg.c index 27d0ef7d7b2f..53c79e830b6a 100644 --- a/drivers/clk/mediatek/clk-mt6795-pericfg.c +++ b/drivers/clk/mediatek/clk-mt6795-pericfg.c @@ -85,77 +85,28 @@ static const struct mtk_clk_rst_desc clk_rst_desc =3D { .rst_idx_map_nr =3D ARRAY_SIZE(peri_idx_map), }; =20 +static const struct mtk_clk_desc pericfg_desc =3D { + .clks =3D peri_gates, + .num_clks =3D ARRAY_SIZE(peri_gates), + .composite_clks =3D peri_clks, + .num_composite_clks =3D ARRAY_SIZE(peri_clks), + .rst_desc =3D &clk_rst_desc, + .clk_lock =3D &mt6795_peri_clk_lock, +}; + static const struct of_device_id of_match_clk_mt6795_pericfg[] =3D { - { .compatible =3D "mediatek,mt6795-pericfg" }, + { .compatible =3D "mediatek,mt6795-pericfg", .data =3D &pericfg_desc }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, of_match_clk_mt6795_pericfg); =20 -static int clk_mt6795_pericfg_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - void __iomem *base; - int ret; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - clk_data =3D mtk_alloc_clk_data(CLK_PERI_NR_CLK); - if (!clk_data) - return -ENOMEM; - - ret =3D mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); - if (ret) - goto free_clk_data; - - ret =3D mtk_clk_register_gates(&pdev->dev, node, peri_gates, - ARRAY_SIZE(peri_gates), clk_data); - if (ret) - goto free_clk_data; - - ret =3D mtk_clk_register_composites(&pdev->dev, peri_clks, - ARRAY_SIZE(peri_clks), base, - &mt6795_peri_clk_lock, clk_data); - if (ret) - goto unregister_gates; - - ret =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (ret) - goto unregister_composites; - - platform_set_drvdata(pdev, clk_data); - - return 0; - -unregister_composites: - mtk_clk_unregister_composites(peri_clks, ARRAY_SIZE(peri_clks), clk_data); -unregister_gates: - mtk_clk_unregister_gates(peri_gates, ARRAY_SIZE(peri_gates), clk_data); -free_clk_data: - mtk_free_clk_data(clk_data); - return ret; -} - -static void clk_mt6795_pericfg_remove(struct platform_device *pdev) -{ - struct device_node *node =3D pdev->dev.of_node; - struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); - - of_clk_del_provider(node); - mtk_clk_unregister_composites(peri_clks, ARRAY_SIZE(peri_clks), clk_data); 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[14.13.71.96]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38fb30dff2esm4078462a91.13.2026.08.03.07.18.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 07:18:48 -0700 (PDT) From: Akari Tsuyukusa To: Michael Turquette , Stephen Boyd , Brian Masney , Matthias Brugger , AngeloGioacchino Del Regno , Yassine Oudjana , Richard Cochran Cc: Laura Nao , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Chen-Yu Tsai , Akari Tsuyukusa , Bartosz Golaszewski , Danilo Krummrich , Bjorn Helgaas , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Nicolas Frattaroli , Takashi Sakamoto , Haotian Zhang , Kees Cook , Miles Chen , Daniel Golle , Sam Shih , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support), netdev@vger.kernel.org (open list:PTP HARDWARE CLOCK SUPPORT:Keyword:(?:\b|_)ptp(?:\b|_)), stable@vger.kernel.org Subject: [PATCH 18/32] clk: mediatek: mt6797: Switch to common probe/remove helpers Date: Mon, 3 Aug 2026 23:16:45 +0900 Message-ID: <20260803141659.559129-19-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803141659.559129-1-akkun11.open@gmail.com> References: <20260803141659.559129-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MT6797 clock drivers can use the MediaTek clock framework common initialization sequence. Reduce boilerplate code by creating struct mtk_clk_desc and using the mtk_clk_simple_probe/remove helpers. Drop the CLK_OF_DECLARE_DRIVER early init for infracfg; the kernel's deferred probe mechanism ensures dependent drivers like cpufreq are initialized correctly. Since all MT6797 clock drivers can now be built as modules, change Kconfig setting to "tristate". Signed-off-by: Akari Tsuyukusa --- drivers/clk/mediatek/Kconfig | 2 +- drivers/clk/mediatek/clk-mt6797.c | 140 +++++------------------------- 2 files changed, 24 insertions(+), 118 deletions(-) diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index b58656a7e8c3..f5460ce3ffba 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -342,7 +342,7 @@ config COMMON_CLK_MT6795_VENCSYS This driver supports MediaTek MT6795 vencsys clocks. =20 config COMMON_CLK_MT6797 - bool "Clock driver for MediaTek MT6797" + tristate "Clock driver for MediaTek MT6797" depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST select COMMON_CLK_MEDIATEK default ARCH_MEDIATEK && ARM64 diff --git a/drivers/clk/mediatek/clk-mt6797.c b/drivers/clk/mediatek/clk-m= t6797.c index ebf850ac57f5..1934420375e8 100644 --- a/drivers/clk/mediatek/clk-mt6797.c +++ b/drivers/clk/mediatek/clk-mt6797.c @@ -379,29 +379,13 @@ static const struct mtk_composite top_muxes[] =3D { 0x0104, 1, 2), }; =20 -static int mtk_topckgen_init(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - void __iomem *base; - struct device_node *node =3D pdev->dev.of_node; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - clk_data =3D mtk_alloc_clk_data(CLK_TOP_NR); - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs), - clk_data); - - mtk_clk_register_composites(&pdev->dev, top_muxes, - ARRAY_SIZE(top_muxes), base, - &mt6797_clk_lock, clk_data); - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -} +static const struct mtk_clk_desc topckgen_desc =3D { + .factor_clks =3D top_fixed_divs, + .num_factor_clks =3D ARRAY_SIZE(top_fixed_divs), + .composite_clks =3D top_muxes, + .num_composite_clks =3D ARRAY_SIZE(top_muxes), + .clk_lock =3D &mt6797_clk_lock, +}; =20 static const struct mtk_gate_regs infra0_cg_regs =3D { .set_ofs =3D 0x0080, @@ -539,58 +523,12 @@ static const struct mtk_fixed_factor infra_fixed_divs= [] =3D { FACTOR(CLK_INFRA_13M, "clk13m", "clk26m", 1, 2), }; =20 -static struct clk_hw_onecell_data *infra_clk_data; - -static void mtk_infrasys_init_early(struct device_node *node) -{ - int r, i; - - if (!infra_clk_data) { - infra_clk_data =3D mtk_alloc_clk_data(CLK_INFRA_NR); - if (!infra_clk_data) - return; - - for (i =3D 0; i < CLK_INFRA_NR; i++) - infra_clk_data->hws[i] =3D ERR_PTR(-EPROBE_DEFER); - } - - mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs), - infra_clk_data); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, - infra_clk_data); - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); -} - -CLK_OF_DECLARE_DRIVER(mtk_infra, "mediatek,mt6797-infracfg", - mtk_infrasys_init_early); - -static int mtk_infrasys_init(struct platform_device *pdev) -{ - int i; - struct device_node *node =3D pdev->dev.of_node; - - if (!infra_clk_data) { - infra_clk_data =3D mtk_alloc_clk_data(CLK_INFRA_NR); - if (!infra_clk_data) - return -ENOMEM; - } else { - for (i =3D 0; i < CLK_INFRA_NR; i++) { - if (infra_clk_data->hws[i] =3D=3D ERR_PTR(-EPROBE_DEFER)) - infra_clk_data->hws[i] =3D ERR_PTR(-ENOENT); - } - } - - mtk_clk_register_gates(&pdev->dev, node, infra_clks, - ARRAY_SIZE(infra_clks), infra_clk_data); - mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs), - infra_clk_data); - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, - infra_clk_data); -} +static const struct mtk_clk_desc infracfg_desc =3D { + .clks =3D infra_clks, + .num_clks =3D ARRAY_SIZE(infra_clks), + .factor_clks =3D infra_fixed_divs, + .num_factor_clks =3D ARRAY_SIZE(infra_fixed_divs), +}; =20 #define MT6797_PLL_FMAX (3000UL * MHZ) =20 @@ -646,68 +584,36 @@ static const struct mtk_pll_data plls[] =3D { 0x2B4, 4, 0x2BC, 0x2B8, 0), }; =20 -static int mtk_apmixedsys_init(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - - clk_data =3D mtk_alloc_clk_data(CLK_APMIXED_NR); - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data); - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -} +static const struct mtk_clk_desc apmixedsys_desc =3D { + .plls =3D plls, + .num_plls =3D ARRAY_SIZE(plls), +}; =20 static const struct of_device_id of_match_clk_mt6797[] =3D { { .compatible =3D "mediatek,mt6797-topckgen", - .data =3D mtk_topckgen_init, + .data =3D &topckgen_desc, }, { .compatible =3D "mediatek,mt6797-infracfg", - .data =3D mtk_infrasys_init, + .data =3D &infracfg_desc, }, { .compatible =3D "mediatek,mt6797-apmixedsys", - .data =3D mtk_apmixedsys_init, + .data =3D &apmixedsys_desc, }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, of_match_clk_mt6797); =20 -static int clk_mt6797_probe(struct platform_device *pdev) -{ - int (*clk_init)(struct platform_device *); - int r; - - clk_init =3D of_device_get_match_data(&pdev->dev); - if (!clk_init) - return -EINVAL; - - r =3D clk_init(pdev); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - return r; -} - static struct platform_driver clk_mt6797_drv =3D { - .probe =3D clk_mt6797_probe, + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, .driver =3D { .name =3D "clk-mt6797", .of_match_table =3D of_match_clk_mt6797, }, }; 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[14.13.71.96]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38fb30dff2esm4078462a91.13.2026.08.03.07.18.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 07:18:53 -0700 (PDT) From: Akari Tsuyukusa To: Michael Turquette , Stephen Boyd , Brian Masney , Matthias Brugger , AngeloGioacchino Del Regno , Yassine Oudjana , Richard Cochran Cc: Laura Nao , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Chen-Yu Tsai , Akari Tsuyukusa , Bartosz Golaszewski , Danilo Krummrich , Bjorn Helgaas , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Nicolas Frattaroli , Takashi Sakamoto , Haotian Zhang , Kees Cook , Miles Chen , Daniel Golle , Sam Shih , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support), netdev@vger.kernel.org (open list:PTP HARDWARE CLOCK SUPPORT:Keyword:(?:\b|_)ptp(?:\b|_)), stable@vger.kernel.org Subject: [PATCH 19/32] clk: mediatek: mt7622: Switch to common probe/remove helpers Date: Mon, 3 Aug 2026 23:16:46 +0900 Message-ID: <20260803141659.559129-20-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803141659.559129-1-akkun11.open@gmail.com> References: <20260803141659.559129-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MT7622 clock drivers can use the MediaTek clock framework common initialization sequence. Reduce boilerplate code by creating struct mtk_clk_desc and using the mtk_clk_simple_probe/remove helpers. Signed-off-by: Akari Tsuyukusa --- drivers/clk/mediatek/clk-mt7622-apmixedsys.c | 62 +++-------------- drivers/clk/mediatek/clk-mt7622-aud.c | 35 +--------- drivers/clk/mediatek/clk-mt7622-infracfg.c | 72 +++----------------- 3 files changed, 23 insertions(+), 146 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7622-apmixedsys.c b/drivers/clk/med= iatek/clk-mt7622-apmixedsys.c index fae8abda14b3..e9f731eadace 100644 --- a/drivers/clk/mediatek/clk-mt7622-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt7622-apmixedsys.c @@ -80,66 +80,22 @@ static const struct mtk_gate apmixed_clks[] =3D { GATE_APMIXED_AO(CLK_APMIXED_MAIN_CORE_EN, "main_core_en", "mainpll", 5), }; =20 -static int clk_mt7622_apmixed_probe(struct platform_device *pdev) -{ - void __iomem *base; - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - struct device *dev =3D &pdev->dev; - int ret; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - clk_data =3D mtk_devm_alloc_clk_data(dev, CLK_APMIXED_NR_CLK); - if (!clk_data) - return -ENOMEM; - - ret =3D mtk_clk_register_plls(dev, plls, ARRAY_SIZE(plls), clk_data); - if (ret) - return ret; - - ret =3D mtk_clk_register_gates(&pdev->dev, node, apmixed_clks, - ARRAY_SIZE(apmixed_clks), clk_data); - if (ret) - goto unregister_plls; - - ret =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (ret) - goto unregister_gates; - - platform_set_drvdata(pdev, clk_data); - - return 0; - -unregister_gates: - mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data= ); -unregister_plls: - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); - - return ret; -} - -static void clk_mt7622_apmixed_remove(struct platform_device *pdev) -{ - struct device_node *node =3D pdev->dev.of_node; - struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); - - of_clk_del_provider(node); - mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data= ); - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); -} +static const struct mtk_clk_desc apmixed_desc =3D { + .plls =3D plls, + .num_plls =3D ARRAY_SIZE(plls), + .clks =3D apmixed_clks, + .num_clks =3D ARRAY_SIZE(apmixed_clks), +}; =20 static const struct of_device_id of_match_clk_mt7622_apmixed[] =3D { - { .compatible =3D "mediatek,mt7622-apmixedsys" }, + { .compatible =3D "mediatek,mt7622-apmixedsys", .data =3D &apmixed_desc }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, of_match_clk_mt7622_apmixed); =20 static struct platform_driver clk_mt7622_apmixed_drv =3D { - .probe =3D clk_mt7622_apmixed_probe, - .remove =3D clk_mt7622_apmixed_remove, + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, .driver =3D { .name =3D "clk-mt7622-apmixed", .of_match_table =3D of_match_clk_mt7622_apmixed, diff --git a/drivers/clk/mediatek/clk-mt7622-aud.c b/drivers/clk/mediatek/c= lk-mt7622-aud.c index a4ea5e20efa2..6004c58be1b5 100644 --- a/drivers/clk/mediatek/clk-mt7622-aud.c +++ b/drivers/clk/mediatek/clk-mt7622-aud.c @@ -110,38 +110,9 @@ static const struct mtk_gate audio_clks[] =3D { static const struct mtk_clk_desc audio_desc =3D { .clks =3D audio_clks, .num_clks =3D ARRAY_SIZE(audio_clks), + .populate_children =3D true, }; =20 -static int clk_mt7622_aud_probe(struct platform_device *pdev) -{ - int r; - - r =3D mtk_clk_simple_probe(pdev); - if (r) { - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - return r; - } - - r =3D devm_of_platform_populate(&pdev->dev); - if (r) - goto err_plat_populate; - - return 0; - -err_plat_populate: - mtk_clk_simple_remove(pdev); - return r; -} - -static void clk_mt7622_aud_remove(struct platform_device *pdev) -{ - of_platform_depopulate(&pdev->dev); - mtk_clk_simple_remove(pdev); -} - static const struct of_device_id of_match_clk_mt7622_aud[] =3D { { .compatible =3D "mediatek,mt7622-audsys", .data =3D &audio_desc }, { /* sentinel */ } @@ -149,8 +120,8 @@ static const struct of_device_id of_match_clk_mt7622_au= d[] =3D { MODULE_DEVICE_TABLE(of, of_match_clk_mt7622_aud); =20 static struct platform_driver clk_mt7622_aud_drv =3D { - .probe =3D clk_mt7622_aud_probe, - .remove =3D clk_mt7622_aud_remove, + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, .driver =3D { .name =3D "clk-mt7622-aud", .of_match_table =3D of_match_clk_mt7622_aud, diff --git a/drivers/clk/mediatek/clk-mt7622-infracfg.c b/drivers/clk/media= tek/clk-mt7622-infracfg.c index cec19447d637..2e463d1481d0 100644 --- a/drivers/clk/mediatek/clk-mt7622-infracfg.c +++ b/drivers/clk/mediatek/clk-mt7622-infracfg.c @@ -9,7 +9,6 @@ #include #include =20 -#include "clk-cpumux.h" #include "clk-gate.h" #include "clk-mtk.h" #include "reset.h" @@ -51,76 +50,27 @@ static const struct mtk_clk_rst_desc clk_rst_desc =3D { .rst_bank_nr =3D ARRAY_SIZE(infrasys_rst_ofs), }; =20 +static const struct mtk_clk_desc infra_desc =3D { + .clks =3D infra_clks, + .num_clks =3D ARRAY_SIZE(infra_clks), + .cpumuxes =3D cpu_muxes, + .num_cpumuxes =3D ARRAY_SIZE(cpu_muxes), + .rst_desc =3D &clk_rst_desc, +}; + static const struct of_device_id of_match_clk_mt7622_infracfg[] =3D { - { .compatible =3D "mediatek,mt7622-infracfg" }, + { .compatible =3D "mediatek,mt7622-infracfg", .data =3D &infra_desc }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, of_match_clk_mt7622_infracfg); =20 -static int clk_mt7622_infracfg_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - void __iomem *base; - int ret; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - clk_data =3D mtk_alloc_clk_data(CLK_INFRA_NR_CLK); - if (!clk_data) - return -ENOMEM; - - ret =3D mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); - if (ret) - goto free_clk_data; - - ret =3D mtk_clk_register_gates(&pdev->dev, node, infra_clks, - ARRAY_SIZE(infra_clks), clk_data); - if (ret) - goto free_clk_data; - - ret =3D mtk_clk_register_cpumuxes(&pdev->dev, node, cpu_muxes, - ARRAY_SIZE(cpu_muxes), clk_data); - if (ret) - goto unregister_gates; - - ret =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (ret) - goto unregister_cpumuxes; - - platform_set_drvdata(pdev, clk_data); - - return 0; - -unregister_cpumuxes: - mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data); -unregister_gates: - mtk_clk_unregister_gates(infra_clks, ARRAY_SIZE(infra_clks), clk_data); -free_clk_data: - mtk_free_clk_data(clk_data); - return ret; -} - -static void clk_mt7622_infracfg_remove(struct platform_device *pdev) -{ - struct device_node *node =3D pdev->dev.of_node; - struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); - - of_clk_del_provider(node); - mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data); - mtk_clk_unregister_gates(infra_clks, ARRAY_SIZE(infra_clks), clk_data); - mtk_free_clk_data(clk_data); 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[14.13.71.96]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38fb30dff2esm4078462a91.13.2026.08.03.07.18.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 07:18:57 -0700 (PDT) From: Akari Tsuyukusa To: Michael Turquette , Stephen Boyd , Brian Masney , Matthias Brugger , AngeloGioacchino Del Regno , Yassine Oudjana , Richard Cochran Cc: Laura Nao , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Chen-Yu Tsai , Akari Tsuyukusa , Bartosz Golaszewski , Danilo Krummrich , Bjorn Helgaas , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Nicolas Frattaroli , Takashi Sakamoto , Haotian Zhang , Kees Cook , Miles Chen , Daniel Golle , Sam Shih , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support), netdev@vger.kernel.org (open list:PTP HARDWARE CLOCK SUPPORT:Keyword:(?:\b|_)ptp(?:\b|_)), stable@vger.kernel.org Subject: [PATCH 20/32] clk: mediatek: mt7981-apmixed: Switch to common probe/remove helpers Date: Mon, 3 Aug 2026 23:16:47 +0900 Message-ID: <20260803141659.559129-21-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803141659.559129-1-akkun11.open@gmail.com> References: <20260803141659.559129-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MT7981 apmixed driver can use the MediaTek clock framework common initialization sequence. Reduce boilerplate code by creating struct mtk_clk_desc and using the mtk_clk_simple_probe/remove helpers. This change also makes it possible to build the driver as a module. Signed-off-by: Akari Tsuyukusa --- drivers/clk/mediatek/Kconfig | 2 +- drivers/clk/mediatek/clk-mt7981-apmixed.c | 37 ++++++----------------- 2 files changed, 10 insertions(+), 29 deletions(-) diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index f5460ce3ffba..6449b77d56ed 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -427,7 +427,7 @@ config COMMON_CLK_MT7629_HIFSYS to PCI-E and USB. =20 config COMMON_CLK_MT7981 - bool "Clock driver for MediaTek MT7981" + tristate "Clock driver for MediaTek MT7981" depends on ARCH_MEDIATEK || COMPILE_TEST select COMMON_CLK_MEDIATEK default ARCH_MEDIATEK diff --git a/drivers/clk/mediatek/clk-mt7981-apmixed.c b/drivers/clk/mediat= ek/clk-mt7981-apmixed.c index 851d0bc7840a..810395aff253 100644 --- a/drivers/clk/mediatek/clk-mt7981-apmixed.c +++ b/drivers/clk/mediatek/clk-mt7981-apmixed.c @@ -59,45 +59,26 @@ static const struct mtk_pll_data plls[] =3D { 0x0278, 4, 0, 0x027C, 0), }; =20 +static const struct mtk_clk_desc apmixed_desc =3D { + .plls =3D plls, + .num_plls =3D ARRAY_SIZE(plls), +}; + static const struct of_device_id of_match_clk_mt7981_apmixed[] =3D { - { .compatible =3D "mediatek,mt7981-apmixedsys", }, + { .compatible =3D "mediatek,mt7981-apmixedsys", .data =3D &apmixed_desc }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, of_match_clk_mt7981_apmixed); =20 -static int clk_mt7981_apmixed_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - int r; - - clk_data =3D mtk_alloc_clk_data(ARRAY_SIZE(plls)); - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) { - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - goto free_apmixed_data; - } - return r; - -free_apmixed_data: - mtk_free_clk_data(clk_data); - return r; -} - static struct platform_driver clk_mt7981_apmixed_drv =3D { - .probe =3D clk_mt7981_apmixed_probe, + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, .driver =3D { .name =3D "clk-mt7981-apmixed", .of_match_table =3D of_match_clk_mt7981_apmixed, }, }; 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[14.13.71.96]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38fb30dff2esm4078462a91.13.2026.08.03.07.18.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 07:19:02 -0700 (PDT) From: Akari Tsuyukusa To: Michael Turquette , Stephen Boyd , Brian Masney , Matthias Brugger , AngeloGioacchino Del Regno , Yassine Oudjana , Richard Cochran Cc: Laura Nao , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Chen-Yu Tsai , Akari Tsuyukusa , Bartosz Golaszewski , Danilo Krummrich , Bjorn Helgaas , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Nicolas Frattaroli , Takashi Sakamoto , Haotian Zhang , Kees Cook , Miles Chen , Daniel Golle , Sam Shih , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support), netdev@vger.kernel.org (open list:PTP HARDWARE CLOCK SUPPORT:Keyword:(?:\b|_)ptp(?:\b|_)), stable@vger.kernel.org Subject: [PATCH 21/32] clk: mediatek: mt7986-apmixed: Switch to common probe/remove helpers Date: Mon, 3 Aug 2026 23:16:48 +0900 Message-ID: <20260803141659.559129-22-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803141659.559129-1-akkun11.open@gmail.com> References: <20260803141659.559129-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MT7986 apmixed driver can use the MediaTek clock framework common initialization sequence. Reduce boilerplate code by creating struct mtk_clk_desc and using the mtk_clk_simple_probe/remove helpers. Also, add a remove callback to properly support module unloading. Signed-off-by: Akari Tsuyukusa --- drivers/clk/mediatek/clk-mt7986-apmixed.c | 37 ++++++----------------- 1 file changed, 9 insertions(+), 28 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7986-apmixed.c b/drivers/clk/mediat= ek/clk-mt7986-apmixed.c index af3e002bbfb7..6df3e9555e4e 100644 --- a/drivers/clk/mediatek/clk-mt7986-apmixed.c +++ b/drivers/clk/mediatek/clk-mt7986-apmixed.c @@ -57,45 +57,26 @@ static const struct mtk_pll_data plls[] =3D { 0x0278, 4, 0, 0x027c, 0), }; =20 +static const struct mtk_clk_desc apmixed_desc =3D { + .plls =3D plls, + .num_plls =3D ARRAY_SIZE(plls), +}; + static const struct of_device_id of_match_clk_mt7986_apmixed[] =3D { - { .compatible =3D "mediatek,mt7986-apmixedsys", }, + { .compatible =3D "mediatek,mt7986-apmixedsys", .data =3D &apmixed_desc }, { } }; MODULE_DEVICE_TABLE(of, of_match_clk_mt7986_apmixed); =20 -static int clk_mt7986_apmixed_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - int r; - - clk_data =3D mtk_alloc_clk_data(ARRAY_SIZE(plls)); - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) { - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - goto free_apmixed_data; - } - return r; - -free_apmixed_data: - mtk_free_clk_data(clk_data); - return r; -} - static struct platform_driver clk_mt7986_apmixed_drv =3D { - .probe =3D clk_mt7986_apmixed_probe, + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, .driver =3D { .name =3D "clk-mt7986-apmixed", .of_match_table =3D of_match_clk_mt7986_apmixed, }, }; -builtin_platform_driver(clk_mt7986_apmixed_drv); +module_platform_driver(clk_mt7986_apmixed_drv); =20 MODULE_DESCRIPTION("MediaTek MT7986 apmixedsys clocks driver"); MODULE_LICENSE("GPL"); --=20 2.55.0 From nobody Fri Oct 2 08:24:59 2026 Received: from mail-pj1-f47.google.com (mail-pj1-f47.google.com [209.85.216.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE5F942BC2A for ; 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[14.13.71.96]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38fb30dff2esm4078462a91.13.2026.08.03.07.19.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 07:19:06 -0700 (PDT) From: Akari Tsuyukusa To: Michael Turquette , Stephen Boyd , Brian Masney , Matthias Brugger , AngeloGioacchino Del Regno , Yassine Oudjana , Richard Cochran Cc: Laura Nao , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Chen-Yu Tsai , Akari Tsuyukusa , Bartosz Golaszewski , Danilo Krummrich , Bjorn Helgaas , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Nicolas Frattaroli , Takashi Sakamoto , Haotian Zhang , Kees Cook , Miles Chen , Daniel Golle , Sam Shih , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support), netdev@vger.kernel.org (open list:PTP HARDWARE CLOCK SUPPORT:Keyword:(?:\b|_)ptp(?:\b|_)), stable@vger.kernel.org Subject: [PATCH 22/32] clk: mediatek: mt7988-apmixed: Switch to common probe/remove helpers Date: Mon, 3 Aug 2026 23:16:49 +0900 Message-ID: <20260803141659.559129-23-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803141659.559129-1-akkun11.open@gmail.com> References: <20260803141659.559129-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MT7988 apmixed driver can use the MediaTek clock framework common initialization sequence. Reduce boilerplate code by creating struct mtk_clk_desc and using the mtk_clk_simple_probe/remove helpers. Signed-off-by: Akari Tsuyukusa --- drivers/clk/mediatek/clk-mt7988-apmixed.c | 39 ++++++----------------- 1 file changed, 9 insertions(+), 30 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7988-apmixed.c b/drivers/clk/mediat= ek/clk-mt7988-apmixed.c index 24f4e7b87a31..f7bb00e7d17a 100644 --- a/drivers/clk/mediatek/clk-mt7988-apmixed.c +++ b/drivers/clk/mediatek/clk-mt7988-apmixed.c @@ -71,47 +71,26 @@ static const struct mtk_pll_data plls[] =3D { 0, 0x0318, 0, 0x0314), }; =20 +static const struct mtk_clk_desc apmixed_desc =3D { + .plls =3D plls, + .num_plls =3D ARRAY_SIZE(plls), +}; + static const struct of_device_id of_match_clk_mt7988_apmixed[] =3D { - { .compatible =3D "mediatek,mt7988-apmixedsys" }, + { .compatible =3D "mediatek,mt7988-apmixedsys", .data =3D &apmixed_desc }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_apmixed); =20 -static int clk_mt7988_apmixed_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - int r; - - clk_data =3D mtk_alloc_clk_data(ARRAY_SIZE(plls)); - if (!clk_data) - return -ENOMEM; - - r =3D mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data); - if (r) - goto free_apmixed_data; - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - goto unregister_plls; - - return r; - -unregister_plls: - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); -free_apmixed_data: - mtk_free_clk_data(clk_data); - return r; -} - static struct platform_driver clk_mt7988_apmixed_drv =3D { - .probe =3D clk_mt7988_apmixed_probe, + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, .driver =3D { .name =3D "clk-mt7988-apmixed", .of_match_table =3D of_match_clk_mt7988_apmixed, }, }; -builtin_platform_driver(clk_mt7988_apmixed_drv); +module_platform_driver(clk_mt7988_apmixed_drv); =20 MODULE_DESCRIPTION("MediaTek MT7988 apmixedsys clocks driver"); MODULE_LICENSE("GPL"); --=20 2.55.0 From nobody Fri Oct 2 08:24:59 2026 Received: from mail-pj1-f54.google.com (mail-pj1-f54.google.com [209.85.216.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 64ACF42BEB2 for ; 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[14.13.71.96]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38fb30dff2esm4078462a91.13.2026.08.03.07.19.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 07:19:11 -0700 (PDT) From: Akari Tsuyukusa To: Michael Turquette , Stephen Boyd , Brian Masney , Matthias Brugger , AngeloGioacchino Del Regno , Yassine Oudjana , Richard Cochran Cc: Laura Nao , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Chen-Yu Tsai , Akari Tsuyukusa , Bartosz Golaszewski , Danilo Krummrich , Bjorn Helgaas , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Nicolas Frattaroli , Takashi Sakamoto , Haotian Zhang , Kees Cook , Miles Chen , Daniel Golle , Sam Shih , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support), netdev@vger.kernel.org (open list:PTP HARDWARE CLOCK SUPPORT:Keyword:(?:\b|_)ptp(?:\b|_)), stable@vger.kernel.org Subject: [PATCH 23/32] clk: mediatek: mt8135-apmixedsys: Switch to common probe/remove helpers Date: Mon, 3 Aug 2026 23:16:50 +0900 Message-ID: <20260803141659.559129-24-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803141659.559129-1-akkun11.open@gmail.com> References: <20260803141659.559129-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MT8135 apmixedsys driver can use the MediaTek clock framework common initialization sequence. Reduce boilerplate code by creating struct mtk_clk_desc and using the mtk_clk_simple_probe/remove helpers. Signed-off-by: Akari Tsuyukusa --- drivers/clk/mediatek/clk-mt8135-apmixedsys.c | 50 +++----------------- 1 file changed, 7 insertions(+), 43 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8135-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8135-apmixedsys.c index e3b7dc13b458..fe868417de48 100644 --- a/drivers/clk/mediatek/clk-mt8135-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8135-apmixedsys.c @@ -47,56 +47,20 @@ static const struct mtk_pll_data plls[] =3D { PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x304, 0x31c, 0x80000000, 0, 21, 0x2b= 0, 6, 0x0, 0x308, 0), }; =20 -static int clk_mt8135_apmixed_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - int ret; - - clk_data =3D mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); - if (!clk_data) - return -ENOMEM; - - ret =3D mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), - clk_data); - if (ret) - goto free_clk_data; - - ret =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (ret) - goto unregister_plls; - - platform_set_drvdata(pdev, clk_data); - - return 0; - -unregister_plls: - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); -free_clk_data: - mtk_free_clk_data(clk_data); - - return ret; -} - -static void clk_mt8135_apmixed_remove(struct platform_device *pdev) -{ - struct device_node *node =3D pdev->dev.of_node; - struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); - - of_clk_del_provider(node); - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); - mtk_free_clk_data(clk_data); -} +static const struct mtk_clk_desc apmixed_desc =3D { + .plls =3D plls, + .num_plls =3D ARRAY_SIZE(plls), +}; =20 static const struct of_device_id of_match_clk_mt8135_apmixed[] =3D { - { .compatible =3D "mediatek,mt8135-apmixedsys" }, + { .compatible =3D "mediatek,mt8135-apmixedsys", .data =3D &apmixed_desc }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, of_match_clk_mt8135_apmixed); =20 static struct platform_driver clk_mt8135_apmixed_drv =3D { - .probe =3D clk_mt8135_apmixed_probe, - .remove =3D clk_mt8135_apmixed_remove, + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, .driver =3D { .name =3D "clk-mt8135-apmixed", .of_match_table =3D of_match_clk_mt8135_apmixed, --=20 2.55.0 From nobody Fri Oct 2 08:24:59 2026 Received: from mail-pl1-f172.google.com (mail-pl1-f172.google.com [209.85.214.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D46642C516 for ; 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[14.13.71.96]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38fb30dff2esm4078462a91.13.2026.08.03.07.19.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 07:19:16 -0700 (PDT) From: Akari Tsuyukusa To: Michael Turquette , Stephen Boyd , Brian Masney , Matthias Brugger , AngeloGioacchino Del Regno , Yassine Oudjana , Richard Cochran Cc: Laura Nao , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Chen-Yu Tsai , Akari Tsuyukusa , Bartosz Golaszewski , Danilo Krummrich , Bjorn Helgaas , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Nicolas Frattaroli , Takashi Sakamoto , Haotian Zhang , Kees Cook , Miles Chen , Daniel Golle , Sam Shih , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support), netdev@vger.kernel.org (open list:PTP HARDWARE CLOCK SUPPORT:Keyword:(?:\b|_)ptp(?:\b|_)), stable@vger.kernel.org Subject: [PATCH 24/32] clk: mediatek: mt8167-apmixedsys: Switch to common probe/remove helpers Date: Mon, 3 Aug 2026 23:16:51 +0900 Message-ID: <20260803141659.559129-25-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803141659.559129-1-akkun11.open@gmail.com> References: <20260803141659.559129-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MT8167 apmixedsys driver can use the MediaTek clock framework common initialization sequence. Reduce boilerplate code by creating struct mtk_clk_desc and using the mtk_clk_simple_probe/remove helpers. Also, add a remove callback to properly support module unloading. Signed-off-by: Akari Tsuyukusa --- drivers/clk/mediatek/clk-mt8167-apmixedsys.c | 50 ++++---------------- 1 file changed, 10 insertions(+), 40 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8167-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8167-apmixedsys.c index fb6c21bbeef8..2b1d1de74cdb 100644 --- a/drivers/clk/mediatek/clk-mt8167-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8167-apmixedsys.c @@ -89,44 +89,13 @@ static const struct mtk_clk_divider adj_divs[] =3D { 0x1c4, 24, 3, CLK_DIVIDER_POWER_OF_TWO), }; =20 -static int clk_mt8167_apmixed_probe(struct platform_device *pdev) -{ - void __iomem *base; - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - struct device *dev =3D &pdev->dev; - int ret; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - clk_data =3D mtk_devm_alloc_clk_data(dev, MT8167_CLK_APMIXED_NR_CLK); - if (!clk_data) - return -ENOMEM; - - ret =3D mtk_clk_register_plls(dev, plls, ARRAY_SIZE(plls), clk_data); - if (ret) - return ret; - - ret =3D mtk_clk_register_dividers(dev, adj_divs, ARRAY_SIZE(adj_divs), ba= se, - &mt8167_apmixed_clk_lock, clk_data); - if (ret) - goto unregister_plls; - - ret =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (ret) - goto unregister_dividers; - - return 0; - -unregister_dividers: - mtk_clk_unregister_dividers(adj_divs, ARRAY_SIZE(adj_divs), clk_data); -unregister_plls: - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); - - return ret; -} +static const struct mtk_clk_desc apmixed_desc =3D { + .plls =3D plls, + .num_plls =3D ARRAY_SIZE(plls), + .divider_clks =3D adj_divs, + .num_divider_clks =3D ARRAY_SIZE(adj_divs), + .clk_lock =3D &mt8167_apmixed_clk_lock, +}; =20 static const struct of_device_id of_match_clk_mt8167_apmixed[] =3D { { .compatible =3D "mediatek,mt8167-apmixedsys" }, @@ -135,13 +104,14 @@ static const struct of_device_id of_match_clk_mt8167_= apmixed[] =3D { MODULE_DEVICE_TABLE(of, of_match_clk_mt8167_apmixed); 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[14.13.71.96]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38fb30dff2esm4078462a91.13.2026.08.03.07.19.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 07:19:20 -0700 (PDT) From: Akari Tsuyukusa To: Michael Turquette , Stephen Boyd , Brian Masney , Matthias Brugger , AngeloGioacchino Del Regno , Yassine Oudjana , Richard Cochran Cc: Laura Nao , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Chen-Yu Tsai , Akari Tsuyukusa , Bartosz Golaszewski , Danilo Krummrich , Bjorn Helgaas , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Nicolas Frattaroli , Takashi Sakamoto , Haotian Zhang , Kees Cook , Miles Chen , Daniel Golle , Sam Shih , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support), netdev@vger.kernel.org (open list:PTP HARDWARE CLOCK SUPPORT:Keyword:(?:\b|_)ptp(?:\b|_)), stable@vger.kernel.org Subject: [PATCH 25/32] clk: mediatek: mt8173-infracfg: Switch to common probe/remove helpers Date: Mon, 3 Aug 2026 23:16:52 +0900 Message-ID: <20260803141659.559129-26-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803141659.559129-1-akkun11.open@gmail.com> References: <20260803141659.559129-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MT8173 infracfg driver can use the MediaTek clock framework common initialization sequence. Reduce boilerplate code by creating struct mtk_clk_desc and using the mtk_clk_simple_probe/remove helpers. Drop the CLK_OF_DECLARE_DRIVER early init for infracfg; the kernel's deferred probe mechanism ensures dependent drivers like cpufreq are initialized correctly. Signed-off-by: Akari Tsuyukusa --- drivers/clk/mediatek/clk-mt8173-infracfg.c | 100 ++++----------------- 1 file changed, 16 insertions(+), 84 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8173-infracfg.c b/drivers/clk/media= tek/clk-mt8173-infracfg.c index 9b8c35897789..fdd994736e83 100644 --- a/drivers/clk/mediatek/clk-mt8173-infracfg.c +++ b/drivers/clk/mediatek/clk-mt8173-infracfg.c @@ -17,22 +17,20 @@ GATE_MTK(_id, _name, _parent, &infra_cg_regs, \ _shift, &mtk_clk_gate_ops_setclr) =20 -static struct clk_hw_onecell_data *infra_clk_data; - static const struct mtk_gate_regs infra_cg_regs =3D { .set_ofs =3D 0x0040, .clr_ofs =3D 0x0044, .sta_ofs =3D 0x0048, }; =20 -static const char * const ca53_parents[] __initconst =3D { +static const char * const ca53_parents[] =3D { "clk26m", "armca7pll", "mainpll", "univpll" }; =20 -static const char * const ca72_parents[] __initconst =3D { +static const char * const ca72_parents[] =3D { "clk26m", "armca15pll", "mainpll", @@ -44,7 +42,7 @@ static const struct mtk_composite cpu_muxes[] =3D { MUX(CLK_INFRA_CA72SEL, "infra_ca72_sel", ca72_parents, 0x0000, 2, 2), }; =20 -static const struct mtk_fixed_factor infra_early_divs[] =3D { +static const struct mtk_fixed_factor infra_divs[] =3D { FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2), }; =20 @@ -70,95 +68,29 @@ static const struct mtk_clk_rst_desc clk_rst_desc =3D { .rst_bank_nr =3D ARRAY_SIZE(infrasys_rst_ofs), }; =20 +static const struct mtk_clk_desc infracfg_desc =3D { + .clks =3D infra_gates, + .num_clks =3D ARRAY_SIZE(infra_gates), + .factor_clks =3D infra_divs, + .num_factor_clks =3D ARRAY_SIZE(infra_divs), + .cpumuxes =3D cpu_muxes, + .num_cpumuxes =3D ARRAY_SIZE(cpu_muxes), + .rst_desc =3D &clk_rst_desc, +}; + static const struct of_device_id of_match_clk_mt8173_infracfg[] =3D { - { .compatible =3D "mediatek,mt8173-infracfg" }, + { .compatible =3D "mediatek,mt8173-infracfg", .data =3D &infracfg_desc }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_infracfg); =20 -static void clk_mt8173_infra_init_early(struct device_node *node) -{ - int i; - - infra_clk_data =3D mtk_alloc_clk_data(CLK_INFRA_NR_CLK); - if (!infra_clk_data) - return; - - for (i =3D 0; i < CLK_INFRA_NR_CLK; i++) - infra_clk_data->hws[i] =3D ERR_PTR(-EPROBE_DEFER); - - mtk_clk_register_factors(infra_early_divs, - ARRAY_SIZE(infra_early_divs), infra_clk_data); - - of_clk_add_hw_provider(node, of_clk_hw_onecell_get, infra_clk_data); -} -CLK_OF_DECLARE_DRIVER(mtk_infrasys, "mediatek,mt8173-infracfg", - clk_mt8173_infra_init_early); - -static int clk_mt8173_infracfg_probe(struct platform_device *pdev) -{ - struct device_node *node =3D pdev->dev.of_node; - int r, i; - - if (!infra_clk_data) { - infra_clk_data =3D mtk_alloc_clk_data(CLK_INFRA_NR_CLK); - if (!infra_clk_data) - return -ENOMEM; - } else { - for (i =3D 0; i < CLK_INFRA_NR_CLK; i++) - if (infra_clk_data->hws[i] =3D=3D ERR_PTR(-EPROBE_DEFER)) - infra_clk_data->hws[i] =3D ERR_PTR(-ENOENT); - } - - r =3D mtk_clk_register_gates(&pdev->dev, node, infra_gates, - ARRAY_SIZE(infra_gates), infra_clk_data); - if (r) - return r; - - r =3D mtk_clk_register_cpumuxes(&pdev->dev, node, cpu_muxes, - ARRAY_SIZE(cpu_muxes), infra_clk_data); - if (r) - goto unregister_gates; - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, infra_clk_data); - if (r) - goto unregister_cpumuxes; - - r =3D mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); - if (r) - goto unregister_clk_hw; - - platform_set_drvdata(pdev, infra_clk_data); - - return 0; - -unregister_clk_hw: - of_clk_del_provider(node); -unregister_cpumuxes: - mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), infra_clk_d= ata); -unregister_gates: - mtk_clk_unregister_gates(infra_gates, ARRAY_SIZE(infra_gates), infra_clk_= data); - return r; -} - -static void clk_mt8173_infracfg_remove(struct platform_device *pdev) -{ - struct device_node *node =3D pdev->dev.of_node; - struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); - - of_clk_del_provider(node); - mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data); - mtk_clk_unregister_gates(infra_gates, ARRAY_SIZE(infra_gates), clk_data); - mtk_free_clk_data(clk_data); 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[14.13.71.96]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38fb30dff2esm4078462a91.13.2026.08.03.07.19.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 07:19:25 -0700 (PDT) From: Akari Tsuyukusa To: Michael Turquette , Stephen Boyd , Brian Masney , Matthias Brugger , AngeloGioacchino Del Regno , Yassine Oudjana , Richard Cochran Cc: Laura Nao , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Chen-Yu Tsai , Akari Tsuyukusa , Bartosz Golaszewski , Danilo Krummrich , Bjorn Helgaas , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Nicolas Frattaroli , Takashi Sakamoto , Haotian Zhang , Kees Cook , Miles Chen , Daniel Golle , Sam Shih , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support), netdev@vger.kernel.org (open list:PTP HARDWARE CLOCK SUPPORT:Keyword:(?:\b|_)ptp(?:\b|_)), stable@vger.kernel.org Subject: [PATCH 26/32] clk: mediatek: mt8183: Switch to common probe/remove helpers Date: Mon, 3 Aug 2026 23:16:53 +0900 Message-ID: <20260803141659.559129-27-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803141659.559129-1-akkun11.open@gmail.com> References: <20260803141659.559129-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MT8183 clock drivers can use the MediaTek clock framework common initialization sequence. Reduce boilerplate code by creating struct mtk_clk_desc and using the mtk_clk_simple_probe/remove helpers. For the apmixedsys driver, add a remove callback to properly support module unloading. Signed-off-by: Akari Tsuyukusa --- drivers/clk/mediatek/clk-mt8183-apmixedsys.c | 51 ++++---------------- drivers/clk/mediatek/clk-mt8183-audio.c | 26 ++-------- 2 files changed, 13 insertions(+), 64 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8183-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8183-apmixedsys.c index 6242d4f5376e..deb96537a3ab 100644 --- a/drivers/clk/mediatek/clk-mt8183-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8183-apmixedsys.c @@ -139,59 +139,28 @@ static const struct mtk_pll_data plls[] =3D { 0, 0, 32, 8, 0x02B4, 1, 0x02BC, 0x0014, 1, 0x02B8, 0, 0x02B4), }; =20 -static int clk_mt8183_apmixed_probe(struct platform_device *pdev) -{ - void __iomem *base; - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - struct device *dev =3D &pdev->dev; - int ret; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - clk_data =3D mtk_devm_alloc_clk_data(dev, CLK_APMIXED_NR_CLK); - if (!clk_data) - return -ENOMEM; - - ret =3D mtk_clk_register_plls(dev, plls, ARRAY_SIZE(plls), clk_data); - if (ret) - return ret; - - ret =3D mtk_clk_register_gates(&pdev->dev, node, apmixed_clks, - ARRAY_SIZE(apmixed_clks), clk_data); - if (ret) - goto unregister_plls; - - ret =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (ret) - goto unregister_gates; - - return 0; - -unregister_gates: - mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data= ); -unregister_plls: - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); - - return ret; -} +static const struct mtk_clk_desc apmixed_desc =3D { + .plls =3D plls, + .num_plls =3D ARRAY_SIZE(plls), + .clks =3D apmixed_clks, + .num_clks =3D ARRAY_SIZE(apmixed_clks), +}; =20 static const struct of_device_id of_match_clk_mt8183_apmixed[] =3D { - { .compatible =3D "mediatek,mt8183-apmixedsys" }, + { .compatible =3D "mediatek,mt8183-apmixedsys", .data =3D &apmixed_desc }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, of_match_clk_mt8183_apmixed); =20 static struct platform_driver clk_mt8183_apmixed_drv =3D { - .probe =3D clk_mt8183_apmixed_probe, + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, .driver =3D { .name =3D "clk-mt8183-apmixed", .of_match_table =3D of_match_clk_mt8183_apmixed, }, }; -builtin_platform_driver(clk_mt8183_apmixed_drv) +module_platform_driver(clk_mt8183_apmixed_drv) =20 MODULE_DESCRIPTION("MediaTek MT8183 apmixedsys clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8183-audio.c b/drivers/clk/mediatek= /clk-mt8183-audio.c index 011d329ad30e..0a53b0408dcc 100644 --- a/drivers/clk/mediatek/clk-mt8183-audio.c +++ b/drivers/clk/mediatek/clk-mt8183-audio.c @@ -70,29 +70,9 @@ static const struct mtk_gate audio_clks[] =3D { static const struct mtk_clk_desc audio_desc =3D { .clks =3D audio_clks, .num_clks =3D ARRAY_SIZE(audio_clks), + .populate_children =3D true, }; =20 -static int clk_mt8183_audio_probe(struct platform_device *pdev) -{ - int r; - - r =3D mtk_clk_simple_probe(pdev); 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[14.13.71.96]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38fb30dff2esm4078462a91.13.2026.08.03.07.19.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 07:19:29 -0700 (PDT) From: Akari Tsuyukusa To: Michael Turquette , Stephen Boyd , Brian Masney , Matthias Brugger , AngeloGioacchino Del Regno , Yassine Oudjana , Richard Cochran Cc: Laura Nao , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Chen-Yu Tsai , Akari Tsuyukusa , Bartosz Golaszewski , Danilo Krummrich , Bjorn Helgaas , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Nicolas Frattaroli , Takashi Sakamoto , Haotian Zhang , Kees Cook , Miles Chen , Daniel Golle , Sam Shih , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support), netdev@vger.kernel.org (open list:PTP HARDWARE CLOCK SUPPORT:Keyword:(?:\b|_)ptp(?:\b|_)), stable@vger.kernel.org Subject: [PATCH 27/32] clk: mediatek: mt8186-apmixedsys: Switch to common probe/remove helpers Date: Mon, 3 Aug 2026 23:16:54 +0900 Message-ID: <20260803141659.559129-28-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803141659.559129-1-akkun11.open@gmail.com> References: <20260803141659.559129-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MT8186 apmixedsys driver can use the MediaTek clock framework common initialization sequence. Reduce boilerplate code by creating struct mtk_clk_desc and using the mtk_clk_simple_probe/remove helpers. Signed-off-by: Akari Tsuyukusa --- drivers/clk/mediatek/clk-mt8186-apmixedsys.c | 59 ++++---------------- 1 file changed, 11 insertions(+), 48 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8186-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8186-apmixedsys.c index d35dd2632e43..b674b1e581a5 100644 --- a/drivers/clk/mediatek/clk-mt8186-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8186-apmixedsys.c @@ -132,60 +132,23 @@ static struct mtk_pllfh_data pllfhs[] =3D { FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x0118), }; =20 +static const struct mtk_clk_desc apmixed_desc =3D { + .plls =3D plls, + .num_plls =3D ARRAY_SIZE(plls), + .fhctl_node =3D "mediatek,mt8186-fhctl", + .pllfhs =3D pllfhs, + .num_pllfhs =3D ARRAY_SIZE(pllfhs), +}; + static const struct of_device_id of_match_clk_mt8186_apmixed[] =3D { - { .compatible =3D "mediatek,mt8186-apmixedsys", }, + { .compatible =3D "mediatek,mt8186-apmixedsys", .data =3D &apmixed_desc }, {} }; MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_apmixed); =20 -static int clk_mt8186_apmixed_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - const u8 *fhctl_node =3D "mediatek,mt8186-fhctl"; - int r; - - clk_data =3D mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); - if (!clk_data) - return -ENOMEM; - - fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs)); - - r =3D mtk_clk_register_pllfhs(&pdev->dev, plls, ARRAY_SIZE(plls), - pllfhs, ARRAY_SIZE(pllfhs), clk_data); - if (r) - goto free_apmixed_data; - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - goto unregister_plls; - - platform_set_drvdata(pdev, clk_data); - - return r; - -unregister_plls: - mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, - ARRAY_SIZE(pllfhs), clk_data); -free_apmixed_data: - mtk_free_clk_data(clk_data); - return r; -} - -static void clk_mt8186_apmixed_remove(struct platform_device *pdev) -{ - struct device_node *node =3D pdev->dev.of_node; - struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); - - of_clk_del_provider(node); - mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, - ARRAY_SIZE(pllfhs), clk_data); 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[14.13.71.96]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38fb30dff2esm4078462a91.13.2026.08.03.07.19.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 07:19:34 -0700 (PDT) From: Akari Tsuyukusa To: Michael Turquette , Stephen Boyd , Brian Masney , Matthias Brugger , AngeloGioacchino Del Regno , Yassine Oudjana , Richard Cochran Cc: Laura Nao , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Chen-Yu Tsai , Akari Tsuyukusa , Bartosz Golaszewski , Danilo Krummrich , Bjorn Helgaas , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Nicolas Frattaroli , Takashi Sakamoto , Haotian Zhang , Kees Cook , Miles Chen , Daniel Golle , Sam Shih , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support), netdev@vger.kernel.org (open list:PTP HARDWARE CLOCK SUPPORT:Keyword:(?:\b|_)ptp(?:\b|_)), stable@vger.kernel.org Subject: [PATCH 28/32] clk: mediatek: mt8188-apmixedsys: Switch to common probe/remove helpers Date: Mon, 3 Aug 2026 23:16:55 +0900 Message-ID: <20260803141659.559129-29-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803141659.559129-1-akkun11.open@gmail.com> References: <20260803141659.559129-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MT8188 apmixedsys driver can use the MediaTek clock framework common initialization sequence. Reduce boilerplate code by creating struct mtk_clk_desc and using the mtk_clk_simple_probe/remove helpers. Signed-off-by: Akari Tsuyukusa --- drivers/clk/mediatek/clk-mt8188-apmixedsys.c | 60 ++++---------------- 1 file changed, 10 insertions(+), 50 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8188-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8188-apmixedsys.c index 48a2f61d4b77..3937d93cac34 100644 --- a/drivers/clk/mediatek/clk-mt8188-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8188-apmixedsys.c @@ -89,62 +89,22 @@ static const struct mtk_pll_data plls[] =3D { 0, 0, 22, 0x0344, 24, 0, 0, 0, 0x0344, 0, 0, 0, 9), }; =20 +static const struct mtk_clk_desc apmixed_desc =3D { + .plls =3D plls, + .num_plls =3D ARRAY_SIZE(plls), + .clks =3D apmixed_clks, + .num_clks =3D ARRAY_SIZE(apmixed_clks), +}; + static const struct of_device_id of_match_clk_mt8188_apmixed[] =3D { - { .compatible =3D "mediatek,mt8188-apmixedsys" }, + { .compatible =3D "mediatek,mt8188-apmixedsys", .data =3D &apmixed_desc }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_apmixed); =20 -static int clk_mt8188_apmixed_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - int r; - - clk_data =3D mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); - if (!clk_data) - return -ENOMEM; - - r =3D mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data); - if (r) - goto free_apmixed_data; - - r =3D mtk_clk_register_gates(&pdev->dev, node, apmixed_clks, - ARRAY_SIZE(apmixed_clks), clk_data); - if (r) - goto unregister_plls; - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - goto unregister_gates; - - platform_set_drvdata(pdev, clk_data); - - return 0; - -unregister_gates: - mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data= ); -unregister_plls: - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); -free_apmixed_data: - mtk_free_clk_data(clk_data); - return r; -} - -static void clk_mt8188_apmixed_remove(struct platform_device *pdev) -{ - struct device_node *node =3D pdev->dev.of_node; - struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); 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[14.13.71.96]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38fb30dff2esm4078462a91.13.2026.08.03.07.19.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 07:19:39 -0700 (PDT) From: Akari Tsuyukusa To: Michael Turquette , Stephen Boyd , Brian Masney , Matthias Brugger , AngeloGioacchino Del Regno , Yassine Oudjana , Richard Cochran Cc: Laura Nao , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Chen-Yu Tsai , Akari Tsuyukusa , Bartosz Golaszewski , Danilo Krummrich , Bjorn Helgaas , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Nicolas Frattaroli , Takashi Sakamoto , Haotian Zhang , Kees Cook , Miles Chen , Daniel Golle , Sam Shih , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support), netdev@vger.kernel.org (open list:PTP HARDWARE CLOCK SUPPORT:Keyword:(?:\b|_)ptp(?:\b|_)), stable@vger.kernel.org Subject: [PATCH 29/32] clk: mediatek: mt8192: Switch to common probe/remove helpers Date: Mon, 3 Aug 2026 23:16:56 +0900 Message-ID: <20260803141659.559129-30-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803141659.559129-1-akkun11.open@gmail.com> References: <20260803141659.559129-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MT8192 clock drivers can use the MediaTek clock framework common initialization sequence. Reduce boilerplate code by creating struct mtk_clk_desc and using the mtk_clk_simple_probe/remove helpers. Signed-off-by: Akari Tsuyukusa --- drivers/clk/mediatek/clk-mt8192-apmixedsys.c | 69 ++++---------------- drivers/clk/mediatek/clk-mt8192-aud.c | 26 +------- 2 files changed, 16 insertions(+), 79 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8192-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8192-apmixedsys.c index e6ac40e2f12d..92593370f23b 100644 --- a/drivers/clk/mediatek/clk-mt8192-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8192-apmixedsys.c @@ -143,72 +143,29 @@ static struct mtk_pllfh_data pllfhs[] =3D { FH(CLK_APMIXED_TVDPLL, FH_TVDPLL, 0x154), }; =20 +static const struct mtk_clk_desc apmixed_desc =3D { + .clks =3D apmixed_clks, + .num_clks =3D ARRAY_SIZE(apmixed_clks), + .plls =3D plls, + .num_plls =3D ARRAY_SIZE(plls), + .fhctl_node =3D "mediatek,mt8192-fhctl", + .pllfhs =3D pllfhs, + .num_pllfhs =3D ARRAY_SIZE(pllfhs), +}; + static const struct of_device_id of_match_clk_mt8192_apmixed[] =3D { - { .compatible =3D "mediatek,mt8192-apmixedsys" }, + { .compatible =3D "mediatek,mt8192-apmixedsys", .data =3D &apmixed_desc }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_apmixed); =20 -static int clk_mt8192_apmixed_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - const u8 *fhctl_node =3D "mediatek,mt8192-fhctl"; - int r; - - clk_data =3D mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); - if (!clk_data) - return -ENOMEM; - - fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs)); - - r =3D mtk_clk_register_pllfhs(&pdev->dev, plls, ARRAY_SIZE(plls), - pllfhs, ARRAY_SIZE(pllfhs), clk_data); - if (r) - goto free_clk_data; - - r =3D mtk_clk_register_gates(&pdev->dev, node, apmixed_clks, - ARRAY_SIZE(apmixed_clks), clk_data); - if (r) - goto unregister_plls; - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - goto unregister_gates; - - platform_set_drvdata(pdev, clk_data); - - return r; - -unregister_gates: - mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data= ); -unregister_plls: - mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, - ARRAY_SIZE(pllfhs), clk_data); -free_clk_data: - mtk_free_clk_data(clk_data); - return r; -} - -static void clk_mt8192_apmixed_remove(struct platform_device *pdev) -{ - struct device_node *node =3D pdev->dev.of_node; - struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); - - of_clk_del_provider(node); - mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data= ); - mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, - ARRAY_SIZE(pllfhs), clk_data); - mtk_free_clk_data(clk_data); -} - static struct platform_driver clk_mt8192_apmixed_drv =3D { .driver =3D { .name =3D "clk-mt8192-apmixed", .of_match_table =3D of_match_clk_mt8192_apmixed, }, - .probe =3D clk_mt8192_apmixed_probe, - .remove =3D clk_mt8192_apmixed_remove, + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, }; module_platform_driver(clk_mt8192_apmixed_drv); MODULE_DESCRIPTION("MediaTek MT8192 apmixed clocks driver"); diff --git a/drivers/clk/mediatek/clk-mt8192-aud.c b/drivers/clk/mediatek/c= lk-mt8192-aud.c index f3ebf8713fbb..8625f656a2e4 100644 --- a/drivers/clk/mediatek/clk-mt8192-aud.c +++ b/drivers/clk/mediatek/clk-mt8192-aud.c @@ -80,29 +80,9 @@ static const struct mtk_gate aud_clks[] =3D { static const struct mtk_clk_desc aud_desc =3D { .clks =3D aud_clks, .num_clks =3D ARRAY_SIZE(aud_clks), + .populate_children =3D true, }; =20 -static int clk_mt8192_aud_probe(struct platform_device *pdev) -{ - int r; - - r =3D mtk_clk_simple_probe(pdev); - if (r) - return r; - - r =3D devm_of_platform_populate(&pdev->dev); - if (r) - mtk_clk_simple_remove(pdev); - - return r; -} - -static void clk_mt8192_aud_remove(struct platform_device *pdev) -{ - of_platform_depopulate(&pdev->dev); - mtk_clk_simple_remove(pdev); -} - static const struct of_device_id of_match_clk_mt8192_aud[] =3D { { .compatible =3D "mediatek,mt8192-audsys", .data =3D &aud_desc }, { /* sentinel */ } @@ -110,8 +90,8 @@ static const struct of_device_id of_match_clk_mt8192_aud= [] =3D { MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_aud); =20 static struct platform_driver clk_mt8192_aud_drv =3D { - .probe =3D clk_mt8192_aud_probe, - .remove =3D clk_mt8192_aud_remove, + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, .driver =3D { .name =3D "clk-mt8192-aud", .of_match_table =3D of_match_clk_mt8192_aud, --=20 2.55.0 From nobody Fri Oct 2 08:24:59 2026 Received: from mail-pj1-f43.google.com (mail-pj1-f43.google.com [209.85.216.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C0FC9432E89 for ; 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[14.13.71.96]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38fb30dff2esm4078462a91.13.2026.08.03.07.19.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 07:19:43 -0700 (PDT) From: Akari Tsuyukusa To: Michael Turquette , Stephen Boyd , Brian Masney , Matthias Brugger , AngeloGioacchino Del Regno , Yassine Oudjana , Richard Cochran Cc: Laura Nao , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Chen-Yu Tsai , Akari Tsuyukusa , Bartosz Golaszewski , Danilo Krummrich , Bjorn Helgaas , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Nicolas Frattaroli , Takashi Sakamoto , Haotian Zhang , Kees Cook , Miles Chen , Daniel Golle , Sam Shih , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support), netdev@vger.kernel.org (open list:PTP HARDWARE CLOCK SUPPORT:Keyword:(?:\b|_)ptp(?:\b|_)), stable@vger.kernel.org Subject: [PATCH 30/32] clk: mediatek: mt8195: Switch to common probe/remove helpers Date: Mon, 3 Aug 2026 23:16:57 +0900 Message-ID: <20260803141659.559129-31-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803141659.559129-1-akkun11.open@gmail.com> References: <20260803141659.559129-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MT8195 apusys_pll and apmixedsys drivers can use the MediaTek clock framework common initialization sequence. Reduce boilerplate code by creating struct mtk_clk_desc and using the mtk_clk_simple_probe/remove helpers. Note that the topckgen driver is excluded from this conversion because it requires devm_mtk_clk_mux_notifier_register(), which is not currently supported by the common simple probe helper. Since all MT8195 clock drivers can now be built as modules, change Kconfig setting to "tristate". Signed-off-by: Akari Tsuyukusa --- drivers/clk/mediatek/Kconfig | 12 ++-- drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 67 ++++---------------- drivers/clk/mediatek/clk-mt8195-apusys_pll.c | 49 ++------------ 3 files changed, 25 insertions(+), 103 deletions(-) diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 6449b77d56ed..ac992cfc6c3e 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -909,13 +909,13 @@ config COMMON_CLK_MT8192_VENCSYS This driver supports MediaTek MT8192 vencsys clocks. =20 config COMMON_CLK_MT8195 - bool "Clock driver for MediaTek MT8195" - depends on ARM64 || COMPILE_TEST - select COMMON_CLK_MEDIATEK + tristate "Clock driver for MediaTek MT8195" + depends on ARM64 || COMPILE_TEST + select COMMON_CLK_MEDIATEK select COMMON_CLK_MEDIATEK_FHCTL - default ARCH_MEDIATEK - help - This driver supports MediaTek MT8195 clocks. + default ARCH_MEDIATEK + help + This driver supports MediaTek MT8195 clocks. =20 config COMMON_CLK_MT8195_APUSYS tristate "Clock driver for MediaTek MT8195 apusys" diff --git a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8195-apmixedsys.c index a120c3305547..fc60cd4d9382 100644 --- a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c @@ -161,68 +161,25 @@ static struct mtk_pllfh_data pllfhs[] =3D { FH(CLK_APMIXED_TVDPLL2, FH_TVDPLL1, 0x154), }; =20 +static const struct mtk_clk_desc apmixed_desc =3D { + .clks =3D apmixed_clks, + .num_clks =3D ARRAY_SIZE(apmixed_clks), + .plls =3D plls, + .num_plls =3D ARRAY_SIZE(plls), + .fhctl_node =3D "mediatek,mt8195-fhctl", + .pllfhs =3D pllfhs, + .num_pllfhs =3D ARRAY_SIZE(pllfhs), +}; + static const struct of_device_id of_match_clk_mt8195_apmixed[] =3D { { .compatible =3D "mediatek,mt8195-apmixedsys", }, {} }; MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_apmixed); =20 -static int clk_mt8195_apmixed_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - const u8 *fhctl_node =3D "mediatek,mt8195-fhctl"; - int r; - - clk_data =3D mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); - if (!clk_data) - return -ENOMEM; - - fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs)); - - r =3D mtk_clk_register_pllfhs(&pdev->dev, plls, ARRAY_SIZE(plls), - pllfhs, ARRAY_SIZE(pllfhs), clk_data); - if (r) - goto free_apmixed_data; - - r =3D mtk_clk_register_gates(&pdev->dev, node, apmixed_clks, - ARRAY_SIZE(apmixed_clks), clk_data); - if (r) - goto unregister_plls; - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - goto unregister_gates; - - platform_set_drvdata(pdev, clk_data); - - return r; - -unregister_gates: - mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data= ); -unregister_plls: - mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, - ARRAY_SIZE(pllfhs), clk_data); -free_apmixed_data: - mtk_free_clk_data(clk_data); - return r; -} - -static void clk_mt8195_apmixed_remove(struct platform_device *pdev) -{ - struct device_node *node =3D pdev->dev.of_node; - struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); - - of_clk_del_provider(node); - mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data= ); - mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, - ARRAY_SIZE(pllfhs), clk_data); - mtk_free_clk_data(clk_data); -} - static struct platform_driver clk_mt8195_apmixed_drv =3D { - .probe =3D clk_mt8195_apmixed_probe, - .remove =3D clk_mt8195_apmixed_remove, + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, .driver =3D { .name =3D "clk-mt8195-apmixed", .of_match_table =3D of_match_clk_mt8195_apmixed, diff --git a/drivers/clk/mediatek/clk-mt8195-apusys_pll.c b/drivers/clk/med= iatek/clk-mt8195-apusys_pll.c index a2d98ed58e34..36d358141ecb 100644 --- a/drivers/clk/mediatek/clk-mt8195-apusys_pll.c +++ b/drivers/clk/mediatek/clk-mt8195-apusys_pll.c @@ -56,55 +56,20 @@ static const struct mtk_pll_data apusys_plls[] =3D { PLL(CLK_APUSYS_PLL_APUPLL2, "apusys_pll_apupll2", 0x038, 0x044, 0x03c, 0x= 03c), }; =20 -static int clk_mt8195_apusys_pll_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - int r; - - clk_data =3D mtk_alloc_clk_data(CLK_APUSYS_PLL_NR_CLK); - if (!clk_data) - return -ENOMEM; - - r =3D mtk_clk_register_plls(&pdev->dev, apusys_plls, - ARRAY_SIZE(apusys_plls), clk_data); - if (r) - goto free_apusys_pll_data; - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - goto unregister_plls; - - platform_set_drvdata(pdev, clk_data); - - return r; - -unregister_plls: - mtk_clk_unregister_plls(apusys_plls, ARRAY_SIZE(apusys_plls), clk_data); -free_apusys_pll_data: - mtk_free_clk_data(clk_data); - return r; -} - -static void clk_mt8195_apusys_pll_remove(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); - struct device_node *node =3D pdev->dev.of_node; - - of_clk_del_provider(node); - mtk_clk_unregister_plls(apusys_plls, ARRAY_SIZE(apusys_plls), clk_data); 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[14.13.71.96]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38fb30dff2esm4078462a91.13.2026.08.03.07.19.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 07:19:48 -0700 (PDT) From: Akari Tsuyukusa To: Michael Turquette , Stephen Boyd , Brian Masney , Matthias Brugger , AngeloGioacchino Del Regno , Yassine Oudjana , Richard Cochran Cc: Laura Nao , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Chen-Yu Tsai , Akari Tsuyukusa , Bartosz Golaszewski , Danilo Krummrich , Bjorn Helgaas , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Nicolas Frattaroli , Takashi Sakamoto , Haotian Zhang , Kees Cook , Miles Chen , Daniel Golle , Sam Shih , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support), netdev@vger.kernel.org (open list:PTP HARDWARE CLOCK SUPPORT:Keyword:(?:\b|_)ptp(?:\b|_)), stable@vger.kernel.org Subject: [PATCH 31/32] clk: mediatek: mt8196: Switch to common probe/remove helpers Date: Mon, 3 Aug 2026 23:16:58 +0900 Message-ID: <20260803141659.559129-32-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803141659.559129-1-akkun11.open@gmail.com> References: <20260803141659.559129-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MT8196 apmixedsys, mcusys and mfg clock drivers can use the MediaTek clock framework common initialization sequence. Reduce boilerplate code by creating struct mtk_clk_desc and using the mtk_clk_simple_probe/remove helpers. Note that the vlpckgen driver is excluded from this conversion because its probe callback needs to initialize the APLL tuner registers, which is not currently supported by the common simple probe helper. Signed-off-by: Akari Tsuyukusa --- drivers/clk/mediatek/clk-mt8196-apmixedsys.c | 67 ++------------ drivers/clk/mediatek/clk-mt8196-mcu.c | 96 +++++++------------- drivers/clk/mediatek/clk-mt8196-mfg.c | 84 +++++------------ 3 files changed, 63 insertions(+), 184 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8196-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8196-apmixedsys.c index c4ebb0170b82..a20fa02070a8 100644 --- a/drivers/clk/mediatek/clk-mt8196-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8196-apmixedsys.c @@ -86,11 +86,6 @@ .ops =3D &mtk_pll_fenc_clr_set_ops, \ } =20 -struct mtk_pll_desc { - const struct mtk_pll_data *clks; - size_t num_clks; -}; - static const struct mtk_pll_data apmixed_plls[] =3D { PLL_FENC(CLK_APMIXED_MAINPLL, "mainpll", MAINPLL_CON0, FENC_STATUS_CON0, 7, PLL_AO, MAINPLL_CON1, 24, MAINPLL_CON1, 0, 22, 0), @@ -110,9 +105,9 @@ static const struct mtk_pll_data apmixed_plls[] =3D { 0, 0, SGMIIPLL_CON1, 24, SGMIIPLL_CON1, 0, 22, 7), }; =20 -static const struct mtk_pll_desc apmixed_desc =3D { - .clks =3D apmixed_plls, - .num_clks =3D ARRAY_SIZE(apmixed_plls), +static const struct mtk_clk_desc apmixed_desc =3D { + .plls =3D apmixed_plls, + .num_plls =3D ARRAY_SIZE(apmixed_plls), }; =20 static const struct mtk_pll_data apmixed2_plls[] =3D { @@ -132,57 +127,11 @@ static const struct mtk_pll_data apmixed2_plls[] =3D { 0, 0, TVDPLL3_CON1, 24, TVDPLL3_CON1, 0, 22, 6), }; =20 -static const struct mtk_pll_desc apmixed2_desc =3D { - .clks =3D apmixed2_plls, - .num_clks =3D ARRAY_SIZE(apmixed2_plls), +static const struct mtk_clk_desc apmixed2_desc =3D { + .plls =3D apmixed2_plls, + .num_plls =3D ARRAY_SIZE(apmixed2_plls), }; =20 -static int clk_mt8196_apmixed_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - const struct mtk_pll_desc *mcd; - int r; - - mcd =3D device_get_match_data(&pdev->dev); - if (!mcd) - return -EINVAL; - - clk_data =3D mtk_alloc_clk_data(mcd->num_clks); - if (!clk_data) - return -ENOMEM; - - r =3D mtk_clk_register_plls(&pdev->dev, mcd->clks, mcd->num_clks, - clk_data); - if (r) - goto free_apmixed_data; - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - goto unregister_plls; - - platform_set_drvdata(pdev, clk_data); - - return r; - -unregister_plls: - mtk_clk_unregister_plls(mcd->clks, mcd->num_clks, clk_data); -free_apmixed_data: - mtk_free_clk_data(clk_data); - return r; -} - -static void clk_mt8196_apmixed_remove(struct platform_device *pdev) -{ - const struct mtk_pll_desc *mcd =3D device_get_match_data(&pdev->dev); - struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); - struct device_node *node =3D pdev->dev.of_node; - - of_clk_del_provider(node); - mtk_clk_unregister_plls(mcd->clks, mcd->num_clks, clk_data); - mtk_free_clk_data(clk_data); -} - static const struct of_device_id of_match_clk_mt8196_apmixed[] =3D { { .compatible =3D "mediatek,mt8196-apmixedsys", .data =3D &apmixed_desc }, { .compatible =3D "mediatek,mt8196-apmixedsys-gp2", @@ -192,8 +141,8 @@ static const struct of_device_id of_match_clk_mt8196_ap= mixed[] =3D { MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_apmixed); =20 static struct platform_driver clk_mt8196_apmixed_drv =3D { - .probe =3D clk_mt8196_apmixed_probe, - .remove =3D clk_mt8196_apmixed_remove, + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, .driver =3D { .name =3D "clk-mt8196-apmixed", .of_match_table =3D of_match_clk_mt8196_apmixed, diff --git a/drivers/clk/mediatek/clk-mt8196-mcu.c b/drivers/clk/mediatek/c= lk-mt8196-mcu.c index 13642fc673c2..e392408c93b2 100644 --- a/drivers/clk/mediatek/clk-mt8196-mcu.c +++ b/drivers/clk/mediatek/clk-mt8196-mcu.c @@ -68,29 +68,44 @@ .pcwibits =3D MT8196_INTEGER_BITS, \ } =20 -static const struct mtk_pll_data cpu_bl_plls[] =3D { - PLL(CLK_CPBL_ARMPLL_BL, "armpll-bl", ARMPLL_BL_CON0, ARMPLL_BL_CON0, 0, - 0, PLL_AO, BIT(0), ARMPLL_BL_CON1, 24, 0, 0, 0, ARMPLL_BL_CON1, 0, 22= ), +static const struct mtk_clk_desc cpu_bl_plls =3D { + .plls =3D (const struct mtk_pll_data[]){ + PLL(CLK_CPBL_ARMPLL_BL, "armpll-bl", ARMPLL_BL_CON0, ARMPLL_BL_CON0, 0, + 0, PLL_AO, BIT(0), ARMPLL_BL_CON1, 24, 0, 0, 0, ARMPLL_BL_CON1, 0, 2= 2), + }, + .num_plls =3D 1, }; =20 -static const struct mtk_pll_data cpu_b_plls[] =3D { - PLL(CLK_CPB_ARMPLL_B, "armpll-b", ARMPLL_B_CON0, ARMPLL_B_CON0, 0, 0, - PLL_AO, BIT(0), ARMPLL_B_CON1, 24, 0, 0, 0, ARMPLL_B_CON1, 0, 22), +static const struct mtk_clk_desc cpu_b_plls =3D { + .plls =3D (const struct mtk_pll_data[]){ + PLL(CLK_CPB_ARMPLL_B, "armpll-b", ARMPLL_B_CON0, ARMPLL_B_CON0, 0, 0, + PLL_AO, BIT(0), ARMPLL_B_CON1, 24, 0, 0, 0, ARMPLL_B_CON1, 0, 22), + }, + .num_plls =3D 1, }; =20 -static const struct mtk_pll_data cpu_ll_plls[] =3D { - PLL(CLK_CPLL_ARMPLL_LL, "armpll-ll", ARMPLL_LL_CON0, ARMPLL_LL_CON0, 0, - 0, PLL_AO, BIT(0), ARMPLL_LL_CON1, 24, 0, 0, 0, ARMPLL_LL_CON1, 0, 22= ), +static const struct mtk_clk_desc cpu_ll_plls =3D { + .plls =3D (const struct mtk_pll_data[]){ + PLL(CLK_CPLL_ARMPLL_LL, "armpll-ll", ARMPLL_LL_CON0, ARMPLL_LL_CON0, 0, + 0, PLL_AO, BIT(0), ARMPLL_LL_CON1, 24, 0, 0, 0, ARMPLL_LL_CON1, 0, 2= 2), + }, + .num_plls =3D 1, }; =20 -static const struct mtk_pll_data cci_plls[] =3D { - PLL(CLK_CCIPLL, "ccipll", CCIPLL_CON0, CCIPLL_CON0, 0, 0, PLL_AO, - BIT(0), CCIPLL_CON1, 24, 0, 0, 0, CCIPLL_CON1, 0, 22), +static const struct mtk_clk_desc cci_plls =3D { + .plls =3D (const struct mtk_pll_data[]){ + PLL(CLK_CCIPLL, "ccipll", CCIPLL_CON0, CCIPLL_CON0, 0, 0, PLL_AO, + BIT(0), CCIPLL_CON1, 24, 0, 0, 0, CCIPLL_CON1, 0, 22), + }, + .num_plls =3D 1, }; =20 -static const struct mtk_pll_data ptp_plls[] =3D { - PLL(CLK_PTPPLL, "ptppll", PTPPLL_CON0, PTPPLL_CON0, 0, 0, PLL_AO, - BIT(0), PTPPLL_CON1, 24, 0, 0, 0, PTPPLL_CON1, 0, 22), +static const struct mtk_clk_desc ptp_plls =3D { + .plls =3D (const struct mtk_pll_data[]){ + PLL(CLK_PTPPLL, "ptppll", PTPPLL_CON0, PTPPLL_CON0, 0, 0, PLL_AO, + BIT(0), PTPPLL_CON1, 24, 0, 0, 0, PTPPLL_CON1, 0, 22), + }, + .num_plls =3D 1, }; =20 static const struct of_device_id of_match_clk_mt8196_mcu[] =3D { @@ -106,56 +121,9 @@ static const struct of_device_id of_match_clk_mt8196_m= cu[] =3D { }; MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_mcu); =20 -static int clk_mt8196_mcu_probe(struct platform_device *pdev) -{ - const struct mtk_pll_data *plls; - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - const int num_plls =3D 1; - int r; - - plls =3D of_device_get_match_data(&pdev->dev); - if (!plls) - return -EINVAL; - - clk_data =3D mtk_alloc_clk_data(num_plls); - if (!clk_data) - return -ENOMEM; - - r =3D mtk_clk_register_plls(&pdev->dev, plls, num_plls, clk_data); - if (r) - goto free_clk_data; - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - goto unregister_plls; - - platform_set_drvdata(pdev, clk_data); - - return r; - -unregister_plls: - mtk_clk_unregister_plls(plls, num_plls, clk_data); -free_clk_data: - mtk_free_clk_data(clk_data); - - return r; -} - -static void clk_mt8196_mcu_remove(struct platform_device *pdev) -{ - const struct mtk_pll_data *plls =3D of_device_get_match_data(&pdev->dev); - struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); - struct device_node *node =3D pdev->dev.of_node; - - of_clk_del_provider(node); - mtk_clk_unregister_plls(plls, 1, clk_data); - mtk_free_clk_data(clk_data); -} - static struct platform_driver clk_mt8196_mcu_drv =3D { - .probe =3D clk_mt8196_mcu_probe, - .remove =3D clk_mt8196_mcu_remove, + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, .driver =3D { .name =3D "clk-mt8196-mcu", .of_match_table =3D of_match_clk_mt8196_mcu, diff --git a/drivers/clk/mediatek/clk-mt8196-mfg.c b/drivers/clk/mediatek/c= lk-mt8196-mfg.c index a317183f1681..a209162f6207 100644 --- a/drivers/clk/mediatek/clk-mt8196-mfg.c +++ b/drivers/clk/mediatek/clk-mt8196-mfg.c @@ -61,22 +61,31 @@ .parent_name =3D "mfg_eb", \ } =20 -static const struct mtk_pll_data mfg_ao_plls[] =3D { - PLL(CLK_MFG_AO_MFGPLL, "mfgpll", MFGPLL_CON0, MFGPLL_CON0, 0, 0, - PLL_PARENT_EN, BIT(0), MFGPLL_CON1, 24, 0, 0, 0, - MFGPLL_CON1, 0, 22), +static const struct mtk_clk_desc mfg_ao_plls =3D { + .plls =3D (const struct mtk_pll_data[]){ + PLL(CLK_MFG_AO_MFGPLL, "mfgpll", MFGPLL_CON0, + MFGPLL_CON0, 0, 0, PLL_PARENT_EN, BIT(0), + MFGPLL_CON1, 24, 0, 0, 0, MFGPLL_CON1, 0, 22), + }, + .num_plls =3D 1, }; =20 -static const struct mtk_pll_data mfgsc0_ao_plls[] =3D { - PLL(CLK_MFGSC0_AO_MFGPLL_SC0, "mfgpll-sc0", MFGPLL_SC0_CON0, - MFGPLL_SC0_CON0, 0, 0, PLL_PARENT_EN, BIT(0), MFGPLL_SC0_CON1, 24, - 0, 0, 0, MFGPLL_SC0_CON1, 0, 22), +static const struct mtk_clk_desc mfgsc0_ao_plls =3D { + .plls =3D (const struct mtk_pll_data[]){ + PLL(CLK_MFGSC0_AO_MFGPLL_SC0, "mfgpll-sc0", MFGPLL_SC0_CON0, + MFGPLL_SC0_CON0, 0, 0, PLL_PARENT_EN, BIT(0), + MFGPLL_SC0_CON1, 24, 0, 0, 0, MFGPLL_SC0_CON1, 0, 22), + }, + .num_plls =3D 1, }; =20 -static const struct mtk_pll_data mfgsc1_ao_plls[] =3D { - PLL(CLK_MFGSC1_AO_MFGPLL_SC1, "mfgpll-sc1", MFGPLL_SC1_CON0, - MFGPLL_SC1_CON0, 0, 0, PLL_PARENT_EN, BIT(0), MFGPLL_SC1_CON1, 24, - 0, 0, 0, MFGPLL_SC1_CON1, 0, 22), +static const struct mtk_clk_desc mfgsc1_ao_plls =3D { + .plls =3D (const struct mtk_pll_data[]){ + PLL(CLK_MFGSC1_AO_MFGPLL_SC1, "mfgpll-sc1", MFGPLL_SC1_CON0, + MFGPLL_SC1_CON0, 0, 0, PLL_PARENT_EN, BIT(0), + MFGPLL_SC1_CON1, 24, 0, 0, 0, MFGPLL_SC1_CON1, 0, 22), + }, + .num_plls =3D 1, }; =20 static const struct of_device_id of_match_clk_mt8196_mfg[] =3D { @@ -90,56 +99,9 @@ static const struct of_device_id of_match_clk_mt8196_mfg= [] =3D { }; MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_mfg); =20 -static int clk_mt8196_mfg_probe(struct platform_device *pdev) -{ - const struct mtk_pll_data *plls; - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - const int num_plls =3D 1; - int r; - - plls =3D of_device_get_match_data(&pdev->dev); - if (!plls) - return -EINVAL; - - clk_data =3D mtk_alloc_clk_data(num_plls); - if (!clk_data) - return -ENOMEM; - - r =3D mtk_clk_register_plls(&pdev->dev, plls, num_plls, clk_data); - if (r) - goto free_clk_data; - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - goto unregister_plls; - - platform_set_drvdata(pdev, clk_data); - - return r; - -unregister_plls: - mtk_clk_unregister_plls(plls, num_plls, clk_data); -free_clk_data: - mtk_free_clk_data(clk_data); - - return r; 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[14.13.71.96]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38fb30dff2esm4078462a91.13.2026.08.03.07.19.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 07:19:52 -0700 (PDT) From: Akari Tsuyukusa To: Michael Turquette , Stephen Boyd , Brian Masney , Matthias Brugger , AngeloGioacchino Del Regno , Yassine Oudjana , Richard Cochran Cc: Laura Nao , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Chen-Yu Tsai , Akari Tsuyukusa , Bartosz Golaszewski , Danilo Krummrich , Bjorn Helgaas , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , Nicolas Frattaroli , Takashi Sakamoto , Haotian Zhang , Kees Cook , Miles Chen , Daniel Golle , Sam Shih , linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support), netdev@vger.kernel.org (open list:PTP HARDWARE CLOCK SUPPORT:Keyword:(?:\b|_)ptp(?:\b|_)), stable@vger.kernel.org Subject: [PATCH 32/32] clk: mediatek: mt8516-apmixedsys: Switch to common probe/remove helpers Date: Mon, 3 Aug 2026 23:16:59 +0900 Message-ID: <20260803141659.559129-33-akkun11.open@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260803141659.559129-1-akkun11.open@gmail.com> References: <20260803141659.559129-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MT8516 apmixedsys driver can use the MediaTek clock framework common initialization sequence. Reduce boilerplate code by creating struct mtk_clk_desc and using the mtk_clk_simple_probe/remove helpers. Also, add a remove callback to properly support module unloading. Signed-off-by: Akari Tsuyukusa --- drivers/clk/mediatek/clk-mt8516-apmixedsys.c | 42 ++++---------------- 1 file changed, 8 insertions(+), 34 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8516-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8516-apmixedsys.c index 2a6206cae2f0..2fb09e7acde7 100644 --- a/drivers/clk/mediatek/clk-mt8516-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8516-apmixedsys.c @@ -71,52 +71,26 @@ static const struct mtk_pll_data plls[] =3D { 31, 0x01A0, 1, 0x01B4, 0x01A4, 0), }; =20 -static int clk_mt8516_apmixed_probe(struct platform_device *pdev) -{ - void __iomem *base; - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - struct device *dev =3D &pdev->dev; - int ret; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - clk_data =3D mtk_devm_alloc_clk_data(dev, CLK_APMIXED_NR_CLK); - if (!clk_data) - return -ENOMEM; - - ret =3D mtk_clk_register_plls(dev, plls, ARRAY_SIZE(plls), clk_data); - if (ret) - return ret; - - ret =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (ret) - goto unregister_plls; - - return 0; - -unregister_plls: - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); - - return ret; -} +static const struct mtk_clk_desc apmixed_desc =3D { + .plls =3D plls, + .num_plls =3D ARRAY_SIZE(plls), +}; =20 static const struct of_device_id of_match_clk_mt8516_apmixed[] =3D { - { .compatible =3D "mediatek,mt8516-apmixedsys" }, + { .compatible =3D "mediatek,mt8516-apmixedsys", .data =3D &apmixed_desc }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, of_match_clk_mt8516_apmixed); =20 static struct platform_driver clk_mt8516_apmixed_drv =3D { - .probe =3D clk_mt8516_apmixed_probe, + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, .driver =3D { .name =3D "clk-mt8516-apmixed", .of_match_table =3D of_match_clk_mt8516_apmixed, }, }; -builtin_platform_driver(clk_mt8516_apmixed_drv) +module_platform_driver(clk_mt8516_apmixed_drv) =20 MODULE_DESCRIPTION("MediaTek MT8516 apmixedsys clocks driver"); MODULE_LICENSE("GPL"); --=20 2.55.0