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Mon, 03 Aug 2026 07:10:38 -0700 (PDT) Received: from chromium.org ([174.51.25.52]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-6ae3a0c9162sm6526695eaf.11.2026.08.03.07.10.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 07:10:37 -0700 (PDT) From: Simon Glass To: Linus Walleij Cc: Heiko Stuebner , linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-gpio@vger.kernel.org, Vladislav Leonov , Jonas Karlman , Simon Glass , Jeffy Chen , huang lin , linux-kernel@vger.kernel.org Subject: [PATCH 1/2] pinctrl: rockchip: Reset the pin count when recalculating SoC data Date: Mon, 3 Aug 2026 08:10:23 -0600 Message-ID: <20260803081024.1.72f72067ea890a9eac79d63bf655738bec374dfd@changeid> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260803141028.710706-1-sjg@chromium.org> References: <20260803141028.710706-1-sjg@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" rockchip_pinctrl_get_soc_data() mutates the static per-SoC data. The iomux and drive offsets are recalculated idempotently, since a rerun anchors at the values calculated before, but the total pin count only accumulates: each run adds every bank's pins again. When the probe is deferred and runs a second time, nr_pins doubles and every bank's pin_base shifts, so later pin lookups resolve to the wrong bank and the wrong registers. Reset the pin count at the start of the calculation, so that a rerun produces the same values. This is verified on a Luckfox Pico Mini B (RV1103, with the pending RV1106 series applied) by forcing the probe to defer once: without this patch the second probe calculates nr_pins=3D304 instead of 152 and no GPIO bank comes up; with it the recalculation matches the first run and all banks work. Fixes: d3e5116119bd ("pinctrl: add pinctrl driver for Rockchip SoCs") Link: https://sashiko.dev/#/patchset/20260729132736.3807082-1-sjg@chromium.= org?part=3D4 Assisted-by: Claude:claude-opus-5 Signed-off-by: Simon Glass --- drivers/pinctrl/pinctrl-rockchip.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-r= ockchip.c index 7e0fcd45fd26..8bfc7ab5de15 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -4296,6 +4296,16 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_ge= t_soc_data( pmu_offs =3D ctrl->pmu_mux_offset; drv_pmu_offs =3D ctrl->pmu_drv_offset; drv_grf_offs =3D ctrl->grf_drv_offset; + + /* + * This function mutates the static per-SoC data. Most of it is + * idempotent: recalculated iomux and drv offsets anchor at the + * values calculated by a previous run. The pin count is not, so + * reset it here; otherwise it accumulates when the probe runs + * again after a probe deferral, shifting every bank's pin_base. + */ + ctrl->nr_pins =3D 0; + bank =3D ctrl->pin_banks; for (i =3D 0; i < ctrl->nr_banks; ++i, ++bank) { int bank_pins =3D 0; --=20 2.43.0 From nobody Fri Oct 2 08:25:50 2026 Received: from mail-oo1-f50.google.com (mail-oo1-f50.google.com [209.85.161.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA6DD411F96 for ; Mon, 3 Aug 2026 14:10:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.161.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785766243; cv=none; b=QGhwtCtnJaIO61yvurFT+wLqP5STL7P53lRw159Vqk6q+ZFt30fUXT9CNgT8M4xei9DCFrxBJFeTYk3cYYf6SazAJpWY0alFgECiTOYGt5zZEQLo2LfMgXHJwouH48t8jvFWYIHy0t37S37Nbpm2nxfMSO94/xmZl5airwhnLXI= ARC-Message-Signature: i=1; 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Mon, 03 Aug 2026 07:10:39 -0700 (PDT) From: Simon Glass To: Linus Walleij Cc: Heiko Stuebner , linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-gpio@vger.kernel.org, Vladislav Leonov , Jonas Karlman , Simon Glass , Fabio Estevam , Jeffy Chen , huang lin , linux-kernel@vger.kernel.org Subject: [PATCH 2/2] pinctrl: rockchip: Restrict the RV1103B 2-bit drive type to bank 2 Date: Mon, 3 Aug 2026 08:10:24 -0600 Message-ID: <20260803081024.2.5ce19c438ee3bdfa91ee7d414bac5ff6b16eaba8@changeid> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260803141028.710706-1-sjg@chromium.org> References: <20260803141028.710706-1-sjg@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The RV1103B override in rockchip_get_drive_perpin() forces the 2-bit level drive type for every pin above 11, but only bank 2 has the 2-bit fields; banks 0 and 1 use the 8-bit level type for all pins, as the corresponding check in rockchip_set_drive_perpin() shows. Today this is harmless, since neither level type is decoded in the get function and both paths fail with -EINVAL. It becomes an active problem once decoding is added, as the pins of banks 0 and 1 would be truncated to 2-bit values. Add the missing bank check, matching the set path. Fixes: 6d3ea3120eaa ("pinctrl: rockchip: Add RV1103B pinctrl support") Link: https://sashiko.dev/#/patchset/20260729132736.3807082-1-sjg@chromium.= org?part=3D1 Assisted-by: Claude:claude-opus-5 Signed-off-by: Simon Glass --- drivers/pinctrl/pinctrl-rockchip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-r= ockchip.c index 8bfc7ab5de15..08084ed2cf1b 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -3212,7 +3212,7 @@ static int rockchip_get_drive_perpin(struct rockchip_= pin_bank *bank, u8 bit; int drv_type =3D bank->drv[pin_num / 8].drv_type; =20 - if (ctrl->type =3D=3D RV1103B && pin_num >=3D 12) + if (ctrl->type =3D=3D RV1103B && bank->bank_num =3D=3D 2 && pin_num >=3D = 12) drv_type =3D DRV_TYPE_IO_LEVEL_2_BIT; =20 ret =3D ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); --=20 2.43.0