From nobody Fri Oct 2 08:24:47 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 673F83839B4; Mon, 3 Aug 2026 14:27:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785767225; cv=none; b=R0+rK6/xe6Cc2Spgv1MUDIi/Oe09wcYl74kQvI/hKJ8Xwc+k7xffC+wI8mfcrZ98r5g2C1loTZcHFy8mzbQhpvzicbELH8mLbp2SxvKWXl41EGbO/e2c2J1BVbyiXFQRK6072DxsHTDB080TXMjRt3O+kGbS9RwUdyy8OQ8IXEU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785767225; c=relaxed/simple; bh=WBsNrxG4CZ2Q6nXNN/z6glyf0grOFnJHg5t3sslSrRM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Ny5m+CWsj69P1X+ON1eNPtxm9/x1ul8fxSrfQr7yXPVNveC9GcqAdkP6QDd/+L1dVZDlS8eXzGFDaTsrd6qfZNeWavBJbFsXqMqpFGBPfs2leQAUrdluXRAlqvxpcl2WydXN0J0g+6Ot51/188SZRto4FrhyFY4zpTt0o91Ana8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GOAtIMPO; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GOAtIMPO" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C30C71F00A3A; Mon, 3 Aug 2026 14:27:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1785767223; bh=kYL1XkAryexw2YQB4KYWoO69pYvf5TKTzaSRYk5HuZo=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=GOAtIMPOoBQobt861jZxNxFWTXR8hHNspZ197ITI3beNgU89JVxeyHQD+yACbJ2ps /XTJDtORABjsXkHM845mcz/TrHIhZtAZ2JsUr2O7JxbyJGD+8cz6RRErY7q93jjdRu h6I61P/d1uVwqgUqdM5Ik6xs2mK6qI70b0Tuxjr8qA76EIa5Hfr3WvHncLdKqhE/bS qJOEeeCOSpdTEPc+jslkVxfDnlOzhHmQnKrclyo++gKhe3PG6DW2gxO2xp7Q7J2Y12 RhjP7NcFAqVIZSkg+QCkpMmyghbTOzaCMnNyD/h/MCrnq9Icg/XmLprwDVVaJpNGez Oht3/9p/dwp1Q== From: Jisheng Zhang To: Mark Brown Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/4] spi: cadence-xspi: group marvell support code together Date: Mon, 3 Aug 2026 22:07:25 +0800 Message-ID: <20260803140728.12747-2-jszhang@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260803140728.12747-1-jszhang@kernel.org> References: <20260803140728.12747-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" We will remove the 64BIT dependency from cadence-xspi for non marvell platform soon. No functionality change. Signed-off-by: Jisheng Zhang --- drivers/spi/spi-cadence-xspi.c | 455 ++++++++++++++++----------------- 1 file changed, 227 insertions(+), 228 deletions(-) diff --git a/drivers/spi/spi-cadence-xspi.c b/drivers/spi/spi-cadence-xspi.c index e1b337789fce..19429b27875a 100644 --- a/drivers/spi/spi-cadence-xspi.c +++ b/drivers/spi/spi-cadence-xspi.c @@ -315,39 +315,10 @@ struct cdns_xspi_driver_data { u32 rfile_phy_dll_slave_ctrl; }; =20 -static struct cdns_xspi_driver_data marvell_driver_data =3D { - .mrvl_hw_overlay =3D true, - .dll_phy_ctrl =3D MARVELL_REGS_DLL_PHY_CTRL, - .ctb_rfile_phy_ctrl =3D MARVELL_CTB_RFILE_PHY_CTRL, - .rfile_phy_tsel =3D MARVELL_RFILE_PHY_TSEL, - .rfile_phy_dq_timing =3D MARVELL_RFILE_PHY_DQ_TIMING, - .rfile_phy_dqs_timing =3D MARVELL_RFILE_PHY_DQS_TIMING, - .rfile_phy_gate_lpbk_ctrl =3D MARVELL_RFILE_PHY_GATE_LPBK_CTRL, - .rfile_phy_dll_master_ctrl =3D MARVELL_RFILE_PHY_DLL_MASTER_CTRL, - .rfile_phy_dll_slave_ctrl =3D MARVELL_RFILE_PHY_DLL_SLAVE_CTRL, -}; - static struct cdns_xspi_driver_data cdns_driver_data =3D { .mrvl_hw_overlay =3D false, }; =20 -static const int cdns_mrvl_xspi_clk_div_list[] =3D { - 4, //0x0 =3D Divide by 4. SPI clock is 200 MHz. - 6, //0x1 =3D Divide by 6. SPI clock is 133.33 MHz. - 8, //0x2 =3D Divide by 8. SPI clock is 100 MHz. - 10, //0x3 =3D Divide by 10. SPI clock is 80 MHz. - 12, //0x4 =3D Divide by 12. SPI clock is 66.666 MHz. - 16, //0x5 =3D Divide by 16. SPI clock is 50 MHz. - 18, //0x6 =3D Divide by 18. SPI clock is 44.44 MHz. - 20, //0x7 =3D Divide by 20. SPI clock is 40 MHz. - 24, //0x8 =3D Divide by 24. SPI clock is 33.33 MHz. - 32, //0x9 =3D Divide by 32. SPI clock is 25 MHz. - 40, //0xA =3D Divide by 40. SPI clock is 20 MHz. - 50, //0xB =3D Divide by 50. SPI clock is 16 MHz. - 64, //0xC =3D Divide by 64. SPI clock is 12.5 MHz. - 128 //0xD =3D Divide by 128. SPI clock is 6.25 MHz. -}; - struct cdns_xspi_dev { struct platform_device *pdev; struct spi_controller *host; @@ -382,92 +353,6 @@ struct cdns_xspi_dev { int current_xfer_qword; }; =20 -static void cdns_xspi_reset_dll(struct cdns_xspi_dev *cdns_xspi) -{ - u32 dll_cntrl =3D readl(cdns_xspi->iobase + - CDNS_XSPI_RF_MINICTRL_REGS_DLL_PHY_CTRL); - - /* Reset DLL */ - dll_cntrl |=3D CDNS_XSPI_DLL_RST_N; - writel(dll_cntrl, cdns_xspi->iobase + - CDNS_XSPI_RF_MINICTRL_REGS_DLL_PHY_CTRL); -} - -static bool cdns_xspi_is_dll_locked(struct cdns_xspi_dev *cdns_xspi) -{ - u32 dll_lock; - - return !readl_relaxed_poll_timeout(cdns_xspi->iobase + - CDNS_XSPI_INTR_STATUS_REG, - dll_lock, ((dll_lock & CDNS_XSPI_DLL_LOCK) =3D=3D 1), 10, 10000); -} - -/* Static configuration of PHY */ -static bool cdns_xspi_configure_phy(struct cdns_xspi_dev *cdns_xspi) -{ - writel(cdns_xspi->driver_data->dll_phy_ctrl, - cdns_xspi->iobase + CDNS_XSPI_RF_MINICTRL_REGS_DLL_PHY_CTRL); - writel(cdns_xspi->driver_data->ctb_rfile_phy_ctrl, - cdns_xspi->auxbase + CDNS_XSPI_PHY_CTB_RFILE_PHY_CTRL); - writel(cdns_xspi->driver_data->rfile_phy_tsel, - cdns_xspi->auxbase + CDNS_XSPI_PHY_CTB_RFILE_PHY_TSEL); - writel(cdns_xspi->driver_data->rfile_phy_dq_timing, - cdns_xspi->auxbase + CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_DQ_TIMING); - writel(cdns_xspi->driver_data->rfile_phy_dqs_timing, - cdns_xspi->auxbase + CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_DQS_TIMING); - writel(cdns_xspi->driver_data->rfile_phy_gate_lpbk_ctrl, - cdns_xspi->auxbase + CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_GATE_LPBK_C= TRL); - writel(cdns_xspi->driver_data->rfile_phy_dll_master_ctrl, - cdns_xspi->auxbase + CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_DLL_MASTER_= CTRL); - writel(cdns_xspi->driver_data->rfile_phy_dll_slave_ctrl, - cdns_xspi->auxbase + CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_DLL_SLAVE_C= TRL); - - cdns_xspi_reset_dll(cdns_xspi); - - return cdns_xspi_is_dll_locked(cdns_xspi); -} - -static bool cdns_mrvl_xspi_setup_clock(struct cdns_xspi_dev *cdns_xspi, - int requested_clk) -{ - int i =3D 0; - int clk_val; - u32 clk_reg; - bool update_clk =3D false; - - while (i < (ARRAY_SIZE(cdns_mrvl_xspi_clk_div_list) - 1)) { - clk_val =3D MRVL_XSPI_CLOCK_DIVIDED( - cdns_mrvl_xspi_clk_div_list[i]); - if (clk_val <=3D requested_clk) - break; - i++; - } - - dev_dbg(cdns_xspi->dev, "Found clk div: %d, clk val: %d\n", - cdns_mrvl_xspi_clk_div_list[i], - MRVL_XSPI_CLOCK_DIVIDED( - cdns_mrvl_xspi_clk_div_list[i])); - - clk_reg =3D readl(cdns_xspi->auxbase + MRVL_XSPI_CLK_CTRL_AUX_REG); - - if (FIELD_GET(MRVL_XSPI_CLK_DIV, clk_reg) !=3D i) { - clk_reg &=3D ~MRVL_XSPI_CLK_ENABLE; - writel(clk_reg, - cdns_xspi->auxbase + MRVL_XSPI_CLK_CTRL_AUX_REG); - clk_reg =3D FIELD_PREP(MRVL_XSPI_CLK_DIV, i); - FIELD_MODIFY(MRVL_XSPI_CLK_DIV, &clk_reg, i); - clk_reg |=3D MRVL_XSPI_CLK_ENABLE; - clk_reg |=3D MRVL_XSPI_IRQ_ENABLE; - update_clk =3D true; - } - - if (update_clk) - writel(clk_reg, - cdns_xspi->auxbase + MRVL_XSPI_CLK_CTRL_AUX_REG); - - return update_clk; -} - static int cdns_xspi_wait_for_controller_idle(struct cdns_xspi_dev *cdns_x= spi) { u32 ctrl_stat; @@ -540,23 +425,6 @@ static void cdns_xspi_set_interrupts(struct cdns_xspi_= dev *cdns_xspi, writel(intr_enable, cdns_xspi->iobase + CDNS_XSPI_INTR_ENABLE_REG); } =20 -static void marvell_xspi_set_interrupts(struct cdns_xspi_dev *cdns_xspi, - bool enabled) -{ - u32 intr_enable; - u32 irq_status; - - irq_status =3D readl(cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG); - writel(irq_status, cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG); - - intr_enable =3D readl(cdns_xspi->iobase + CDNS_XSPI_INTR_ENABLE_REG); - if (enabled) - intr_enable |=3D CDNS_XSPI_INTR_MASK; - else - intr_enable &=3D ~CDNS_XSPI_INTR_MASK; - writel(intr_enable, cdns_xspi->iobase + CDNS_XSPI_INTR_ENABLE_REG); -} - static int cdns_xspi_controller_init(struct cdns_xspi_dev *cdns_xspi) { u32 ctrl_ver; @@ -644,78 +512,6 @@ static void cdns_xspi_sdma_handle(struct cdns_xspi_dev= *cdns_xspi) } } =20 -static void m_ioreadq(void __iomem *addr, void *buf, int len) -{ - if (IS_ALIGNED((long)buf, 8) && len >=3D 8) { - u64 full_ops =3D len / 8; - u64 *buffer =3D buf; - - len -=3D full_ops * 8; - buf +=3D full_ops * 8; - - do { - u64 b =3D readq(addr); - *buffer++ =3D b; - } while (--full_ops); - } - - - while (len) { - u64 tmp_buf; - - tmp_buf =3D readq(addr); - memcpy(buf, &tmp_buf, min(len, 8)); - len =3D len > 8 ? len - 8 : 0; - buf +=3D 8; - } -} - -static void m_iowriteq(void __iomem *addr, const void *buf, int len) -{ - if (IS_ALIGNED((long)buf, 8) && len >=3D 8) { - u64 full_ops =3D len / 8; - const u64 *buffer =3D buf; - - len -=3D full_ops * 8; - buf +=3D full_ops * 8; - - do { - writeq(*buffer++, addr); - } while (--full_ops); - } - - while (len) { - u64 tmp_buf; - - memcpy(&tmp_buf, buf, min(len, 8)); - writeq(tmp_buf, addr); - len =3D len > 8 ? len - 8 : 0; - buf +=3D 8; - } -} - -static void marvell_xspi_sdma_handle(struct cdns_xspi_dev *cdns_xspi) -{ - u32 sdma_size, sdma_trd_info; - u8 sdma_dir; - - sdma_size =3D readl(cdns_xspi->iobase + CDNS_XSPI_SDMA_SIZE_REG); - sdma_trd_info =3D readl(cdns_xspi->iobase + CDNS_XSPI_SDMA_TRD_INFO_REG); - sdma_dir =3D FIELD_GET(CDNS_XSPI_SDMA_DIR, sdma_trd_info); - - switch (sdma_dir) { - case CDNS_XSPI_SDMA_DIR_READ: - m_ioreadq(cdns_xspi->sdmabase, - cdns_xspi->in_buffer, sdma_size); - break; - - case CDNS_XSPI_SDMA_DIR_WRITE: - m_iowriteq(cdns_xspi->sdmabase, - cdns_xspi->out_buffer, sdma_size); - break; - } -} - static int cdns_xspi_send_stig_command(struct cdns_xspi_dev *cdns_xspi, const struct spi_mem_op *op, bool data_phase) @@ -805,20 +601,6 @@ static int cdns_xspi_mem_op_execute(struct spi_mem *me= m, return ret; } =20 -static int marvell_xspi_mem_op_execute(struct spi_mem *mem, - const struct spi_mem_op *op) -{ - struct cdns_xspi_dev *cdns_xspi =3D - spi_controller_get_devdata(mem->spi->controller); - int ret =3D 0; - - cdns_mrvl_xspi_setup_clock(cdns_xspi, mem->spi->max_speed_hz); - - ret =3D cdns_xspi_mem_op(cdns_xspi, mem, op); - - return ret; -} - static bool cdns_xspi_supports_op(struct spi_mem *mem, const struct spi_mem_op *op) { @@ -886,12 +668,6 @@ static const struct spi_controller_mem_ops cadence_xsp= i_mem_ops =3D { .adjust_op_size =3D cdns_xspi_adjust_mem_op_size, }; =20 -static const struct spi_controller_mem_ops marvell_xspi_mem_ops =3D { - .supports_op =3D PTR_IF(IS_ENABLED(CONFIG_ACPI), cdns_xspi_supports_op), - .exec_op =3D marvell_xspi_mem_op_execute, - .adjust_op_size =3D cdns_xspi_adjust_mem_op_size, -}; - static irqreturn_t cdns_xspi_irq_handler(int this_irq, void *dev) { struct cdns_xspi_dev *cdns_xspi =3D dev; @@ -973,6 +749,230 @@ static void cdns_xspi_print_phy_config(struct cdns_xs= pi_dev *cdns_xspi) readl(cdns_xspi->auxbase + CDNS_XSPI_CCP_PHY_DLL_SLAVE_CTRL)); } =20 +static struct cdns_xspi_driver_data marvell_driver_data =3D { + .mrvl_hw_overlay =3D true, + .dll_phy_ctrl =3D MARVELL_REGS_DLL_PHY_CTRL, + .ctb_rfile_phy_ctrl =3D MARVELL_CTB_RFILE_PHY_CTRL, + .rfile_phy_tsel =3D MARVELL_RFILE_PHY_TSEL, + .rfile_phy_dq_timing =3D MARVELL_RFILE_PHY_DQ_TIMING, + .rfile_phy_dqs_timing =3D MARVELL_RFILE_PHY_DQS_TIMING, + .rfile_phy_gate_lpbk_ctrl =3D MARVELL_RFILE_PHY_GATE_LPBK_CTRL, + .rfile_phy_dll_master_ctrl =3D MARVELL_RFILE_PHY_DLL_MASTER_CTRL, + .rfile_phy_dll_slave_ctrl =3D MARVELL_RFILE_PHY_DLL_SLAVE_CTRL, +}; + +static const int cdns_mrvl_xspi_clk_div_list[] =3D { + 4, //0x0 =3D Divide by 4. SPI clock is 200 MHz. + 6, //0x1 =3D Divide by 6. SPI clock is 133.33 MHz. + 8, //0x2 =3D Divide by 8. SPI clock is 100 MHz. + 10, //0x3 =3D Divide by 10. SPI clock is 80 MHz. + 12, //0x4 =3D Divide by 12. SPI clock is 66.666 MHz. + 16, //0x5 =3D Divide by 16. SPI clock is 50 MHz. + 18, //0x6 =3D Divide by 18. SPI clock is 44.44 MHz. + 20, //0x7 =3D Divide by 20. SPI clock is 40 MHz. + 24, //0x8 =3D Divide by 24. SPI clock is 33.33 MHz. + 32, //0x9 =3D Divide by 32. SPI clock is 25 MHz. + 40, //0xA =3D Divide by 40. SPI clock is 20 MHz. + 50, //0xB =3D Divide by 50. SPI clock is 16 MHz. + 64, //0xC =3D Divide by 64. SPI clock is 12.5 MHz. + 128 //0xD =3D Divide by 128. SPI clock is 6.25 MHz. +}; + +static void cdns_xspi_reset_dll(struct cdns_xspi_dev *cdns_xspi) +{ + u32 dll_cntrl =3D readl(cdns_xspi->iobase + + CDNS_XSPI_RF_MINICTRL_REGS_DLL_PHY_CTRL); + + /* Reset DLL */ + dll_cntrl |=3D CDNS_XSPI_DLL_RST_N; + writel(dll_cntrl, cdns_xspi->iobase + + CDNS_XSPI_RF_MINICTRL_REGS_DLL_PHY_CTRL); +} + +static bool cdns_xspi_is_dll_locked(struct cdns_xspi_dev *cdns_xspi) +{ + u32 dll_lock; + + return !readl_relaxed_poll_timeout(cdns_xspi->iobase + + CDNS_XSPI_INTR_STATUS_REG, + dll_lock, ((dll_lock & CDNS_XSPI_DLL_LOCK) =3D=3D 1), 10, 10000); +} + +/* Static configuration of PHY */ +static bool cdns_xspi_configure_phy(struct cdns_xspi_dev *cdns_xspi) +{ + writel(cdns_xspi->driver_data->dll_phy_ctrl, + cdns_xspi->iobase + CDNS_XSPI_RF_MINICTRL_REGS_DLL_PHY_CTRL); + writel(cdns_xspi->driver_data->ctb_rfile_phy_ctrl, + cdns_xspi->auxbase + CDNS_XSPI_PHY_CTB_RFILE_PHY_CTRL); + writel(cdns_xspi->driver_data->rfile_phy_tsel, + cdns_xspi->auxbase + CDNS_XSPI_PHY_CTB_RFILE_PHY_TSEL); + writel(cdns_xspi->driver_data->rfile_phy_dq_timing, + cdns_xspi->auxbase + CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_DQ_TIMING); + writel(cdns_xspi->driver_data->rfile_phy_dqs_timing, + cdns_xspi->auxbase + CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_DQS_TIMING); + writel(cdns_xspi->driver_data->rfile_phy_gate_lpbk_ctrl, + cdns_xspi->auxbase + CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_GATE_LPBK_C= TRL); + writel(cdns_xspi->driver_data->rfile_phy_dll_master_ctrl, + cdns_xspi->auxbase + CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_DLL_MASTER_= CTRL); + writel(cdns_xspi->driver_data->rfile_phy_dll_slave_ctrl, + cdns_xspi->auxbase + CDNS_XSPI_PHY_DATASLICE_RFILE_PHY_DLL_SLAVE_C= TRL); + + cdns_xspi_reset_dll(cdns_xspi); + + return cdns_xspi_is_dll_locked(cdns_xspi); +} + +static bool cdns_mrvl_xspi_setup_clock(struct cdns_xspi_dev *cdns_xspi, + int requested_clk) +{ + int i =3D 0; + int clk_val; + u32 clk_reg; + bool update_clk =3D false; + + while (i < (ARRAY_SIZE(cdns_mrvl_xspi_clk_div_list) - 1)) { + clk_val =3D MRVL_XSPI_CLOCK_DIVIDED( + cdns_mrvl_xspi_clk_div_list[i]); + if (clk_val <=3D requested_clk) + break; + i++; + } + + dev_dbg(cdns_xspi->dev, "Found clk div: %d, clk val: %d\n", + cdns_mrvl_xspi_clk_div_list[i], + MRVL_XSPI_CLOCK_DIVIDED( + cdns_mrvl_xspi_clk_div_list[i])); + + clk_reg =3D readl(cdns_xspi->auxbase + MRVL_XSPI_CLK_CTRL_AUX_REG); + + if (FIELD_GET(MRVL_XSPI_CLK_DIV, clk_reg) !=3D i) { + clk_reg &=3D ~MRVL_XSPI_CLK_ENABLE; + writel(clk_reg, + cdns_xspi->auxbase + MRVL_XSPI_CLK_CTRL_AUX_REG); + clk_reg =3D FIELD_PREP(MRVL_XSPI_CLK_DIV, i); + FIELD_MODIFY(MRVL_XSPI_CLK_DIV, &clk_reg, i); + clk_reg |=3D MRVL_XSPI_CLK_ENABLE; + clk_reg |=3D MRVL_XSPI_IRQ_ENABLE; + update_clk =3D true; + } + + if (update_clk) + writel(clk_reg, + cdns_xspi->auxbase + MRVL_XSPI_CLK_CTRL_AUX_REG); + + return update_clk; +} + +static void marvell_xspi_set_interrupts(struct cdns_xspi_dev *cdns_xspi, + bool enabled) +{ + u32 intr_enable; + u32 irq_status; + + irq_status =3D readl(cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG); + writel(irq_status, cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG); + + intr_enable =3D readl(cdns_xspi->iobase + CDNS_XSPI_INTR_ENABLE_REG); + if (enabled) + intr_enable |=3D CDNS_XSPI_INTR_MASK; + else + intr_enable &=3D ~CDNS_XSPI_INTR_MASK; + writel(intr_enable, cdns_xspi->iobase + CDNS_XSPI_INTR_ENABLE_REG); +} + +static int marvell_xspi_mem_op_execute(struct spi_mem *mem, + const struct spi_mem_op *op) +{ + struct cdns_xspi_dev *cdns_xspi =3D + spi_controller_get_devdata(mem->spi->controller); + int ret =3D 0; + + cdns_mrvl_xspi_setup_clock(cdns_xspi, mem->spi->max_speed_hz); + + ret =3D cdns_xspi_mem_op(cdns_xspi, mem, op); + + return ret; +} + +static void m_ioreadq(void __iomem *addr, void *buf, int len) +{ + if (IS_ALIGNED((long)buf, 8) && len >=3D 8) { + u64 full_ops =3D len / 8; + u64 *buffer =3D buf; + + len -=3D full_ops * 8; + buf +=3D full_ops * 8; + + do { + u64 b =3D readq(addr); + *buffer++ =3D b; + } while (--full_ops); + } + + + while (len) { + u64 tmp_buf; + + tmp_buf =3D readq(addr); + memcpy(buf, &tmp_buf, min(len, 8)); + len =3D len > 8 ? len - 8 : 0; + buf +=3D 8; + } +} + +static void m_iowriteq(void __iomem *addr, const void *buf, int len) +{ + if (IS_ALIGNED((long)buf, 8) && len >=3D 8) { + u64 full_ops =3D len / 8; + const u64 *buffer =3D buf; + + len -=3D full_ops * 8; + buf +=3D full_ops * 8; + + do { + writeq(*buffer++, addr); + } while (--full_ops); + } + + while (len) { + u64 tmp_buf; + + memcpy(&tmp_buf, buf, min(len, 8)); + writeq(tmp_buf, addr); + len =3D len > 8 ? len - 8 : 0; + buf +=3D 8; + } +} + +static void marvell_xspi_sdma_handle(struct cdns_xspi_dev *cdns_xspi) +{ + u32 sdma_size, sdma_trd_info; + u8 sdma_dir; + + sdma_size =3D readl(cdns_xspi->iobase + CDNS_XSPI_SDMA_SIZE_REG); + sdma_trd_info =3D readl(cdns_xspi->iobase + CDNS_XSPI_SDMA_TRD_INFO_REG); + sdma_dir =3D FIELD_GET(CDNS_XSPI_SDMA_DIR, sdma_trd_info); + + switch (sdma_dir) { + case CDNS_XSPI_SDMA_DIR_READ: + m_ioreadq(cdns_xspi->sdmabase, + cdns_xspi->in_buffer, sdma_size); + break; + + case CDNS_XSPI_SDMA_DIR_WRITE: + m_iowriteq(cdns_xspi->sdmabase, + cdns_xspi->out_buffer, sdma_size); + break; + } +} + +static const struct spi_controller_mem_ops marvell_xspi_mem_ops =3D { + .supports_op =3D PTR_IF(IS_ENABLED(CONFIG_ACPI), cdns_xspi_supports_op), + .exec_op =3D marvell_xspi_mem_op_execute, + .adjust_op_size =3D cdns_xspi_adjust_mem_op_size, +}; + static int cdns_xspi_prepare_generic(int cs, const void *dout, int len, in= t glue, u32 *cmd_regs) { u8 *data =3D (u8 *)dout; @@ -1192,15 +1192,14 @@ static int cdns_xspi_probe(struct platform_device *= pdev) if (!cdns_xspi->driver_data) return -ENODEV; =20 + host->mem_ops =3D &cadence_xspi_mem_ops; + cdns_xspi->sdma_handler =3D &cdns_xspi_sdma_handle; + cdns_xspi->set_interrupts_handler =3D &cdns_xspi_set_interrupts; if (cdns_xspi->driver_data->mrvl_hw_overlay) { host->mem_ops =3D &marvell_xspi_mem_ops; host->transfer_one_message =3D cdns_xspi_transfer_one_message_b0; cdns_xspi->sdma_handler =3D &marvell_xspi_sdma_handle; cdns_xspi->set_interrupts_handler =3D &marvell_xspi_set_interrupts; - } else { - host->mem_ops =3D &cadence_xspi_mem_ops; - cdns_xspi->sdma_handler =3D &cdns_xspi_sdma_handle; - cdns_xspi->set_interrupts_handler =3D &cdns_xspi_set_interrupts; } host->bus_num =3D -1; =20 --=20 2.53.0 From nobody Fri Oct 2 08:24:47 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6EC6540EB81; Mon, 3 Aug 2026 14:27:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785767225; cv=none; b=jWKOrRwymPOVHd9z+fM0YdQrloWYnidl4d8RRVbVvGFscdxiZ8BVl8qYoCPTi3CVZqK7A/KZKV0RAC7BvMoC+O6BEqVnKo3TPXRXvPXqhVD7RQDZcuMPJJEDRKUmm7W46YOSWtlS6ohdJYRhohd+64UM5DWUrMsntFGX8xQ9WNI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785767225; c=relaxed/simple; bh=zmozbLU9vs783oHkMqBPJmyCBekvkPbhBI7ZT3KWNiE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=m9B5eDUKX18z4N5M27Pqnsc/vspHXWyfVfeatNcocm0B2GzvWRzml4qRVFrkJizXqhbGJ2knQTo8Y7jGIq5PjlDL9CkC9kbWqKccw/XctGT9XJRYI0iybvkiwNAVBaUeEeSeuS5gpmbCYtkJqwaIFf0BQBYiLsrHgxXxFPCKVjc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TdUY7Tj2; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TdUY7Tj2" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6857F1F000E9; Mon, 3 Aug 2026 14:27:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1785767224; bh=aD53Id0kbNiB4q+flkg2JQiI1EYQKieMCph/8OEkBAY=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=TdUY7Tj2auR+XtJPKasMf0xIQCUM2lIDYnypPALrHx2gf6qEcEFw+5efd3Y7MQBpS XWgsJClBP0jwniTkfE/NtsgMyWAI6+oFh4XfXu//qV0dmMSaUExxKZ0XbLyYPiO4h0 7lkVMYMRUXKXEjFcbZ8MiHJtL27P3lrD0GfF4nbBDPjBw3CqBCZcN8M/7JjUvflF6s YcKxMSgy9OaLgkuipCkStHmaPpMDwJ6yGgpHzKhqqG934GuN7burUxYs4yWyxfpGim CroMjaZnOUeBUjxyHnvGF6UwcXAWuoDHi8YzpGCpbNrw3QxagdKfvJsPWSdzEAdsDV pktTBAr3OmrBQ== From: Jisheng Zhang To: Mark Brown Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/4] spi: cadence-xspi: put marvell support code under CONFIG_64BIT Date: Mon, 3 Aug 2026 22:07:26 +0800 Message-ID: <20260803140728.12747-3-jszhang@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260803140728.12747-1-jszhang@kernel.org> References: <20260803140728.12747-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently, cadence-xspi depends on 64BIT. This dependency isn't from cadence xspi controller itself, but from marvell support code and 64bit slave dma interface performance optimization. Put marvell support code under CONFIG_64BIT to remove one reason of the 64BIT dependency. Signed-off-by: Jisheng Zhang --- drivers/spi/spi-cadence-xspi.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/spi/spi-cadence-xspi.c b/drivers/spi/spi-cadence-xspi.c index 19429b27875a..784619f17b40 100644 --- a/drivers/spi/spi-cadence-xspi.c +++ b/drivers/spi/spi-cadence-xspi.c @@ -749,6 +749,7 @@ static void cdns_xspi_print_phy_config(struct cdns_xspi= _dev *cdns_xspi) readl(cdns_xspi->auxbase + CDNS_XSPI_CCP_PHY_DLL_SLAVE_CTRL)); } =20 +#ifdef CONFIG_64BIT static struct cdns_xspi_driver_data marvell_driver_data =3D { .mrvl_hw_overlay =3D true, .dll_phy_ctrl =3D MARVELL_REGS_DLL_PHY_CTRL, @@ -1170,6 +1171,7 @@ static int cdns_xspi_transfer_one_message_b0(struct s= pi_controller *controller, =20 return 0; } +#endif =20 static int cdns_xspi_probe(struct platform_device *pdev) { @@ -1195,12 +1197,14 @@ static int cdns_xspi_probe(struct platform_device *= pdev) host->mem_ops =3D &cadence_xspi_mem_ops; cdns_xspi->sdma_handler =3D &cdns_xspi_sdma_handle; cdns_xspi->set_interrupts_handler =3D &cdns_xspi_set_interrupts; +#ifdef CONFIG_64BIT if (cdns_xspi->driver_data->mrvl_hw_overlay) { host->mem_ops =3D &marvell_xspi_mem_ops; host->transfer_one_message =3D cdns_xspi_transfer_one_message_b0; cdns_xspi->sdma_handler =3D &marvell_xspi_sdma_handle; cdns_xspi->set_interrupts_handler =3D &marvell_xspi_set_interrupts; } +#endif host->bus_num =3D -1; =20 platform_set_drvdata(pdev, cdns_xspi); @@ -1246,6 +1250,7 @@ static int cdns_xspi_probe(struct platform_device *pd= ev) } } =20 +#ifdef CONFIG_64BIT if (cdns_xspi->driver_data->mrvl_hw_overlay) { cdns_xspi->xferbase =3D devm_platform_ioremap_resource_byname(pdev, "xfe= r"); if (IS_ERR(cdns_xspi->xferbase)) { @@ -1257,6 +1262,7 @@ static int cdns_xspi_probe(struct platform_device *pd= ev) } } } +#endif =20 cdns_xspi->irq =3D platform_get_irq(pdev, 0); if (cdns_xspi->irq < 0) @@ -1269,10 +1275,12 @@ static int cdns_xspi_probe(struct platform_device *= pdev) return ret; } =20 +#ifdef CONFIG_64BIT if (cdns_xspi->driver_data->mrvl_hw_overlay) { cdns_mrvl_xspi_setup_clock(cdns_xspi, MRVL_DEFAULT_CLK); cdns_xspi_configure_phy(cdns_xspi); } +#endif =20 cdns_xspi_print_phy_config(cdns_xspi); =20 @@ -1306,10 +1314,12 @@ static int cdns_xspi_resume(struct device *dev) { struct cdns_xspi_dev *cdns_xspi =3D dev_get_drvdata(dev); =20 +#ifdef CONFIG_64BIT if (cdns_xspi->driver_data->mrvl_hw_overlay) { cdns_mrvl_xspi_setup_clock(cdns_xspi, MRVL_DEFAULT_CLK); cdns_xspi_configure_phy(cdns_xspi); } +#endif =20 cdns_xspi->set_interrupts_handler(cdns_xspi, false); =20 @@ -1324,10 +1334,12 @@ static const struct of_device_id cdns_xspi_of_match= [] =3D { .compatible =3D "cdns,xspi-nor", .data =3D &cdns_driver_data, }, +#ifdef CONFIG_64BIT { .compatible =3D "marvell,cn10-xspi-nor", .data =3D &marvell_driver_data, }, +#endif { /* end of table */} }; MODULE_DEVICE_TABLE(of, cdns_xspi_of_match); --=20 2.53.0 From nobody Fri Oct 2 08:24:47 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 89E4340F751; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="imWpEIu9" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 821CB1F00A3F; Mon, 3 Aug 2026 14:27:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1785767225; bh=6uD6QEkytfnVGllMV/alSAyNpq5AY0njMQmDldmoj+o=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=imWpEIu9ICb2G4HuNAmmxDo8Fm4Z1R7p0Y0vKZByZZndT5hvqchLa56bW3iRXLQag GYz35+7a8SKSEED7iiHJLJTsAloCRSQChPeKD1CQqK2XzmFj4EV8lu8AFkMrZYE7q7 yATCpnnKqHOIfyYpNBMxg0n0SDEcoDhnnNoQPiA/L+k8QYgFgA7xNBRCWqzX8nreyR B15DvFAvSIcHfpIFjXj/gdzywOufYikVWumadOIBGcZvzAdAgJ538pgQH4+AL2ZVPq Q2LnqQLbTjncl/W7N/zGPJLXqPFaU+a6tDAQKgot6Iftq1mgSAzEGSm5geJFTGOHhA XPePSS63qqG3g== From: Jisheng Zhang To: Mark Brown Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/4] spi: cadence-xspi: only use readsq/writesq under 64BIT Date: Mon, 3 Aug 2026 22:07:27 +0800 Message-ID: <20260803140728.12747-4-jszhang@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260803140728.12747-1-jszhang@kernel.org> References: <20260803140728.12747-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently, cadence-xspi depends on 64BIT. This dependency isn't from cadence xspi controller itself, but from marvell support code and 64bit slave dma interface performance optimization. readsq and writesq are only available under 64BIT. For 32BIT platforms, we can fallback to ioread32_rep/iowrite32_rep. So we can remove another reason of the 64BIT dependency. Signed-off-by: Jisheng Zhang --- drivers/spi/spi-cadence-xspi.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-cadence-xspi.c b/drivers/spi/spi-cadence-xspi.c index 784619f17b40..39c868a5b171 100644 --- a/drivers/spi/spi-cadence-xspi.c +++ b/drivers/spi/spi-cadence-xspi.c @@ -454,18 +454,20 @@ static inline void cdns_xspi_sdma_read(struct cdns_xs= pi_dev *cdns_xspi, size_t l void *buf =3D cdns_xspi->in_buffer; size_t offset =3D 0; =20 - if (cdns_xspi->dma_data_width =3D=3D 4) { + if (!IS_ENABLED(CONFIG_64BIT) || cdns_xspi->dma_data_width =3D=3D 4) { if (IS_ALIGNED((uintptr_t)src, 4) && IS_ALIGNED((uintptr_t)buf, 4)) { ioread32_rep(src, buf, len >> 2); offset =3D len & ~0x3; len -=3D offset; } +#ifdef CONFIG_64BIT } else { if (IS_ALIGNED((uintptr_t)src, 8) && IS_ALIGNED((uintptr_t)buf, 8)) { readsq(src, buf, len >> 3); offset =3D len & ~0x7; len -=3D offset; } +#endif } ioread8_rep(src, (u8 *)buf + offset, len); } @@ -476,18 +478,20 @@ static inline void cdns_xspi_sdma_write(struct cdns_x= spi_dev *cdns_xspi, size_t const void *buf =3D cdns_xspi->out_buffer; size_t offset =3D 0; =20 - if (cdns_xspi->dma_data_width =3D=3D 4) { + if (!IS_ENABLED(CONFIG_64BIT) || cdns_xspi->dma_data_width =3D=3D 4) { if (IS_ALIGNED((uintptr_t)dst, 4) && IS_ALIGNED((uintptr_t)buf, 4)) { iowrite32_rep(dst, buf, len >> 2); offset =3D len & ~0x3; len -=3D offset; } +#ifdef CONFIG_64BIT } else { if (IS_ALIGNED((uintptr_t)dst, 8) && IS_ALIGNED((uintptr_t)buf, 8)) { writesq(dst, buf, len >> 3); offset =3D len & ~0x7; len -=3D offset; } +#endif } iowrite8_rep(dst, (const u8 *)buf + offset, len); } --=20 2.53.0 From nobody Fri Oct 2 08:24:47 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 30A2B41A93A; Mon, 3 Aug 2026 14:27:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785767228; cv=none; b=ZcrqWjbYZTUZkQtGy5CB0GssCpwMRsLyYGnUtrSQWuSZfWOgwIWyw+imVsYfBkqKPayxI8+pjhry3lyJwW8CqwlBrQDiHDHgsdQ/aS86zX5yWH9fqrT8HlpHor1t7NxrYn5nOFCEnObHPdvh70QbxGslUubaY8rTp8jrqjdnq4o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785767228; c=relaxed/simple; bh=YtUjK2t6V1+fOLlxYatYTj2nwVl8W5O/qyi5DneuEto=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hTV6okz01w6mq0B+chq6+gCTkC/08UL+o73njFFQ07KjJlX6zNXM+XjOMLQm5Dv3AcVuH2kugyVYm4JavlDLSAQQIFPwGpZ3UKcddkv7hoZX0JO7kzXsgG7p7zZlyvD/0PW1tVYP7djnHtoMUnF9NO8UFK3Czhl8SopyZCTLJvk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=myQ8NEcr; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="myQ8NEcr" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9B51A1F00A3D; Mon, 3 Aug 2026 14:27:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1785767227; bh=lA2uaonlGGEnsffT43uMEYcrS5+hPlWlCaa1MynRySg=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=myQ8NEcrYInS1nRLoIZ+zjbog11Og1HYlztU4l71COV9PIA7falKI5+5Z8cmP7gQP aYXoaTiVrAmlT406kfioPCAwl6XyJzwYSD7Cou3n+cnHD9s21F7KviyuN5lk1HI2JI yRBd2BTUwEKR1Vin74LJtIAYBO7QSjpjYqDPHn2b5U42ozmHmgiqf3+u7q4rtNyZ7s N73jUe24d/1T47iDt0uZTMlaFi2X1Z0V6KDOJ2eQU9QlFDwkMUn9zMDIo9onV2IbS0 tycIaSkFudX57e6Pkx/jBtY2OC56CiAddrHIdHqVGcCLAHsAuzU/govFhJLXh9w+xO gojaVuQQ3QC2Q== From: Jisheng Zhang To: Mark Brown Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/4] spi: cadence-xspi: remove 64BIT Kconfig dependency Date: Mon, 3 Aug 2026 22:07:28 +0800 Message-ID: <20260803140728.12747-5-jszhang@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260803140728.12747-1-jszhang@kernel.org> References: <20260803140728.12747-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now everything is ready, we can remove 64BIT Kconfig dependency now. Signed-off-by: Jisheng Zhang --- drivers/spi/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 8782514bb89b..601bfa321adb 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -321,7 +321,7 @@ config SPI_CADENCE_QUADSPI =20 config SPI_CADENCE_XSPI tristate "Cadence XSPI controller" - depends on OF && HAS_IOMEM && 64BIT + depends on OF && HAS_IOMEM depends on SPI_MEM help Enable support for the Cadence XSPI Flash controller. --=20 2.53.0