From nobody Fri Oct 2 08:26:23 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 23AF440DB47 for ; Mon, 3 Aug 2026 13:09:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785762567; cv=none; b=MwfjBpxbegxECYZLc0Da2iE5qCiDkWqIK8xKt2JazUg3yREiZ99nDArWX9JSdEOn9n38oIelwAFzXcXmmncjWw1o2NG7004N1vlJsxPOWd5XQM+kXEXjRW1em3VL3PhUlN95Pz5oLnIjoTePMPJ5IRCxE6eKk7Sc5YkhsAFb1/M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785762567; c=relaxed/simple; bh=SqDX++W5SqSo7JukB7+qWbbJ3Rzm1LMAD2Gvp8Zc0R4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=eXdkogm03xpFOZM9ojKzK/lDAthwYUf5ZEJsu3WVljhRJOeLkoK/TyiUC2cS5DyPLr07wHZXwODZMSlM48ZqHQNwECbr1pFOMWlUztvf2ermaElzlyMe7rNEYai5Li/mwVelXhx1oSmLfpnWyG3sYZ4ikFVyZnUcbFk9VPNwu18= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=oCBCoton; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=ib5AfV56; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="oCBCoton"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="ib5AfV56" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 673C4Tg11722014 for ; Mon, 3 Aug 2026 13:09:24 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=HyrK3/fBxvW uXnvSyn5+qD0hj9Y2OHr93c8zvV4OBC4=; b=oCBCotonzdYROegHoxbanmjJ9iP v8WzGzmEt52Z+fhNA5DUWBWKxFvaM296RKuhvYW+2f6Z3g+WJSfpc2uVSayQep7V MC9lq5Toz6wmXrCTEVf0cnju9BAdWM9RiV50TBmM1Sqa+xRTyzjvClfnC3oODbye Sx8t68dbvBCQFXvIhzB9lx3R/k2FItrcUyoZYqDseT+FLYq5wmpGPygNYxI8BDcv m7k8x/uvMy5nEb5wAVbLAYaq+5fvfvlBmHOnkEzJ5nGIVLtcVoIzZEv2MN3DXNig zLtZmAXPsdE1VaEfR6toE8WjzmcV1jhEBbd1Bo/fe2b5w3b997lXJkva8ag== Received: from mail-ot1-f71.google.com (mail-ot1-f71.google.com [209.85.210.71]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ft9faka41-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 03 Aug 2026 13:09:24 +0000 (GMT) Received: by mail-ot1-f71.google.com with SMTP id 46e09a7af769-7e7624e584dso4337497a34.2 for ; Mon, 03 Aug 2026 06:09:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1785762563; x=1786367363; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=HyrK3/fBxvWuXnvSyn5+qD0hj9Y2OHr93c8zvV4OBC4=; b=ib5AfV561S5EsOYqu3yO1KKR+PeFv1lMJhySupAKJuvokAcYptLh6Q/jQTi8WeZgHp frqP8Z1PgcK2cdewzHzyiMkDb3X+slhOu9CZvUAyfWM3zEqHh0qbIqaNGj0Dh4CzcmzC 03nKGTWz6vAN+fTAmovzc0SteYT24/SlXBynDxrdJL0ODhHXxsDZiVQoloEp4A8NjhHy NTRgR//4PBt+VV4gtu66RUgk3C3BCxJYkXoaqzHPhhfyKV6yavpbk0Ru2s712Xr/4yto GeRyymRi5Z6gggqvMxg7srdb+03ZJWCZ1hm6+Yrie6YUZxsvCUxVeCo+j5JDfiqpdBfk 85gQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1785762563; x=1786367363; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=HyrK3/fBxvWuXnvSyn5+qD0hj9Y2OHr93c8zvV4OBC4=; b=PAL9CjJ0OUuxuXK67YV1lwOV6AJBuyH6mY09F8W8xu42ocQSOisUXVH01AMcaKd5Y4 659iW7FzfkfWSJUDI0CDC8gjDqr6j2slUw8hU0/Lj7m5VzJ73R/PPgIztAsvLGjsKd+3 dd+W/PFKTPiBveqRJlgJCrjodxvVBdfxqXY6h20jgVmaxplZMdqbuDM8Vvgxp4ZK8fYv qxCze9wmytzD8o2iSyJ6qbl2LuwLyxDLLoOkzXX92Q6btwPA/cqEY4Q9zLvdwbDngMZI AZOl0Gs/cUFewwLMUHxuPrY7xWA994PLRcbNsRU+PlTYx60q+fpuejm4EwhzAnU8LlMR hVlg== X-Forwarded-Encrypted: i=1; AHgh+Rq/TaXVz/nM4T9bZxcoVCGVoz1duMUa+B0+nEOCuQgA5sIs9tZIzppSM7xIV02aml6cfDf7SoupBfpjheA=@vger.kernel.org X-Gm-Message-State: AOJu0Yy5LaKA2hW2+ZlThYOEBbzRHOir95pX/e8UNIYuAP2F4GdRmxJ8 VG7xVKPUBCSjXLdRb4m/0V5MD4CG2ebB19eg0IBg5ZIHjIcaV56T9nvFWUoLo//tdGvdY98OP7p JMXmwIgP6P36wgh/z8gkamFQKDe+Z8KsCLZYhqqGAFDu+ZwZX5rP5VEHMsCdqHn0BVXw= X-Gm-Gg: AR+sD13LWa/+jWARnpG9UGQ01av7Q/F0XKkt7kRw3Hb7n/X7sGWOOmm5zBozGV62i7L Ei6cZ+qCIqjBxR/l37zuFO0ekk9KcwR6tQM76P9400HQ97PRhlit7mT6oNZp1uvYYIw3WxHBTms yO4IMiuxff8WqzUvtZbA05tYsv+dV2H3P/HMBFwXzzebZJYOfgwrIUxLH6n0st2pZfdkpMGqP7K I1RzvdF2ovQRdyNSN8rH5wPEuTiJE3h5XUy0/500V4iNG61v2A+AwAIh+7fg2E39S+KGzlAQiRo U0P+JBBSE/dTIRUlL+Fp8MrFfbvAB2ykQQqVjtkeM3TtRkEq9SO//dJ754YBhc+xuNDaPFjk9gw pYppR8fk6FVLFRKfBOQBEbKSQcS+CkvFQ X-Received: by 2002:a05:6830:2a8b:b0:7e9:cd7a:7c34 with SMTP id 46e09a7af769-7f196d7d3d1mr16575393a34.10.1785762558477; Mon, 03 Aug 2026 06:09:18 -0700 (PDT) X-Received: by 2002:a05:6830:2a8b:b0:7e9:cd7a:7c34 with SMTP id 46e09a7af769-7f196d7d3d1mr16574514a34.10.1785762553231; Mon, 03 Aug 2026 06:09:13 -0700 (PDT) Received: from hu-pkambar-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7f18f0d6ef6sm7366929a34.21.2026.08.03.06.09.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 06:09:12 -0700 (PDT) From: palash.kambar@oss.qualcomm.com To: vkoul@kernel.org, neil.armstrong@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mani@kernel.org, alim.akhtar@samsung.com, bvanassche@acm.org, andersson@kernel.org, dmitry.baryshkov@oss.qualcomm.com, abel.vesa@oss.qualcomm.com, luca.weiss@fairphone.com Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, nitin.rawat@oss.qualcomm.com, Palash Kambar Subject: [PATCH v5 1/2] phy: qcom-qmp-ufs: Add UFS PHY support on Hawi Date: Mon, 3 Aug 2026 18:38:51 +0530 Message-Id: <20260803130852.1432714-2-palash.kambar@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260803130852.1432714-1-palash.kambar@oss.qualcomm.com> References: <20260803130852.1432714-1-palash.kambar@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=PZPPQChd c=1 sm=1 tr=0 ts=6a709304 cx=c_pps a=OI0sxtj7PyCX9F1bxD/puw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=C2KyqtCk6L2573COy70A:9 a=Z1Yy7GAxqfX1iEi80vsk:22 X-Proofpoint-GUID: DW8je5B-3R-PccidSlMl5Bb4EMm1_SNZ X-Proofpoint-Spam-Info: AW1haW4tMjYwODAzMDExOCBTYWx0ZWRfX/hCiOYVd74of +w2RWt65tVpW4e4GRj438lR146YZ/cA2h3SKRhKrzuOOC3qUqItqpPybTo8AA2geoYXnNJRKgCB +YgUUavv/ywbBv1GrqE6QCLeZZ3ROcY= X-Proofpoint-ORIG-GUID: DW8je5B-3R-PccidSlMl5Bb4EMm1_SNZ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODAzMDExOCBTYWx0ZWRfX0uL2KtH1jK17 hLlFz8BfTe5IP24EhZjzQ3nqNES0u5bVPR2xvB0tpC1tiAf+Zj+A1W2ssFmhz4CP2wXA6ShzfCu tmqfS/vJg9O3ScnIJTdw+00y+xsBM1Sx/i+83FVRBGp0AnNQDOR2RDteknW2c7v319xNcp+sw9v Qqt9Zrdwmrx62BTbr4xWzgijeobVyRZREej9G449XnNRjj+rWhrHuYjz1zf3c+nOusqchMQ8gtH fjS+P1ZrRdh8tPHPPYq1oZH/VlSFIBI+tfbg6Y01AuxDvZgITqdcdCPYUz8MYocGuxs2cttXJaH LFUU067iV0QIEu9ENZqmqbhqNe0xT21ixxhKN3DKaNDnghId34yzMi5lU1LD58P5y+/qYjs2aKT JLgBNSJ872iFAYCE/UeZrgAAF8m0eRI1z8kvypv2ZUVv5QHjBbUJZnKM1zTU9NRx1oNoSYQT8X4 brpK/td2NOdblJPgutQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-03_03,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 spamscore=0 clxscore=1015 adultscore=0 suspectscore=0 malwarescore=0 impostorscore=0 bulkscore=0 phishscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608030118 Content-Type: text/plain; charset="utf-8" From: Palash Kambar Add the init sequence tables and config for the UFS QMP phy found in the Hawi SoC. Reviewed-by: Manivannan Sadhasivam Reviewed-by: Dmitry Baryshkov Signed-off-by: Palash Kambar Reviewed-by: Abel Vesa --- .../phy/qualcomm/phy-qcom-qmp-pcs-ufs-v7.h | 24 +++ .../qualcomm/phy-qcom-qmp-qserdes-com-v8.h | 13 +- .../phy-qcom-qmp-qserdes-txrx-ufs-v8.h | 37 +++++ drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 139 ++++++++++++++++++ 4 files changed, 212 insertions(+), 1 deletion(-) create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v7.h create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v8.h diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v7.h b/drivers/phy/q= ualcomm/phy-qcom-qmp-pcs-ufs-v7.h new file mode 100644 index 000000000000..e80d3dd6a190 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v7.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2026, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_UFS_V7_H_ +#define QCOM_PHY_QMP_PCS_UFS_V7_H_ + +/* Only for QMP V7 PHY - UFS PCS registers */ +#define QPHY_V7_PCS_UFS_PHY_START 0x000 +#define QPHY_V7_PCS_UFS_POWER_DOWN_CONTROL 0x004 +#define QPHY_V7_PCS_UFS_SW_RESET 0x008 +#define QPHY_V7_PCS_UFS_PCS_CTRL1 0x01C +#define QPHY_V7_PCS_UFS_PLL_CNTL 0x028 +#define QPHY_V7_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x02C +#define QPHY_V7_PCS_UFS_TX_HSGEAR_CAPABILITY 0x060 +#define QPHY_V7_PCS_UFS_RX_HSGEAR_CAPABILITY 0x094 +#define QPHY_V7_PCS_UFS_LINECFG_DISABLE 0x140 +#define QPHY_V7_PCS_UFS_RX_SIGDET_CTRL2 0x150 +#define QPHY_V7_PCS_UFS_READY_STATUS 0x16c +#define QPHY_V7_PCS_UFS_TX_MID_TERM_CTRL1 0x1b8 +#define QPHY_V7_PCS_UFS_MULTI_LANE_CTRL1 0x1c0 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v8.h b/drivers/p= hy/qualcomm/phy-qcom-qmp-qserdes-com-v8.h index d8ac4c4a2c31..d416113bcb3c 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v8.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v8.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2026, The Linux Foundation. All rights reserved. */ =20 #ifndef QCOM_PHY_QMP_QSERDES_COM_V8_H_ @@ -71,5 +71,16 @@ #define QSERDES_V8_COM_ADDITIONAL_MISC 0x1b4 #define QSERDES_V8_COM_CMN_STATUS 0x2c8 #define QSERDES_V8_COM_C_READY_STATUS 0x2f0 +#define QSERDES_V8_COM_PLL_IVCO_MODE1 0xf8 +#define QSERDES_V8_COM_CMN_IETRIM 0xfc +#define QSERDES_V8_COM_CMN_IPTRIM 0x100 +#define QSERDES_V8_COM_VCO_TUNE_CTRL 0x13c +#define QSERDES_V8_COM_ADAPTIVE_ANALOG_CONFIG 0x268 +#define QSERDES_V8_COM_CP_CTRL_ADAPTIVE_MODE0 0x26c +#define QSERDES_V8_COM_PLL_RCCTRL_ADAPTIVE_MODE0 0x270 +#define QSERDES_V8_COM_PLL_CCTRL_ADAPTIVE_MODE0 0x274 +#define QSERDES_V8_COM_CP_CTRL_ADAPTIVE_MODE1 0x278 +#define QSERDES_V8_COM_PLL_RCCTRL_ADAPTIVE_MODE1 0x27c +#define QSERDES_V8_COM_PLL_CCTRL_ADAPTIVE_MODE1 0x280 =20 #endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v8.h b/driv= ers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v8.h new file mode 100644 index 000000000000..5f923c3e64ec --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v8.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2026, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_QSERDES_TXRX_UFS_V8_H_ +#define QCOM_PHY_QMP_QSERDES_TXRX_UFS_V8_H_ + +#define QSERDES_UFS_V8_TX_RES_CODE_LANE_OFFSET_TX (0x34) +#define QSERDES_UFS_V8_TX_RES_CODE_LANE_OFFSET_RX (0x38) +#define QSERDES_UFS_V8_TX_LANE_MODE_1 (0x80) +#define QSERDES_UFS_V8_RX_UCDR_FO_GAIN_RATE2 (0x1BC) +#define QSERDES_UFS_V8_RX_UCDR_FO_GAIN_RATE4 (0x1C4) +#define QSERDES_UFS_V8_RX_UCDR_SO_GAIN_RATE4 (0x1DC) +#define QSERDES_UFS_V8_RX_EQ_OFFSET_ADAPTOR_CNTRL1 (0x2C8) +#define QSERDES_UFS_V8_RX_UCDR_PI_CONTROLS (0x1E4) +#define QSERDES_UFS_V8_RX_OFFSET_ADAPTOR_CNTRL3 (0x2D0) +#define QSERDES_UFS_V8_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 (0x120) +#define QSERDES_UFS_V8_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 (0xD4) +#define QSERDES_UFS_V8_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 (0xEC) +#define QSERDES_UFS_V8_RX_VGA_CAL_MAN_VAL (0x288) +#define QSERDES_UFS_V8_RX_EQU_ADAPTOR_CNTRL4 (0x2B0) +#define QSERDES_UFS_V8_RX_MODE_RATE_0_1_B4 (0x324) +#define QSERDES_UFS_V8_RX_MODE_RATE4_SA_B7 (0x3B4) +#define QSERDES_UFS_V8_RX_MODE_RATE4_SA_B9 (0x3BC) +#define QSERDES_UFS_V8_RX_MODE_RATE4_SB_B7 (0x3E0) +#define QSERDES_UFS_V8_RX_MODE_RATE4_SB_B9 (0x3E8) +#define QSERDES_UFS_V8_RX_MODE_RATE5_SA_B7 (0x40C) +#define QSERDES_UFS_V8_RX_MODE_RATE5_SA_B9 (0x414) +#define QSERDES_UFS_V8_RX_MODE_RATE5_SB_B7 (0x438) +#define QSERDES_UFS_V8_RX_MODE_RATE5_SB_B9 (0x440) +#define QSERDES_UFS_V8_RX_UCDR_SO_SATURATION (0xF4) +#define QSERDES_UFS_V8_RX_TERM_BW_CTRL0 (0x1AC) +#define QSERDES_UFS_V8_RX_DLL0_FTUNE_CTRL (0x498) +#define QSERDES_UFS_V8_RX_SIGDET_CAL_TRIM (0x4d0) + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 0f4ad24aa405..d4aca22c181e 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -29,9 +29,11 @@ #include "phy-qcom-qmp-pcs-ufs-v4.h" #include "phy-qcom-qmp-pcs-ufs-v5.h" #include "phy-qcom-qmp-pcs-ufs-v6.h" +#include "phy-qcom-qmp-pcs-ufs-v7.h" =20 #include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h" #include "phy-qcom-qmp-qserdes-txrx-ufs-v7.h" +#include "phy-qcom-qmp-qserdes-txrx-ufs-v8.h" =20 /* QPHY_PCS_READY_STATUS bit */ #define PCS_READY BIT(0) @@ -84,6 +86,13 @@ static const unsigned int ufsphy_v6_regs_layout[QPHY_LAY= OUT_SIZE] =3D { [QPHY_PCS_POWER_DOWN_CONTROL] =3D QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL, }; =20 +static const unsigned int ufsphy_v7_regs_layout[QPHY_LAYOUT_SIZE] =3D { + [QPHY_START_CTRL] =3D QPHY_V7_PCS_UFS_PHY_START, + [QPHY_PCS_READY_STATUS] =3D QPHY_V7_PCS_UFS_READY_STATUS, + [QPHY_SW_RESET] =3D QPHY_V7_PCS_UFS_SW_RESET, + [QPHY_PCS_POWER_DOWN_CONTROL] =3D QPHY_V7_PCS_UFS_POWER_DOWN_CONTROL, +}; + static const struct qmp_phy_init_tbl milos_ufsphy_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9), QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), @@ -1307,6 +1316,11 @@ static const struct regulator_bulk_data sm8750_ufsph= y_vreg_l[] =3D { { .supply =3D "vdda-pll", .init_load_uA =3D 18300 }, }; =20 +static const struct regulator_bulk_data hawi_ufsphy_vreg_l[] =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 324000 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 27000 }, +}; + static const struct qmp_ufs_offsets qmp_ufs_offsets =3D { .serdes =3D 0, .pcs =3D 0xc00, @@ -1325,6 +1339,15 @@ static const struct qmp_ufs_offsets qmp_ufs_offsets_= v6 =3D { .rx2 =3D 0x1a00, }; =20 +static const struct qmp_ufs_offsets qmp_ufs_offsets_v7 =3D { + .serdes =3D 0, + .pcs =3D 0x0400, + .tx =3D 0x2000, + .rx =3D 0x2000, + .tx2 =3D 0x3000, + .rx2 =3D 0x3000, +}; + static const struct qmp_phy_cfg milos_ufsphy_cfg =3D { .lanes =3D 2, =20 @@ -1845,6 +1868,119 @@ static const struct qmp_phy_cfg sm8750_ufsphy_cfg = =3D { =20 }; =20 +static const struct qmp_phy_init_tbl hawi_ufsphy_serdes[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V8_COM_SYSCLK_EN_SEL, 0xd9), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_CMN_CONFIG_1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_HSCLK_SEL_1, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP_EN, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP_CFG, 0x60), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_IVCO, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_IVCO_MODE1, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_CMN_IETRIM, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_CMN_IPTRIM, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE_MAP, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE_CTRL, 0x40), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_ADAPTIVE_ANALOG_CONFIG, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MODE0, 0x41), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCTRL_MODE0, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_MODE0, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_ADAPTIVE_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCCTRL_ADAPTIVE_MODE0, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_ADAPTIVE_MODE0, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP1_MODE0, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP2_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x92), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MODE1, 0x4c), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_MODE1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCTRL_MODE1, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_MODE1, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_ADAPTIVE_MODE1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCCTRL_ADAPTIVE_MODE1, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_ADAPTIVE_MODE1, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP1_MODE1, 0x99), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP2_MODE1, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xbe), + QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), +}; + +static const struct qmp_phy_init_tbl hawi_ufsphy_tx[] =3D { + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_TX_LANE_MODE_1, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_TX_RES_CODE_LANE_OFFSET_TX, 0x07), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_TX_RES_CODE_LANE_OFFSET_RX, 0x17), +}; + +static const struct qmp_phy_init_tbl hawi_ufsphy_rx[] =3D { + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_UCDR_FO_GAIN_RATE2, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_UCDR_FO_GAIN_RATE4, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_UCDR_SO_GAIN_RATE4, 0x04), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_UCDR_PI_CONTROLS, 0x07), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_VGA_CAL_MAN_VAL, 0x8e), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_EQU_ADAPTOR_CNTRL4, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE_0_1_B4, 0xb8), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE4_SA_B7, 0x66), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE4_SA_B9, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE4_SB_B7, 0x66), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE4_SB_B9, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE5_SA_B7, 0x66), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE5_SA_B9, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE5_SB_B7, 0x66), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE5_SB_B9, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_UCDR_SO_SATURATION, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_TERM_BW_CTRL0, 0xfa), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_DLL0_FTUNE_CTRL, 0x30), + QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_SIGDET_CAL_TRIM, 0x77), +}; + +static const struct qmp_phy_init_tbl hawi_ufsphy_pcs[] =3D { + QMP_PHY_INIT_CFG(QPHY_V7_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), + QMP_PHY_INIT_CFG(QPHY_V7_PCS_UFS_PCS_CTRL1, 0x42), + QMP_PHY_INIT_CFG(QPHY_V7_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f), + QMP_PHY_INIT_CFG(QPHY_V7_PCS_UFS_RX_SIGDET_CTRL2, 0x68), + QMP_PHY_INIT_CFG(QPHY_V7_PCS_UFS_MULTI_LANE_CTRL1, 0x02), +}; + +static const struct qmp_phy_init_tbl hawi_ufsphy_g5_pcs[] =3D { + QMP_PHY_INIT_CFG(QPHY_V7_PCS_UFS_PLL_CNTL, 0x3b), + QMP_PHY_INIT_CFG(QPHY_V7_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x05), + QMP_PHY_INIT_CFG(QPHY_V7_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x05), +}; + +static const struct qmp_phy_cfg hawi_ufsphy_cfg =3D { + .lanes =3D 2, + + .offsets =3D &qmp_ufs_offsets_v7, + .max_supported_gear =3D UFS_HS_G5, + + .tbls =3D { + .serdes =3D hawi_ufsphy_serdes, + .serdes_num =3D ARRAY_SIZE(hawi_ufsphy_serdes), + .tx =3D hawi_ufsphy_tx, + .tx_num =3D ARRAY_SIZE(hawi_ufsphy_tx), + .rx =3D hawi_ufsphy_rx, + .rx_num =3D ARRAY_SIZE(hawi_ufsphy_rx), + .pcs =3D hawi_ufsphy_pcs, + .pcs_num =3D ARRAY_SIZE(hawi_ufsphy_pcs), + }, + + .tbls_hs_overlay[0] =3D { + .pcs =3D hawi_ufsphy_g5_pcs, + .pcs_num =3D ARRAY_SIZE(hawi_ufsphy_g5_pcs), + .max_gear =3D UFS_HS_G5, + }, + + .vreg_list =3D hawi_ufsphy_vreg_l, + .num_vregs =3D ARRAY_SIZE(hawi_ufsphy_vreg_l), + .regs =3D ufsphy_v7_regs_layout, +}; + static void qmp_ufs_serdes_init(struct qmp_ufs *qmp, const struct qmp_phy_= cfg_tbls *tbls) { void __iomem *serdes =3D qmp->serdes; @@ -2259,6 +2395,9 @@ static int qmp_ufs_probe(struct platform_device *pdev) =20 static const struct of_device_id qmp_ufs_of_match_table[] =3D { { + .compatible =3D "qcom,hawi-qmp-ufs-phy", + .data =3D &hawi_ufsphy_cfg, + }, { .compatible =3D "qcom,milos-qmp-ufs-phy", .data =3D &milos_ufsphy_cfg, }, { --=20 2.34.1 From nobody Fri Oct 2 08:26:23 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 019A2259498 for ; Mon, 3 Aug 2026 13:09:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785762565; cv=none; b=CdS0xBeiPXVR7VXZMuKdIdkfkDYl9EC83iH44GpDtWjIF02Ur7thOZ0OJYgfZV4M9FFoy7jqEqbsWivNyCvrcC91nqOERBOO/cMRvorcrtwPPYRhDGpzd95ksSBwXyS/psU59r/Y0KPxRnNtv2XjJj5PKcVcIikpyYVb+dJr16w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785762565; c=relaxed/simple; bh=Ao4k8UCAQ63pTsAXW+nwl6jaANXflQZYV4NF+HzDpas=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=R4Rv7Am2j4B2w9d7fXciVF1UcG6f5JjxkQ4EWxMZYJCLCfDZj3He1QfzXHjjei3Sgn+6w3Ista2KoR1yeMVSiClxbV+hwIkpBpVoruoZ2c/kNSLcR2Mb9viut8PzKtzqqIulrohnFQIbNcD8PEptWX6TVX6O1+9oZtoC5HPAroI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=Q4zX++W4; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=jy+PMJME; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="Q4zX++W4"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="jy+PMJME" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 673C4d17344373 for ; Mon, 3 Aug 2026 13:09:22 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=Tx+tU+JavHm 9jlJKkOPRaMWM/yiGuddWBQeSbrpsom8=; b=Q4zX++W4DpOC2XJ2Hlyk3E51ssf KnA9bGQ8/Ln7WojVcwbba25OUr5BVB5g1WRiKiqyXbd/KN8uEJ0Q2Md/1SIUMK6A o1G9c753HmMVSfdebN0C3x9v/+xDVrlgqyujKQRKjVnJBna50s5Ho+qZRROFPGZM KRaAqlLBbaP1YQZ7OhSoz30tnEZGctYYa0LJphUYVrvMdx9oiGICqQJ4OPywV2sS e3ej0EWkdyVe7gmP7OmOvPH7WCRDZECSaFvgKhHRQNvbihYn5U3S+MNOge1J1ewq 71OkQSjm9NDh/H6NwfYoUDQiyyzuFPWMzcK1+Gw0xTTpBhn69cLs0jpoGwQ== Received: from mail-ot1-f72.google.com (mail-ot1-f72.google.com [209.85.210.72]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ftp4r1j4r-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 03 Aug 2026 13:09:22 +0000 (GMT) Received: by mail-ot1-f72.google.com with SMTP id 46e09a7af769-7ec3b429610so3708140a34.1 for ; Mon, 03 Aug 2026 06:09:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1785762562; x=1786367362; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=Tx+tU+JavHm9jlJKkOPRaMWM/yiGuddWBQeSbrpsom8=; b=jy+PMJMEqc49CHFp8k4jQrx2PoslU7Xq24aI+gt/XvhTV5z8biEfEsNtCAgCpBpZl1 Bq3BOx5MpR4rH1nY54MpV77RJbeWf2ri5ktfNWFGqIyERpBHjMHsiIoHB7O1SVcLEqAK RzQhYvk+qLOOEDoTO4n9pzs0FI+EB2Z6TKrrkfDYCG0p4QnM3V4qSycWiMM7k0fmP6G2 yRQTU2pdeiNEwoHC9NLCMRIQEnXdS5s3vNFKQugeelhDET0OS1i1wSadCizI5LulaItB Wh0+Vf0pjouGd7Wa2KXZurmO6//Lf09rFDJCB3jG2+Hk1SQdDE0RM0DEF1/xmeD2H8U1 /UtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1785762562; x=1786367362; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=Tx+tU+JavHm9jlJKkOPRaMWM/yiGuddWBQeSbrpsom8=; b=k7LrO5aVfe/PcGmttsa00aadYDQd68vXvf+oFGOVLi4n9giSS7q/ba0ClCwl/HNA1s 4A4BvIvVBzN5DN98GgD3/KJV2niynZ2ZrUa9oSiYtbQmd9nbytNUNEFu/dJcNmpTdRPa e35GcSDlf7CpvYgInY/4O4BBzIjgdj13gmmYQL43VtyBUE+ovj8RCngcpdmmgw+Lx+fY EfscmHA7/5yJdYZE5BPU69dXEIALH9FHb08eF6vw1elFPN/eYQbTXvNZgFj1EgQOt2xi 8bjuiI1mBxJzWslUHLQMBOLZMAM/kMjH/jJwcB7MBMy9IE/WvBKXZN/Rm0MKCgpnhFPN jM/w== X-Forwarded-Encrypted: i=1; AHgh+Robp/IV/lkBpCZMcldWW2W0UzXmwI7PNMEA0KxZSSZKKWkL7dduHsN8T1MARi3t8X7iV8sTRhRrJ7RF/pU=@vger.kernel.org X-Gm-Message-State: AOJu0Yxeb2p3/U+rA6Qk1DEy2maYx9C9AMgTFbr0jFuYrUSlxTa7OKfZ lpMtaeGQmRnjmWugsUBGoK7XGbrtjHxY/6oZdOjeMDLNbsLo1GgTKGTKlyOVk4EEeDOFfF3UmJt dBP/6WQM6FkmlB7Zhlp/CFpfAz91h5XYBnCri5ZV/zdjXCHEedurd4Jvw5qWdnEGBdWA= X-Gm-Gg: AR+sD12fKJyp9sLZuGURpzxttWYL4reJpOnv3hIgmXqQy4/aD158ho9fPmdvy7g3fxI 2j8KputnuBmefsYXmhrO0imcGby9DBFoergf/WPfvuiFow5yYoonF9A8bCy5kRI8M+pekrWLf1N 4jXXhBfktSVtSUpq9HUxrav8pH3PQ9pEUkv/2tadzUDCLl62khYXQcDXEyYEcknA3GsnbRrRn6j iSsjZEkEN5rXZWincZF8UcWkCzG7ie0VF97xfCI70nz1sCL4CH2ujLBA4VSTpWKgeO/a4sqvdJD 7viBICSiB1vBLC5uC4wJRXs+nDD9SOuZO3AyXDSYWBkANVwnwmT6oyAf+p7lOXuRyH3HpftUvuK j9fXNNg7kL1xA8hZolu5xYFsRUobBMkK+ X-Received: by 2002:a05:6830:8299:b0:7ee:3bdc:9205 with SMTP id 46e09a7af769-7f1970380c7mr18910201a34.13.1785762562132; Mon, 03 Aug 2026 06:09:22 -0700 (PDT) X-Received: by 2002:a05:6830:8299:b0:7ee:3bdc:9205 with SMTP id 46e09a7af769-7f1970380c7mr18910128a34.13.1785762561654; Mon, 03 Aug 2026 06:09:21 -0700 (PDT) Received: from hu-pkambar-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7f18f0d6ef6sm7366929a34.21.2026.08.03.06.09.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 06:09:21 -0700 (PDT) From: palash.kambar@oss.qualcomm.com To: vkoul@kernel.org, neil.armstrong@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mani@kernel.org, alim.akhtar@samsung.com, bvanassche@acm.org, andersson@kernel.org, dmitry.baryshkov@oss.qualcomm.com, abel.vesa@oss.qualcomm.com, luca.weiss@fairphone.com Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, nitin.rawat@oss.qualcomm.com, Palash Kambar , Krzysztof Kozlowski Subject: [PATCH v5 2/2] dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Add Hawi UFS PHY compatible Date: Mon, 3 Aug 2026 18:38:52 +0530 Message-Id: <20260803130852.1432714-3-palash.kambar@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260803130852.1432714-1-palash.kambar@oss.qualcomm.com> References: <20260803130852.1432714-1-palash.kambar@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=X9Ri7mTe c=1 sm=1 tr=0 ts=6a709302 cx=c_pps a=+3WqYijBVYhDct2f5Fivkw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=MMZtLZuhhDi3SW52_uAA:9 a=eYe2g0i6gJ5uXG_o6N4q:22 X-Proofpoint-ORIG-GUID: rsM5XzuBZYD3cplRxrfFxJs8oATv4uiG X-Proofpoint-GUID: rsM5XzuBZYD3cplRxrfFxJs8oATv4uiG X-Proofpoint-Spam-Info: AW1haW4tMjYwODAzMDExOCBTYWx0ZWRfX5uSeeXkSm9lW PSptjpMhBO10xcRcQgAgzCG7wnczIxE9mqASm9DiQuXkFKPqLgLkGm8xgvlV3FVvBrG59/aoUqh tpnfy6ylOTfZTX9r8DqZjoxoMCUR34I= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODAzMDExOCBTYWx0ZWRfX6TOKm9gSO/je odzjnGZz75kXB3a1L/aXFk/I0KRUzJsy17WLklAF0oterGXTE8Ty8k60DFophmrqkli72p75exm zz9qE+HG1QfrZsjdTA5xVXS75IMEw8jUw9qS4JmYqatcgSyaGZk8gvKuuG4/qPPF7nVeWNVnFN/ lrpHNRRnfXyEjukM2uw22ukVuQ3xOD8mAUHxJIMD/BIWwRdKak5OPAdgud4SqGw+95c0hE/XYJA WLKeZz3W26ihD8gfXXSS2sa0OMg5X+VCmkbuGnYEm3T7LiN8NS2L/qGWt2yqbP0rwPtj/Qv8mzS aJKiJT3XfVNHUbCLsIS/EglLgzX97OzFx0v3tevYBbIdNKaadi2Sr8DrAaqk/OKMsku8Loe020e zAyyOYJm8Mf9UNgV3bO65V8lHt8YJupNcPogUfAbO+lZYReSKSNZAAM3ocHgtofDid4Es/1XcA0 LySDv8eyZ6sGNK89Ksw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-03_03,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 phishscore=0 adultscore=0 spamscore=0 lowpriorityscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608030118 Content-Type: text/plain; charset="utf-8" From: Palash Kambar Document QMP UFS PHY compatible for Hawi SoC. Reviewed-by: Manivannan Sadhasivam Reviewed-by: Krzysztof Kozlowski Signed-off-by: Palash Kambar --- .../devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-ph= y.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.ya= ml index b2c5c9a375a3..4efe40c0dc97 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml @@ -38,6 +38,7 @@ properties: - qcom,kaanapali-qmp-ufs-phy - const: qcom,sm8750-qmp-ufs-phy - enum: + - qcom,hawi-qmp-ufs-phy - qcom,milos-qmp-ufs-phy - qcom,msm8996-qmp-ufs-phy - qcom,msm8998-qmp-ufs-phy @@ -108,6 +109,7 @@ allOf: compatible: contains: enum: + - qcom,hawi-qmp-ufs-phy - qcom,milos-qmp-ufs-phy - qcom,msm8998-qmp-ufs-phy - qcom,sa8775p-qmp-ufs-phy --=20 2.34.1