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Mon, 3 Aug 2026 12:40:52 +0000 From: Changhuang Liang To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mark Brown Cc: Sudip Mukherjee , Serge Semin , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Changhuang Liang Subject: [PATCH v2 01/11] spi: dw: Introduce spi_frf and STD_SPI Date: Mon, 3 Aug 2026 05:40:34 -0700 Message-Id: <20260803124044.156998-2-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260803124044.156998-1-changhuang.liang@starfivetech.com> References: <20260803124044.156998-1-changhuang.liang@starfivetech.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SHXPR01CA0023.CHNPR01.prod.partner.outlook.cn (2406:e500:c311:1b::32) To ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:17::6) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ4PR01MB1202:EE_|ZQ4PR01MB1267:EE_ X-MS-Office365-Filtering-Correlation-Id: 46f7c7d6-11d3-4842-12b6-08def15c7479 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|52116014|1800799024|366016|23010399003|38350700014|10067099003|56012099006|22082099003|18002099003; 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charset="utf-8" From: Sudip Mukherjee The DW APB SSI controllers of v4.x and newer and DW AHB SSI controllers supports enhanced SPI modes which can be defined from SPI_FRF of DW_SPI_CTRLR0 register. Without enhanced mode, these controllers will work in the standard spi mode. Signed-off-by: Sudip Mukherjee Co-developed-by: Changhuang Liang Signed-off-by: Changhuang Liang --- drivers/spi/spi-dw-core.c | 13 ++++++++++++- drivers/spi/spi-dw.h | 7 +++++++ 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index eff08461c2f5..86e3e7487bc7 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -330,6 +330,16 @@ void dw_spi_update_config(struct dw_spi *dws, struct s= pi_device *spi, /* CTRLR0[11:10] Transfer Mode */ cr0 |=3D FIELD_PREP(DW_HSSI_CTRLR0_TMOD_MASK, cfg->tmode); =20 + if (dw_spi_ver_is_ge(dws, HSSI, 103A)) { + cr0 &=3D ~DW_HSSI_CTRLR0_SPI_FRF_MASK; + cr0 |=3D FIELD_PREP(DW_HSSI_CTRLR0_SPI_FRF_MASK, + cfg->spi_frf); + } else if (dw_spi_ver_is_ge(dws, PSSI, 400A)) { + cr0 &=3D ~DW_PSSI_CTRLR0_SPI_FRF_MASK; + cr0 |=3D FIELD_PREP(DW_PSSI_CTRLR0_SPI_FRF_MASK, + cfg->spi_frf); + } + dw_writel(dws, DW_SPI_CTRLR0, cr0); =20 if (spi_controller_is_target(dws->ctlr)) @@ -422,6 +432,7 @@ static int dw_spi_transfer_one(struct spi_controller *c= tlr, .tmode =3D DW_SPI_CTRLR0_TMOD_TR, .dfs =3D transfer->bits_per_word, .freq =3D transfer->speed_hz, + .spi_frf =3D DW_SPI_CTRLR0_SPI_FRF_STD_SPI, }; int ret; =20 @@ -677,7 +688,7 @@ static void dw_spi_stop_mem_op(struct dw_spi *dws, stru= ct spi_device *spi) static int dw_spi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op= *op) { struct dw_spi *dws =3D spi_controller_get_devdata(mem->spi->controller); - struct dw_spi_cfg cfg; + struct dw_spi_cfg cfg =3D {0}; unsigned long flags; int ret; =20 diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index 2f2debc64e73..19cf1b1a5d4f 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -17,6 +17,9 @@ =20 /* Synopsys DW SSI component versions (FourCC sequence) */ #define DW_HSSI_102A 0x3130322a +#define DW_HSSI_103A 0x3130332a +#define DW_HSSI_200A 0x3230302a +#define DW_PSSI_400A 0x3430302a =20 /* DW SSI IP-core ID and version check helpers */ #define dw_spi_ip_is(_dws, _ip) \ @@ -94,6 +97,9 @@ #define DW_HSSI_CTRLR0_TMOD_MASK GENMASK(11, 10) #define DW_HSSI_CTRLR0_SRL BIT(13) #define DW_HSSI_CTRLR0_MST BIT(31) +#define DW_HSSI_CTRLR0_SPI_FRF_MASK GENMASK(23, 22) +#define DW_PSSI_CTRLR0_SPI_FRF_MASK GENMASK(22, 21) +#define DW_SPI_CTRLR0_SPI_FRF_STD_SPI 0x0 =20 /* Bit fields in CTRLR1 */ #define DW_SPI_NDF_MASK GENMASK(15, 0) @@ -135,6 +141,7 @@ struct dw_spi_cfg { u8 dfs; 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Mon, 3 Aug 2026 12:40:53 +0000 Received: from ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn ([fe80::e7d4:256c:b066:850d]) by ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn ([fe80::e7d4:256c:b066:850d%4]) with mapi id 15.21.0270.016; Mon, 3 Aug 2026 12:40:53 +0000 From: Changhuang Liang To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mark Brown Cc: Sudip Mukherjee , Serge Semin , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Changhuang Liang Subject: [PATCH v2 02/11] spi: dw: update SPI_CTRLR0 register Date: Mon, 3 Aug 2026 05:40:35 -0700 Message-Id: <20260803124044.156998-3-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260803124044.156998-1-changhuang.liang@starfivetech.com> References: <20260803124044.156998-1-changhuang.liang@starfivetech.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SHXPR01CA0023.CHNPR01.prod.partner.outlook.cn (2406:e500:c311:1b::32) To ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:17::6) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ4PR01MB1202:EE_|ZQ4PR01MB1267:EE_ X-MS-Office365-Filtering-Correlation-Id: 9f199778-c06c-465b-e2f7-08def15c7502 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|52116014|1800799024|366016|23010399003|38350700014|10067099003|56012099006|22082099003|18002099003|3023799007; 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charset="utf-8" From: Sudip Mukherjee If the SPI transfer is being done in enhanced mode then SPI_CTRLR0 register needs to be updated to mention the instruction length, address length, address and instruction transfer format, wait cycles. And, we also need to enable clock stretching. Signed-off-by: Sudip Mukherjee Co-developed-by: Changhuang Liang Signed-off-by: Changhuang Liang --- drivers/spi/spi-dw-core.c | 15 ++++++++++++--- drivers/spi/spi-dw.h | 17 ++++++++++++++++- 2 files changed, 28 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index 86e3e7487bc7..7601a53d6f34 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -313,7 +313,7 @@ static u32 dw_spi_prepare_cr0(struct dw_spi *dws, struc= t spi_device *spi) } =20 void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi, - struct dw_spi_cfg *cfg) + struct dw_spi_cfg *cfg, struct dw_spi_enh_cfg *enh_cfg) { struct dw_spi_chip_data *chip =3D spi_get_ctldata(spi); u32 cr0 =3D chip->cr0; @@ -363,6 +363,15 @@ void dw_spi_update_config(struct dw_spi *dws, struct s= pi_device *spi, dw_writel(dws, DW_SPI_RX_SAMPLE_DLY, chip->rx_sample_dly); dws->cur_rx_sample_dly =3D chip->rx_sample_dly; } + + if (enh_cfg) { + cr0 =3D DW_SPI_ENH_CTRLR0_CLK_STRETCH_EN; + cr0 |=3D FIELD_PREP(DW_SPI_ENH_CTRLR0_WAIT_CYCLE_MASK, enh_cfg->wait_c); + cr0 |=3D FIELD_PREP(DW_SPI_ENH_CTRLR0_INST_L_MASK, enh_cfg->inst_l); + cr0 |=3D FIELD_PREP(DW_SPI_ENH_CTRLR0_ADDR_L_MASK, enh_cfg->addr_l); + cr0 |=3D FIELD_PREP(DW_SPI_ENH_CTRLR0_TRANS_TYPE_MASK, enh_cfg->trans_t); + dw_writel(dws, DW_SPI_SPI_CTRLR0, cr0); + } } EXPORT_SYMBOL_NS_GPL(dw_spi_update_config, "SPI_DW_CORE"); =20 @@ -448,7 +457,7 @@ static int dw_spi_transfer_one(struct spi_controller *c= tlr, =20 dw_spi_enable_chip(dws, 0); =20 - dw_spi_update_config(dws, spi, &cfg); + dw_spi_update_config(dws, spi, &cfg, NULL); =20 transfer->effective_speed_hz =3D dws->current_freq; =20 @@ -715,7 +724,7 @@ static int dw_spi_exec_mem_op(struct spi_mem *mem, cons= t struct spi_mem_op *op) =20 dw_spi_enable_chip(dws, 0); =20 - dw_spi_update_config(dws, mem->spi, &cfg); + dw_spi_update_config(dws, mem->spi, &cfg, NULL); =20 dw_spi_mask_intr(dws, 0xff); =20 diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index 19cf1b1a5d4f..16a8c7ab7364 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -63,6 +63,7 @@ #define DW_SPI_VERSION 0x5c #define DW_SPI_DR 0x60 #define DW_SPI_RX_SAMPLE_DLY 0xf0 +#define DW_SPI_SPI_CTRLR0 0xf4 #define DW_SPI_CS_OVERRIDE 0xf4 =20 /* Bit fields in CTRLR0 (DWC APB SSI) */ @@ -127,6 +128,13 @@ #define DW_SPI_DMACR_RDMAE BIT(0) #define DW_SPI_DMACR_TDMAE BIT(1) =20 +/* Bit fields in SPI_CTRLR0 */ +#define DW_SPI_ENH_CTRLR0_CLK_STRETCH_EN BIT(30) +#define DW_SPI_ENH_CTRLR0_WAIT_CYCLE_MASK GENMASK(15, 11) +#define DW_SPI_ENH_CTRLR0_INST_L_MASK GENMASK(9, 8) +#define DW_SPI_ENH_CTRLR0_ADDR_L_MASK GENMASK(5, 2) +#define DW_SPI_ENH_CTRLR0_TRANS_TYPE_MASK GENMASK(1, 0) + /* Mem/DMA operations helpers */ #define DW_SPI_WAIT_RETRIES 5 #define DW_SPI_BUF_SIZE \ @@ -144,6 +152,13 @@ struct dw_spi_cfg { u8 spi_frf; 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charset="utf-8" From: Sudip Mukherjee Before doing the mem op, spi controller will be queried about the buswidths it supports. Add the single/dual/quad/octal if the controller has the DW_SPI_CAP_EMODE capability. The DW_SPI_CAP_EMODE capability will be enabled in a later patch. Signed-off-by: Sudip Mukherjee Co-developed-by: Changhuang Liang Signed-off-by: Changhuang Liang --- drivers/spi/spi-dw-core.c | 34 +++++++++++++++++++++++++++++++++- drivers/spi/spi-dw.h | 1 + 2 files changed, 34 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index 7601a53d6f34..7275b7a9945f 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -518,6 +518,35 @@ static int dw_spi_adjust_mem_op_size(struct spi_mem *m= em, struct spi_mem_op *op) return 0; } =20 +static bool dw_spi_supports_enh_mem_op(struct spi_mem *mem, + const struct spi_mem_op *op) +{ + if (op->addr.nbytes !=3D 0 && op->addr.buswidth !=3D 1 && + op->addr.buswidth !=3D op->data.buswidth) + return false; + + if (op->addr.nbytes >=3D 8) + return false; + + if (op->cmd.buswidth !=3D 1 && op->cmd.buswidth !=3D op->addr.buswidth && + op->cmd.buswidth !=3D op->data.buswidth) + return false; + + if (op->dummy.nbytes && !op->dummy.buswidth) + return false; + + if (op->dummy.nbytes !=3D 0 && op->data.dir =3D=3D SPI_MEM_DATA_OUT) + return false; + + /* WAIT_CYCLES is a 5-bit field in SPI_CTRLR0 */ + if (op->dummy.nbytes !=3D 0 && + op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth > + FIELD_MAX(DW_SPI_ENH_CTRLR0_WAIT_CYCLE_MASK)) + return false; + + return spi_mem_default_supports_op(mem, op); +} + static bool dw_spi_supports_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) { @@ -800,7 +829,10 @@ static void dw_spi_init_mem_ops(struct dw_spi *dws) if (!dws->mem_ops.exec_op && !(dws->caps & DW_SPI_CAP_CS_OVERRIDE) && !dws->set_cs) { dws->mem_ops.adjust_op_size =3D dw_spi_adjust_mem_op_size; - dws->mem_ops.supports_op =3D dw_spi_supports_mem_op; + if (dws->caps & DW_SPI_CAP_EMODE) + dws->mem_ops.supports_op =3D dw_spi_supports_enh_mem_op; + else + dws->mem_ops.supports_op =3D dw_spi_supports_mem_op; dws->mem_ops.exec_op =3D dw_spi_exec_mem_op; if (!dws->max_mem_freq) dws->max_mem_freq =3D dws->max_freq; diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index 16a8c7ab7364..81a433ab759b 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -35,6 +35,7 @@ /* DW SPI controller capabilities */ #define DW_SPI_CAP_CS_OVERRIDE BIT(0) #define DW_SPI_CAP_DFS32 BIT(1) +#define DW_SPI_CAP_EMODE BIT(2) =20 /* Register offsets (Generic for both DWC APB SSI and DWC SSI IP-cores) */ #define DW_SPI_CTRLR0 0x00 --=20 2.25.1 From nobody Fri Oct 2 08:25:48 2026 Received: from CHN02-SH0-obe.outbound.protection.partner.outlook.cn (mail-sh0chn02on2115.outbound.protection.partner.outlook.cn [139.219.146.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A061A40B0FE; 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charset="utf-8" From: Sudip Mukherjee In enhanced mode adjust the size of the data that can be sent or received as this will then be used to set the NDF. Signed-off-by: Sudip Mukherjee Co-developed-by: Changhuang Liang Signed-off-by: Changhuang Liang --- drivers/spi/spi-dw-core.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index 7275b7a9945f..c7cd24337188 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -510,6 +510,16 @@ static int dw_spi_target_abort(struct spi_controller *= ctlr) return 0; } =20 +static int dw_spi_adjust_enh_mem_op_size(struct spi_mem *mem, struct spi_m= em_op *op) +{ + if (op->data.dir =3D=3D SPI_MEM_DATA_IN) + op->data.nbytes =3D clamp_val(op->data.nbytes, 0, DW_SPI_NDF_MASK + 1); + else + op->data.nbytes =3D clamp_val(op->data.nbytes, 0, DW_SPI_NDF_MASK); + + return 0; +} + static int dw_spi_adjust_mem_op_size(struct spi_mem *mem, struct spi_mem_o= p *op) { if (op->data.dir =3D=3D SPI_MEM_DATA_IN) @@ -829,10 +839,14 @@ static void dw_spi_init_mem_ops(struct dw_spi *dws) if (!dws->mem_ops.exec_op && !(dws->caps & DW_SPI_CAP_CS_OVERRIDE) && !dws->set_cs) { dws->mem_ops.adjust_op_size =3D dw_spi_adjust_mem_op_size; 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charset="utf-8" From: Sudip Mukherjee If the transfer of Transmit only mode is using enhanced SPI then NDF needs to be updated with the number of data frames. If the Transmit FIFO goes empty in-between, DWC_ssi masks the serial clock and wait for rest of the data until the programmed amount of frames are transferred successfully. In receive mode, the number of data frames received is equal to this register value plus 1. In transmit mode, the number of data frames is equal this register value. Signed-off-by: Sudip Mukherjee Co-developed-by: Changhuang Liang Signed-off-by: Changhuang Liang --- drivers/spi/spi-dw-core.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index c7cd24337188..5f215e76a7ad 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -348,6 +348,9 @@ void dw_spi_update_config(struct dw_spi *dws, struct sp= i_device *spi, if (cfg->tmode =3D=3D DW_SPI_CTRLR0_TMOD_EPROMREAD || cfg->tmode =3D=3D DW_SPI_CTRLR0_TMOD_RO) dw_writel(dws, DW_SPI_CTRLR1, cfg->ndf ? cfg->ndf - 1 : 0); + else if (cfg->tmode =3D=3D DW_SPI_CTRLR0_TMOD_TO && + dws->caps & DW_SPI_CAP_EMODE) + dw_writel(dws, DW_SPI_CTRLR1, cfg->ndf); =20 /* Note DW APB SSI clock divider doesn't support odd numbers */ clk_div =3D (DIV_ROUND_UP(dws->max_freq, cfg->freq) + 1) & 0xfffe; --=20 2.25.1 From nobody Fri Oct 2 08:25:48 2026 Received: from CHN02-SH0-obe.outbound.protection.partner.outlook.cn (mail-sh0chn02on2115.outbound.protection.partner.outlook.cn [139.219.146.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B46341CB5C; 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charset="utf-8" From: Sudip Mukherjee If the spi transfer is using enhanced single/dual/quad/octal spi mode, then we need to update the SPI_CTRLR0 register. The SPI_CTRLR0 register will be updated in dw_spi_update_config() via the values in dw_spi_enh_cfg. Signed-off-by: Sudip Mukherjee Co-developed-by: Changhuang Liang Signed-off-by: Changhuang Liang --- drivers/spi/spi-dw-core.c | 87 ++++++++++++++++++++++++++++++++++++++- drivers/spi/spi-dw.h | 9 ++++ 2 files changed, 95 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index 5f215e76a7ad..7441e8db0ea7 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -828,6 +828,90 @@ static int dw_spi_exec_mem_op(struct spi_mem *mem, con= st struct spi_mem_op *op) return ret; } =20 +static void dw_spi_init_enh_mem_buf(struct dw_spi *dws, const struct spi_m= em_op *op) +{ + dws->n_bytes =3D 1; + if (op->data.dir =3D=3D SPI_MEM_DATA_IN) { + dws->rx =3D op->data.buf.in; + dws->rx_len =3D op->data.nbytes; + dws->tx =3D NULL; + dws->tx_len =3D 0; + } else if (op->data.dir =3D=3D SPI_MEM_DATA_OUT) { + dws->tx_len =3D op->data.nbytes; + dws->tx =3D (void *)op->data.buf.out; + dws->rx =3D NULL; + dws->rx_len =3D 0; + } else { + dws->rx =3D NULL; + dws->rx_len =3D 0; + dws->tx =3D NULL; + dws->tx_len =3D 0; + } +} + +static int dw_spi_exec_enh_mem_op(struct spi_mem *mem, const struct spi_me= m_op *op) +{ + struct spi_controller *ctlr =3D mem->spi->controller; + struct dw_spi *dws =3D spi_controller_get_devdata(ctlr); + struct dw_spi_enh_cfg enh_cfg =3D {0}; + struct dw_spi_cfg cfg =3D {0}; + + switch (op->data.buswidth) { + case 0: + case 1: + cfg.spi_frf =3D DW_SPI_CTRLR0_SPI_FRF_STD_SPI; + break; + case 2: + cfg.spi_frf =3D DW_SPI_CTRLR0_SPI_FRF_DUAL_SPI; + break; + case 4: + cfg.spi_frf =3D DW_SPI_CTRLR0_SPI_FRF_QUAD_SPI; + break; + case 8: + cfg.spi_frf =3D DW_SPI_CTRLR0_SPI_FRF_OCT_SPI; + break; + default: + return -EINVAL; + } + + dw_spi_init_enh_mem_buf(dws, op); + + cfg.dfs =3D 8; + cfg.freq =3D clamp(op->max_freq, 0U, dws->max_mem_freq); + cfg.ndf =3D op->data.nbytes; + if (op->data.dir =3D=3D SPI_MEM_DATA_IN) + cfg.tmode =3D DW_SPI_CTRLR0_TMOD_RO; + else + cfg.tmode =3D DW_SPI_CTRLR0_TMOD_TO; + + if (op->data.buswidth =3D=3D op->addr.buswidth && + op->data.buswidth =3D=3D op->cmd.buswidth) + enh_cfg.trans_t =3D DW_SPI_ENH_CTRLR0_TRANS_TYPE_TT2; + else if (op->data.buswidth =3D=3D op->addr.buswidth) + enh_cfg.trans_t =3D DW_SPI_ENH_CTRLR0_TRANS_TYPE_TT1; + else + enh_cfg.trans_t =3D DW_SPI_ENH_CTRLR0_TRANS_TYPE_TT0; + + enh_cfg.addr_l =3D op->addr.nbytes << 1; + if (op->cmd.nbytes =3D=3D 2) + enh_cfg.inst_l =3D DW_SPI_ENH_CTRLR0_INST_L_INST_L16; + else if (op->cmd.nbytes =3D=3D 1) + enh_cfg.inst_l =3D DW_SPI_ENH_CTRLR0_INST_L_INST_L8; + else + enh_cfg.inst_l =3D DW_SPI_ENH_CTRLR0_INST_L_INST_L0; + + if (op->dummy.buswidth) + enh_cfg.wait_c =3D op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth; + + dw_spi_enable_chip(dws, 0); + + dw_spi_update_config(dws, mem->spi, &cfg, &enh_cfg); + + dw_spi_enable_chip(dws, 1); + + return 0; +} + /* * Initialize the default memory operations if a glue layer hasn't specifi= ed * custom ones. Direct mapping operations will be preserved anyway since D= W SPI @@ -843,14 +927,15 @@ static void dw_spi_init_mem_ops(struct dw_spi *dws) !dws->set_cs) { dws->mem_ops.adjust_op_size =3D dw_spi_adjust_mem_op_size; if (dws->caps & DW_SPI_CAP_EMODE) { + dws->mem_ops.exec_op =3D dw_spi_exec_enh_mem_op; dws->mem_ops.supports_op =3D dw_spi_supports_enh_mem_op; dws->mem_ops.adjust_op_size =3D dw_spi_adjust_enh_mem_op_size; } else { + dws->mem_ops.exec_op =3D dw_spi_exec_mem_op; dws->mem_ops.supports_op =3D dw_spi_supports_mem_op; dws->mem_ops.adjust_op_size =3D dw_spi_adjust_mem_op_size; } =20 - dws->mem_ops.exec_op =3D dw_spi_exec_mem_op; if (!dws->max_mem_freq) dws->max_mem_freq =3D dws->max_freq; } diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index 81a433ab759b..2dae81c15423 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -102,6 +102,9 @@ #define DW_HSSI_CTRLR0_SPI_FRF_MASK GENMASK(23, 22) #define DW_PSSI_CTRLR0_SPI_FRF_MASK GENMASK(22, 21) #define DW_SPI_CTRLR0_SPI_FRF_STD_SPI 0x0 +#define DW_SPI_CTRLR0_SPI_FRF_DUAL_SPI 0x1 +#define DW_SPI_CTRLR0_SPI_FRF_QUAD_SPI 0x2 +#define DW_SPI_CTRLR0_SPI_FRF_OCT_SPI 0x3 =20 /* Bit fields in CTRLR1 */ #define DW_SPI_NDF_MASK GENMASK(15, 0) @@ -133,7 +136,13 @@ #define DW_SPI_ENH_CTRLR0_CLK_STRETCH_EN BIT(30) #define DW_SPI_ENH_CTRLR0_WAIT_CYCLE_MASK GENMASK(15, 11) #define DW_SPI_ENH_CTRLR0_INST_L_MASK GENMASK(9, 8) +#define DW_SPI_ENH_CTRLR0_INST_L_INST_L0 0x0 +#define DW_SPI_ENH_CTRLR0_INST_L_INST_L8 0x2 +#define DW_SPI_ENH_CTRLR0_INST_L_INST_L16 0x3 #define DW_SPI_ENH_CTRLR0_ADDR_L_MASK GENMASK(5, 2) +#define DW_SPI_ENH_CTRLR0_TRANS_TYPE_TT0 0x0 +#define DW_SPI_ENH_CTRLR0_TRANS_TYPE_TT1 0x1 +#define DW_SPI_ENH_CTRLR0_TRANS_TYPE_TT2 0x2 #define DW_SPI_ENH_CTRLR0_TRANS_TYPE_MASK GENMASK(1, 0) =20 /* Mem/DMA operations helpers */ --=20 2.25.1 From nobody Fri Oct 2 08:25:48 2026 Received: from CHN02-SH0-obe.outbound.protection.partner.outlook.cn (mail-sh0chn02on2115.outbound.protection.partner.outlook.cn [139.219.146.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A37D141D136; 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charset="utf-8" From: Sudip Mukherjee In enhanced spi mode, read or write will start by sending the cmd and address (if present). Signed-off-by: Sudip Mukherjee Co-developed-by: Changhuang Liang Signed-off-by: Changhuang Liang --- drivers/spi/spi-dw-core.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index 7441e8db0ea7..2b3149ac64b3 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -849,6 +849,19 @@ static void dw_spi_init_enh_mem_buf(struct dw_spi *dws= , const struct spi_mem_op } } =20 +static void dw_spi_enh_write_cmd_addr(struct dw_spi *dws, const struct spi= _mem_op *op) +{ + /* Send cmd as 32 bit value */ + dw_write_io_reg(dws, DW_SPI_DR, op->cmd.opcode); + if (op->addr.nbytes) { + dw_write_io_reg(dws, DW_SPI_DR, lower_32_bits(op->addr.val)); + if (op->addr.nbytes > 4) { + /* address more than 32bit */ + dw_write_io_reg(dws, DW_SPI_DR, upper_32_bits(op->addr.val)); + } + } +} + static int dw_spi_exec_enh_mem_op(struct spi_mem *mem, const struct spi_me= m_op *op) { struct spi_controller *ctlr =3D mem->spi->controller; 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charset="utf-8" From: Sudip Mukherjee Introduce the interrupt handler for enhanced spi to read or write based on the generated irq. Also, use the xfer_completion from spi_controller to wait for a timeout or completion from irq handler. In enhanced mode we need to calculate RXFTLR based on the length of data we are expecting to receive or the fifo length. Signed-off-by: Sudip Mukherjee Co-developed-by: Changhuang Liang Signed-off-by: Changhuang Liang --- drivers/spi/spi-dw-core.c | 106 +++++++++++++++++++++++++++++++++++++- 1 file changed, 104 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index 2b3149ac64b3..a1c6fa1a780b 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -248,6 +248,29 @@ static irqreturn_t dw_spi_transfer_handler(struct dw_s= pi *dws) return IRQ_HANDLED; } =20 +static irqreturn_t dw_spi_enh_handler(struct dw_spi *dws) +{ + u16 irq_status =3D dw_readl(dws, DW_SPI_ISR); + + if (irq_status & DW_SPI_INT_RXFI) { + dw_reader(dws); + if (dws->rx_len && dws->rx_len <=3D dw_readl(dws, DW_SPI_RXFTLR)) + dw_writel(dws, DW_SPI_RXFTLR, dws->rx_len - 1); + } + + if (irq_status & DW_SPI_INT_TXEI) + dw_writer(dws); + + if (!dws->tx_len && dws->rx_len) { + dw_spi_mask_intr(dws, DW_SPI_INT_TXEI); + } else if (!dws->rx_len && !dws->tx_len) { + dw_spi_mask_intr(dws, 0xff); + spi_finalize_current_transfer(dws->ctlr); + } + + return IRQ_HANDLED; +} + static irqreturn_t dw_spi_irq(int irq, void *dev_id) { struct spi_controller *ctlr =3D dev_id; @@ -257,10 +280,17 @@ static irqreturn_t dw_spi_irq(int irq, void *dev_id) if (!irq_status) return IRQ_NONE; =20 - if (!ctlr->cur_msg) { + if (!dws->transfer_handler || + (!ctlr->cur_msg && dws->transfer_handler =3D=3D dw_spi_transfer_handl= er)) { dw_spi_mask_intr(dws, 0xff); return IRQ_HANDLED; } + if (dws->transfer_handler =3D=3D dw_spi_enh_handler && + !dws->rx_len && !dws->tx_len) { + dw_spi_mask_intr(dws, 0xff); + spi_finalize_current_transfer(ctlr); + return IRQ_HANDLED; + } =20 return dws->transfer_handler(dws); } @@ -399,6 +429,33 @@ static void dw_spi_irq_setup(struct dw_spi *dws) dw_spi_umask_intr(dws, imask); } =20 +static void dw_spi_enh_irq_setup(struct dw_spi *dws) +{ + u16 level; + u8 imask; + + /* + * Originally Tx and Rx data lengths match. Rx FIFO Threshold level + * will be adjusted at the final stage of the IRQ-based SPI transfer + * execution so not to lose the leftover of the incoming data. + */ + level =3D min_t(unsigned int, dws->fifo_len / 2, dws->tx_len); + dw_writel(dws, DW_SPI_TXFTLR, level); + + /* + * In enhanced mode if we are reading then tx_len is 0 as we + * have nothing to transmit. Calculate DW_SPI_RXFTLR with + * rx_len. + */ + level =3D min_t(unsigned int, dws->fifo_len / 2, dws->rx_len); + dw_writel(dws, DW_SPI_RXFTLR, level ? level - 1 : 0); + + dws->transfer_handler =3D dw_spi_enh_handler; + + imask =3D DW_SPI_INT_TXEI | DW_SPI_INT_RXFI; + dw_spi_umask_intr(dws, imask); +} + /* * The iterative procedure of the poll-based transfer is simple: write as = much * as possible to the Tx FIFO, wait until the pending to receive data is r= eady @@ -868,6 +925,8 @@ static int dw_spi_exec_enh_mem_op(struct spi_mem *mem, = const struct spi_mem_op * struct dw_spi *dws =3D spi_controller_get_devdata(ctlr); struct dw_spi_enh_cfg enh_cfg =3D {0}; struct dw_spi_cfg cfg =3D {0}; + unsigned long long ms; + int ret; =20 switch (op->data.buswidth) { case 0: @@ -920,11 +979,54 @@ static int dw_spi_exec_enh_mem_op(struct spi_mem *mem= , const struct spi_mem_op * =20 dw_spi_update_config(dws, mem->spi, &cfg, &enh_cfg); =20 + dw_spi_mask_intr(dws, 0xff); + reinit_completion(&ctlr->xfer_completion); dw_spi_enable_chip(dws, 1); =20 dw_spi_enh_write_cmd_addr(dws, op); + dw_spi_set_cs(mem->spi, false); =20 - return 0; + /* + * FIXME: The exact reason for this delay is not fully understood, + * but empirical testing shows it significantly improves the stability + * of read/write operations. Without this delay, occasional transfer + * errors or timeouts may occur under certain conditions. + * Keeping it as a safeguard based on practical validation. + */ + udelay(5); + + dw_spi_enh_irq_setup(dws); + + /* Use timeout calculation from spi_transfer_wait() */ + ms =3D 8LL * MSEC_PER_SEC * (dws->rx_len ? dws->rx_len : dws->tx_len); + do_div(ms, dws->current_freq); + + /* + * Increase it twice and add 200 ms tolerance, use + * predefined maximum in case of overflow. + */ + ms +=3D ms + 200; + if (ms > UINT_MAX) + ms =3D UINT_MAX; + + ms =3D wait_for_completion_timeout(&ctlr->xfer_completion, + msecs_to_jiffies(ms)); + if (ms =3D=3D 0) { + dw_spi_mask_intr(dws, 0xff); + synchronize_irq(dws->irq); + dws->rx =3D NULL; + dws->tx =3D NULL; + dws->rx_len =3D 0; + dws->tx_len =3D 0; + dw_spi_stop_mem_op(dws, mem->spi); + return -EIO; + } + + ret =3D dw_spi_wait_mem_op_done(dws); + + dw_spi_stop_mem_op(dws, mem->spi); + + return ret; } =20 /* --=20 2.25.1 From nobody Fri Oct 2 08:25:48 2026 Received: from CHN02-SH0-obe.outbound.protection.partner.outlook.cn (mail-sh0chn02on2115.outbound.protection.partner.outlook.cn [139.219.146.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D2FD41D22E; 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charset="utf-8" From: Sudip Mukherjee All the SSI controllers supporting enhanced spi modes might not support all the three dual or quad or octal modes. Detect the modes that are supported and finally enable the DW_SPI_CAP_EMODE capability which will start using all the enhanced spi functions that has been added. Signed-off-by: Sudip Mukherjee Co-developed-by: Changhuang Liang Signed-off-by: Changhuang Liang --- drivers/spi/spi-dw-core.c | 75 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 72 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index a1c6fa1a780b..0d900afa015d 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -1029,6 +1029,12 @@ static int dw_spi_exec_enh_mem_op(struct spi_mem *me= m, const struct spi_mem_op * return ret; } =20 +static bool dw_spi_can_use_mem_ops(struct dw_spi *dws) +{ + return !dws->mem_ops.exec_op && !(dws->caps & DW_SPI_CAP_CS_OVERRIDE) && + !dws->set_cs; +} + /* * Initialize the default memory operations if a glue layer hasn't specifi= ed * custom ones. Direct mapping operations will be preserved anyway since D= W SPI @@ -1040,8 +1046,7 @@ static int dw_spi_exec_enh_mem_op(struct spi_mem *mem= , const struct spi_mem_op * */ static void dw_spi_init_mem_ops(struct dw_spi *dws) { - if (!dws->mem_ops.exec_op && !(dws->caps & DW_SPI_CAP_CS_OVERRIDE) && - !dws->set_cs) { + if (dw_spi_can_use_mem_ops(dws)) { dws->mem_ops.adjust_op_size =3D dw_spi_adjust_mem_op_size; if (dws->caps & DW_SPI_CAP_EMODE) { dws->mem_ops.exec_op =3D dw_spi_exec_enh_mem_op; @@ -1103,6 +1108,66 @@ static void dw_spi_cleanup(struct spi_device *spi) spi_set_ctldata(spi, NULL); } =20 +static u16 detect_enh_mode(struct dw_spi *dws) +{ + u32 tmp_spi_ctrlr0, tmp_ctrlr0; + u32 tmp_val, frf_shift; + u16 mode =3D 0; + + if (dw_spi_ver_is_ge(dws, HSSI, 103A)) + frf_shift =3D __bf_shf(DW_HSSI_CTRLR0_SPI_FRF_MASK); + else if (dw_spi_ver_is_ge(dws, PSSI, 400A)) + frf_shift =3D __bf_shf(DW_PSSI_CTRLR0_SPI_FRF_MASK); + else + return 0; + + tmp_ctrlr0 =3D dw_readl(dws, DW_SPI_CTRLR0); + tmp_spi_ctrlr0 =3D dw_readl(dws, DW_SPI_SPI_CTRLR0); + dw_spi_enable_chip(dws, 0); + + /* test dual mode */ + tmp_val =3D DW_SPI_CTRLR0_SPI_FRF_DUAL_SPI << frf_shift; + dw_writel(dws, DW_SPI_CTRLR0, tmp_val); + if ((tmp_val & dw_readl(dws, DW_SPI_CTRLR0)) =3D=3D tmp_val) + mode |=3D SPI_TX_DUAL | SPI_RX_DUAL; + + /* test quad mode */ + tmp_val =3D DW_SPI_CTRLR0_SPI_FRF_QUAD_SPI << frf_shift; + dw_writel(dws, DW_SPI_CTRLR0, tmp_val); + if ((tmp_val & dw_readl(dws, DW_SPI_CTRLR0)) =3D=3D tmp_val) + mode |=3D SPI_TX_QUAD | SPI_RX_QUAD; + + /* test octal mode */ + tmp_val =3D DW_SPI_CTRLR0_SPI_FRF_OCT_SPI << frf_shift; + dw_writel(dws, DW_SPI_CTRLR0, tmp_val); + if ((tmp_val & dw_readl(dws, DW_SPI_CTRLR0)) =3D=3D tmp_val) + mode |=3D SPI_TX_OCTAL | SPI_RX_OCTAL; + + if (!mode) + goto disable_enh; + + /* test clock stretching */ + dw_writel(dws, DW_SPI_SPI_CTRLR0, DW_SPI_ENH_CTRLR0_CLK_STRETCH_EN); + if ((DW_SPI_ENH_CTRLR0_CLK_STRETCH_EN & dw_readl(dws, DW_SPI_SPI_CTRLR0))= !=3D + DW_SPI_ENH_CTRLR0_CLK_STRETCH_EN) { + /* + * If clock stretching is not enabled then do not use + * enhanced mode. + */ + mode =3D 0; + goto disable_enh; + } + + dws->caps |=3D DW_SPI_CAP_EMODE; + +disable_enh: + dw_writel(dws, DW_SPI_CTRLR0, tmp_ctrlr0); + dw_writel(dws, DW_SPI_SPI_CTRLR0, tmp_spi_ctrlr0); + dw_spi_enable_chip(dws, 1); + + return mode; +} + /* Restart the controller, disable all interrupts, clean rx fifo */ static void dw_spi_hw_init(struct device *dev, struct dw_spi *dws) { @@ -1182,6 +1247,11 @@ static void dw_spi_hw_init(struct device *dev, struc= t dw_spi *dws) dws->caps |=3D DW_SPI_CAP_DFS32; } =20 + dws->ctlr->mode_bits |=3D SPI_CPOL | SPI_CPHA; + + if (!spi_controller_is_target(dws->ctlr) && dw_spi_can_use_mem_ops(dws)) + dws->ctlr->mode_bits |=3D detect_enh_mode(dws); + /* enable HW fixup for explicit CS deselect for Amazon's alpine chip */ if (dws->caps & DW_SPI_CAP_CS_OVERRIDE) dw_writel(dws, DW_SPI_CS_OVERRIDE, 0xF); @@ -1226,7 +1296,6 @@ int dw_spi_add_controller(struct device *dev, struct = dw_spi *dws) =20 dw_spi_init_mem_ops(dws); =20 - ctlr->mode_bits =3D SPI_CPOL | SPI_CPHA; if (dws->caps & DW_SPI_CAP_DFS32) ctlr->bits_per_word_mask =3D SPI_BPW_RANGE_MASK(4, 32); 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charset="utf-8" Add a new compatible string "starfive,jhb100-sfc" for the StarFive JHB100 SPI Flash Controller, it based on the Synopsys DesignWare SSI version 2.00a but with minor modifications. Due to these minor modifications, it only supports access for flash memory and requires a system controller register to configure the address mode filter for SPI NOR flash devices. The starfive,sfc-filter-syscon property is required to provide a phandle to the system controller that manages switching between 3-byte and 4-byte addressing modes, essential for supporting SPI NOR flash devices with different address width requirements. Signed-off-by: Changhuang Liang Acked-by: Conor Dooley --- .../bindings/spi/snps,dw-apb-ssi.yaml | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/D= ocumentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml index 4458316326fc..f13cb963db88 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml @@ -33,6 +33,17 @@ allOf: else: properties: amd,pensando-elba-syscon: false + - if: + properties: + compatible: + contains: + const: starfive,jhb100-sfc + then: + required: + - starfive,sfc-filter-syscon + else: + properties: + starfive,sfc-filter-syscon: false =20 properties: compatible: @@ -68,6 +79,8 @@ properties: const: amd,pensando-elba-spi - description: Canaan Kendryte K210 SoS SPI Controller const: canaan,k210-spi + - description: StarFive JHB100 SoC SPI Flash Controller + const: starfive,jhb100-sfc - description: Renesas RZ/N1 SPI Controller items: - const: renesas,r9a06g032-spi # RZ/N1D @@ -139,6 +152,15 @@ properties: Block address to control SPI chip-selects. The Elba SoC system contr= oller provides an interface to override the native DWC SSI CS control. =20 + starfive,sfc-filter-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Phandle to the system controller register that controls the SPI NOR = flash + address mode filter. This system controller interface provides addit= ional + configuration to switch between 3-byte and 4-byte addressing modes, = which + is required when accessing SPI NOR flash devices with different addr= ess + width requirements. + patternProperties: "@[0-9a-f]$": type: object --=20 2.25.1 From nobody Fri Oct 2 08:25:48 2026 Received: from CHN02-SH0-obe.outbound.protection.partner.outlook.cn (mail-sh0chn02on2115.outbound.protection.partner.outlook.cn [139.219.146.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B87E541DE00; Mon, 3 Aug 2026 12:41:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=139.219.146.115 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785760884; cv=fail; b=ivJwypZx+lLJglMWa/+9PYvnu0r+Ywxon9dpDn5LxmnsfEHrH1tuesgLBZZyoGCRYud0t/kKzBlP489cJR+C3/LbZax++TQxnjhE7M8bGn8dwpfkPIrzhsbhiwAOPOTSAr8lt8qL2DyF6u4h/soXe5uKtyfN1LLcxE5X+RF1hhk= ARC-Message-Signature: i=2; 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charset="utf-8" Add support for the StarFive JHB100 SoC SPI Flash Controller (SFC), which is based on the Synopsys DesignWare SSI version 2.00a but with some customizations. The JHB100 SFC controller has the following special features: 1. Separate registers for instruction and address (DW_SPI_JHB100_INST and DW_SPI_JHB100_ADDR) instead of using the common data register. 2. A filter interrupt mask register (DW_SPI_JHB100_FILTER_IMR), which is default masked to disable filter interrupts as they are not used. 3. Requires a system controller phandle "starfive,sfc-filter-syscon" to configure 3-byte/4-byte address mode switching per chip select. 4. Different Set CS and Enable Controller Timing. A new quirk flag DW_SPI_QUIRK_JHB100 is introduced to handle these differences in the enhanced SPI memory operation path. The controller uses the HSSI initialization path (DW_HSSI_ID) and shares the same interrupt masking logic. Limit the JHB100 SFC address to 3-byte or 4-byte length. Additionally, the platform_suspend() and platform_resume() callbacks are introduced to handle platform-private suspend/resume procedures. Signed-off-by: Changhuang Liang --- drivers/spi/spi-dw-core.c | 48 ++++++++++++++++++++------ drivers/spi/spi-dw-mmio.c | 72 +++++++++++++++++++++++++++++++++++++++ drivers/spi/spi-dw.h | 18 ++++++++++ 3 files changed, 127 insertions(+), 11 deletions(-) diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index 0d900afa015d..ce6144a34785 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -591,6 +591,8 @@ static int dw_spi_adjust_mem_op_size(struct spi_mem *me= m, struct spi_mem_op *op) static bool dw_spi_supports_enh_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) { + struct dw_spi *dws =3D spi_controller_get_devdata(mem->spi->controller); + if (op->addr.nbytes !=3D 0 && op->addr.buswidth !=3D 1 && op->addr.buswidth !=3D op->data.buswidth) return false; @@ -614,6 +616,10 @@ static bool dw_spi_supports_enh_mem_op(struct spi_mem = *mem, FIELD_MAX(DW_SPI_ENH_CTRLR0_WAIT_CYCLE_MASK)) return false; =20 + if ((dws->quirk_flags & DW_SPI_QUIRK_JHB100) && op->addr.nbytes && + op->addr.nbytes !=3D 3 && op->addr.nbytes !=3D 4) + return false; + return spi_mem_default_supports_op(mem, op); } =20 @@ -906,16 +912,30 @@ static void dw_spi_init_enh_mem_buf(struct dw_spi *dw= s, const struct spi_mem_op } } =20 -static void dw_spi_enh_write_cmd_addr(struct dw_spi *dws, const struct spi= _mem_op *op) +static void dw_spi_enh_write_cmd_addr(struct dw_spi *dws, const struct spi= _mem_op *op, + struct spi_mem *mem) { - /* Send cmd as 32 bit value */ - dw_write_io_reg(dws, DW_SPI_DR, op->cmd.opcode); - if (op->addr.nbytes) { - dw_write_io_reg(dws, DW_SPI_DR, lower_32_bits(op->addr.val)); - if (op->addr.nbytes > 4) { - /* address more than 32bit */ - dw_write_io_reg(dws, DW_SPI_DR, upper_32_bits(op->addr.val)); + if (dws->quirk_flags & DW_SPI_QUIRK_JHB100) { + dw_write_io_reg(dws, DW_SPI_JHB100_INST, op->cmd.opcode); + if (op->addr.nbytes) + dw_write_io_reg(dws, DW_SPI_JHB100_ADDR, op->addr.val); + + dw_spi_set_cs(mem->spi, false); + dw_spi_enable_chip(dws, 1); + } else { + dw_spi_enable_chip(dws, 1); + + /* Send cmd as 32 bit value */ + dw_write_io_reg(dws, DW_SPI_DR, op->cmd.opcode); + if (op->addr.nbytes) { + dw_write_io_reg(dws, DW_SPI_DR, lower_32_bits(op->addr.val)); + if (op->addr.nbytes > 4) { + /* address more than 32bit */ + dw_write_io_reg(dws, DW_SPI_DR, upper_32_bits(op->addr.val)); + } } + + dw_spi_set_cs(mem->spi, false); } } =20 @@ -981,10 +1001,16 @@ static int dw_spi_exec_enh_mem_op(struct spi_mem *me= m, const struct spi_mem_op * =20 dw_spi_mask_intr(dws, 0xff); reinit_completion(&ctlr->xfer_completion); - dw_spi_enable_chip(dws, 1); =20 - dw_spi_enh_write_cmd_addr(dws, op); - dw_spi_set_cs(mem->spi, false); + if (op->addr.nbytes && dws->set_addr_nbyte) { + ret =3D dws->set_addr_nbyte(mem->spi, op->addr.nbytes); + if (ret) { + dw_spi_enable_chip(dws, 1); + return ret; + } + } + + dw_spi_enh_write_cmd_addr(dws, op, mem); =20 /* * FIXME: The exact reason for this delay is not fully understood, diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c index 603e81a92c57..8cdb0351605b 100644 --- a/drivers/spi/spi-dw-mmio.c +++ b/drivers/spi/spi-dw-mmio.c @@ -31,6 +31,8 @@ struct dw_spi_mmio { struct clk *pclk; void *priv; struct reset_control *rstc; + void (*platform_suspend)(struct dw_spi_mmio *dwsmmio); + int (*platform_resume)(struct dw_spi_mmio *dwsmmio); }; =20 #define MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL 0x24 @@ -48,6 +50,8 @@ struct dw_spi_mmio { #define SPARX5_FORCE_ENA 0xa4 #define SPARX5_FORCE_VAL 0xa8 =20 +#define JHB100_ADDRMODE_CS 0x00 + struct dw_spi_mscc { struct regmap *syscon; void __iomem *spi_mst; /* Not sparx5 */ @@ -310,6 +314,58 @@ static int dw_spi_elba_init(struct platform_device *pd= ev, return 0; } =20 +static int dw_spi_jhb100_set_addr_nbyte(struct spi_device *spi, u8 nbyte) +{ + struct dw_spi *dws =3D spi_controller_get_devdata(spi->controller); + struct dw_spi_mmio *dwsmmio =3D container_of(dws, struct dw_spi_mmio, dws= ); + struct regmap *syscon =3D dwsmmio->priv; + + if (nbyte =3D=3D 3) { + regmap_update_bits(syscon, JHB100_ADDRMODE_CS, + BIT(spi_get_chipselect(spi, 0)), + 0); + } else if (nbyte =3D=3D 4) { + regmap_update_bits(syscon, JHB100_ADDRMODE_CS, + BIT(spi_get_chipselect(spi, 0)), + BIT(spi_get_chipselect(spi, 0))); + } else { + dev_err(&spi->dev, "Unsupported address nbyte %d\n", nbyte); + return -EINVAL; + } + + return 0; +} + +static int dw_spi_jhb100_resume(struct dw_spi_mmio *dwsmmio) +{ + dw_spi_jhb100_mask_intr(&dwsmmio->dws, 0xff); + + return 0; +} + +static int dw_spi_jhb100_init(struct platform_device *pdev, + struct dw_spi_mmio *dwsmmio) +{ + struct regmap *syscon; + + syscon =3D syscon_regmap_lookup_by_phandle(dev_of_node(&pdev->dev), + "starfive,sfc-filter-syscon"); + if (IS_ERR(syscon)) + return dev_err_probe(&pdev->dev, PTR_ERR(syscon), + "syscon regmap lookup failed\n"); + + dwsmmio->priv =3D syscon; + dwsmmio->platform_resume =3D dw_spi_jhb100_resume; + + dwsmmio->dws.set_addr_nbyte =3D dw_spi_jhb100_set_addr_nbyte; + dwsmmio->dws.ip =3D DW_HSSI_ID; + dwsmmio->dws.quirk_flags =3D DW_SPI_QUIRK_JHB100; + + dw_spi_jhb100_mask_intr(&dwsmmio->dws, 0xff); + + return 0; +} + static int dw_spi_mmio_probe(struct platform_device *pdev) { int (*init_func)(struct platform_device *pdev, @@ -399,6 +455,9 @@ static int dw_spi_mmio_suspend(struct device *dev) if (ret) return ret; =20 + if (dwsmmio->platform_suspend) + dwsmmio->platform_suspend(dwsmmio); + reset_control_assert(dwsmmio->rstc); =20 clk_disable_unprepare(dwsmmio->pclk); @@ -410,12 +469,24 @@ static int dw_spi_mmio_suspend(struct device *dev) static int dw_spi_mmio_resume(struct device *dev) { struct dw_spi_mmio *dwsmmio =3D dev_get_drvdata(dev); + int ret; =20 clk_prepare_enable(dwsmmio->clk); clk_prepare_enable(dwsmmio->pclk); =20 reset_control_deassert(dwsmmio->rstc); =20 + if (dwsmmio->platform_resume) { + ret =3D dwsmmio->platform_resume(dwsmmio); + if (ret) { + reset_control_assert(dwsmmio->rstc); + + clk_disable_unprepare(dwsmmio->pclk); + clk_disable_unprepare(dwsmmio->clk); + return ret; + } + } + return dw_spi_resume_controller(&dwsmmio->dws); } =20 @@ -447,6 +518,7 @@ static const struct of_device_id dw_spi_mmio_of_match[]= =3D { { .compatible =3D "microchip,sparx5-spi", dw_spi_mscc_sparx5_init}, { .compatible =3D "canaan,k210-spi", dw_spi_canaan_k210_init}, { .compatible =3D "amd,pensando-elba-spi", .data =3D dw_spi_elba_init}, + { .compatible =3D "starfive,jhb100-sfc", .data =3D dw_spi_jhb100_init}, { /* end of table */} }; MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match); diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index 2dae81c15423..2fce5bde75f0 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -67,6 +67,11 @@ #define DW_SPI_SPI_CTRLR0 0xf4 #define DW_SPI_CS_OVERRIDE 0xf4 =20 +/* Register offsets (StarFive JHB100 DWC SSI IP-cores) */ +#define DW_SPI_JHB100_INST 0x1000 +#define DW_SPI_JHB100_ADDR 0x1004 +#define DW_SPI_JHB100_FILTER_IMR 0x1008 + /* Bit fields in CTRLR0 (DWC APB SSI) */ #define DW_PSSI_CTRLR0_DFS_MASK GENMASK(3, 0) #define DW_PSSI_CTRLR0_DFS32_MASK GENMASK(20, 16) @@ -199,6 +204,7 @@ struct dw_spi { u32 num_cs; /* chip select lines */ u16 bus_num; void (*set_cs)(struct spi_device *spi, bool enable); + int (*set_addr_nbyte)(struct spi_device *spi, u8 nbyte); =20 /* Current message transfer state info */ void *tx; @@ -228,6 +234,9 @@ struct dw_spi { const struct dw_spi_dma_ops *dma_ops; struct completion dma_completion; =20 +#define DW_SPI_QUIRK_JHB100 BIT(0) + u32 quirk_flags; + #ifdef CONFIG_DEBUG_FS struct dentry *debugfs; struct debugfs_regset32 regset; @@ -296,6 +305,15 @@ static inline void dw_spi_umask_intr(struct dw_spi *dw= s, u32 mask) dw_writel(dws, DW_SPI_IMR, new_mask); } =20 +/* Disable JHB100 SPI filter IRQ bits */ +static inline void dw_spi_jhb100_mask_intr(struct dw_spi *dws, u32 mask) +{ + u32 new_mask; + + new_mask =3D dw_readl(dws, DW_SPI_JHB100_FILTER_IMR) & ~mask; + dw_writel(dws, DW_SPI_JHB100_FILTER_IMR, new_mask); +} + /* * This disables the SPI controller, interrupts, clears the interrupts sta= tus * and CS, then re-enables the controller back. Transmit and receive FIFO --=20 2.25.1