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Mon, 03 Aug 2026 04:21:21 -0700 (PDT) From: Tomer Maimon To: andrew@codeconstruct.com.au, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: openbmc@lists.ozlabs.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, avifishman70@gmail.com, tmaimon77@gmail.com, tali.perry1@gmail.com, venture@google.com, yuenn@google.com, benjaminfair@google.com Subject: [PATCH v9 1/5] arm64: dts: nuvoton: npcm845: Drop redundant timer clock-names Date: Mon, 3 Aug 2026 14:19:02 +0300 Message-Id: <20260803111906.1931384-2-tmaimon77@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260803111906.1931384-1-tmaimon77@gmail.com> References: <20260803111906.1931384-1-tmaimon77@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The NPCM845 timer0 node references a single clock, but its clock-names property is not described by the timer binding. Drop the undocumented name so the DTS matches the binding. Signed-off-by: Tomer Maimon --- arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch= /arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi index c781190b4..9e4fa2669 100644 --- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi @@ -73,7 +73,6 @@ timer0: timer@8000 { interrupts =3D ; reg =3D <0x8000 0x1C>; clocks =3D <&refclk>; - clock-names =3D "refclk"; }; =20 serial0: serial@0 { --=20 2.34.1 From nobody Fri Oct 2 08:24:49 2026 Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EB8E9400966 for ; Mon, 3 Aug 2026 11:21:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.47 ARC-Seal: i=1; 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Mon, 03 Aug 2026 04:21:24 -0700 (PDT) Received: from taln60.nuvoton.co.il ([212.199.177.18]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47fd458adc9sm34154913f8f.27.2026.08.03.04.21.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 04:21:23 -0700 (PDT) From: Tomer Maimon To: andrew@codeconstruct.com.au, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: openbmc@lists.ozlabs.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, avifishman70@gmail.com, tmaimon77@gmail.com, tali.perry1@gmail.com, venture@google.com, yuenn@google.com, benjaminfair@google.com Subject: [PATCH v9 2/5] arm64: dts: nuvoton: npcm845: Reorder timer0 and PECI nodes Date: Mon, 3 Aug 2026 14:19:03 +0300 Message-Id: <20260803111906.1931384-3-tmaimon77@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260803111906.1931384-1-tmaimon77@gmail.com> References: <20260803111906.1931384-1-tmaimon77@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move the timer0 and PECI nodes so the APB children are ordered by ascending unit address. Signed-off-by: Tomer Maimon --- .../dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 32 +++++++++---------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch= /arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi index 9e4fa2669..545034ac1 100644 --- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi @@ -59,22 +59,6 @@ apb { ranges =3D <0x0 0x0 0xf0000000 0x00300000>, <0xfff00000 0x0 0xfff00000 0x00016000>; =20 - peci: peci-controller@100000 { - compatible =3D "nuvoton,npcm845-peci"; - reg =3D <0x100000 0x1000>; - interrupts =3D ; - clocks =3D <&clk NPCM8XX_CLK_APB3>; - cmd-timeout-ms =3D <1000>; - status =3D "disabled"; - }; - - timer0: timer@8000 { - compatible =3D "nuvoton,npcm845-timer"; - interrupts =3D ; - reg =3D <0x8000 0x1C>; - clocks =3D <&refclk>; - }; - serial0: serial@0 { compatible =3D "nuvoton,npcm845-uart", "nuvoton,npcm750-uart"; reg =3D <0x0 0x1000>; @@ -138,6 +122,13 @@ serial6: serial@6000 { status =3D "disabled"; }; =20 + timer0: timer@8000 { + compatible =3D "nuvoton,npcm845-timer"; + interrupts =3D ; + reg =3D <0x8000 0x1C>; + clocks =3D <&refclk>; + }; + watchdog0: watchdog@801c { compatible =3D "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt"; interrupts =3D ; @@ -161,6 +152,15 @@ watchdog2: watchdog@a01c { status =3D "disabled"; clocks =3D <&refclk>; }; + + peci: peci-controller@100000 { + compatible =3D "nuvoton,npcm845-peci"; + reg =3D <0x100000 0x1000>; + interrupts =3D ; + clocks =3D <&clk NPCM8XX_CLK_APB3>; + cmd-timeout-ms =3D <1000>; + status =3D "disabled"; + }; }; }; =20 --=20 2.34.1 From nobody Fri Oct 2 08:24:49 2026 Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0AD913FC5A4 for ; Mon, 3 Aug 2026 11:21:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 03 Aug 2026 04:21:26 -0700 (PDT) Received: from taln60.nuvoton.co.il ([212.199.177.18]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47fd458adc9sm34154913f8f.27.2026.08.03.04.21.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 04:21:25 -0700 (PDT) From: Tomer Maimon To: andrew@codeconstruct.com.au, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: openbmc@lists.ozlabs.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, avifishman70@gmail.com, tmaimon77@gmail.com, tali.perry1@gmail.com, venture@google.com, yuenn@google.com, benjaminfair@google.com Subject: [PATCH v9 3/5] arm64: dts: nuvoton: npcm845: Add peripheral nodes Date: Mon, 3 Aug 2026 14:19:04 +0300 Message-Id: <20260803111906.1931384-4-tmaimon77@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260803111906.1931384-1-tmaimon77@gmail.com> References: <20260803111906.1931384-1-tmaimon77@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Extend the NPCM845 SoC DTSI with the peripheral controller nodes needed by the evaluation board and downstream platforms. Add the Ethernet MACs, USB device controllers and PHY, MMC controller, FIU controllers, memory controller, RNG, ADC, PWM/FAN controller, PSPI, and I2C buses. Also add the OP-TEE firmware node needed to describe these blocks. Signed-off-by: Tomer Maimon --- .../dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 688 ++++++++++++++++++ .../boot/dts/nuvoton/nuvoton-npcm845.dtsi | 7 + 2 files changed, 695 insertions(+) diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch= /arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi index 545034ac1..32ee8d284 100644 --- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi @@ -4,6 +4,7 @@ #include #include #include +#include =20 / { #address-cells =3D <2>; @@ -35,6 +36,11 @@ gic: interrupt-controller@dfff9000 { }; }; =20 + udc0_phy: usb-phy { + compatible =3D "usb-nop-xceiv"; + #phy-cells =3D <0>; + }; + ahb { #address-cells =3D <2>; #size-cells =3D <2>; @@ -51,6 +57,252 @@ clk: rstc: reset-controller@f0801000 { #clock-cells =3D <1>; }; =20 + gmac1: ethernet@f0804000 { + device_type =3D "network"; + compatible =3D "snps,dwmac-3.72a", "snps,dwmac"; + reg =3D <0x0 0xf0804000 0x0 0x2000>; + interrupts =3D ; + interrupt-names =3D "macirq"; + clocks =3D <&clk NPCM8XX_CLK_AHB>; + clock-names =3D "stmmaceth"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rg2_pins + &rg2mdio_pins>; + status =3D "disabled"; + }; + + gmac2: ethernet@f0806000 { + device_type =3D "network"; + compatible =3D "snps,dwmac-3.72a", "snps,dwmac"; + reg =3D <0x0 0xf0806000 0x0 0x2000>; + interrupts =3D ; + interrupt-names =3D "macirq"; + clocks =3D <&clk NPCM8XX_CLK_AHB>; + clock-names =3D "stmmaceth"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&r1_pins + &r1err_pins + &r1md_pins>; + status =3D "disabled"; + }; + + gmac3: ethernet@f0808000 { + device_type =3D "network"; + compatible =3D "snps,dwmac-3.72a", "snps,dwmac"; + reg =3D <0x0 0xf0808000 0x0 0x2000>; + interrupts =3D ; + interrupt-names =3D "macirq"; + clocks =3D <&clk NPCM8XX_CLK_AHB>; + clock-names =3D "stmmaceth"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&r2_pins + &r2err_pins + &r2md_pins>; + status =3D "disabled"; + }; + + mc: memory-controller@f0824000 { + compatible =3D "nuvoton,npcm845-memory-controller"; + reg =3D <0x0 0xf0824000 0x0 0x1000>; + interrupts =3D ; + }; + + udc0: usb@f0830000 { + compatible =3D "nuvoton,npcm845-udc", "nuvoton,npcm750-udc"; + reg =3D <0x0 0xf0830000 0x0 0x1000 + 0x0 0xfffeb000 0x0 0x800>; + interrupts =3D ; + clocks =3D <&clk NPCM8XX_CLK_SU>; + clock-names =3D "clk_usb_bridge"; + + phys =3D <&udc0_phy>; + phy_type =3D "utmi_wide"; + dr_mode =3D "peripheral"; + status =3D "disabled"; + }; + + udc1: usb@f0831000 { + compatible =3D "nuvoton,npcm845-udc", "nuvoton,npcm750-udc"; + reg =3D <0x0 0xf0831000 0x0 0x1000 + 0x0 0xfffeb800 0x0 0x800>; + interrupts =3D ; + clocks =3D <&clk NPCM8XX_CLK_SU>; + clock-names =3D "clk_usb_bridge"; + + phys =3D <&udc0_phy>; + phy_type =3D "utmi_wide"; + dr_mode =3D "peripheral"; + status =3D "disabled"; + }; + + udc2: usb@f0832000 { + compatible =3D "nuvoton,npcm845-udc", "nuvoton,npcm750-udc"; + reg =3D <0x0 0xf0832000 0x0 0x1000 + 0x0 0xfffec000 0x0 0x800>; + interrupts =3D ; + clocks =3D <&clk NPCM8XX_CLK_SU>; + clock-names =3D "clk_usb_bridge"; + + phys =3D <&udc0_phy>; + phy_type =3D "utmi_wide"; + dr_mode =3D "peripheral"; + status =3D "disabled"; + }; + + udc3: usb@f0833000 { + compatible =3D "nuvoton,npcm845-udc", "nuvoton,npcm750-udc"; + reg =3D <0x0 0xf0833000 0x0 0x1000 + 0x0 0xfffec800 0x0 0x800>; + interrupts =3D ; + clocks =3D <&clk NPCM8XX_CLK_SU>; + clock-names =3D "clk_usb_bridge"; + + phys =3D <&udc0_phy>; + phy_type =3D "utmi_wide"; + dr_mode =3D "peripheral"; + status =3D "disabled"; + }; + + udc4: usb@f0834000 { + compatible =3D "nuvoton,npcm845-udc", "nuvoton,npcm750-udc"; + reg =3D <0x0 0xf0834000 0x0 0x1000 + 0x0 0xfffed000 0x0 0x800>; + interrupts =3D ; + clocks =3D <&clk NPCM8XX_CLK_SU>; + clock-names =3D "clk_usb_bridge"; + + phys =3D <&udc0_phy>; + phy_type =3D "utmi_wide"; + dr_mode =3D "peripheral"; + status =3D "disabled"; + }; + + udc5: usb@f0835000 { + compatible =3D "nuvoton,npcm845-udc", "nuvoton,npcm750-udc"; + reg =3D <0x0 0xf0835000 0x0 0x1000 + 0x0 0xfffed800 0x0 0x800>; + interrupts =3D ; + clocks =3D <&clk NPCM8XX_CLK_SU>; + clock-names =3D "clk_usb_bridge"; + + phys =3D <&udc0_phy>; + phy_type =3D "utmi_wide"; + dr_mode =3D "peripheral"; + status =3D "disabled"; + }; + + udc6: usb@f0836000 { + compatible =3D "nuvoton,npcm845-udc", "nuvoton,npcm750-udc"; + reg =3D <0x0 0xf0836000 0x0 0x1000 + 0x0 0xfffee000 0x0 0x800>; + interrupts =3D ; + clocks =3D <&clk NPCM8XX_CLK_SU>; + clock-names =3D "clk_usb_bridge"; + + phys =3D <&udc0_phy>; + phy_type =3D "utmi_wide"; + dr_mode =3D "peripheral"; + status =3D "disabled"; + }; + + udc7: usb@f0837000 { + compatible =3D "nuvoton,npcm845-udc", "nuvoton,npcm750-udc"; + reg =3D <0x0 0xf0837000 0x0 0x1000 + 0x0 0xfffee800 0x0 0x800>; + interrupts =3D ; + clocks =3D <&clk NPCM8XX_CLK_SU>; + clock-names =3D "clk_usb_bridge"; + + phys =3D <&udc0_phy>; + phy_type =3D "utmi_wide"; + dr_mode =3D "peripheral"; + status =3D "disabled"; + }; + + udc8: usb@f0838000 { + compatible =3D "nuvoton,npcm845-udc", "nuvoton,npcm750-udc"; + reg =3D <0x0 0xf0838000 0x0 0x1000 + 0x0 0xfffef000 0x0 0x800>; + interrupts =3D ; + clocks =3D <&clk NPCM8XX_CLK_SU>; + clock-names =3D "clk_usb_bridge"; + + phys =3D <&udc0_phy>; + phy_type =3D "utmi_wide"; + dr_mode =3D "peripheral"; + status =3D "disabled"; + }; + + udc9: usb@f0839000 { + compatible =3D "nuvoton,npcm845-udc", "nuvoton,npcm750-udc"; + reg =3D <0x0 0xf0839000 0x0 0x1000 + 0x0 0xfffef800 0x0 0x800>; + interrupts =3D ; + clocks =3D <&clk NPCM8XX_CLK_SU>; + clock-names =3D "clk_usb_bridge"; + + phys =3D <&udc0_phy>; + phy_type =3D "utmi_wide"; + dr_mode =3D "peripheral"; + status =3D "disabled"; + }; + + sdhci: mmc@f0842000 { + compatible =3D "nuvoton,npcm845-sdhci"; + reg =3D <0x0 0xf0842000 0x0 0x100>; + interrupts =3D ; + clocks =3D <&clk NPCM8XX_CLK_AHB>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mmc8_pins + &mmc_pins>; + status =3D "disabled"; + }; + + fiu0: spi@fb000000 { + compatible =3D "nuvoton,npcm845-fiu"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x0 0xfb000000 0x0 0x1000>; + reg-names =3D "control"; + clocks =3D <&clk NPCM8XX_CLK_SPI0>; + status =3D "disabled"; + }; + + fiu1: spi@fb002000 { + compatible =3D "nuvoton,npcm845-fiu"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x0 0xfb002000 0x0 0x1000>; + reg-names =3D "control"; + clocks =3D <&clk NPCM8XX_CLK_SPI1>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi1_pins>; + status =3D "disabled"; + }; + + fiu3: spi@c0000000 { + compatible =3D "nuvoton,npcm845-fiu"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x0 0xc0000000 0x0 0x1000>; + reg-names =3D "control"; + clocks =3D <&clk NPCM8XX_CLK_SPI3>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi3_pins>; + status =3D "disabled"; + }; + + fiux: spi@fb001000 { + compatible =3D "nuvoton,npcm845-fiu"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x0 0xfb001000 0x0 0x1000>, + <0x0 0xf8000000 0x0 0x2000000>; + reg-names =3D "control", "memory"; + clocks =3D <&clk NPCM8XX_CLK_SPIX>; + status =3D "disabled"; + }; + apb { #address-cells =3D <1>; #size-cells =3D <1>; @@ -153,6 +405,393 @@ watchdog2: watchdog@a01c { clocks =3D <&refclk>; }; =20 + rng: rng@b000 { + compatible =3D "nuvoton,npcm845-rng"; + reg =3D <0xb000 0x8>; + status =3D "disabled"; + }; + + adc: adc@c000 { + compatible =3D "nuvoton,npcm845-adc"; + reg =3D <0xC000 0x8>; + interrupts =3D ; + clocks =3D <&clk NPCM8XX_CLK_ADC>; + resets =3D <&rstc 0x20 27>; + status =3D "disabled"; + }; + + i2c0: i2c@80000 { + reg =3D <0x80000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb0_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c1: i2c@81000 { + reg =3D <0x81000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb1_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c2: i2c@82000 { + reg =3D <0x82000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb2_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c3: i2c@83000 { + reg =3D <0x83000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb3_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c4: i2c@84000 { + reg =3D <0x84000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb4_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c5: i2c@85000 { + reg =3D <0x85000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb5_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c6: i2c@86000 { + reg =3D <0x86000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb6_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c7: i2c@87000 { + reg =3D <0x87000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb7_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c8: i2c@88000 { + reg =3D <0x88000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb8_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c9: i2c@89000 { + reg =3D <0x89000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb9_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c10: i2c@8a000 { + reg =3D <0x8a000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb10_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c11: i2c@8b000 { + reg =3D <0x8b000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb11_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c12: i2c@8c000 { + reg =3D <0x8c000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb12_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c13: i2c@8d000 { + reg =3D <0x8d000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb13_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c14: i2c@8e000 { + reg =3D <0x8e000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb14_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c15: i2c@8f000 { + reg =3D <0x8f000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb15_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c16: i2c@fff00000 { + reg =3D <0xfff00000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb16_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c17: i2c@fff01000 { + reg =3D <0xfff01000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb17_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c18: i2c@fff02000 { + reg =3D <0xfff02000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb18_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c19: i2c@fff03000 { + reg =3D <0xfff03000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb19_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c20: i2c@fff04000 { + reg =3D <0xfff04000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb20_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c21: i2c@fff05000 { + reg =3D <0xfff05000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb21_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c22: i2c@fff06000 { + reg =3D <0xfff06000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb22_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c23: i2c@fff07000 { + reg =3D <0xfff07000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&smb23_pins>; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c24: i2c@fff08000 { + reg =3D <0xfff08000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c25: i2c@fff09000 { + reg =3D <0xfff09000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + + i2c26: i2c@fff0a000 { + reg =3D <0xfff0a000 0x1000>; + compatible =3D "nuvoton,npcm845-i2c"; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk NPCM8XX_CLK_APB2>; + clock-frequency =3D <100000>; + interrupts =3D ; + nuvoton,sys-mgr =3D <&gcr>; + status =3D "disabled"; + }; + peci: peci-controller@100000 { compatible =3D "nuvoton,npcm845-peci"; reg =3D <0x100000 0x1000>; @@ -161,6 +800,55 @@ peci: peci-controller@100000 { cmd-timeout-ms =3D <1000>; status =3D "disabled"; }; + + pwm_fan:pwm-fan-controller@103000 { + compatible =3D "nuvoton,npcm845-pwm-fan"; + reg =3D <0x103000 0x3000>, + <0x180000 0x8000>; + reg-names =3D "pwm", "fan"; + clocks =3D <&clk NPCM8XX_CLK_APB3>, + <&clk NPCM8XX_CLK_APB4>; + clock-names =3D "pwm","fan"; + interrupts =3D , + , + , + , + , + , + , + ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwm0_pins &pwm1_pins + &pwm2_pins &pwm3_pins + &pwm4_pins &pwm5_pins + &pwm6_pins &pwm7_pins + &pwm8_pins &pwm9_pins + &pwm10_pins &pwm11_pins + &fanin0_pins &fanin1_pins + &fanin2_pins &fanin3_pins + &fanin4_pins &fanin5_pins + &fanin6_pins &fanin7_pins + &fanin8_pins &fanin9_pins + &fanin10_pins &fanin11_pins + &fanin12_pins &fanin13_pins + &fanin14_pins &fanin15_pins>; + status =3D "disabled"; + }; + + pspi: spi@201000 { + compatible =3D "nuvoton,npcm845-pspi"; + reg =3D <0x201000 0x1000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pspi_pins>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clocks =3D <&clk NPCM8XX_CLK_APB5>; + clock-names =3D "clk_apb5"; + resets =3D <&rstc 0x24 23>; + status =3D "disabled"; + }; + }; }; =20 diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi b/arch/arm64/= boot/dts/nuvoton/nuvoton-npcm845.dtsi index 8239d9a9f..0be38b062 100644 --- a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi @@ -75,4 +75,11 @@ timer { , ; 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Mon, 03 Aug 2026 04:21:27 -0700 (PDT) From: Tomer Maimon To: andrew@codeconstruct.com.au, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: openbmc@lists.ozlabs.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, avifishman70@gmail.com, tmaimon77@gmail.com, tali.perry1@gmail.com, venture@google.com, yuenn@google.com, benjaminfair@google.com Subject: [PATCH v9 4/5] arm64: dts: nuvoton: npcm845-evb: Fix DTS coding style Date: Mon, 3 Aug 2026 14:19:05 +0300 Message-Id: <20260803111906.1931384-5-tmaimon77@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260803111906.1931384-1-tmaimon77@gmail.com> References: <20260803111906.1931384-1-tmaimon77@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Reorder the pre-existing NPCM845 EVB DTS properties so the base board file follows strict dt-check-style canonical ordering. Keep this cleanup separate from the peripheral enablement changes so the functional EVB additions remain focused. Signed-off-by: Tomer Maimon --- arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts b/arch/arm= 64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts index 5edf5d133..2dc1a4fbb 100644 --- a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts @@ -5,8 +5,8 @@ #include "nuvoton-npcm845.dtsi" =20 / { - model =3D "Nuvoton npcm845 Development Board (Device Tree)"; compatible =3D "nuvoton,npcm845-evb", "nuvoton,npcm845"; + model =3D "Nuvoton npcm845 Development Board (Device Tree)"; =20 aliases { serial0 =3D &serial0; @@ -17,14 +17,14 @@ chosen { }; =20 memory@0 { - device_type =3D "memory"; reg =3D <0x0 0x0 0x0 0x40000000>; + device_type =3D "memory"; }; =20 refclk: refclk-25mhz { compatible =3D "fixed-clock"; - clock-frequency =3D <25000000>; #clock-cells =3D <0>; + clock-frequency =3D <25000000>; }; }; =20 --=20 2.34.1 From nobody Fri Oct 2 08:24:49 2026 Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC2F43FFACC for ; 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Mon, 03 Aug 2026 04:21:30 -0700 (PDT) Received: from taln60.nuvoton.co.il ([212.199.177.18]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47fd458adc9sm34154913f8f.27.2026.08.03.04.21.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 04:21:29 -0700 (PDT) From: Tomer Maimon To: andrew@codeconstruct.com.au, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: openbmc@lists.ozlabs.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, avifishman70@gmail.com, tmaimon77@gmail.com, tali.perry1@gmail.com, venture@google.com, yuenn@google.com, benjaminfair@google.com Subject: [PATCH v9 5/5] arm64: dts: nuvoton: npcm845-evb: Add peripheral nodes Date: Mon, 3 Aug 2026 14:19:06 +0300 Message-Id: <20260803111906.1931384-6-tmaimon77@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260803111906.1931384-1-tmaimon77@gmail.com> References: <20260803111906.1931384-1-tmaimon77@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable peripheral support for the NPCM845 evaluation board by wiring up the SoC controller nodes to the board design. Add board aliases, GPIO-backed MDIO buses for the external PHYs, a reserved-memory region for TIP firmware, and flash partitions for the FIU boot flash. Enable the Ethernet MACs, MMC controller, FIU controllers, USB device controllers, ADC, RNG, PWM/FAN controller, I2C buses, and PECI interface with the board-specific pinctrl and PHY connections they require. Signed-off-by: Tomer Maimon --- .../boot/dts/nuvoton/nuvoton-npcm845-evb.dts | 435 ++++++++++++++++++ 1 file changed, 435 insertions(+) diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts b/arch/arm= 64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts index 2dc1a4fbb..3d88af388 100644 --- a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts @@ -9,6 +9,42 @@ / { model =3D "Nuvoton npcm845 Development Board (Device Tree)"; =20 aliases { + ethernet1 =3D &gmac1; + ethernet2 =3D &gmac2; + ethernet3 =3D &gmac3; + fiu0 =3D &fiu0; + fiu1 =3D &fiu3; + fiu2 =3D &fiux; + fiu3 =3D &fiu1; + i2c0 =3D &i2c0; + i2c1 =3D &i2c1; + i2c2 =3D &i2c2; + i2c3 =3D &i2c3; + i2c4 =3D &i2c4; + i2c5 =3D &i2c5; + i2c6 =3D &i2c6; + i2c7 =3D &i2c7; + i2c8 =3D &i2c8; + i2c9 =3D &i2c9; + i2c10 =3D &i2c10; + i2c11 =3D &i2c11; + i2c12 =3D &i2c12; + i2c13 =3D &i2c13; + i2c14 =3D &i2c14; + i2c15 =3D &i2c15; + i2c16 =3D &i2c16; + i2c17 =3D &i2c17; + i2c18 =3D &i2c18; + i2c19 =3D &i2c19; + i2c20 =3D &i2c20; + i2c21 =3D &i2c21; + i2c22 =3D &i2c22; + i2c23 =3D &i2c23; + i2c24 =3D &i2c24; + i2c25 =3D &i2c25; + i2c26 =3D &i2c26; + mdio-gpio0 =3D &mdio0; + mdio-gpio1 =3D &mdio1; serial0 =3D &serial0; }; =20 @@ -16,6 +52,30 @@ chosen { stdout-path =3D &serial0; }; =20 + mdio0: mdio-0 { + compatible =3D "virtual,mdio-gpio"; + #address-cells =3D <1>; + gpios =3D <&gpio1 25 GPIO_ACTIVE_HIGH>, + <&gpio1 26 GPIO_ACTIVE_HIGH>; + #size-cells =3D <0>; + + phy0: ethernet-phy@0 { + reg =3D <0>; + }; + }; + + mdio1: mdio-1 { + compatible =3D "virtual,mdio-gpio"; + #address-cells =3D <1>; + gpios =3D <&gpio2 27 GPIO_ACTIVE_HIGH>, + <&gpio2 28 GPIO_ACTIVE_HIGH>; + #size-cells =3D <0>; + + phy1: ethernet-phy@0 { + reg =3D <0>; + }; + }; + memory@0 { reg =3D <0x0 0x0 0x0 0x40000000>; device_type =3D "memory"; @@ -26,12 +86,387 @@ refclk: refclk-25mhz { #clock-cells =3D <0>; clock-frequency =3D <25000000>; }; + + reserved-memory { + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + + tip@0 { + reg =3D <0x0 0x0 0x0 0x6200000>; + no-map; + }; + }; +}; + +&gmac1 { + phy-mode =3D "rgmii-id"; + + status =3D "okay"; +}; + +&gmac2 { + phy-handle =3D <&phy0>; + phy-mode =3D "rmii"; + pinctrl-0 =3D <&r1_pins + &r1oen_pins>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&gmac3 { + phy-handle =3D <&phy1>; + phy-mode =3D "rmii"; + pinctrl-0 =3D <&r2_pins + &r2oen_pins>; + pinctrl-names =3D "default"; + + status =3D "okay"; }; =20 &serial0 { status =3D "okay"; }; =20 +&fiu0 { + status =3D "okay"; + + flash@0 { + compatible =3D "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <5000000>; + spi-rx-bus-width =3D <1>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + bmc@0 { + compatible =3D "fixed-partitions"; + reg =3D <0x00000000 0x04000000>; + #address-cells =3D <1>; + label =3D "bmc"; + #size-cells =3D <1>; + + u-boot@0 { + reg =3D <0x00000000 0x007c0000>; + label =3D "u-boot"; + }; + + u-boot-env@7c0000 { + reg =3D <0x007c0000 0x00040000>; + label =3D "u-boot-env"; + }; + + kernel@800000 { + reg =3D <0x00800000 0x00800000>; + label =3D "kernel"; + }; + + rofs@1000000 { + reg =3D <0x01000000 0x02c00000>; + label =3D "rofs"; + }; + + rwfs@3c00000 { + reg =3D <0x03c00000 0x00400000>; + label =3D "rwfs"; + }; + }; + }; + }; +}; + +&fiu1 { + status =3D "okay"; + + flash@0 { + compatible =3D "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <5000000>; + spi-rx-bus-width =3D <2>; + spi-tx-bus-width =3D <2>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + reg =3D <0x0 0x0>; + label =3D "spi1-system1"; + }; + }; + }; +}; + +&fiu3 { + pinctrl-0 =3D <&spi3_pins>, <&spi3quad_pins>; + pinctrl-names =3D "default"; + + status =3D "okay"; + + flash@0 { + compatible =3D "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <5000000>; + spi-rx-bus-width =3D <1>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + reg =3D <0x0 0x0>; + label =3D "spi3-system1"; + }; + }; + }; +}; + +&fiux { + nuvoton,spix-mode; + + status =3D "okay"; +}; + +&sdhci { + status =3D "okay"; +}; + +&udc0 { + status =3D "okay"; +}; + +&udc1 { + status =3D "okay"; +}; + +&udc2 { + status =3D "okay"; +}; + +&udc3 { + status =3D "okay"; +}; + +&udc4 { + status =3D "okay"; +}; + +&udc5 { + status =3D "okay"; +}; + +&udc6 { + status =3D "okay"; +}; + +&udc7 { + status =3D "okay"; +}; + +&mc { + status =3D "okay"; +}; + +&peci { + status =3D "okay"; +}; + +&rng { + status =3D "okay"; +}; + +&adc { + #io-channel-cells =3D <1>; + + status =3D "okay"; +}; + &watchdog1 { status =3D "okay"; }; + +&pwm_fan { + #address-cells =3D <1>; + pinctrl-0 =3D <&pwm0_pins &pwm1_pins + &pwm2_pins &pwm3_pins + &pwm4_pins &pwm5_pins + &pwm6_pins &pwm7_pins + &fanin0_pins &fanin1_pins + &fanin2_pins &fanin3_pins + &fanin4_pins &fanin5_pins + &fanin6_pins &fanin7_pins>; + pinctrl-names =3D "default"; + #size-cells =3D <0>; + + status =3D "okay"; + + fan@0 { + reg =3D <0x00>; + cooling-levels =3D <127 255>; + fan-tach-ch =3D /bits/ 8 <0x0 0x1>; + }; + + fan@1 { + reg =3D <0x01>; + cooling-levels =3D <127 255>; + fan-tach-ch =3D /bits/ 8 <0x2 0x3>; + }; + + fan@2 { + reg =3D <0x02>; + cooling-levels =3D <127 255>; + fan-tach-ch =3D /bits/ 8 <0x4 0x5>; + }; + + fan@3 { + reg =3D <0x03>; + cooling-levels =3D <127 255>; + fan-tach-ch =3D /bits/ 8 <0x6 0x7>; + }; + + fan@4 { + reg =3D <0x04>; + cooling-levels =3D <127 255>; + fan-tach-ch =3D /bits/ 8 <0x8 0x9>; + }; + + fan@5 { + reg =3D <0x05>; + cooling-levels =3D <127 255>; + fan-tach-ch =3D /bits/ 8 <0xa 0xb>; + }; + + fan@6 { + reg =3D <0x06>; + cooling-levels =3D <127 255>; + fan-tach-ch =3D /bits/ 8 <0xc 0xd>; + }; + + fan@7 { + reg =3D <0x07>; + cooling-levels =3D <127 255>; + fan-tach-ch =3D /bits/ 8 <0xe 0xf>; + }; +}; + +&i2c0 { + status =3D "okay"; +}; + +&i2c1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "okay"; + + eeprom@50 { + compatible =3D "atmel,24c256"; + reg =3D <0x50>; + }; +}; + +&i2c2 { + status =3D "okay"; +}; + +&i2c3 { + status =3D "okay"; +}; + +&i2c4 { + status =3D "okay"; +}; + +&i2c5 { + status =3D "okay"; +}; + +&i2c6 { + status =3D "okay"; +}; + +&i2c7 { + status =3D "okay"; +}; + +&i2c8 { + status =3D "okay"; +}; + +&i2c9 { + status =3D "okay"; +}; + +&i2c10 { + status =3D "okay"; +}; + +&i2c11 { + status =3D "okay"; +}; + +&i2c12 { + status =3D "okay"; +}; + +&i2c13 { + status =3D "okay"; +}; + +&i2c14 { + status =3D "okay"; +}; + +&i2c15 { + status =3D "okay"; +}; + +&i2c16 { + status =3D "okay"; +}; + +&i2c17 { + status =3D "okay"; +}; + +&i2c18 { + status =3D "okay"; +}; + +&i2c19 { + status =3D "okay"; +}; + +&i2c20 { + status =3D "okay"; +}; + +&i2c21 { + status =3D "okay"; +}; + +&i2c22 { + status =3D "okay"; +}; + +&i2c23 { + status =3D "okay"; +}; + +&i2c24 { + status =3D "okay"; +}; + +&i2c25 { + status =3D "okay"; +}; + +&i2c26 { + status =3D "okay"; +}; --=20 2.34.1