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([188.243.183.76]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6a09c6566b3sm5355731a12.23.2026.08.03.03.17.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 03:17:39 -0700 (PDT) From: Artem Shimko To: netdev@vger.kernel.org, Andrew Lunn , Heiner Kallweit , Russell King , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Chevallier Cc: Artem Shimko , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH net-next v5 1/3] dt-bindings: vendor-prefixes: add Guangdong Dapu Telecom Co., Ltd. Date: Mon, 3 Aug 2026 13:17:32 +0300 Message-ID: <20260803101734.270821-2-a.shimko.dev@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260803101734.270821-1-a.shimko.dev@gmail.com> References: <20260803101734.270821-1-a.shimko.dev@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add vendor prefix for Guangdong Dapu Telecom Co., Ltd. [1], a manufacturer of Ethernet PHYs, networking and other equipment. The prefix will be used in the DAP8211R(I) Gigabit Ethernet PHY binding. [1] https://www.dptel.com/ Signed-off-by: Artem Shimko --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index 396044f368e7..c3db857b9837 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -403,6 +403,8 @@ patternProperties: description: CZ.NIC, z.s.p.o. "^dallas,.*": description: Maxim Integrated Products (formerly Dallas Semiconductor) + "^dapu,.*": + description: Guangdong Dapu Telecom Co., Ltd. "^dataimage,.*": description: DataImage, Inc. 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([188.243.183.76]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6a09c6566b3sm5355731a12.23.2026.08.03.03.17.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 03:17:41 -0700 (PDT) From: Artem Shimko To: netdev@vger.kernel.org, Andrew Lunn , Heiner Kallweit , Russell King , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Chevallier Cc: Artem Shimko , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH net-next v5 2/3] dt-bindings: net: add DAPU Telecom DAP8211R(I) PHY binding Date: Mon, 3 Aug 2026 13:17:33 +0300 Message-ID: <20260803101734.270821-3-a.shimko.dev@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260803101734.270821-1-a.shimko.dev@gmail.com> References: <20260803101734.270821-1-a.shimko.dev@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree binding documentation for the DAPU Telecom DAP8211R(I) Gigabit Ethernet PHY. The PHY supports TX and RX clock delays in 150 ps steps from 0 to 2250 ps, with a default of 1950 ps if not specified. Signed-off-by: Artem Shimko --- .../bindings/net/dapu,dap8211r.yaml | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/dapu,dap8211r.yaml diff --git a/Documentation/devicetree/bindings/net/dapu,dap8211r.yaml b/Doc= umentation/devicetree/bindings/net/dapu,dap8211r.yaml new file mode 100644 index 000000000000..fb78fa4f58ca --- /dev/null +++ b/Documentation/devicetree/bindings/net/dapu,dap8211r.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/dapu,dap8211r.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: DAPU Telecom DAP8211R(I) Gigabit Ethernet PHY + +maintainers: + - Artem Shimko + +description: | + The DAP8211R(I) is a Gigabit Ethernet PHY with RGMII interface, + supporting IEEE 802.3az Energy Efficient Ethernet, IEEE 1588 SyncE, + and an internal packet generator for diagnostics. + + Specifications: + - 10BASE-Te, 100BASE-TX, 1000BASE-T + - RGMII with configurable TX/RX clock delays (150 ps steps, 0-2250 ps) + - IEEE 802.3az-2010 Energy Efficient Ethernet + - IEEE 1588 SyncE support + - Internal packet generator and checker for link diagnostics + +allOf: + - $ref: ethernet-phy.yaml# + +properties: + compatible: + const: ethernet-phy-id0008.011b + + reg: + maxItems: 1 + + rx-internal-delay-ps: + description: + RGMII RX clock delay in picoseconds (0 to maximum). + multipleOf: 150 + maximum: 2250 + default: 1950 + + tx-internal-delay-ps: + description: + RGMII TX clock delay in picoseconds (0 to maximum). + multipleOf: 150 + maximum: 2250 + default: 1950 + +unevaluatedProperties: false + +examples: + - | + mdio { + #address-cells =3D <1>; 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([188.243.183.76]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6a09c6566b3sm5355731a12.23.2026.08.03.03.17.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 03:17:43 -0700 (PDT) From: Artem Shimko To: netdev@vger.kernel.org, Andrew Lunn , Heiner Kallweit , Russell King , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Chevallier Cc: Artem Shimko , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH net-next v5 3/3] net: phy: add DAPU Telecom DAP8211R(I) Gigabit Ethernet PHY driver Date: Mon, 3 Aug 2026 13:17:34 +0300 Message-ID: <20260803101734.270821-4-a.shimko.dev@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260803101734.270821-1-a.shimko.dev@gmail.com> References: <20260803101734.270821-1-a.shimko.dev@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a new PHY driver for the DAPU Telecom DAP8211R(I) Gigabit Ethernet PHY, which is commonly used in enterprise and industrial networking applications. The driver implements extended register access via indirect addressing through corresponding registers, and provides comprehensive device tree support for RGMII delay configuration. The rx-internal-delay-ps and tx-internal-delay-ps properties allow precise tuning of clock delays in 150 ps steps from 0 to 2250 ps. Signed-off-by: Artem Shimko --- drivers/net/phy/Kconfig | 9 ++ drivers/net/phy/Makefile | 1 + drivers/net/phy/dap8211r.c | 206 +++++++++++++++++++++++++++++++++++++ 3 files changed, 216 insertions(+) create mode 100644 drivers/net/phy/dap8211r.c diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 099f25dceabb..395bcd35bffa 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -232,6 +232,15 @@ config CORTINA_PHY help Currently supports the CS4340 phy. =20 +config DAP8211R_PHY + tristate "DAPU Telecom DAP8211R(I) Gigabit Ethernet PHY" + depends on OF + help + Support for the DAPU Telecom DAP8211R(I) Gigabit Ethernet PHY. + This PHY is designed for enterprise and industrial networking + applications, supporting 10/100/1000 Mbps operation. Supports + RGMII interface with configurable TX/RX clock delays. + config DAVICOM_PHY tristate "Davicom PHYs" help diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index de660ae94945..c72f7730e25d 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -52,6 +52,7 @@ obj-$(CONFIG_BCM_NET_PHYPTP) +=3D bcm-phy-ptp.o obj-$(CONFIG_BROADCOM_PHY) +=3D broadcom.o obj-$(CONFIG_CICADA_PHY) +=3D cicada.o obj-$(CONFIG_CORTINA_PHY) +=3D cortina.o +obj-$(CONFIG_DAP8211R_PHY) +=3D dap8211r.o obj-$(CONFIG_DAVICOM_PHY) +=3D davicom.o obj-$(CONFIG_DP83640_PHY) +=3D dp83640.o obj-$(CONFIG_DP83822_PHY) +=3D dp83822.o diff --git a/drivers/net/phy/dap8211r.c b/drivers/net/phy/dap8211r.c new file mode 100644 index 000000000000..f010ce0c3bd1 --- /dev/null +++ b/drivers/net/phy/dap8211r.c @@ -0,0 +1,206 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for the DAPU Telecom DAP8211R(I) Gigabit Ethernet PHY. + * + * Specifications: + * - IEEE 802.3 10BASE-Te, 100BASE-TX, 1000BASE-T + * - IEEE 802.3az-2010 Energy Efficient Ethernet + * - IEEE 1588 SyncE support + * - RGMII + * + * Author: Artem Shimko + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DAP8211R_PHY_ID 0x0008011B +#define DAP8211R_PHY_ID_MASK 0xFFFFFFFF + +#define DAP8211R_EXT_ADD 0x1E +#define DAP8211R_EXT_DATA 0x1F + +#define DAP8211R_PHY_CON 0xA001 +#define DAP8211R_PHY_SW_RST BIT(15) + +#define DAP8211R_RGMII_CON 0xA003 +#define DAP8211R_RGMII_TX_DEL_MASK GENMASK(3, 0) +#define DAP8211R_RGMII_RX_DEL_MASK GENMASK(13, 10) + +#define DAP8211R_RGMII_CONFIG_MASK (DAP8211R_RGMII_RX_DEL_MASK | DAP8211R_= RGMII_TX_DEL_MASK) + +/* Initial RGMII RX delay per hardware specification: 0 * 150ps =3D=3D 0.0= 0ns */ +#define DAP8211R_INITIAL_RX_DEL_VAL 0 +/* Initial RGMII TX delay per hardware specification: 1 * 150ps =3D=3D 0.1= 5ns*/ +#define DAP8211R_INITIAL_TX_DEL_VAL 1 +/* Default RGMII delay: 13 * 150 =3D=3D 1.95ns */ +#define DAP8211R_DEFAULT_DEL_SEL 0xD + +static const int dap8211r_internal_delay[] =3D {0, 150, 300, 450, 600, 750= , 900, + 1050, 1200, 1350, 1500, 1650, 1800, + 1950, 2100, 2250}; + +#define DAP8211R_DELAY_SIZE ARRAY_SIZE(dap8211r_internal_delay) + +/** + * dap8211r_read_ext() - Read extended register + * @phydev: PHY device structure + * @reg: Extended register address + * + * Reads a PHY extended register using the indirect access method. + * The caller must hold the MDIO bus lock. + * + * Return: Register value on success, or negative error code + */ +static int dap8211r_read_ext(struct phy_device *phydev, u16 reg) +{ + int ret; + + phy_lock_mdio_bus(phydev); + ret =3D __phy_write(phydev, DAP8211R_EXT_ADD, reg); + if (ret < 0) + goto out; + + ret =3D __phy_read(phydev, DAP8211R_EXT_DATA); +out: + phy_unlock_mdio_bus(phydev); + return ret; +} + +/** + * dap8211r_modify_ext() - Modify extended register bits + * @phydev: PHY device structure + * @reg: Extended register address + * @mask: Bit mask of bits to clear + * @set: Bit mask of bits to set + * + * Modifies a PHY extended register using the indirect access method. + * New value =3D (old value & ~mask) | set. + * The caller must hold the MDIO bus lock. + * + * Return: 0 on success, or negative error code + */ +static int dap8211r_modify_ext(struct phy_device *phydev, u16 reg, u16 mas= k, u16 set) +{ + int ret; + + phy_lock_mdio_bus(phydev); + ret =3D __phy_write(phydev, DAP8211R_EXT_ADD, reg); + if (ret < 0) + goto out; + + ret =3D __phy_modify(phydev, DAP8211R_EXT_DATA, mask, set); +out: + phy_unlock_mdio_bus(phydev); + return ret; +} + +/** + * dap8211r_config_init() - Initialize PHY + * @phydev: PHY device structure + * + * Configures the PHY during initialization: + * - RGMII delays based on interface mode + * - Software reset to apply settings (low active, self clear) + * + * Return: 0 on success, or negative error code + */ +static int dap8211r_config_init(struct phy_device *phydev) +{ + u16 set =3D 0; + int ret, val; + s32 rx_internal_delay =3D DAP8211R_INITIAL_RX_DEL_VAL; + s32 tx_internal_delay =3D DAP8211R_INITIAL_TX_DEL_VAL; + + if (!phy_interface_is_rgmii(phydev)) + return 0; + + if (phydev->interface !=3D PHY_INTERFACE_MODE_RGMII_TXID) + rx_internal_delay =3D phy_get_internal_delay(phydev, dap8211r_internal_d= elay, + DAP8211R_DELAY_SIZE, true); + + if (phydev->interface !=3D PHY_INTERFACE_MODE_RGMII_RXID) + tx_internal_delay =3D phy_get_internal_delay(phydev, dap8211r_internal_d= elay, + DAP8211R_DELAY_SIZE, false); + + switch (phydev->interface) { + case PHY_INTERFACE_MODE_RGMII: + if (rx_internal_delay < 0) + rx_internal_delay =3D DAP8211R_INITIAL_RX_DEL_VAL; + + if (tx_internal_delay < 0) + tx_internal_delay =3D DAP8211R_INITIAL_TX_DEL_VAL; + break; + case PHY_INTERFACE_MODE_RGMII_RXID: + if (rx_internal_delay < 0) + rx_internal_delay =3D DAP8211R_DEFAULT_DEL_SEL; + break; + case PHY_INTERFACE_MODE_RGMII_ID: + if (rx_internal_delay < 0) + rx_internal_delay =3D DAP8211R_DEFAULT_DEL_SEL; + fallthrough; + case PHY_INTERFACE_MODE_RGMII_TXID: + if (tx_internal_delay < 0) + tx_internal_delay =3D DAP8211R_DEFAULT_DEL_SEL; + break; + default: + phydev_err(phydev, "Unsupported interface: %d\n", + phydev->interface); + return -EINVAL; + } + + set |=3D FIELD_PREP(DAP8211R_RGMII_RX_DEL_MASK, rx_internal_delay); + set |=3D FIELD_PREP(DAP8211R_RGMII_TX_DEL_MASK, tx_internal_delay); + + ret =3D dap8211r_modify_ext(phydev, DAP8211R_PHY_CON, DAP8211R_PHY_SW_RST= , 0); + if (ret) + return ret; + + /* Wait for reset self-clear (from low active to high) */ + ret =3D read_poll_timeout(dap8211r_read_ext, val, + (val & DAP8211R_PHY_SW_RST), + 20, 200, false, phydev, DAP8211R_PHY_CON); + if (ret) + return ret; + if (val < 0) + return val; + + ret =3D dap8211r_modify_ext(phydev, DAP8211R_RGMII_CON, DAP8211R_RGMII_CO= NFIG_MASK, set); + if (ret) + return ret; + + return 0; +} + +static struct phy_driver dap8211r_driver[] =3D { + { + PHY_ID_MATCH_EXACT(DAP8211R_PHY_ID), + .name =3D "DAP8211R Gigabit Ethernet", + .soft_reset =3D genphy_soft_reset, + .config_init =3D dap8211r_config_init, + .read_status =3D genphy_read_status, + .set_loopback =3D genphy_loopback, + .config_aneg =3D genphy_config_aneg, + .suspend =3D genphy_suspend, + .resume =3D genphy_resume, + }, +}; +module_phy_driver(dap8211r_driver); + +MODULE_DESCRIPTION("DAP8211R Gigabit Ethernet PHY driver"); +MODULE_AUTHOR("Artem Shimko "); +MODULE_LICENSE("GPL"); + +static const struct mdio_device_id __maybe_unused dap8211r_tb[] =3D { + { DAP8211R_PHY_ID, DAP8211R_PHY_ID_MASK }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(mdio, dap8211r_tb); + --=20 2.43.0