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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2d04b120f2fsm33679845ad.64.2026.08.03.00.49.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 00:49:37 -0700 (PDT) From: Chi-Wen Weng To: broonie@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cwweng@nuvoton.com, cwweng.linux@gmail.com Subject: [PATCH v3 1/2] dt-bindings: spi: nuvoton,ma35d1-qspi: Allow additional GPIO chip selects Date: Mon, 3 Aug 2026 15:49:12 +0800 Message-Id: <20260803074913.1656675-2-cwweng.linux@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260803074913.1656675-1-cwweng.linux@gmail.com> References: <5769eae0-1b40-419f-8311-0d919bf619fa@sirena.org.uk> <20260803074913.1656675-1-cwweng.linux@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chi-Wen Weng The MA35D1 QSPI controller provides two native chip selects, but the generic SPI controller binding defines num-cs as the total number of native and GPIO-based chip selects. Remove the maximum value of two from num-cs so that board device trees can describe additional GPIO chip selects while retaining two as the default chip-select count. Signed-off-by: Chi-Wen Weng --- Documentation/devicetree/bindings/spi/nuvoton,ma35d1-qspi.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/devicetree/bindings/spi/nuvoton,ma35d1-qspi.yaml= b/Documentation/devicetree/bindings/spi/nuvoton,ma35d1-qspi.yaml index 377ccf4fb224..f837367e6d5f 100644 --- a/Documentation/devicetree/bindings/spi/nuvoton,ma35d1-qspi.yaml +++ b/Documentation/devicetree/bindings/spi/nuvoton,ma35d1-qspi.yaml @@ -30,7 +30,6 @@ properties: =20 num-cs: minimum: 1 - maximum: 2 default: 2 =20 required: --=20 2.25.1 From nobody Fri Oct 2 09:21:37 2026 Received: from mail-pl1-f176.google.com (mail-pl1-f176.google.com [209.85.214.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 244B43AE190 for ; Mon, 3 Aug 2026 07:49:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785743386; cv=none; b=CjEwV25MUz2TspQW3mj/dTfqJwX7Z4fyBSTW7e2XWCNSudrabnEtTc2plHA+7If4k7pQNumvDRVmQzRdj2+1FxY3fhPLW3J/HZNJIBusN+LumQUYs9u5sz++sdq9AoctlvNv0xpdCGhQ1tP94pvShfjq+yFq+KjeKoOw0zdHq5U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785743386; c=relaxed/simple; bh=GO3Sz/cw7cI0HCk+Bed3MtNGnWNHKZUKealu4ttJIp4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=PrEa7jDy4tH5T4RWca9BcqdUx5s/tJkqULx705We/TPFeG+lz/nL0jC3mN/42ApEfFyEoGhgUC2fDcgKp05KCPe4d2nkmv1M7E88WjXS+k5uv3LWRbVYf2BGWLjDTmXorncHiQ+Tg6SykGmpqbkpm56Qe4Qh7nCYRvgMNM2n5tI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=NiJrzgIP; arc=none smtp.client-ip=209.85.214.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="NiJrzgIP" Received: by mail-pl1-f176.google.com with SMTP id d9443c01a7336-2cacf197759so44183235ad.2 for ; Mon, 03 Aug 2026 00:49:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1785743384; x=1786348184; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=Mh0zq1YTh3UJhLL40JBJykkOmBY5F9aAuS/qMZKEofk=; b=NiJrzgIPYFhc2/us9ghPkcRkp5HcupJzWqyhgtMu+uRP2dfBWIfg6yfIEfLEnhyrId 49cTGO5fZ8UHi7wJs4VNT8FwVDZqvrOht99wac0PQppr5ZLf4QHP73ILMvXGE7akngxo 9acVt17rVets2HdclsdpJIv3nXzopyZU5qJ1cNrYYXCQetvseuVc76MRFXSkM9jfZY1W BhgaylV6iI3PajbMqouAya26xWcUvHELSqP4jlQyiwakKN139QT4FvlP/FJRcr+7vpTZ X4DgvY5ZZXC5YK7cbDTnAJRVSskbFoTiJh4MaupJvyFiGzuhUr7JZOHCq/PuOX6x55S3 m5XQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1785743384; x=1786348184; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=Mh0zq1YTh3UJhLL40JBJykkOmBY5F9aAuS/qMZKEofk=; b=YNslBXIBDVxo9Ey26hkLYWoa5IUorFPEOfCV7L7FpcW0OO+eTRQDOLDKoKDAF+EeA/ vjveRdo4FDH5DL8He4AaVJJcVEMdvIMbIPaK0BKkytKcRtj69vj6CN6QCyiX1UIYIQZY B8P2k5uWyk+Ky4IA+nph943k7L4u3PeNp+2XqbZn+5JbNQMo7FU42Xsy18zDp8j34/8j H0FAmVIGpgI5JFO24pma7h5OOuD3uoOCPIyt58lbEpLZ+XZr/ysOsHldsSktBgpv1b3P rMQspvhXWlgVA2I9/ctuIOkyAmdc9FiFKXuUPxLPbfu+YUN8EW8UqPUxPTIUJFrFb/ER DfUg== X-Forwarded-Encrypted: i=1; AHgh+RpqIZc4Cmb9b+CXirU0zAAGJ7Rc3LjuPO/bVKQ6Ljp7jtSv8Gl6Kv78QN2j54Jy1C06O1DRdhtTWKFu0+8=@vger.kernel.org X-Gm-Message-State: AOJu0YxHZT7tzoTWGsm120gIrdq+7IL4kivLAKFuDFd+1XPuwSgfHmej DqW2mopRzgsHJqkGrkfhnWUN5rKe8Bdexv/n9MDzPu1SIKxeQ9O1IU2u X-Gm-Gg: AR+sD12KDJDo40I/V8/RiLbkMpBMbrK+HOoI1A7iqobdRgb3Qf8skZ1XZcpdkiyfXcH XE37Xq7NU7ALj8+Nn2NMZ+ILcW6gUhaHHvX4BOxSVI2ZA6HO9o5F9lf2J8lt10xA9fd5GuX5CnZ Nae1QPPcQLjqFQMOwXCbUkh6ANRh7dLwyO/f05nwn5P1wkYEkNdA7EGufGoL4Q2ZE5jfTvViFBn +sg/zTDkQiE9omcyAWjfHIzms3L3BHWo30pPXwSfBiltFt+sWRpnok4JrnbqtpdRLWxKTGt9w5D iqEsMCK+WkovSL1K6qRa6begKwELbymMPyYIhPM7kvkZAw0aCmW+PMX1I+SmW/9NaoH7vwWcCHg 0ompG/MBPsX0DnPLKI/ho1jr5pvK+Nk/qbk8y4gMgoOJEMk05VnZ5BSq149jyywcNjQgkyCRR7P PpzOhSIvSBY+RMC1gY4eGP4fji85MDpdsAi0yIQlij/e0lkvyz74VsdMsBLctlkQnZ+Xf/KCxKE Y26U9Esk6ycMSZttjNgy4ZqVJufhfdDTUsrE0gGOKfZAq+YHyg= X-Received: by 2002:a17:902:e84d:b0:2cf:84bb:1ebc with SMTP id d9443c01a7336-2d0521e9e05mr90498015ad.15.1785743384392; Mon, 03 Aug 2026 00:49:44 -0700 (PDT) Received: from localhost.localdomain (60-250-196-139.hinet-ip.hinet.net. [60.250.196.139]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2d04b120f2fsm33679845ad.64.2026.08.03.00.49.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 00:49:43 -0700 (PDT) From: Chi-Wen Weng To: broonie@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cwweng@nuvoton.com, cwweng.linux@gmail.com Subject: [PATCH v3 2/2] spi: ma35d1-qspi: Enable GPIO chip selects Date: Mon, 3 Aug 2026 15:49:13 +0800 Message-Id: <20260803074913.1656675-3-cwweng.linux@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260803074913.1656675-1-cwweng.linux@gmail.com> References: <5769eae0-1b40-419f-8311-0d919bf619fa@sirena.org.uk> <20260803074913.1656675-1-cwweng.linux@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chi-Wen Weng The generic SPI controller binding allows GPIO-based chip selects, but the MA35D1 QSPI driver does not currently enable the SPI core's GPIO descriptor handling. Enable GPIO chip-select support and distinguish the total number of chip selects from the controller's two native chip selects. Allow num-cs to include additional GPIO chip selects and set max_native_cs to the native hardware limit. Add a setup callback that rejects chip-select indices beyond the native limit when no GPIO descriptor is present. Also reject active-high polarity only for native chip selects, while allowing GPIO chip-select polarity to be handled by the GPIO subsystem. Signed-off-by: Chi-Wen Weng --- drivers/spi/spi-ma35d1-qspi.c | 32 ++++++++++++++++++++++++++++---- 1 file changed, 28 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-ma35d1-qspi.c b/drivers/spi/spi-ma35d1-qspi.c index 541d5d72484c..f893a4160528 100644 --- a/drivers/spi/spi-ma35d1-qspi.c +++ b/drivers/spi/spi-ma35d1-qspi.c @@ -61,7 +61,7 @@ #define NUVOTON_QSPI_STATUS_RXEMPTY_MASK BIT(8) /* Receive FIFO Empty */ #define NUVOTON_QSPI_STATUS_BUSY_MASK BIT(0) /* Busy Status */ =20 -#define NUVOTON_QSPI_MAX_NUM_CS 2 +#define NUVOTON_QSPI_MAX_NATIVE_CS 2 #define NUVOTON_QSPI_DEFAULT_NUM_CS 2 #define NUVOTON_QSPI_DEFAULT_BPW 8 /* Bound PIO operations to avoid long atomic polling loops. */ @@ -430,13 +430,34 @@ static void nuvoton_qspi_set_cs_level(struct nuvoton_= qspi *qspi, spin_unlock_irqrestore(&qspi->ssctl_lock, flags); } =20 +static int nuvoton_qspi_setup(struct spi_device *spi) +{ + unsigned int cs =3D spi_get_chipselect(spi, 0); + + if (spi_get_csgpiod(spi, 0)) + return 0; + + if (cs >=3D NUVOTON_QSPI_MAX_NATIVE_CS) { + dev_err(&spi->dev, "invalid native chip select %u\n", cs); + return -EINVAL; + } + + if (spi->mode & SPI_CS_HIGH) { + dev_err(&spi->dev, + "active-high native chip select is not supported\n"); + return -EINVAL; + } + + return 0; +} + static void nuvoton_qspi_set_cs(struct spi_device *spi, bool level) { struct nuvoton_qspi *qspi =3D spi_controller_get_devdata(spi->controller); =20 /* - * The SPI core passes the physical CS level to ->set_cs(). This - * initial driver only supports active-low native chip selects. + * The SPI core passes the physical CS level to ->set_cs(). Native + * chip selects are active low. */ nuvoton_qspi_set_cs_level(qspi, spi_get_chipselect(spi, 0), !level); } @@ -608,15 +629,18 @@ static int nuvoton_qspi_probe(struct platform_device = *pdev) if (ret && ret !=3D -EINVAL) return dev_err_probe(dev, ret, "failed to read num-cs\n"); =20 - if (!num_cs || num_cs > NUVOTON_QSPI_MAX_NUM_CS) + if (!num_cs) return dev_err_probe(dev, -EINVAL, "invalid num-cs %u\n", num_cs); =20 ctlr->num_chipselect =3D num_cs; + ctlr->max_native_cs =3D NUVOTON_QSPI_MAX_NATIVE_CS; + ctlr->use_gpio_descriptors =3D true; ctlr->max_transfer_size =3D nuvoton_qspi_max_transfer_size; ctlr->max_message_size =3D nuvoton_qspi_max_message_size; ctlr->mem_ops =3D &nuvoton_qspi_mem_ops; ctlr->mem_caps =3D &nuvoton_qspi_mem_caps; + ctlr->setup =3D nuvoton_qspi_setup; ctlr->set_cs =3D nuvoton_qspi_set_cs; ctlr->transfer_one =3D nuvoton_qspi_transfer_one; ctlr->bits_per_word_mask =3D SPI_BPW_MASK(8); --=20 2.25.1