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[79.17.119.233]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47fd41d1a58sm30370503f8f.7.2026.08.03.00.42.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 00:42:32 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: domenico.acri@engicam.com, linux-amarula@amarulasolutions.com, michael@amarulasolutions.com, francesco.utel@engicam.com, Dario Binacchi , Conor Dooley , Alexandre Torgue , Christophe Parant , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RESEND PATCH v7 01/16] dt-bindings: arm: stm32: support Engicam MicroGEA-STM32MP257-RMM board Date: Mon, 3 Aug 2026 09:25:56 +0200 Message-ID: <20260803074224.3821911-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260803074224.3821911-1-dario.binacchi@amarulasolutions.com> References: <20260803074224.3821911-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add devicetree bindings for Engicam MicroGEA-STM32MP257-RMM board based on the Engicam MicroGEA-STM32MP257 SoM (System-on-Module). The use of an enum for a single element is justified by the future addition of other boards based on the same SoM. Signed-off-by: Dario Binacchi Acked-by: Conor Dooley --- (no changes since v2) Changes in v2: - Add Acked-by of Conor Dooley for patch 0/1 "dt-bindings: arm: stm32: support Engicam MicroGEA-STM32MP257-RMM board" Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Docum= entation/devicetree/bindings/arm/stm32/stm32.yaml index c6af3a46364f..c5ce81e3ce45 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -203,6 +203,13 @@ properties: - st,stm32mp257f-ev1 - const: st,stm32mp257 =20 + - description: Engicam MicroGEA STM32MP257 SoM based Boards + items: + - enum: + - engicam,microgea-stm32mp257-rmm + - const: engicam,microgea-stm32mp257 + - const: st,stm32mp257 + - description: ST STM32MP235 based Boards items: - enum: --=20 2.43.0 From nobody Fri Oct 2 09:26:35 2026 Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3B2A83AD52D for ; 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[79.17.119.233]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47fd41d1a58sm30370503f8f.7.2026.08.03.00.42.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 00:42:33 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: domenico.acri@engicam.com, linux-amarula@amarulasolutions.com, michael@amarulasolutions.com, francesco.utel@engicam.com, Dario Binacchi , Alexandre Torgue , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RESEND PATCH v7 02/16] arm64: dts: st: add power-domains to sdmmc1 on stm32mp231 Date: Mon, 3 Aug 2026 09:25:57 +0200 Message-ID: <20260803074224.3821911-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260803074224.3821911-1-dario.binacchi@amarulasolutions.com> References: <20260803074224.3821911-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The sdmmc1 node was introduced early in the SoC bring-up before power domains were systematically mapped. Add the missing power-domains property to align it with the rest of the peripheral nodes. Signed-off-by: Dario Binacchi --- (no changes since v5) Changes in v5: - Added in version 5. Suggested by Sashiko. arch/arm64/boot/dts/st/stm32mp231.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/st/stm32mp231.dtsi b/arch/arm64/boot/dts/s= t/stm32mp231.dtsi index 9e1d240888ff..0feb8943efae 100644 --- a/arch/arm64/boot/dts/st/stm32mp231.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp231.dtsi @@ -727,6 +727,7 @@ sdmmc1: mmc@48220000 { cap-mmc-highspeed; max-frequency =3D <120000000>; access-controllers =3D <&rifsc 76>; + power-domains =3D <&cluster_pd>; status =3D "disabled"; }; =20 --=20 2.43.0 From nobody Fri Oct 2 09:26:35 2026 Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B99B13128B6 for ; Mon, 3 Aug 2026 07:42:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785742968; cv=none; b=gavu2JQf09MIxKrOKAf7nYbq7P0G6ghyBcsRphmk1vXkjjXdV7mN5JNwfdCMt57d3DIP7i0yx54UmxzA/KfvOwHUERFJgRzFhzI9+ZbR1jeaEr8qcJqZw5c0sZIs7bwttj8i3MGBP1FqsvD+IvmhGMKtcqWxX6eDSPxJIgHtQgw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785742968; c=relaxed/simple; bh=SRq4aV3Vv1KtanwaZu/HUbm5QTW8rISjxiq71Wm2JKY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=dVbU8e4dcXkOYaHJqzCiWaWVV9Ht9ve7gVhyesW5/7OmA3qf4PaSEn+J3fUfUkKr7m3FgeoHUSbmqwXt7144fjTttY6xRKl4pFCOXW471u73hybQ2revc5m8XNhZHWZErVNbYZjTGDzTjZFkLVcxwAznX52tHaUmBWvtfydSeLw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=pDHt2nS3; arc=none smtp.client-ip=209.85.221.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="pDHt2nS3" Received: by mail-wr1-f51.google.com with SMTP id ffacd0b85a97d-47f633e6058so2906470f8f.0 for ; Mon, 03 Aug 2026 00:42:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1785742965; x=1786347765; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=kjf+9zwLvFnbMj2uY67jnA57NYs5qvgfofKcphxJQbw=; b=pDHt2nS3+aDXlDddwagM2LlKlUWTgJuO2G5f0IAQLjIbovK6GkwuL337HDiiWlqmJs djlEEO9fpJmRlTrYT/iDO85pBgQmBaSskdy88kTwPdjM3vlsVscFIEg9+ReQPZbdv9BI Uo30AqfaVPuzJo3TyZ+94ZkmcTbbsDG/lFVWw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1785742965; x=1786347765; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=kjf+9zwLvFnbMj2uY67jnA57NYs5qvgfofKcphxJQbw=; b=EXFgb/V9ATUKexkKRPkquN+8scv+J7t4q1EBSCnQZ+FSCdojpNhMR09JxdHMgpe4md vUGAb6JaUFXz1EUSda+SWJNwwqym8dUFNp33piNnp9NtdgqimcQprNje5YAPMak+/sxE TTAES+5fNYs67p7fOrxlO2WVNA/x6/+G5Qqjs1hQdKsCW2jS94sJCh6bqFK/TC6V4+we QKwtj8n27I5WqJ2hxPdnjuy7AVJQFbR6CpA72xqjTbgndIHSZnth2rEl2L/P0cFNdiBO KPTgzkqT7bP7y/hzT1LDAbBd87bud40KF4cXakNX/fgV7uepgEVNnQT5LtDqozbCePEb 8Ibw== X-Gm-Message-State: AOJu0Ywf7t8BgEAkNm/ZR2gs2uRSDa6vbODq19nuhAN2YT+2x/1XTbV8 qYgt+m+t6+boXk/t+j8OZtSyGr3MDRpAgCzcvb+jokjh0MdnoSMW3l4eP14fhORL2ogaiS5U4dM +eymV X-Gm-Gg: AR+sD121e00zytMrGsHv3M2PkIGV7TtlqChKHf1Q1MHZLrcVbjoT6qNivfFKo51K9gI DD2YIVl4U6mSbdsT9sIyE+F9mUPqL9s/9bTW2xBHuIKq9JGcbFOwir9MOI1yKGT7QgY5VzGAvZO ELnJ7z9DwBo1R3fPKar8tkdfQCrdK0elTdc4OruVcRO9QAaIf0L/Zmxl0LFEx1PIsbCIuJS18oD LPFP0PtZmRbP4YkLYO8+JxHeMzI4zuj/S3sd7v/FpcMsie1qGM+CR5wf3YJ4QxHMgWAf8xY2pyf l+t1/D9bLAiwdHqrTnxl0bUow0KwHp7eHq752H804oOC9tQg6Bvi230mdHPoJ/CqXsN5TWiEwf6 C1n4jp4JDDdbyhHYpgBWIBLDgpW8UP0/LtsKmxFxzes3FK/v297Csvh1acEhK3DrFcR+hNTjVew zcE4E2o04GzaYEE3mrT4cgYC6vaEZ4uCv2NqTyOuMixtmk9kewhWiVJ05+ny5Zc8QKRc4gJflxz MvGbQeiKhJRAO17wOGEffco/biZP31gEmFDUgn7RdUU0ynKlC2r9zAWZVIPjIr5guJhM4uXJirZ 7tc+fKzCPFVUwiXT3efiFtUyKJ7GtuEUA8RdWQ9H7K9PBu8MhfFNkWJJywSlFA6h X-Received: by 2002:a05:6000:188f:b0:47f:c62e:9cca with SMTP id ffacd0b85a97d-47fd9cfd167mr21692191f8f.22.1785742965078; Mon, 03 Aug 2026 00:42:45 -0700 (PDT) Received: from dario-ThinkPad-P14s-Gen-5.homenet.telecomitalia.it (host-79-17-119-233.retail.telecomitalia.it. [79.17.119.233]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47fd41d1a58sm30370503f8f.7.2026.08.03.00.42.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 00:42:44 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: domenico.acri@engicam.com, linux-amarula@amarulasolutions.com, michael@amarulasolutions.com, francesco.utel@engicam.com, Dario Binacchi , Alexandre Torgue , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RESEND PATCH v7 03/16] arm64: dts: st: add power-domains to sdmmc1 on stm32mp251 Date: Mon, 3 Aug 2026 09:25:58 +0200 Message-ID: <20260803074224.3821911-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260803074224.3821911-1-dario.binacchi@amarulasolutions.com> References: <20260803074224.3821911-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The sdmmc1 node was introduced early in the SoC bring-up before power domains were systematically mapped. Add the missing power-domains property to align it with the rest of the peripheral nodes. Signed-off-by: Dario Binacchi --- (no changes since v5) Changes in v5: - Added in version 5. Suggested by Sashiko. arch/arm64/boot/dts/st/stm32mp251.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index 9c63fdb5a885..ae36d703532c 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -1664,6 +1664,7 @@ sdmmc1: mmc@48220000 { cap-mmc-highspeed; max-frequency =3D <120000000>; access-controllers =3D <&rifsc 76>; + power-domains =3D <&CLUSTER_PD>; status =3D "disabled"; }; =20 --=20 2.43.0 From nobody Fri Oct 2 09:26:35 2026 Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 45E663AAF52 for ; Mon, 3 Aug 2026 07:42:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785742969; cv=none; b=A5PXII+43X8UmFj1vQV+VwSBOEDwqFi9SPPbveg2ntNlsPdieargFLTd5lKg1jgeBoy57OfwPxqE+D9eJZNmULfoI1ApJaSlhTadyomq5SMdy1PxmPjZmQUQojennemJ8R1+CyXNUap6PJBokD9pAw7U8DCFXHwOZ/nDmXRQVJ4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785742969; c=relaxed/simple; bh=9IgDtyv6yAMUkWsg7RNaWcItxtFHo8kakpm/KHcWfnA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=EM2QQcXPxJUuPUOBRdFloNAYHz0ORdsuwbPxCf22yzbZwlx0WEI1lxeat5kLJk7/jxDxIkCiW7DIQgZ6cL4TpPRceRFZ5aRyNHlRRijQn1/rkR4DRMiKnsCEijBp33ZkCY3BY57DI0tUNmt4az+Y7atZ0WZzJZ03WvjJwxR0BDg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=SY6XxHU1; arc=none smtp.client-ip=209.85.221.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="SY6XxHU1" Received: by mail-wr1-f49.google.com with SMTP id ffacd0b85a97d-47f7854678cso1435499f8f.1 for ; Mon, 03 Aug 2026 00:42:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1785742966; x=1786347766; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=fAmctwTyX9ptfNTsOcFrY+BzuI2WSByIHEJFFIRpN/Y=; b=SY6XxHU13k2yacG6QigOPqX8rtLedxyNeOwEZAS2kvXdkAnVpaSk4tXNIDrQ5zYoqM 3oq/zxUUhUenwRZGmDxk1weoG6M3Q7Saa62ymioGhGr9k/mlxHTi55B7TmOiBQx6XRY5 abprX505V4lyFbJkPI0x4koTqYIaDsz9m3kOc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1785742966; x=1786347766; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=fAmctwTyX9ptfNTsOcFrY+BzuI2WSByIHEJFFIRpN/Y=; b=TcDaSIuUStRkv7rMgKGHP1ekJFVt2DBxN42h/CRBJwu1QXlVyrjEdq/6X+AoCSi+4S pGtsB6BsKZ/C9XCbVpDyIO93RwBSBLMs9RlDrtCwe3Np7EUhxlhMJ4vMJ8rOIc2gFJJA 0o57CwfXTDI2MIqNa2BclhDtioMDt1ZQ1oWEfn1cjNjFUXo1WanJsYpHeenbvSiCOgxm odkEcWgHulFO+bkCxZY+QMPwZ9+DkEBEzbPgdw2UGQL4gkpZvpX2VMP2zSTGthK9yhoY EekyR7DeyVfKV8QBAyug50Gm5o0UcF3IBDeFoY8R+51qPKrqCxB3rNMElDGJDzt0k9Vp YpEg== X-Gm-Message-State: AOJu0Yx1ra7Ni93d5KjZBQ2avLEecsbEvG0qwFqOKyUqLSEBHIGpGUto eQ7qNOEaODs/hVJShX10Va1MN+Lti4XbOlVNRMrILzawZlMhKPiMnAG/c1pp5Dnok5HF/oiRe4x arsMe X-Gm-Gg: AR+sD12KcQXGlTiRc/d+Baq9Qoih037SK0NPY0faScJhxIMbuS0aZoivdVjlXd+gsTI PtHlPbdAcE8oafxbqbtsPfIvpbt/9G+onnQ86Eoqw30VyVf+Ek1R9bX4kpOwY8tV6jyPqSWKjGZ e3L44ICKX7CIUlGpM6Biupde9TNT6DPWCgjEf+88Ysg6TCetCDiiz5y6pU8d0PtgrSaQJRxn4h4 KVGmR3EsDvT7ffbGo6p8WQVk2mUlSkbu9jSek5CySeqNXCmciEnWN2v+TJMiUZ23zK9FhjzT3Su WtAO+ij42v5+2HQ/UV2rDoRe5dpm/7qHsYpQPm/xx/kwMYF8iNMV7x/nAlYpDtCc4G/9IZ59sgk OiuaXscXKWydDpbcWW1pi6vyx7ASs/u2wzd3Jyw500RvT9VKF3zOSKPMo0BCowgEgM5q6mF3VR7 GMC5cLXcT4bxTvc8sep6EutMNsLnaPRmhBWLrL0lZhYA3RjPqAxmmRpprrKJWTr0sa8mr1KNesi mzOpfRyx3zoknoX6orrntVQvDdX4SalL6RnVmpgOI4w5OuHA3J0eP0JAaImd+BgbLis7OjbWq/p RmmXWVNFe+KkzsqykFaVClI44e2UoWELRXtNQ4g6E6ItflMWUyHpCaf9HtSAiDat X-Received: by 2002:a05:6000:22c2:b0:47f:c648:e265 with SMTP id ffacd0b85a97d-47fd9cf7670mr21118173f8f.17.1785742966560; Mon, 03 Aug 2026 00:42:46 -0700 (PDT) Received: from dario-ThinkPad-P14s-Gen-5.homenet.telecomitalia.it (host-79-17-119-233.retail.telecomitalia.it. [79.17.119.233]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47fd41d1a58sm30370503f8f.7.2026.08.03.00.42.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 00:42:46 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: domenico.acri@engicam.com, linux-amarula@amarulasolutions.com, michael@amarulasolutions.com, francesco.utel@engicam.com, Dario Binacchi , Alexandre Torgue , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RESEND PATCH v7 04/16] arm64: dts: st: add SDMMC2 support on stm32mp25 Date: Mon, 3 Aug 2026 09:25:59 +0200 Message-ID: <20260803074224.3821911-5-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260803074224.3821911-1-dario.binacchi@amarulasolutions.com> References: <20260803074224.3821911-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The SDMMC2 controller supports SD cards, eMMC memories and SDIO devices. Signed-off-by: Dario Binacchi --- (no changes since v3) Changes in v3: - Add power-domains property. Suggested by Sashiko. arch/arm64/boot/dts/st/stm32mp251.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index ae36d703532c..44938c036e30 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -1668,6 +1668,22 @@ sdmmc1: mmc@48220000 { status =3D "disabled"; }; =20 + sdmmc2: mmc@48230000 { + compatible =3D "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid =3D <0x00353180>; + reg =3D <0x48230000 0x400>, <0x44230800 0x8>; + interrupts =3D ; + clocks =3D <&rcc CK_KER_SDMMC2>; + clock-names =3D "apb_pclk"; + resets =3D <&rcc SDMMC2_R>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency =3D <120000000>; + access-controllers =3D <&rifsc 77>; + power-domains =3D <&CLUSTER_PD>; + status =3D "disabled"; + }; + ethernet1: ethernet@482c0000 { compatible =3D "st,stm32mp25-dwmac", "snps,dwmac-5.20"; reg =3D <0x482c0000 0x4000>; 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Signed-off-by: Dario Binacchi --- (no changes since v2) Changes in v2: - Add resets property to dts CAN node. Suggested by Sashiko. arch/arm64/boot/dts/st/stm32mp253.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp253.dtsi b/arch/arm64/boot/dts/s= t/stm32mp253.dtsi index eeceb086252b..7e82f01fdc10 100644 --- a/arch/arm64/boot/dts/st/stm32mp253.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp253.dtsi @@ -43,6 +43,22 @@ &optee { }; =20 &rifsc { + m_can1: can@402d0000 { + compatible =3D "bosch,m_can"; + reg =3D <0x402d0000 0x400>, <0x40310000 0xd50>; + reg-names =3D "m_can", "message_ram"; + interrupts =3D , + ; + interrupt-names =3D "int0", "int1"; + clocks =3D <&rcc CK_BUS_FDCAN>, <&rcc CK_KER_FDCAN>; + clock-names =3D "hclk", "cclk"; + resets =3D <&rcc FDCAN_R>; + bosch,mram-cfg =3D <0x0 0 0 32 0 0 2 2>; + access-controllers =3D <&rifsc 56>; + power-domains =3D <&CLUSTER_PD>; + status =3D "disabled"; + }; + ethernet2: ethernet@482d0000 { compatible =3D "st,stm32mp25-dwmac", "snps,dwmac-5.20"; reg =3D <0x482d0000 0x4000>; --=20 2.43.0 From nobody Fri Oct 2 09:26:35 2026 Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6762D3AEF50 for ; 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[79.17.119.233]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47fd41d1a58sm30370503f8f.7.2026.08.03.00.42.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 00:42:49 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: domenico.acri@engicam.com, linux-amarula@amarulasolutions.com, michael@amarulasolutions.com, francesco.utel@engicam.com, Dario Binacchi , Alexandre Torgue , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RESEND PATCH v7 06/16] arm64: dts: st: add i2c1 pins for stm32mp25 Date: Mon, 3 Aug 2026 09:26:01 +0200 Message-ID: <20260803074224.3821911-7-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260803074224.3821911-1-dario.binacchi@amarulasolutions.com> References: <20260803074224.3821911-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the i2c1 pins used on MicroGEA-STM32MP257-RMM board. Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boo= t/dts/st/stm32mp25-pinctrl.dtsi index 456ece7f8ebc..db485b9ed904 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -203,6 +203,25 @@ pins { }; }; =20 + /omit-if-no-ref/ + i2c1_pins_a: i2c1-0 { + pins { + pinmux =3D , /* I2C1_SCL */ + ; /* I2C1_SDA */ + bias-disable; + drive-open-drain; + slew-rate =3D <0>; + }; + }; + + /omit-if-no-ref/ + i2c1_sleep_pins_a: i2c1-sleep-0 { + pins { + pinmux =3D , /* I2C1_SCL */ + ; /* I2C1_SDA */ + }; + }; + /omit-if-no-ref/ i2c2_pins_a: i2c2-0 { pins { --=20 2.43.0 From nobody Fri Oct 2 09:26:35 2026 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F23F93AFCF0 for ; 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[79.17.119.233]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47fd41d1a58sm30370503f8f.7.2026.08.03.00.42.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 00:42:50 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: domenico.acri@engicam.com, linux-amarula@amarulasolutions.com, michael@amarulasolutions.com, francesco.utel@engicam.com, Dario Binacchi , Alexandre Torgue , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RESEND PATCH v7 07/16] arm64: dts: st: add ltdc pins for stm32mp25 Date: Mon, 3 Aug 2026 09:26:02 +0200 Message-ID: <20260803074224.3821911-8-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260803074224.3821911-1-dario.binacchi@amarulasolutions.com> References: <20260803074224.3821911-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the LTDC pins used on MicroGEA-STM32MP257-RMM board. Signed-off-by: Dario Binacchi --- (no changes since v5) Changes in v5: - Increase slew-rate to <1> to support the 27 MHz pixel clock and prevent timing violations. Suggested by Sashiko arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boo= t/dts/st/stm32mp25-pinctrl.dtsi index db485b9ed904..50f454630cf2 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -260,6 +260,77 @@ pins { }; }; =20 + /omit-if-no-ref/ + ltdc_pins_a: ltdc-0 { + pins { + pinmux =3D , /* LCD_CLK */ + , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_DE */ + , /* LCD_R0 */ + , /* LCD_R1 */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G0 */ + , /* LCD_G1 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B0 */ + , /* LCD_B1 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + ; /* LCD_B7 */ + bias-disable; + drive-push-pull; + slew-rate =3D <1>; + }; + }; + + /omit-if-no-ref/ + ltdc_sleep_pins_a: ltdc-sleep-0 { + pins { + pinmux =3D , /* LCD_CLK */ + , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_DE */ + , /* LCD_R0 */ + , /* LCD_R1 */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G0 */ + , /* LCD_G1 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B0 */ + , /* LCD_B1 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + ; /* LCD_B7 */ + }; + }; + /omit-if-no-ref/ ospi_port1_clk_pins_a: ospi-port1-clk-0 { pins { --=20 2.43.0 From nobody Fri Oct 2 09:26:35 2026 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A9F9E3B0AC4 for ; Mon, 3 Aug 2026 07:42:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[79.17.119.233]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47fd41d1a58sm30370503f8f.7.2026.08.03.00.42.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 00:42:52 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: domenico.acri@engicam.com, linux-amarula@amarulasolutions.com, michael@amarulasolutions.com, francesco.utel@engicam.com, Dario Binacchi , Alexandre Torgue , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RESEND PATCH v7 08/16] arm64: dts: st: add can1 pins for stm32mp25 Date: Mon, 3 Aug 2026 09:26:03 +0200 Message-ID: <20260803074224.3821911-9-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260803074224.3821911-1-dario.binacchi@amarulasolutions.com> References: <20260803074224.3821911-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the can1 pins used on MicroGEA-STM32MP257-RMM board. Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boo= t/dts/st/stm32mp25-pinctrl.dtsi index 50f454630cf2..6482dd47e977 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -331,6 +331,28 @@ pins { }; }; =20 + /omit-if-no-ref/ + m_can1_pins_a: m-can1-0 { + pins1 { + pinmux =3D ; /* CAN1_TX */ + slew-rate =3D <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux =3D ; /* CAN1_RX */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + m_can1_sleep_pins_a: m-can1-sleep-0 { + pins { + pinmux =3D , /* CAN1_TX */ + ; /* CAN1_RX */ + }; + }; + /omit-if-no-ref/ ospi_port1_clk_pins_a: ospi-port1-clk-0 { pins { --=20 2.43.0 From nobody Fri Oct 2 09:26:35 2026 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA9A4331EB4 for ; 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[79.17.119.233]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47fd41d1a58sm30370503f8f.7.2026.08.03.00.42.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 00:43:03 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: domenico.acri@engicam.com, linux-amarula@amarulasolutions.com, michael@amarulasolutions.com, francesco.utel@engicam.com, Dario Binacchi , Alexandre Torgue , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RESEND PATCH v7 09/16] arm64: dts: st: add pwm2/pwm4 pins for stm32mp25 Date: Mon, 3 Aug 2026 09:26:04 +0200 Message-ID: <20260803074224.3821911-10-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260803074224.3821911-1-dario.binacchi@amarulasolutions.com> References: <20260803074224.3821911-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the pwm2 and pwm4 pins used on MicroGEA-STM32MP257-RMM board. Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boo= t/dts/st/stm32mp25-pinctrl.dtsi index 6482dd47e977..695c9d771853 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -433,6 +433,23 @@ pins { }; }; =20 + /omit-if-no-ref/ + pwm2_pins_a: pwm2-0 { + pins { + pinmux =3D ; /* TIM2_CH1 */ + bias-pull-down; + drive-push-pull; + slew-rate =3D <0>; + }; + }; + + /omit-if-no-ref/ + pwm2_sleep_pins_a: pwm2-sleep-0 { + pins { + pinmux =3D ; /* TIM2_CH1 */ + }; + }; + /omit-if-no-ref/ pwm3_pins_a: pwm3-0 { pins { @@ -450,6 +467,23 @@ pins { }; }; =20 + /omit-if-no-ref/ + pwm4_pins_a: pwm4-0 { + pins { + pinmux =3D ; /* TIM4_CH1 */ + bias-pull-down; + drive-push-pull; + slew-rate =3D <0>; + }; + }; + + /omit-if-no-ref/ + pwm4_sleep_pins_a: pwm4-sleep-0 { + pins { + pinmux =3D ; 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[79.17.119.233]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47fd41d1a58sm30370503f8f.7.2026.08.03.00.43.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 00:43:05 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: domenico.acri@engicam.com, linux-amarula@amarulasolutions.com, michael@amarulasolutions.com, francesco.utel@engicam.com, Dario Binacchi , Olivier Moysan , Alexandre Torgue , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RESEND PATCH v7 10/16] arm64: dts: st: add sai1 pins for stm32mp25 Date: Mon, 3 Aug 2026 09:26:05 +0200 Message-ID: <20260803074224.3821911-11-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260803074224.3821911-1-dario.binacchi@amarulasolutions.com> References: <20260803074224.3821911-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the sai1 pins used on MicroGEA-STM32MP257-RMM board. Signed-off-by: Dario Binacchi Reviewed-by: Olivier Moysan --- Changes in v7: - Add Reviewed-by tag of Olivier Moysan arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boo= t/dts/st/stm32mp25-pinctrl.dtsi index 695c9d771853..002fbc724b9d 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -520,6 +520,51 @@ pins { }; }; =20 + /omit-if-no-ref/ + sai1a_pins_a: sai1a-0 { + pins1 { + pinmux =3D , /* SAI1_SD_A */ + , /* SAI1_FS_A */ + ; /* SAI1_SCK_A */ + bias-disable; + drive-push-pull; + slew-rate =3D <1>; + }; + pins2 { + pinmux =3D ; /* SAI1_MCLK_A */ + bias-disable; + drive-push-pull; + slew-rate =3D <2>; + }; + }; + + /omit-if-no-ref/ + sai1a_sleep_pins_a: sai1a-sleep-0 { + pins { + pinmux =3D , /* SAI1_SD_A */ + , /* SAI1_FS_A */ + , /* SAI1_SCK_A */ + ; /* SAI1_MCLK_A */ + }; + }; + + /omit-if-no-ref/ + sai1b_pins_a: sai1b-0 { + pins { + pinmux =3D ; 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[79.17.119.233]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47fd41d1a58sm30370503f8f.7.2026.08.03.00.43.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 00:43:06 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: domenico.acri@engicam.com, linux-amarula@amarulasolutions.com, michael@amarulasolutions.com, francesco.utel@engicam.com, Dario Binacchi , Alexandre Torgue , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RESEND PATCH v7 11/16] arm64: dts: st: add sdmmc2 pins for stm32mp25 Date: Mon, 3 Aug 2026 09:26:06 +0200 Message-ID: <20260803074224.3821911-12-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260803074224.3821911-1-dario.binacchi@amarulasolutions.com> References: <20260803074224.3821911-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the sdmmc2 pins used on MicroGEA-STM32MP257-RMM board. Signed-off-by: Dario Binacchi --- (no changes since v5) Changes in v5: - Change SDMMC2_CK pin bias from pull-up to bias-disable to avoid signal integrity issues on the clock line. Suggested by Sashiko arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 80 +++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boo= t/dts/st/stm32mp25-pinctrl.dtsi index 002fbc724b9d..c816a6aece47 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -622,6 +622,86 @@ pins { }; }; =20 + /omit-if-no-ref/ + sdmmc2_b4_pins_a: sdmmc2-b4-0 { + pins1 { + pinmux =3D , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + ; /* SDMMC2_CMD */ + slew-rate =3D <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux =3D ; /* SDMMC2_CK */ + slew-rate =3D <2>; + drive-push-pull; + bias-disable; + }; + }; + + /omit-if-no-ref/ + sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { + pins1 { + pinmux =3D , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + ; /* SDMMC2_D3 */ + slew-rate =3D <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux =3D ; /* SDMMC2_CK */ + slew-rate =3D <2>; + drive-push-pull; + bias-disable; + }; + pins3 { + pinmux =3D ; /* SDMMC2_CMD */ + slew-rate =3D <1>; + drive-open-drain; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { + pins { + pinmux =3D , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + , /* SDMMC2_CK */ + ; /* SDMMC2_CMD */ + }; + }; + + /omit-if-no-ref/ + sdmmc2_d47_pins_a: sdmmc2-d47-0 { + pins { + pinmux =3D , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + slew-rate =3D <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 { + pins { + pinmux =3D , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + }; + }; + /omit-if-no-ref/ spi3_pins_a: spi3-0 { pins1 { --=20 2.43.0 From nobody Fri Oct 2 09:26:35 2026 Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C0F93B059D for ; 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[79.17.119.233]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47fd41d1a58sm30370503f8f.7.2026.08.03.00.43.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 00:43:08 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: domenico.acri@engicam.com, linux-amarula@amarulasolutions.com, michael@amarulasolutions.com, francesco.utel@engicam.com, Dario Binacchi , Alexandre Torgue , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RESEND PATCH v7 12/16] arm64: dts: st: add spi1 pins for stm32mp25 Date: Mon, 3 Aug 2026 09:26:07 +0200 Message-ID: <20260803074224.3821911-13-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260803074224.3821911-1-dario.binacchi@amarulasolutions.com> References: <20260803074224.3821911-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the spi1 pins used on MicroGEA-STM32MP257-RMM board. Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boo= t/dts/st/stm32mp25-pinctrl.dtsi index c816a6aece47..4e570e2e5157 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -702,6 +702,30 @@ pins { }; }; =20 + /omit-if-no-ref/ + spi1_pins_a: spi1-0 { + pins1 { + pinmux =3D , /* SPI1_SCK */ + ; /* SPI1_MOSI */ + drive-push-pull; + bias-disable; + slew-rate =3D <1>; + }; + pins2 { + pinmux =3D ; /* SPI1_MISO */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + spi1_sleep_pins_a: spi1-sleep-0 { + pins1 { + pinmux =3D , /* SPI1_SCK */ + , /* SPI1_MOSI */ + ; /* SPI1_MISO */ + }; + }; + /omit-if-no-ref/ spi3_pins_a: spi3-0 { pins1 { --=20 2.43.0 From nobody Fri Oct 2 09:26:35 2026 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D71953B3BE1 for ; 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[79.17.119.233]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47fd41d1a58sm30370503f8f.7.2026.08.03.00.43.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 00:43:09 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: domenico.acri@engicam.com, linux-amarula@amarulasolutions.com, michael@amarulasolutions.com, francesco.utel@engicam.com, Dario Binacchi , Alexandre Torgue , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RESEND PATCH v7 13/16] arm64: dts: st: add usart1 pins for stm32mp25 Date: Mon, 3 Aug 2026 09:26:08 +0200 Message-ID: <20260803074224.3821911-14-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260803074224.3821911-1-dario.binacchi@amarulasolutions.com> References: <20260803074224.3821911-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the usart1 pins used on MicroGEA-STM32MP257-RMM board. Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boo= t/dts/st/stm32mp25-pinctrl.dtsi index 4e570e2e5157..d515e44832d7 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -766,6 +766,39 @@ pins { }; }; =20 + /omit-if-no-ref/ + usart1_pins_b: usart1-1 { + pins1 { + pinmux =3D ; /* USART1_TX */ + bias-disable; + drive-push-pull; + slew-rate =3D <0>; + }; + pins2 { + pinmux =3D ; /* USART1_RX */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + usart1_idle_pins_b: usart1-idle-1 { + pins1 { + pinmux =3D ; /* USART1_TX */ + }; + pins2 { + pinmux =3D ; /* USART1_RX */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + usart1_sleep_pins_b: usart1-sleep-1 { + pins { + pinmux =3D , /* USART1_TX */ + ; /* USART1_RX */ + }; + }; + /omit-if-no-ref/ usart2_pins_a: usart2-0 { pins1 { --=20 2.43.0 From nobody Fri Oct 2 09:26:35 2026 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 702783B4432 for ; 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[79.17.119.233]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47fd41d1a58sm30370503f8f.7.2026.08.03.00.43.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 00:43:11 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: domenico.acri@engicam.com, linux-amarula@amarulasolutions.com, michael@amarulasolutions.com, francesco.utel@engicam.com, Dario Binacchi , Alexandre Torgue , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RESEND PATCH v7 14/16] arm64: dts: st: support Engicam MicroGEA-STM32MP257 SoM Date: Mon, 3 Aug 2026 09:26:09 +0200 Message-ID: <20260803074224.3821911-15-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260803074224.3821911-1-dario.binacchi@amarulasolutions.com> References: <20260803074224.3821911-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support Engicam MicroGEA-STM32MP257 SoM with: - 8 GB eMMC Flash - 2 GB LPDDR4 DRAM The SoM also provides an Ethernet MAC, but Ethernet support is not enabled at this stage due to a known silicon limitation documented in [1]. This corresponds to section 2.21.2 ("ETH1 RMII mode could have CRC errors"), where CRC errors may occur in ETH1 RMII direct mode when directly connected to I/Os. The workaround requires use of the Ethernet switch (ETHSW), which introduces additional DT bindings and topology complexity. This is intended to be addressed in a separate patch series. [1] https://www.st.com/resource/en/errata_sheet/es0598-stm32mp23xx25xx-devi= ce-errata-stmicroelectronics.pdf Signed-off-by: Dario Binacchi --- (no changes since v4) Changes in v4: - Drop inclusion of stm32mp25xf.dtsi, we are using stm32mp257d. Changes in v3: - Fix a typo in the URL .../dts/st/stm32mp257-engicam-microgea.dtsi | 63 +++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 arch/arm64/boot/dts/st/stm32mp257-engicam-microgea.dtsi diff --git a/arch/arm64/boot/dts/st/stm32mp257-engicam-microgea.dtsi b/arch= /arm64/boot/dts/st/stm32mp257-engicam-microgea.dtsi new file mode 100644 index 000000000000..5b4287e86def --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp257-engicam-microgea.dtsi @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2026 Amarula Solutions, Dario Binacchi + * Copyright (C) 2026 Engicam srl + */ + +/dts-v1/; + +#include +#include "stm32mp257.dtsi" +#include "stm32mp25-pinctrl.dtsi" +#include "stm32mp25xxai-pinctrl.dtsi" + +/ { + model =3D "Engicam MicroGEA STM32MP257 SoM"; + compatible =3D "engicam,microgea-stm32mp257", "st,stm32mp257"; + + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x0 0x80000000 0x0 0x80000000>; + }; +}; + +&scmi_regu { + scmi_vddio1: regulator@0 { + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; + scmi_vddcore: regulator@b { + reg =3D ; + regulator-name =3D "vddcore"; + }; + scmi_v1v8: regulator@e { + reg =3D ; + regulator-name =3D "v1v8"; + }; + scmi_v3v3: regulator@10 { + reg =3D ; + regulator-name =3D "v3v3"; + }; + scmi_vdd3v3_usb: regulator@14 { + reg =3D ; + regulator-name =3D "vdd3v3_usb"; + }; +}; + +/* eMMC */ +&sdmmc2 { + pinctrl-names =3D "default", "opendrain", "sleep"; + pinctrl-0 =3D <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; + pinctrl-1 =3D <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>; + pinctrl-2 =3D <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; + non-removable; + no-sd; + no-sdio; + st,neg-edge; + bus-width =3D <8>; + vmmc-supply =3D <&scmi_v3v3>; + vqmmc-supply =3D <&scmi_vddio2>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + status =3D "okay"; +}; --=20 2.43.0 From nobody Fri Oct 2 09:26:35 2026 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC2A53B4EBF for ; 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Mon, 03 Aug 2026 00:43:13 -0700 (PDT) Received: from dario-ThinkPad-P14s-Gen-5.homenet.telecomitalia.it (host-79-17-119-233.retail.telecomitalia.it. [79.17.119.233]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47fd41d1a58sm30370503f8f.7.2026.08.03.00.43.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 00:43:12 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: domenico.acri@engicam.com, linux-amarula@amarulasolutions.com, michael@amarulasolutions.com, francesco.utel@engicam.com, Dario Binacchi , Alexandre Torgue , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RESEND PATCH v7 15/16] arm64: dts: st: support Engicam MicroGEA-STM32MP257-RMM board Date: Mon, 3 Aug 2026 09:26:10 +0200 Message-ID: <20260803074224.3821911-16-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260803074224.3821911-1-dario.binacchi@amarulasolutions.com> References: <20260803074224.3821911-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support for Engicam MicroGEA-STM32MP257-RMM board with: - 8 GB eMMC Flash - 2 GB LPDDR4 DRAM - CAN - LEDs - LCD panel with touchscreen - Micro SD card connector - Audio codec - Buzzer Signed-off-by: Dario Binacchi --- (no changes since v5) Changes in v5: - Fix touchscreen resolution to 480x854 - Fix SPI1 CS0 polarity to GPIO_ACTIVE_LOW Changes in v2: - Drop the clocks property from the sai1 node in stm32mp257-engicam-microge= a-rmm.dts to avoid overriding the peripheral bus clock reference defined in the base SoC device tree. Suggested by Sashiko. - Reference the existing labeled nodes directly at the root level using &sai1a and &sai1b in stm32mp257-engicam-microgea-rmm.dts instead of redefining the entire node structure and redeclaring the labels. Suggeste= d by Sashiko. - Drop the #clock-cells property from sai1a and remove the reference to sai= 1a from the clocks array in sai1b, relying strictly on the st,sync property to ha= ndle internal synchronization. arch/arm64/boot/dts/st/Makefile | 1 + .../st/stm32mp257-engicam-microgea-rmm.dts | 319 ++++++++++++++++++ 2 files changed, 320 insertions(+) create mode 100644 arch/arm64/boot/dts/st/stm32mp257-engicam-microgea-rmm.= dts diff --git a/arch/arm64/boot/dts/st/Makefile b/arch/arm64/boot/dts/st/Makef= ile index 63908113ae36..386eca593c54 100644 --- a/arch/arm64/boot/dts/st/Makefile +++ b/arch/arm64/boot/dts/st/Makefile @@ -2,5 +2,6 @@ dtb-$(CONFIG_ARCH_STM32) +=3D \ stm32mp215f-dk.dtb \ stm32mp235f-dk.dtb \ + stm32mp257-engicam-microgea-rmm.dtb \ stm32mp257f-dk.dtb \ stm32mp257f-ev1.dtb diff --git a/arch/arm64/boot/dts/st/stm32mp257-engicam-microgea-rmm.dts b/a= rch/arm64/boot/dts/st/stm32mp257-engicam-microgea-rmm.dts new file mode 100644 index 000000000000..3aea0c2f6651 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp257-engicam-microgea-rmm.dts @@ -0,0 +1,319 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2026 Amarula Solutions, Dario Binacchi + * Copyright (C) 2026 Engicam srl + */ + +/dts-v1/; + +#include +#include +#include + +#include "stm32mp257-engicam-microgea.dtsi" + +/ { + model =3D "Engicam MicroGEA STM32MP257D RMM Board"; + compatible =3D "engicam,microgea-stm32mp257-rmm", + "engicam,microgea-stm32mp257", "st,stm32mp257"; + + aliases { + mmc0 =3D &sdmmc1; + mmc1 =3D &sdmmc2; + serial0 =3D &usart2; + serial1 =3D &usart1; + }; + + backlight: backlight { + compatible =3D "pwm-backlight"; + brightness-levels =3D <0 100>; + num-interpolated-steps =3D <100>; + default-brightness-level =3D <85>; + pwms =3D <&pwm2 0 100000 0>; + }; + + buzzer { + compatible =3D "pwm-beeper"; + pwms =3D <&pwm4 0 1000000 0>; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + framebuffer { + compatible =3D "simple-framebuffer"; + clocks =3D <&rcc CK_BUS_LTDC>, <&rcc CK_KER_LTDC>; + lcd-supply =3D <®_3v3>; + status =3D "disabled"; + }; + }; + + leds { + compatible =3D "gpio-leds"; + + led-0 { + gpios =3D <&gpioh 2 GPIO_ACTIVE_HIGH>; + default-state =3D "off"; + status =3D "okay"; + }; + + led-1 { + gpios =3D <&gpioh 6 GPIO_ACTIVE_HIGH>; + default-state =3D "off"; + status =3D "okay"; + }; + }; + + mclk: clock-mclk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + }; + + reg_1v8: regulator-1v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + reg_3v3: regulator-3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; + + reg_ext_pwr: regulator-ext-pwr { + compatible =3D "regulator-fixed"; + regulator-name =3D "ext-pwr"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&gpiog 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + sound { + compatible =3D "audio-graph-card"; + label =3D "STM32MP25-RMM"; + widgets =3D "Headphone", "Headphone Jack", + "Microphone", "Microphone Jack"; + routing =3D "Headphone Jack", "HP_OUT", + "MIC_IN", "Microphone Jack", + "Microphone Jack", "Mic Bias"; + dais =3D <&sai1a_port &sai1b_port>; + status =3D "okay"; + }; +}; + +&arm_wdt { + timeout-sec =3D <32>; + status =3D "okay"; +}; + +&i2c1 { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&i2c1_pins_a>; + pinctrl-1 =3D <&i2c1_sleep_pins_a>; + i2c-scl-rising-time-ns =3D <185>; + i2c-scl-falling-time-ns =3D <20>; + status =3D "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + touchscreen@38 { + compatible =3D "edt,edt-ft5306"; + reg =3D <0x38>; + interrupt-parent =3D <&gpiob>; + interrupts =3D <0 IRQ_TYPE_EDGE_FALLING>; + reset-gpios =3D <&gpiod 1 GPIO_ACTIVE_LOW>; + touchscreen-size-x =3D <480>; + touchscreen-size-y =3D <854>; + }; +}; + +&i2c2 { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&i2c2_pins_a>; + pinctrl-1 =3D <&i2c2_sleep_pins_a>; + i2c-scl-rising-time-ns =3D <185>; + i2c-scl-falling-time-ns =3D <20>; + status =3D "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + sgtl5000: codec@a { + compatible =3D "fsl,sgtl5000"; + reg =3D <0x0a>; + #sound-dai-cells =3D <0>; + clocks =3D <&mclk>; + + VDDA-supply =3D <®_3v3>; + VDDIO-supply =3D <®_3v3>; + VDDD-supply =3D <®_1v8>; + + sgtl5000_port: port { + #address-cells =3D <1>; + #size-cells =3D <0>; + + sgtl5000_tx_endpoint: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&sai1a_endpoint>; + frame-master =3D <&sgtl5000_tx_endpoint>; + bitclock-master =3D <&sgtl5000_tx_endpoint>; + }; + + sgtl5000_rx_endpoint: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&sai1b_endpoint>; + frame-master =3D <&sgtl5000_rx_endpoint>; + bitclock-master =3D <&sgtl5000_rx_endpoint>; + }; + }; + }; +}; + +<dc { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <<dc_pins_a>; + pinctrl-1 =3D <<dc_sleep_pins_a>; + status =3D "okay"; + + port { + ltdc_out: endpoint { + remote-endpoint =3D <&panel_in>; + }; + }; +}; + +&m_can1 { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&m_can1_pins_a>; + pinctrl-1 =3D <&m_can1_sleep_pins_a>; + status =3D "okay"; +}; + +&sai1 { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&sai1a_pins_a>, <&sai1b_pins_a>; + pinctrl-1 =3D <&sai1a_sleep_pins_a>, <&sai1b_sleep_pins_a>; + status =3D "okay"; +}; + +&sai1a { + dma-names =3D "tx"; + status =3D "okay"; + + sai1a_port: port { + sai1a_endpoint: endpoint { + remote-endpoint =3D <&sgtl5000_tx_endpoint>; + dai-format =3D "i2s"; + mclk-fs =3D <512>; + }; + }; +}; + +&sai1b { + dma-names =3D "rx"; + st,sync =3D <&sai1a 2>; + clocks =3D <&rcc CK_KER_SAI1>; + clock-names =3D "sai_ck"; + status =3D "okay"; + + sai1b_port: port { + sai1b_endpoint: endpoint { + remote-endpoint =3D <&sgtl5000_rx_endpoint>; + dai-format =3D "i2s"; + mclk-fs =3D <512>; + }; + }; +}; + +/* MicroSD */ +&sdmmc1 { + pinctrl-names =3D "default", "opendrain", "sleep"; + pinctrl-0 =3D <&sdmmc1_b4_pins_a>; + pinctrl-1 =3D <&sdmmc1_b4_od_pins_a>; + pinctrl-2 =3D <&sdmmc1_b4_sleep_pins_a>; + broken-cd; + disable-wp; + st,neg-edge; + bus-width =3D <4>; + vmmc-supply =3D <&scmi_v3v3>; + vqmmc-supply =3D <&scmi_vddio1>; + no-1-8-v; + status =3D "okay"; +}; + +&spi1 { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&spi1_pins_a>; + pinctrl-1 =3D <&spi1_sleep_pins_a>; + #address-cells =3D <1>; + #size-cells =3D <0>; + cs-gpios =3D <&gpioh 8 GPIO_ACTIVE_LOW>, <&gpioh 3 GPIO_ACTIVE_HIGH>; + status =3D "okay"; + + display: display@0 { + compatible =3D "rocktech,rk050hr345-ct106a", "ilitek,ili9806e"; + reg =3D <0>; + vdd-supply =3D <®_3v3>; + spi-max-frequency =3D <10000000>; + reset-gpios =3D <&gpiob 6 GPIO_ACTIVE_LOW>; + backlight =3D <&backlight>; + + port { + panel_in: endpoint { + remote-endpoint =3D <<dc_out>; + }; + }; + }; +}; + +&timers2 { + status =3D "okay"; + + pwm2: pwm { + pinctrl-0 =3D <&pwm2_pins_a>; + pinctrl-1 =3D <&pwm2_sleep_pins_a>; + pinctrl-names =3D "default", "sleep"; + status =3D "okay"; + }; +}; + +&timers4 { + status =3D "okay"; + + pwm4: pwm { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&pwm4_pins_a>; + pinctrl-1 =3D <&pwm4_sleep_pins_a>; + status =3D "okay"; + }; +}; + +&usart1 { + pinctrl-names =3D "default", "idle", "sleep"; + pinctrl-0 =3D <&usart1_pins_b>; + pinctrl-1 =3D <&usart1_idle_pins_b>; + pinctrl-2 =3D <&usart1_sleep_pins_b>; + /delete-property/ dmas; + /delete-property/ dma-names; + status =3D "okay"; +}; + +&usart2 { + pinctrl-names =3D "default", "idle", "sleep"; + pinctrl-0 =3D <&usart2_pins_a>; + pinctrl-1 =3D <&usart2_idle_pins_a>; + pinctrl-2 =3D <&usart2_sleep_pins_a>; + /delete-property/ dmas; + /delete-property/ dma-names; + status =3D "okay"; +}; --=20 2.43.0 From nobody Fri Oct 2 09:26:35 2026 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 751F13B2D14 for ; Mon, 3 Aug 2026 07:43:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[79.17.119.233]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47fd41d1a58sm30370503f8f.7.2026.08.03.00.43.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 00:43:14 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: domenico.acri@engicam.com, linux-amarula@amarulasolutions.com, michael@amarulasolutions.com, francesco.utel@engicam.com, Dario Binacchi , Arnd Bergmann , Bjorn Andersson , Dmitry Baryshkov , Eric Biggers , Geert Uytterhoeven , Krzysztof Kozlowski , Luca Weiss , Michal Simek , Sven Peter Subject: [RESEND PATCH v7 16/16] arm64: defconfig: enable configs for Engicam MicroGEA-STM32MP257-RMM Date: Mon, 3 Aug 2026 09:26:11 +0200 Message-ID: <20260803074224.3821911-17-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260803074224.3821911-1-dario.binacchi@amarulasolutions.com> References: <20260803074224.3821911-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable I2C (touchscreen and audio codec), SPI (display configuration), DRM panel and SAI (audio) configurations required to support the Engicam MicroGEA-STM32MP257-RMM board Signed-off-by: Dario Binacchi --- Changes in v7: - Add Reviewed-by tag of Olivier Moysan to patch 10/16 "arm64: dts: st: add sai1 pins for stm32mp25" - Switch CONFIG_I2C_STM32F7 and CONFIG_SPI_STM32 to modules. Changes in v6: - Update arch/arm64/configs/defconfig to match the current upstream defconf= ig after merge window changes (no functional changes). Changes in v5: - Add patch 2/16 arm64: dts: st: add power-domains to sdmmc1 on stm32mp231 - Add patch 3/16 arm64: dts: st: add power-domains to sdmmc1 on stm32mp251 - Increase slew-rate to <1> of ltdc pins to support the 27 MHz pixel clock and prevent timing violations. - Change SDMMC2_CK pin bias from pull-up to bias-disable to avoid signal integrity issues on the clock line - Fix touchscreen resolution to 480x854 - Fix SPI1 CS0 polarity to GPIO_ACTIVE_LOW Changes in v4: - Drop inclusion of stm32mp25xf.dtsi from stm32mp257-engicam-microgea.dtsi Changes in v3: - Add power-domains property in the SDMMC2 node. - Drop patch "arm64: defconfig: cleanup the defconfig" - Rebased after dropping patch "arm64: defconfig: cleanup the defconfig" arch/arm64/configs/defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 654a102cb5bc..99cd81b684ea 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -633,6 +633,7 @@ CONFIG_I2C_RK3X=3Dy CONFIG_I2C_RZV2M=3Dm CONFIG_I2C_S3C2410=3Dy CONFIG_I2C_SH_MOBILE=3Dy +CONFIG_I2C_STM32F7=3Dm CONFIG_I2C_TEGRA=3Dy CONFIG_I2C_UNIPHIER_F=3Dy CONFIG_I2C_XILINX=3Dm @@ -670,6 +671,7 @@ CONFIG_SPI_QUP=3Dy CONFIG_SPI_QCOM_GENI=3Dm CONFIG_SPI_S3C64XX=3Dy CONFIG_SPI_SH_MSIOF=3Dm +CONFIG_SPI_STM32=3Dm CONFIG_SPI_STM32_OSPI=3Dm CONFIG_SPI_SUN6I=3Dy CONFIG_SPI_TEGRA210_QUAD=3Dm @@ -1011,6 +1013,7 @@ CONFIG_DRM_PANEL_LVDS=3Dm CONFIG_DRM_PANEL_HIMAX_HX8279=3Dm CONFIG_DRM_PANEL_HIMAX_HX83112A=3Dm CONFIG_DRM_PANEL_HIMAX_HX83112B=3Dm +CONFIG_DRM_PANEL_ILITEK_ILI9806E_SPI=3Dm CONFIG_DRM_PANEL_ILITEK_ILI9882T=3Dm CONFIG_DRM_PANEL_KHADAS_TS050=3Dm CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=3Dm @@ -1113,6 +1116,7 @@ CONFIG_SND_SOC_ROCKCHIP_SPDIF=3Dm CONFIG_SND_SOC_ROCKCHIP_RT5645=3Dm CONFIG_SND_SOC_RK3399_GRU_SOUND=3Dm CONFIG_SND_SOC_SAMSUNG=3Dm +CONFIG_SND_SOC_STM32_SAI=3Dm CONFIG_SND_SUN8I_CODEC=3Dm CONFIG_SND_SUN8I_CODEC_ANALOG=3Dm CONFIG_SND_SUN50I_CODEC_ANALOG=3Dm --=20 2.43.0