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charset="utf-8" From: Richard Zhu We observed poor bandwidth margins during i.MX95 Gen3 PCIe tests with the default MPLLB_BANDWIDTH value (120). The margins worsened across voltage and temperature (VT) variations and different test matrices, potentially causing link stability issues. Testing with MPLLB_BANDWIDTH value of 140 (0x8c) shows significant improvement in bandwidth margins across all VT conditions and test scenarios. Implement PHY register write helper function and configure: - MPLLB_BW_OVRD_IN =3D 140 (0x8c) for improved bandwidth margin - MPLLB_BW_OVRD_EN to enable the override This ensures robust PCIe Gen3 performance across all operating conditions. Signed-off-by: Richard Zhu Reviewed-by: Frank Li --- Changes in v5: Update the commit log refer to Bjorn's suggestions. Changes in v4: Move the delay to imx95_pcie_init_phy() with a comment added. Changes in v3: Regarding Frank's comments, refine naming consistency and clarity. Changes in v2: Update the register name and bit definitions. Don't move IMX95_PCIE_PHY_CR_PARA_SEL settings. --- drivers/pci/controller/dwc/pci-imx6.c | 32 +++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index 39790e66b98dc..3bc52c4781903 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -80,6 +80,17 @@ #define IMX95_SID_MASK GENMASK(5, 0) #define IMX95_MAX_LUT 32 =20 +#define IMX95_PCIE_PHY_REG_ADDR 0x3008 +#define IMX95_PCIE_PHY_REG_EN BIT(31) +#define IMX95_PCIE_PHY_REG_ADDR_MASK GENMASK(15, 0) +#define IMX95_PCIE_PHY_REG_DATA 0x300c +#define IMX95_PCIE_PHY_MPLLB_OVRD_IN 0x2004 +/* BIT(10): Override enable for mpllb_bandwidth[15:0] */ +#define IMX95_PCIE_PHY_MPLLB_OVRD_BW_EN BIT(10) +/* Register offset: Override value for mpllb_bandwidth[15:0] */ +#define IMX95_PCIE_PHY_MPLLB_BW_IN 0x2005 +#define IMX95_PCIE_PHY_MPLLB_BW_VAL 0x8c + #define IMX95_PCIE_RST_CTRL 0x3010 #define IMX95_PCIE_COLD_RST BIT(0) =20 @@ -270,6 +281,15 @@ static int imx95_pcie_select_ref_clk_src(struct imx_pc= ie *imx_pcie) return 0; } =20 +static void imx95_pcie_phy_write(struct imx_pcie *imx_pcie, int addr, u16 = data) +{ + regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_PHY_REG_ADDR, + IMX95_PCIE_PHY_REG_EN, IMX95_PCIE_PHY_REG_EN); + regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_PHY_REG_ADDR, + IMX95_PCIE_PHY_REG_ADDR_MASK, addr); + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PCIE_PHY_REG_DATA, data); +} + static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie) { /* @@ -290,6 +310,18 @@ static int imx95_pcie_init_phy(struct imx_pcie *imx_pc= ie) IMX95_PCIE_PHY_CR_PARA_SEL, IMX95_PCIE_PHY_CR_PARA_SEL); =20 + /* + * A delay is required between the assertion of + * IMX95_PCIE_PHY_CR_PARA_SEL and subsequent PHY register write + * operation to ensure values are successfully written. + */ + udelay(200); + + imx95_pcie_phy_write(imx_pcie, IMX95_PCIE_PHY_MPLLB_BW_IN, + IMX95_PCIE_PHY_MPLLB_BW_VAL); + imx95_pcie_phy_write(imx_pcie, IMX95_PCIE_PHY_MPLLB_OVRD_IN, + IMX95_PCIE_PHY_MPLLB_OVRD_BW_EN); + return 0; } =20 --=20 2.34.1