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Shikra has 10 QUP serial engines under a single QUP wrapper, all with support of GPI DMA engines. Signed-off-by: Xueyao An Reviewed-by: Dmitry Baryshkov Signed-off-by: Komal Bajaj --- arch/arm64/boot/dts/qcom/shikra.dtsi | 951 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 951 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qco= m/shikra.dtsi index 80e8045282d8..524c88615d08 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -348,6 +349,161 @@ tlmm: pinctrl@500000 { gpio-ranges =3D <&tlmm 0 0 165>; wakeup-parent =3D <&mpm>; =20 + qup_i2c0_data_clk: qup-i2c0-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio2", "gpio3"; + function =3D "qup0_se0"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c1_data_clk: qup-i2c1-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio4", "gpio5"; + function =3D "qup0_se1_01"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c2_data_clk: qup-i2c2-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio6", "gpio7"; + function =3D "qup0_se2"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c3_data_clk: qup-i2c3-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio10", "gpio11"; + function =3D "qup0_se3_01"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c4_data_clk: qup-i2c4-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio12", "gpio13"; + function =3D "qup0_se4_01"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c5_data_clk: qup-i2c5-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio14", "gpio15"; + function =3D "qup0_se5"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c6_data_clk: qup-i2c6-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio18", "gpio19"; + function =3D "qup0_se6"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c7_data_clk: qup-i2c7-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio20", "gpio21"; + function =3D "qup0_se7_01"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c8_data_clk: qup-i2c8-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio22", "gpio23"; + function =3D "qup0_se8"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c9_data_clk: qup-i2c9-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio27", "gpio26"; + function =3D "qup0_se9_01"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi0_cs: qup-spi0-cs-state { + pins =3D "gpio1"; + function =3D "qup0_se0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi0_data_clk: qup-spi0-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio2", "gpio3", "gpio0"; + function =3D "qup0_se0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi2_cs: qup-spi2-cs-state { + pins =3D "gpio9"; + function =3D "qup0_se2"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi2_data_clk: qup-spi2-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio6", "gpio7", "gpio8"; + function =3D "qup0_se2"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi5_cs: qup-spi5-cs-state { + pins =3D "gpio17"; + function =3D "qup0_se5"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi5_data_clk: qup-spi5-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio14", "gpio15", "gpio16"; + function =3D "qup0_se5"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi6_cs: qup-spi6-cs-state { + pins =3D "gpio29"; + function =3D "qup0_se6"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi6_data_clk: qup-spi6-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio18", "gpio19", "gpio28"; + function =3D "qup0_se6"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi8_cs: qup-spi8-cs-state { + pins =3D "gpio25"; + function =3D "qup0_se8"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi8_data_clk: qup-spi8-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio22", "gpio23", "gpio24"; + function =3D "qup0_se8"; + drive-strength =3D <6>; + bias-disable; + }; + qup_uart0_default: qup-uart0-default-state { pins =3D "gpio0", "gpio1"; function =3D "qup0_se0"; @@ -355,6 +511,105 @@ qup_uart0_default: qup-uart0-default-state { bias-disable; }; =20 + qup_uart1_default: qup-uart1-default-state { + pins =3D "gpio4", "gpio5"; + function =3D "qup0_se1_23"; + drive-strength =3D <2>; + bias-disable; + }; + + qup_uart2_default: qup-uart2-default-state { + /* TX, RX */ + pins =3D "gpio8", "gpio9"; + function =3D "qup0_se2"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_uart2_cts_rts: qup-uart2-cts-rts-state { + /* CTS, RTS */ + pins =3D "gpio6", "gpio7"; + function =3D "qup0_se2"; + drive-strength =3D <2>; + bias-pull-down; + }; + + qup_uart3_default: qup-uart3-default-state { + pins =3D "gpio10", "gpio11"; + function =3D "qup0_se3_23"; + drive-strength =3D <2>; + bias-disable; + }; + + qup_uart4_default: qup-uart4-default-state { + pins =3D "gpio12", "gpio13"; + function =3D "qup0_se4_23"; + drive-strength =3D <2>; + bias-disable; + }; + + qup_uart5_default: qup-uart5-default-state { + /* TX, RX */ + pins =3D "gpio16", "gpio17"; + function =3D "qup0_se5"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_uart5_cts_rts: qup-uart5-cts-rts-state { + /* CTS, RTS */ + pins =3D "gpio14", "gpio15"; + function =3D "qup0_se5"; + drive-strength =3D <2>; + bias-pull-down; + }; + + qup_uart6_default: qup-uart6-default-state { + /* TX, RX */ + pins =3D "gpio28", "gpio29"; + function =3D "qup0_se6"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_uart6_cts_rts: qup-uart6-cts-rts-state { + /* CTS, RTS */ + pins =3D "gpio18", "gpio19"; + function =3D "qup0_se6"; + drive-strength =3D <2>; + bias-pull-down; + }; + + qup_uart7_default: qup-uart7-default-state { + pins =3D "gpio20", "gpio21"; + function =3D "qup0_se7_23"; + drive-strength =3D <2>; + bias-disable; + }; + + qup_uart8_default: qup-uart8-default-state { + /* TX, RX */ + pins =3D "gpio24", "gpio25"; + function =3D "qup0_se8"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_uart8_cts_rts: qup-uart8-cts-rts-state { + /* CTS, RTS */ + pins =3D "gpio22", "gpio23"; + function =3D "qup0_se8"; + drive-strength =3D <2>; + bias-pull-down; + }; + + qup_uart9_default: qup-uart9-default-state { + pins =3D "gpio26", "gpio27"; + function =3D "qup0_se9_23"; + drive-strength =3D <2>; + bias-disable; + }; + sdc1_state_on: sdc1-on-state { clk-pins { pins =3D "sdc1_clk"; @@ -604,6 +859,34 @@ opp-384000000 { }; }; =20 + gpi_dma0: dma-controller@4a00000 { + compatible =3D "qcom,shikra-gpi-dma", "qcom,sm6350-gpi-dma"; + reg =3D <0x0 0x04a00000 0x0 0x60000>; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels =3D <16>; + dma-channel-mask =3D <0xff>; + #dma-cells =3D <3>; + + iommus =3D <&apps_smmu 0xf6 0x0>; + }; + qupv3_0: geniqup@4ac0000 { compatible =3D "qcom,geni-se-qup"; reg =3D <0x0 0x04ac0000 0x0 0x2000>; @@ -613,10 +896,75 @@ qupv3_0: geniqup@4ac0000 { clock-names =3D "m-ahb", "s-ahb"; =20 + iommus =3D <&apps_smmu 0xe3 0x0>; + #address-cells =3D <2>; #size-cells =3D <2>; ranges; =20 + status =3D "disabled"; + + i2c0: i2c@4a80000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x4a80000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names =3D "tx", "rx"; + + pinctrl-0 =3D <&qup_i2c0_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi0: spi@4a80000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x4a80000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names =3D "tx", "rx"; + + pinctrl-0 =3D <&qup_spi0_data_clk>, <&qup_spi0_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + uart0: serial@4a80000 { compatible =3D "qcom,geni-debug-uart"; reg =3D <0x0 0x04a80000 0x0 0x4000>; @@ -638,6 +986,609 @@ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, =20 status =3D "disabled"; }; + + i2c1: i2c@4a84000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x4a84000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names =3D "tx", "rx"; + + pinctrl-0 =3D <&qup_i2c1_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart1: serial@4a84000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x04a84000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart1_default>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + + i2c2: i2c@4a88000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x4a88000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + pinctrl-0 =3D <&qup_i2c2_data_clk>; + pinctrl-names =3D "default"; + + dmas =3D <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names =3D "tx", "rx"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi2: spi@4a88000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x4a88000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names =3D "tx", "rx"; + + pinctrl-0 =3D <&qup_spi2_data_clk>, <&qup_spi2_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart2: serial@4a88000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x04a88000 0x0 0x4000>; + + interrupts-extended =3D <&intc GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH 0>, + <&tlmm 9 IRQ_TYPE_LEVEL_HIGH>; + + clocks =3D <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart2_default>, <&qup_uart2_cts_rts>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + + i2c3: i2c@4a8c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x4a8c000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names =3D "tx", "rx"; + + pinctrl-0 =3D <&qup_i2c3_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart3: serial@4a8c000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x04a8c000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart3_default>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + + i2c4: i2c@4a90000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x4a90000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names =3D "tx", "rx"; + + pinctrl-0 =3D <&qup_i2c4_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart4: serial@4a90000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x04a90000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart4_default>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + + i2c5: i2c@4a94000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x4a94000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dma-names =3D "tx", "rx"; + + pinctrl-0 =3D <&qup_i2c5_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi5: spi@4a94000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x4a94000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma0 0 5 QCOM_GPI_SPI>, + <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dma-names =3D "tx", "rx"; + + pinctrl-0 =3D <&qup_spi5_data_clk>, <&qup_spi5_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart5: serial@4a94000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x04a94000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart5_default>, <&qup_uart5_cts_rts>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + + i2c6: i2c@4a98000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x4a98000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma0 0 6 QCOM_GPI_I2C>, + <&gpi_dma0 1 6 QCOM_GPI_I2C>; + dma-names =3D "tx", "rx"; + + pinctrl-0 =3D <&qup_i2c6_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi6: spi@4a98000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x4a98000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma0 0 6 QCOM_GPI_SPI>, + <&gpi_dma0 1 6 QCOM_GPI_SPI>; + dma-names =3D "tx", "rx"; + + pinctrl-0 =3D <&qup_spi6_data_clk>, <&qup_spi6_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart6: serial@4a98000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x04a98000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart6_default>, <&qup_uart6_cts_rts>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + + i2c7: i2c@4a9c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x4a9c000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma0 0 7 QCOM_GPI_I2C>, + <&gpi_dma0 1 7 QCOM_GPI_I2C>; + dma-names =3D "tx", "rx"; + + pinctrl-0 =3D <&qup_i2c7_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart7: serial@4a9c000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x04a9c000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart7_default>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + + i2c8: i2c@4aa0000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x4aa0000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP0_S8_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma0 0 8 QCOM_GPI_I2C>, + <&gpi_dma0 1 8 QCOM_GPI_I2C>; + dma-names =3D "tx", "rx"; + + pinctrl-0 =3D <&qup_i2c8_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + spi8: spi@4aa0000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x4aa0000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP0_S8_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names =3D "qup-core", + "qup-config"; + + dmas =3D <&gpi_dma0 0 8 QCOM_GPI_SPI>, + <&gpi_dma0 1 8 QCOM_GPI_SPI>; + dma-names =3D "tx", "rx"; + + pinctrl-0 =3D <&qup_spi8_data_clk>, <&qup_spi8_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart8: serial@4aa0000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x04aa0000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP0_S8_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart8_default>, <&qup_uart8_cts_rts>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + + i2c9: i2c@4aa4000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x4aa4000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP0_S9_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma0 0 9 QCOM_GPI_I2C>, + <&gpi_dma0 1 9 QCOM_GPI_I2C>; + dma-names =3D "tx", "rx"; + + pinctrl-0 =3D <&qup_i2c9_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart9: serial@4aa4000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x04aa4000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP0_S9_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart9_default>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; }; =20 sram@c11e000 { --=20 2.34.1 From nobody Fri Oct 2 08:28:42 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 886543FF1B5 for ; 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Mon, 03 Aug 2026 04:26:57 -0700 (PDT) Received: from [10.213.101.118] ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-13fab132cc4sm29967043c88.2.2026.08.03.04.26.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 04:26:56 -0700 (PDT) From: Komal Bajaj Date: Mon, 03 Aug 2026 16:56:31 +0530 Subject: [PATCH RESEND v7 02/10] arm64: dts: qcom: shikra: Add DDR BWMON support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260803-shikra-dt-m1-v7-2-7fec8e777076@oss.qualcomm.com> References: <20260803-shikra-dt-m1-v7-0-7fec8e777076@oss.qualcomm.com> In-Reply-To: <20260803-shikra-dt-m1-v7-0-7fec8e777076@oss.qualcomm.com> To: Vinod Koul , Frank Li , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Georgi Djakov , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Komal Bajaj , Sayantan Chakraborty , Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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This is necessary to enable power management and optimize system performance from the perspective of dynamically changing DDR frequencies. Signed-off-by: Sayantan Chakraborty Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Komal Bajaj --- arch/arm64/boot/dts/qcom/shikra.dtsi | 40 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qco= m/shikra.dtsi index 524c88615d08..3582352dcff7 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -661,6 +661,46 @@ rclk-pins { }; }; =20 + pmu@c91000 { + compatible =3D "qcom,shikra-cpu-bwmon", "qcom,sc7280-llcc-bwmon"; + reg =3D <0x0 0x00c91000 0x0 0x1000>; + + interrupts =3D ; + + interconnects =3D <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>; + + operating-points-v2 =3D <&cpu_bwmon_opp_table>; + + cpu_bwmon_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-0 { + opp-peak-kBps =3D <1200000>; + }; + + opp-1 { + opp-peak-kBps =3D <2188000>; + }; + + opp-2 { + opp-peak-kBps =3D <3072000>; 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Also, add Epoch Subsystem (EPSS) L3 interconnect provider node and OPP tables required to scale DDR and L3 per freq-domain on Shikra SoC. Co-developed-by: Aastha Pandey Signed-off-by: Aastha Pandey Co-developed-by: Imran Shaik Signed-off-by: Imran Shaik Co-developed-by: Raviteja Laggyshetty Signed-off-by: Raviteja Laggyshetty Co-developed-by: Sayantan Chakraborty Signed-off-by: Sayantan Chakraborty Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Komal Bajaj --- arch/arm64/boot/dts/qcom/shikra.dtsi | 140 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 140 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qco= m/shikra.dtsi index 3582352dcff7..a01e26d9ee6d 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -44,6 +45,14 @@ cpu0: cpu@0 { next-level-cache =3D <&l3>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; + clocks =3D <&cpufreq_hw 0>; + qcom,freq-domain =3D <&cpufreq_hw 0>; + #cooling-cells =3D <2>; + operating-points-v2 =3D <&cpu0_opp_table>; + interconnects =3D <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; }; =20 cpu1: cpu@100 { @@ -54,6 +63,14 @@ cpu1: cpu@100 { next-level-cache =3D <&l3>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; + clocks =3D <&cpufreq_hw 0>; + qcom,freq-domain =3D <&cpufreq_hw 0>; + #cooling-cells =3D <2>; + operating-points-v2 =3D <&cpu0_opp_table>; + interconnects =3D <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; }; =20 cpu2: cpu@200 { @@ -64,6 +81,14 @@ cpu2: cpu@200 { next-level-cache =3D <&l3>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; + clocks =3D <&cpufreq_hw 0>; + qcom,freq-domain =3D <&cpufreq_hw 0>; + #cooling-cells =3D <2>; + operating-points-v2 =3D <&cpu0_opp_table>; + interconnects =3D <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; }; =20 cpu3: cpu@300 { @@ -74,6 +99,14 @@ cpu3: cpu@300 { next-level-cache =3D <&l2_3>; capacity-dmips-mhz =3D <1946>; dynamic-power-coefficient =3D <489>; + clocks =3D <&cpufreq_hw 1>; + qcom,freq-domain =3D <&cpufreq_hw 1>; + #cooling-cells =3D <2>; + operating-points-v2 =3D <&cpu3_opp_table>; + interconnects =3D <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; =20 l2_3: l2-cache { compatible =3D "cache"; @@ -132,6 +165,86 @@ memory@80000000 { reg =3D <0x0 0x80000000 0x0 0x0>; }; =20 + cpu0_opp_table: opp-table-cpu0 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-768000000 { + opp-hz =3D /bits/ 64 <768000000>; + opp-peak-kBps =3D <1200000 17817600>; + }; + + opp-1017600000 { + opp-hz =3D /bits/ 64 <1017600000>; + opp-peak-kBps =3D <2188000 25804800>; + }; + + opp-1094400000 { + opp-hz =3D /bits/ 64 <1094400000>; + opp-peak-kBps =3D <3072000 30105600>; + }; + + opp-1497600000 { + opp-hz =3D /bits/ 64 <1497600000>; + opp-peak-kBps =3D <4068000 38707200>; + }; + + opp-1612800000 { + opp-hz =3D /bits/ 64 <1612800000>; + opp-peak-kBps =3D <6220000 43008000>; + }; + + opp-1804800000 { + opp-hz =3D /bits/ 64 <1804800000>; + opp-peak-kBps =3D <7216000 43622400>; + }; + + opp-2208000000 { + opp-hz =3D /bits/ 64 <2208000000>; + opp-peak-kBps =3D <7216000 43622400>; + }; + }; + + cpu3_opp_table: opp-table-cpu3 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-768000000 { + opp-hz =3D /bits/ 64 <768000000>; + opp-peak-kBps =3D <1200000 17817600>; + }; + + opp-1017600000 { + opp-hz =3D /bits/ 64 <1017600000>; + opp-peak-kBps =3D <2188000 25804800>; + }; + + opp-1190400000 { + opp-hz =3D /bits/ 64 <1190400000>; + opp-peak-kBps =3D <3072000 30105600>; + }; + + opp-1497600000 { + opp-hz =3D /bits/ 64 <1497600000>; + opp-peak-kBps =3D <4068000 38707200>; + }; + + opp-1708800000 { + opp-hz =3D /bits/ 64 <1708800000>; + opp-peak-kBps =3D <6220000 43008000>; + }; + + opp-1900800000 { + opp-hz =3D /bits/ 64 <1900800000>; + opp-peak-kBps =3D <7216000 43622400>; + }; + + opp-2208000000 { + opp-hz =3D /bits/ 64 <2208000000>; + opp-peak-kBps =3D <7216000 43622400>; + }; + }; + pmu-a55 { compatible =3D "arm,cortex-a55-pmu"; interrupts =3D ; @@ -1820,6 +1933,33 @@ frame@f42d000 { status =3D "disabled"; }; }; + + epss_l3: interconnect@fd90000 { + compatible =3D "qcom,shikra-epss-l3"; + reg =3D <0x0 0x0fd90000 0x0 0x1000>; + clocks =3D <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; + #interconnect-cells =3D <1>; + }; + + cpufreq_hw: cpufreq@fd91000 { + compatible =3D "qcom,shikra-epss"; + reg =3D <0x0 0x0fd91000 0x0 0x1000>, + <0x0 0x0fd92000 0x0 0x1000>; + reg-names =3D "freq-domain0", + "freq-domain1"; + + clocks =3D <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; + + interrupts =3D , + ; + interrupt-names =3D "dcvsh-irq-0", + "dcvsh-irq-1"; + + #freq-domain-cells =3D <1>; + #clock-cells =3D <1>; + }; }; =20 timer { --=20 2.34.1 From nobody Fri Oct 2 08:28:42 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B239C401497 for ; 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Signed-off-by: Vishnu Santhosh Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Komal Bajaj --- arch/arm64/boot/dts/qcom/shikra.dtsi | 69 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 69 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qco= m/shikra.dtsi index a01e26d9ee6d..42a17ffc040f 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -428,6 +428,75 @@ lmcu_dtb_mem: lmcu-dtb@b4702000 { }; }; =20 + smp2p-cdsp { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <94>, <432>; + + interrupts =3D ; + + mboxes =3D <&apcs_glb 6>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-lmcu { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <617>, <616>; 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Mon, 03 Aug 2026 04:27:17 -0700 (PDT) Received: from [10.213.101.118] ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-13fab132cc4sm29967043c88.2.2026.08.03.04.27.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 04:27:16 -0700 (PDT) From: Komal Bajaj Date: Mon, 03 Aug 2026 16:56:34 +0530 Subject: [PATCH RESEND v7 05/10] arm64: dts: qcom: shikra: Add CDSP, LPAICP, MPSS remoteproc PAS nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260803-shikra-dt-m1-v7-5-7fec8e777076@oss.qualcomm.com> References: <20260803-shikra-dt-m1-v7-0-7fec8e777076@oss.qualcomm.com> In-Reply-To: <20260803-shikra-dt-m1-v7-0-7fec8e777076@oss.qualcomm.com> To: Vinod Koul , Frank Li , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Georgi Djakov , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Komal Bajaj , Bibek Kumar Patro , Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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Signed-off-by: Bibek Kumar Patro Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Komal Bajaj --- arch/arm64/boot/dts/qcom/shikra.dtsi | 164 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 164 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qco= m/shikra.dtsi index 42a17ffc040f..570505c927bb 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -1813,6 +1813,170 @@ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, }; }; =20 + remoteproc_mpss: remoteproc@6080000 { + compatible =3D "qcom,shikra-mpss-pas"; + reg =3D <0x0 0x06080000 0x0 0x100>; + + interrupts-extended =3D <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING 0>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks =3D <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "xo"; + + interconnects =3D <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + + power-domains =3D <&rpmpd RPMHPD_CX>; + + memory-region =3D <&mpss_wlan_mem>; + + qcom,smem-states =3D <&modem_smp2p_out 0>; + qcom,smem-state-names =3D "stop"; + + status =3D "disabled"; + + glink-edge { + interrupts =3D ; + mboxes =3D <&apcs_glb 12>; + qcom,remote-pid =3D <1>; + label =3D "mpss"; + }; + }; + + remoteproc_cdsp: remoteproc@b300000 { + compatible =3D "qcom,shikra-cdsp-pas"; + reg =3D <0x0 0x0b300000 0x0 0x100000>; + + interrupts-extended =3D <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING 0>, + <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks =3D <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "xo"; + + interconnects =3D <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + + power-domains =3D <&rpmpd RPMHPD_CX>; + + memory-region =3D <&cdsp_mem>; + + qcom,smem-states =3D <&cdsp_smp2p_out 0>; + qcom,smem-state-names =3D "stop"; + + status =3D "disabled"; + + glink-edge { + interrupts =3D ; + mboxes =3D <&apcs_glb 4>; + qcom,remote-pid =3D <5>; + label =3D "cdsp"; + + fastrpc { + compatible =3D "qcom,fastrpc"; + #address-cells =3D <1>; + #size-cells =3D <0>; + label =3D "cdsp"; + qcom,glink-channels =3D "fastrpcglink-apps-dsp"; + + compute-cb@1 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <1>; + iommus =3D <&apps_smmu 0x0201 0x0000>; + }; + + compute-cb@2 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <2>; + iommus =3D <&apps_smmu 0x0202 0x0000>; + }; + + compute-cb@3 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <3>; + iommus =3D <&apps_smmu 0x0203 0x0000>; + }; + + compute-cb@4 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <4>; + iommus =3D <&apps_smmu 0x0204 0x0000>; + }; + + compute-cb@5 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <5>; + iommus =3D <&apps_smmu 0x0205 0x0000>; + }; + + compute-cb@6 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <6>; + iommus =3D <&apps_smmu 0x0206 0x0000>; + }; + + compute-cb@9 { + compatible =3D "qcom,fastrpc-compute-cb"; + reg =3D <9>; + iommus =3D <&apps_smmu 0x0209 0x0000>; + }; + }; + }; + }; + + remoteproc_lpaicp: remoteproc@b800000 { + compatible =3D "qcom,shikra-lpaicp-pas"; + reg =3D <0x0 0x0b800000 0x0 0x200000>; + + interrupts-extended =3D <&intc GIC_SPI 257 IRQ_TYPE_EDGE_RISING 0>, + <&lmcu_smp2p_in 0 IRQ_TYPE_NONE>, + <&lmcu_smp2p_in 1 IRQ_TYPE_NONE>, + <&lmcu_smp2p_in 2 IRQ_TYPE_NONE>, + <&lmcu_smp2p_in 3 IRQ_TYPE_NONE>; + + interrupt-names =3D "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + clocks =3D <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "xo"; + + memory-region =3D <&lmcu_mem &lmcu_dtb_mem>; + + qcom,smem-states =3D <&lmcu_smp2p_out 0>; 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Signed-off-by: Bibek Kumar Patro Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Komal Bajaj --- arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 19 +++++++++++++++++++ arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 19 +++++++++++++++++++ arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 19 +++++++++++++++++++ 3 files changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/= dts/qcom/shikra-cqm-evk.dts index 0a52ab9b7a4c..b112b21b1d79 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts @@ -23,6 +23,25 @@ chosen { }; }; =20 +&remoteproc_cdsp { + firmware-name =3D "qcom/shikra/cdsp.mbn"; + + status =3D "okay"; +}; + +&remoteproc_lpaicp { + firmware-name =3D "qcom/shikra/lpaicp.mbn", + "qcom/shikra/lpaicp_dtb.mbn"; + + status =3D "okay"; +}; + +&remoteproc_mpss { + firmware-name =3D "qcom/shikra/cqm/qdsp6sw.mbn"; + + status =3D "okay"; +}; + &sdhc_1 { vmmc-supply =3D <&pm4125_l20>; vqmmc-supply =3D <&pm4125_l14>; diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/= dts/qcom/shikra-cqs-evk.dts index b3f19a64d7ae..e62ba5aef71f 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts @@ -23,6 +23,25 @@ chosen { }; }; =20 +&remoteproc_cdsp { + firmware-name =3D "qcom/shikra/cdsp.mbn"; + + status =3D "okay"; +}; + +&remoteproc_lpaicp { + firmware-name =3D "qcom/shikra/lpaicp.mbn", + "qcom/shikra/lpaicp_dtb.mbn"; + + status =3D "okay"; +}; + +&remoteproc_mpss { + firmware-name =3D "qcom/shikra/cqs/qdsp6sw.mbn"; + + status =3D "okay"; +}; + &sdhc_1 { vmmc-supply =3D <&pm4125_l20>; vqmmc-supply =3D <&pm4125_l14>; diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/= dts/qcom/shikra-iqs-evk.dts index 3003a47bd759..727809430fd1 100644 --- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts @@ -23,6 +23,25 @@ chosen { }; }; =20 +&remoteproc_cdsp { + firmware-name =3D "qcom/shikra/cdsp.mbn"; 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The TSENS max/reset threshold is configured to 120=C2=B0C in the hardware. Enable all TSENS instances, and define the thermal zones with a hot trip at 110=C2=B0C and critical trip at 115=C2=B0C. Signed-off-by: Gaurav Kohli Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Komal Bajaj --- arch/arm64/boot/dts/qcom/shikra.dtsi | 267 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 267 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qco= m/shikra.dtsi index 570505c927bb..fb0391bef460 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include =20 / { interrupt-parent =3D <&intc>; @@ -998,6 +999,18 @@ spmi_bus: spmi@1c40000 { qcom,ee =3D <0>; }; =20 + tsens0: thermal-sensor@4411000 { + compatible =3D "qcom,shikra-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x04411000 0x0 0x1000>, + <0x0 0x04410000 0x0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + #qcom,sensors =3D <14>; + #thermal-sensor-cells =3D <1>; + }; + rpm_msg_ram: sram@45f0000 { compatible =3D "qcom,rpm-msg-ram", "mmio-sram"; reg =3D <0x0 0x045f0000 0x0 0x7000>; @@ -2195,6 +2208,260 @@ cpufreq_hw: cpufreq@fd91000 { }; }; =20 + thermal_zones: thermal-zones { + aoss0-thermal { + thermal-sensors =3D <&tsens0 0>; + + trips { + trip-point0 { + temperature =3D <110000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + aoss0-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-0-0-thermal { + thermal-sensors =3D <&tsens0 1>; + + trips { + trip-point0 { + temperature =3D <110000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu00-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-0-1-thermal { + thermal-sensors =3D <&tsens0 2>; + + trips { + trip-point0 { + temperature =3D <110000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu01-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-1-0-thermal { + thermal-sensors =3D <&tsens0 3>; + + trips { + trip-point0 { + temperature =3D <110000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu10-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu-1-1-thermal { + thermal-sensors =3D <&tsens0 4>; + + trips { + trip-point0 { + temperature =3D <110000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpu11-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpuss0-thermal { + thermal-sensors =3D <&tsens0 5>; + + trips { + trip-point0 { + temperature =3D <110000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + cpuss0-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpuss-thermal { + thermal-sensors =3D <&tsens0 6>; + + trips { + trip-point0 { + temperature =3D <110000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + gpuss-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nsp-thermal { + thermal-sensors =3D <&tsens0 7>; + + trips { + trip-point0 { + temperature =3D <110000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + nsp-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + mdmss0-thermal { + thermal-sensors =3D <&tsens0 8>; + + trips { + trip-point0 { + temperature =3D <110000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + mdmss0-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + mdmss1-thermal { + thermal-sensors =3D <&tsens0 9>; + + trips { + trip-point0 { + temperature =3D <110000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + mdmss1-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + camera-thermal { + thermal-sensors =3D <&tsens0 10>; + + trips { + trip-point0 { + temperature =3D <110000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + + camera-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; 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The node is kept disabled by default and is intended to be enabled by board-specific device trees. Signed-off-by: Miaoqing Pan Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Komal Bajaj --- arch/arm64/boot/dts/qcom/shikra.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qco= m/shikra.dtsi index fb0391bef460..efb02e8719e9 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -2079,6 +2079,29 @@ apps_smmu: iommu@c600000 { ; }; =20 + wifi: wifi@c800000 { + compatible =3D "qcom,wcn3990-wifi"; + reg =3D <0x0 0x0c800000 0x0 0x800000>; + reg-names =3D "membase"; + memory-region =3D <&wlan_mem>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + ; + iommus =3D <&apps_smmu 0x1a0 0x1>; + qcom,msa-fixed-perm; + + status =3D "disabled"; + }; + intc: interrupt-controller@f200000 { compatible =3D "arm,gic-v3"; reg =3D <0x0 0xf200000 0x0 0x10000>, --=20 2.34.1 From nobody Fri Oct 2 08:28:42 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7617940DB20 for ; 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Enable both interfaces and provide the required supply and calibration data. Co-developed-by: Yepuri Siddu Signed-off-by: Yepuri Siddu Co-developed-by: Miaoqing Pan Signed-off-by: Miaoqing Pan Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Komal Bajaj --- arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi | 74 +++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi | 82 ++++++++++++++++++++++++= ++++ 2 files changed, 156 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi b/arch/arm64/boot= /dts/qcom/shikra-cqm-som.dtsi index dc3861489f64..2fff5fe9f6d2 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi @@ -11,6 +11,10 @@ #include "pm8005.dtsi" =20 / { + aliases { + serial1 =3D &uart8; + }; + gpio-keys { compatible =3D "gpio-keys"; label =3D "gpio-keys"; @@ -27,6 +31,42 @@ key-volume-up { linux,can-disable; }; }; + + wcn3988-pmu { + compatible =3D "qcom,wcn3988-pmu"; + + pinctrl-0 =3D <&sw_ctrl_default>; + pinctrl-names =3D "default"; + + swctrl-gpios =3D <&tlmm 88 GPIO_ACTIVE_HIGH>; + + vddio-supply =3D <&pm4125_l7>; + vddxo-supply =3D <&pm4125_l13>; + vddrf-supply =3D <&pm4125_l10>; + vddch0-supply =3D <&pm4125_l22>; + + regulators { + vreg_pmu_io: ldo0 { + regulator-name =3D "vreg_pmu_io"; + }; + + vreg_pmu_xo: ldo1 { + regulator-name =3D "vreg_pmu_xo"; + }; + + vreg_pmu_rf: ldo2 { + regulator-name =3D "vreg_pmu_rf"; + }; + + vreg_pmu_ch0: ldo3 { + regulator-name =3D "vreg_pmu_ch0"; + }; + + vreg_pmu_ch1: ldo4 { + regulator-name =3D "vreg_pmu_ch1"; + }; + }; + }; }; =20 &pm4125_gpios { @@ -154,3 +194,37 @@ pm4125_l22: l22 { }; }; }; + +&tlmm { + sw_ctrl_default: sw-ctrl-default-state { + pins =3D "gpio88"; + function =3D "gpio"; + bias-pull-down; + }; +}; + +&uart8 { + status =3D "okay"; + + bluetooth { + compatible =3D "qcom,wcn3988-bt"; + max-speed =3D <3200000>; + + vddio-supply =3D <&vreg_pmu_io>; + vddxo-supply =3D <&vreg_pmu_xo>; + vddrf-supply =3D <&vreg_pmu_rf>; + vddch0-supply =3D <&vreg_pmu_ch0>; + }; +}; + +&wifi { + vdd-0.8-cx-mx-supply =3D <&pm4125_l7>; + vdd-1.8-xo-supply =3D <&vreg_pmu_xo>; + vdd-1.3-rfa-supply =3D <&vreg_pmu_rf>; + vdd-3.3-ch0-supply =3D <&vreg_pmu_ch0>; + + qcom,calibration-variant =3D "Shikra_EVK"; + firmware-name =3D "shikra"; + + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi b/arch/arm64/boot= /dts/qcom/shikra-iqs-som.dtsi index 73945bf42112..657a14ca9606 100644 --- a/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi @@ -10,6 +10,10 @@ #include "pm8150.dtsi" =20 / { + aliases { + serial1 =3D &uart8; + }; + gpio-key { compatible =3D "gpio-keys"; label =3D "gpio-keys"; @@ -26,6 +30,50 @@ key-volume-up { linux,can-disable; }; }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "wcn_3p3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + }; + + wcn3988-pmu { + compatible =3D "qcom,wcn3988-pmu"; + + pinctrl-0 =3D <&sw_ctrl_default>; + pinctrl-names =3D "default"; + + swctrl-gpios =3D <&tlmm 88 GPIO_ACTIVE_HIGH>; + + vddio-supply =3D <&pm8150_s4>; + vddxo-supply =3D <&pm8150_l12>; + vddrf-supply =3D <&pm8150_l8>; + vddch0-supply =3D <&vreg_wcn_3p3>; + + regulators { + vreg_pmu_io: ldo0 { + regulator-name =3D "vreg_pmu_io"; + }; + + vreg_pmu_xo: ldo1 { + regulator-name =3D "vreg_pmu_xo"; + }; + + vreg_pmu_rf: ldo2 { + regulator-name =3D "vreg_pmu_rf"; + }; + + vreg_pmu_ch0: ldo3 { + regulator-name =3D "vreg_pmu_ch0"; + }; + + vreg_pmu_ch1: ldo4 { + regulator-name =3D "vreg_pmu_ch1"; + }; + }; + }; }; =20 &pm8150_gpios { @@ -168,3 +216,37 @@ pm8150_l18: l18 { }; }; }; + +&tlmm { + sw_ctrl_default: sw-ctrl-default-state { + pins =3D "gpio88"; + function =3D "gpio"; + bias-pull-down; + }; +}; + +&uart8 { + status =3D "okay"; + + bluetooth { + compatible =3D "qcom,wcn3988-bt"; + max-speed =3D <3200000>; + + vddio-supply =3D <&vreg_pmu_io>; + vddxo-supply =3D <&vreg_pmu_xo>; + vddrf-supply =3D <&vreg_pmu_rf>; + vddch0-supply =3D <&vreg_pmu_ch0>; + }; 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These reserved GPIOs are inaccessible from the non-secure world and dedicated to fixed functions. Co-developed-by: Anurag Pateriya Signed-off-by: Anurag Pateriya Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Komal Bajaj --- arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi | 6 ++++++ arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi b/arch/arm64/boot= /dts/qcom/shikra-cqm-som.dtsi index 2fff5fe9f6d2..8ac42ff625a0 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi @@ -196,6 +196,12 @@ pm4125_l22: l22 { }; =20 &tlmm { + gpio-reserved-ranges =3D <6 4>, /* Fingerprint SPI */ + <14 4>, /* eSE SPI */ + <30 2>, /* NFC SPI */ + <138 1>, /* NFC Secure IO */ + <155 11>; /* eMMC Boot */ + sw_ctrl_default: sw-ctrl-default-state { pins =3D "gpio88"; function =3D "gpio"; diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi b/arch/arm64/boot= /dts/qcom/shikra-iqs-som.dtsi index 657a14ca9606..4ff97945274d 100644 --- a/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi @@ -218,6 +218,12 @@ pm8150_l18: l18 { }; =20 &tlmm { + gpio-reserved-ranges =3D <6 4>, /* Fingerprint SPI */ + <14 4>, /* eSE SPI */ + <30 2>, /* NFC SPI */ + <138 1>, /* NFC Secure IO */ + <155 11>; /* eMMC Boot */ + sw_ctrl_default: sw-ctrl-default-state { pins =3D "gpio88"; function =3D "gpio"; --=20 2.34.1