From nobody Fri Oct 2 08:28:41 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD1CD346E5E for ; Mon, 3 Aug 2026 16:02:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785772931; cv=none; b=CcCcdNworCGS70CKMnOgXRNe7P3IShBEXcqOOZQEDL1UE0mLMm5YWRX+mQaMUGMp9tCkvAiFphFZ7cTuWXYGte3ROtjczWuC6cnjxU9sGelkTIk1Qcp/mcEv0F6CDl07jUN9K9nJI78BQQzg4IXHmnTE7oCc/K1x5JnsWbHbe48= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785772931; c=relaxed/simple; bh=rcrXOB/MDti0XujRnNl/f0gqeQyDm9VyutAE6mB3l7I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CkvD/PrzL5nMYJ4YEuvS3mkfYoWbMa2I23sh2qQcyg3M/milb3ftVwLYkDKExJ+hE+cEOvKZFyl5CYh7gU+UeuUjCjOCJZ8qhFQo9ZJD1YI/42vaY9Dvh1iHaSVM9dSNzFh1XU0I7UsEI9FfHgeYeUHe9z3+4r7l7OiVbICQXKg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=rp/Ru4eK; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="rp/Ru4eK" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 827EF4E410BA; Mon, 3 Aug 2026 16:02:07 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 5173C6029B; Mon, 3 Aug 2026 16:02:07 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id CE2B811C311B7; Mon, 3 Aug 2026 18:02:05 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1785772926; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=NZ/GiBhDFTiUo4Y3KYKCP9noKNO98CrnzSpzv4RAto8=; b=rp/Ru4eKDBPFrkS6e4H1lVaOQ9esQbDOqUm2PeouJgbKotY/Xh5Sd2R7V3KaVD42/aebTD w7RKEqUVFM1k5wJYmfB60Gf9NNev5aqZDEFiSqUKZDLqBZwb5LKKSdNX6/deYHKXLrwUvp B4UJSSM4WhblKg2qkMq6ea8GBUtr89+J16GtsdOZyKl+231sqB7Pvvg1JFt31PoaD1xBbB OI1nQgvSetUNSopxCq5nBmsVnjy5dW9lqoxmzoJPlQbdIY62hqpE5t6aDHdJYXCYQB6RXj Khofc8rDEI+q2YNzbOgd676gPd0ZeHY2UQzJnM7q1Kgj/Sr/IHI4NQimvFSmEg== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Mon, 03 Aug 2026 18:02:00 +0200 Subject: [PATCH v8 1/2] dmaengine: fsl-edma: Implement device_prep_peripheral_dma_vec Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260803-fsl-edma-dyn-sg-v8-1-dc2b0317206d@bootlin.com> References: <20260803-fsl-edma-dyn-sg-v8-0-dc2b0317206d@bootlin.com> In-Reply-To: <20260803-fsl-edma-dyn-sg-v8-0-dc2b0317206d@bootlin.com> To: Frank Li , Vinod Koul Cc: Thomas Petazzoni , Frank Li , imx@lists.linux.dev, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.15.2 X-Last-TLS-Session-Version: TLSv1.3 Add implementation of .device_prep_peripheral_dma_vec() callback to setup a scatter/gather DMA transfer from an array of dma_vec structures. Setup a cyclic transfer if the DMA_PREP_REPEAT flag is set. Reviewed-by: Frank Li Signed-off-by: Beno=C3=AEt Monin --- drivers/dma/fsl-edma-common.c | 116 ++++++++++++++++++++++++++++++++++++++= ++++ drivers/dma/fsl-edma-common.h | 4 ++ drivers/dma/fsl-edma-main.c | 2 + 3 files changed, 122 insertions(+) diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c index bb7531c456df..c5f5951c988b 100644 --- a/drivers/dma/fsl-edma-common.c +++ b/drivers/dma/fsl-edma-common.c @@ -673,6 +673,122 @@ struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyc= lic( return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); } =20 +struct dma_async_tx_descriptor * +fsl_edma_prep_peripheral_dma_vec(struct dma_chan *chan, const struct dma_v= ec *vecs, + size_t nb, enum dma_transfer_direction direction, + unsigned long flags) +{ + struct fsl_edma_chan *fsl_chan =3D to_fsl_edma_chan(chan); + dma_addr_t src_addr, dst_addr, last_sg; + struct fsl_edma_desc *fsl_desc; + u16 soff, doff, iter; + u32 nbytes; + int i; + + if (!is_slave_direction(direction)) + return NULL; + + if (!fsl_edma_prep_slave_dma(fsl_chan, direction)) + return NULL; + + fsl_desc =3D fsl_edma_alloc_desc(fsl_chan, nb); + if (!fsl_desc) + return NULL; + fsl_desc->iscyclic =3D flags & DMA_PREP_REPEAT; + fsl_desc->dirn =3D direction; + + if (direction =3D=3D DMA_MEM_TO_DEV) { + if (!fsl_chan->cfg.src_addr_width) + fsl_chan->cfg.src_addr_width =3D fsl_chan->cfg.dst_addr_width; + fsl_chan->attr =3D + fsl_edma_get_tcd_attr(fsl_chan->cfg.src_addr_width, + fsl_chan->cfg.dst_addr_width); + nbytes =3D fsl_chan->cfg.dst_addr_width * fsl_chan->cfg.dst_maxburst; + } else { + if (!fsl_chan->cfg.dst_addr_width) + fsl_chan->cfg.dst_addr_width =3D fsl_chan->cfg.src_addr_width; + fsl_chan->attr =3D + fsl_edma_get_tcd_attr(fsl_chan->cfg.src_addr_width, + fsl_chan->cfg.dst_addr_width); + nbytes =3D fsl_chan->cfg.src_addr_width * fsl_chan->cfg.src_maxburst; + } + + for (i =3D 0; i < nb; i++) { + if (direction =3D=3D DMA_MEM_TO_DEV) { + src_addr =3D vecs[i].addr; + dst_addr =3D fsl_chan->dma_dev_addr; + soff =3D fsl_chan->cfg.dst_addr_width; + doff =3D 0; + } else if (direction =3D=3D DMA_DEV_TO_MEM) { + src_addr =3D fsl_chan->dma_dev_addr; + dst_addr =3D vecs[i].addr; + soff =3D 0; + doff =3D fsl_chan->cfg.src_addr_width; + } else { + /* DMA_DEV_TO_DEV */ + src_addr =3D fsl_chan->cfg.src_addr; + dst_addr =3D fsl_chan->cfg.dst_addr; + soff =3D 0; + doff =3D 0; + } + + /* + * Choose the suitable burst length if dma_vec length is not + * multiple of burst length so that the whole transfer length is + * multiple of minor loop(burst length). + */ + if (nbytes && vecs[i].len % nbytes) { + u32 width =3D (direction =3D=3D DMA_DEV_TO_MEM) ? doff : soff; + u32 burst =3D (direction =3D=3D DMA_DEV_TO_MEM) ? + fsl_chan->cfg.src_maxburst : + fsl_chan->cfg.dst_maxburst; + int j; + + for (j =3D burst; j > 1; j--) { + if (!(vecs[i].len % (j * width))) { + nbytes =3D j * width; + break; + } + } + /* Set burst size as 1 if there's no suitable one */ + if (j =3D=3D 1) + nbytes =3D width; + } + + if (!nbytes || vecs[i].len / nbytes > FIELD_MAX(EDMA_TCD_ITER_MASK)) + goto err_free_desc; + + iter =3D vecs[i].len / nbytes; + if (i < nb - 1) { + last_sg =3D fsl_desc->tcd[(i + 1)].ptcd; + fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, src_addr, + dst_addr, fsl_chan->attr, soff, + nbytes, 0, iter, iter, doff, last_sg, + false, false, true); + } else { + if (fsl_desc->iscyclic) { + last_sg =3D fsl_desc->tcd[0].ptcd; + fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, src_addr, + dst_addr, fsl_chan->attr, soff, + nbytes, 0, iter, iter, doff, last_sg, + true, false, true); + } else { + last_sg =3D 0; + fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, src_addr, + dst_addr, fsl_chan->attr, soff, + nbytes, 0, iter, iter, doff, last_sg, + true, true, false); + } + } + } + + return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags); + +err_free_desc: + fsl_edma_free_desc(&fsl_desc->vdesc); + return NULL; +} + struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg( struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, enum dma_transfer_direction direction, diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h index 205a96489094..0d028048701d 100644 --- a/drivers/dma/fsl-edma-common.h +++ b/drivers/dma/fsl-edma-common.h @@ -496,6 +496,10 @@ struct dma_async_tx_descriptor *fsl_edma_prep_dma_cycl= ic( struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, size_t period_len, enum dma_transfer_direction direction, unsigned long flags); +struct dma_async_tx_descriptor *fsl_edma_prep_peripheral_dma_vec( + struct dma_chan *chan, const struct dma_vec *vecs, + size_t nb, enum dma_transfer_direction direction, + unsigned long flags); struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg( struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, enum dma_transfer_direction direction, diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c index 36155ab1602a..6693b4270a1a 100644 --- a/drivers/dma/fsl-edma-main.c +++ b/drivers/dma/fsl-edma-main.c @@ -841,6 +841,8 @@ static int fsl_edma_probe(struct platform_device *pdev) fsl_edma->dma_dev.device_free_chan_resources =3D fsl_edma_free_chan_resources; fsl_edma->dma_dev.device_tx_status =3D fsl_edma_tx_status; + fsl_edma->dma_dev.device_prep_peripheral_dma_vec + =3D fsl_edma_prep_peripheral_dma_vec; fsl_edma->dma_dev.device_prep_slave_sg =3D fsl_edma_prep_slave_sg; fsl_edma->dma_dev.device_prep_dma_cyclic =3D fsl_edma_prep_dma_cyclic; fsl_edma->dma_dev.device_prep_dma_memcpy =3D fsl_edma_prep_memcpy; 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Mon, 3 Aug 2026 18:02:06 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1785772927; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=Sx9Qw3UFpLKxQMZA52u1Kv4B8cIvHS9uQN3V4nHaRfA=; b=DUiBU2BMarpcgmIJZqn119ePNYCYX82g+iyttqx477h0wC+ZWJGuHj6qQEtK3Zd8br/A7Z dArMsON8xTFSX8N5x4RaWOdqiRQXg9INS6pGrWiFf/YwGmzHcgLjV+3gleNfNFH2cUG/no 2xvmJwkx8AX5TU7detEE+URaNUGjlGTbqSEiBSuWDP3n0E8tFtL2m6XYh0zUSm7lQY9+dc GT1HIPJSGibeEVjIfJqehAB+KvhIyMnhbUSeo+GQesQtQgi/noWHTXrzpR2U+n6lgAdPvW ko8CLjKa2MxKOc9WX5ex7cW3MXk1RnP72cUCg1a7hdyHeoaGCGaV4Su0DtpJlA== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Mon, 03 Aug 2026 18:02:01 +0200 Subject: [PATCH v8 2/2] dmaengine: fsl-edma: Support dynamic scatter/gather chaining Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260803-fsl-edma-dyn-sg-v8-2-dc2b0317206d@bootlin.com> References: <20260803-fsl-edma-dyn-sg-v8-0-dc2b0317206d@bootlin.com> In-Reply-To: <20260803-fsl-edma-dyn-sg-v8-0-dc2b0317206d@bootlin.com> To: Frank Li , Vinod Koul Cc: Thomas Petazzoni , Frank Li , imx@lists.linux.dev, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.15.2 X-Last-TLS-Session-Version: TLSv1.3 Implement dynamic linking of scatter/gather transfers to enable chaining multiple DMA descriptors without stopping the channel. This avoids waiting for the channel to go idle if there is another transaction already issued. Add fsl_edma_link_sg() to dynamically link the last TCD of a previously issued descriptor to the first TCD of a new descriptor by setting the scatter/gather address and the E_SG flag, and keeping the channel active by clearing the DREQ bit. Also in fsl_edma_link_sg(), we assign a non-zero identifier to the new descriptor that is stored in the EDMA_TCD_CSR_LINKCH field of the CSR of each TCD, after checking that the descriptors are not using channel linking. The use of this field (MAJORLINKCH in the datasheet) as an identifier for dynamic scatter/gather is suggested in the i.MX93 datasheet. When the last issued descriptor is the one currently active on the channel and has a single TCD, the scatter/gather address and CSR are also written directly to the hardware registers to ensure the link takes effect immediately, unless the DMA controller requires the DONE bit to be cleared for the CSR change to take effect. Clearing the DONE bit would disrupt the interrupt handler. Linking is done in fsl_edma_issue_pending(), which iterates over the submitted descriptors, links each one to the previously issued descriptor via fsl_edma_link_sg(), and then moves it to the issued list. This ensures that transactions are linked in the order they were issued. Linking of a descriptor is limited to 31 outstanding descriptors on the issued list so the identifier fits in the LINKCH field of the CSR register. The value of zero is left to identify non-linked descriptors. Update fsl_edma_xfer_desc() to avoid re-initializing the hardware when a transfer is already in progress, allowing seamless chaining of descriptors. Modify the transfer completion handler to check the DONE flag in the channel CSR before marking the transfer complete. Since this flag is only available on SoC with the split registers layout, we only link transactions for DMA controllers flagged with FSL_EDMA_DRV_SPLIT_REG. The completion handler also reaps issued descriptors whose link channel ID (EDMA_TCD_CSR_LINKCH) has already been passed by the hardware, marking them as completed even if their corresponding interrupt has been missed. Add trace event for scatter/gather linking operations. Signed-off-by: Beno=C3=AEt Monin --- drivers/dma/fsl-edma-common.c | 125 ++++++++++++++++++++++++++++++++++++++= +--- drivers/dma/fsl-edma-common.h | 3 + drivers/dma/fsl-edma-trace.h | 5 ++ 3 files changed, 126 insertions(+), 7 deletions(-) diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c index c5f5951c988b..189eb9d1269e 100644 --- a/drivers/dma/fsl-edma-common.c +++ b/drivers/dma/fsl-edma-common.c @@ -55,10 +55,37 @@ void fsl_edma_tx_chan_handler(struct fsl_edma_chan *fsl= _chan) } =20 if (!fsl_chan->edesc->iscyclic) { - list_del(&fsl_chan->edesc->vdesc.node); - vchan_cookie_complete(&fsl_chan->edesc->vdesc); + u16 csr =3D edma_read_tcdreg(fsl_chan, csr); + u8 link_sg_id =3D FIELD_GET(EDMA_TCD_CSR_LINKCH, csr); + bool e_link =3D FIELD_GET(EDMA_TCD_CSR_E_LINK, csr); + struct virt_dma_desc *vdesc, *tmp; + + /* Channel is DONE when a TCD with D_REQ set completes */ + if (!(fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_SPLIT_REG) || + (edma_readl_chreg(fsl_chan, ch_csr) & EDMA_V3_CH_CSR_DONE)) { + fsl_chan->status =3D DMA_COMPLETE; + } + + list_for_each_entry_safe(vdesc, tmp, &fsl_chan->vchan.desc_issued, node)= { + struct fsl_edma_desc *fsl_desc =3D to_fsl_edma_desc(vdesc); + bool id_match =3D (link_sg_id =3D=3D fsl_desc->link_sg_id); + + /* + * If the transfer is still running, + * don't mark as complete the current descriptor + */ + if ((e_link || id_match) && fsl_chan->status !=3D DMA_COMPLETE) + break; + + list_del(&vdesc->node); + vchan_cookie_complete(vdesc); + + if (e_link || id_match) + break; + } + fsl_chan->edesc =3D NULL; - fsl_chan->status =3D DMA_COMPLETE; + } else { vchan_cyclic_callback(&fsl_chan->edesc->vdesc); } @@ -931,14 +958,93 @@ void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_cha= n) if (!vdesc) return; fsl_chan->edesc =3D to_fsl_edma_desc(vdesc); - fsl_edma_set_tcd_regs(fsl_chan, fsl_chan->edesc->tcd[0].vtcd); - fsl_edma_enable_request(fsl_chan); - fsl_chan->status =3D DMA_IN_PROGRESS; + + if (fsl_chan->status !=3D DMA_IN_PROGRESS) { + fsl_edma_set_tcd_regs(fsl_chan, fsl_chan->edesc->tcd[0].vtcd); + fsl_edma_enable_request(fsl_chan); + fsl_chan->status =3D DMA_IN_PROGRESS; + } +} + +static void fsl_edma_link_sg(struct fsl_edma_chan *fsl_chan, struct fsl_ed= ma_desc *fsl_desc) +{ + u32 flags =3D fsl_edma_drvflags(fsl_chan); + struct fsl_edma_hw_tcd *last_tcd; + struct fsl_edma_desc *prev_desc; + struct virt_dma_desc *vdesc; + u16 last_csr; + + lockdep_assert_held(&fsl_chan->vchan.lock); + + if (!(flags & FSL_EDMA_DRV_SPLIT_REG) || fsl_desc->iscyclic) + return; + + vdesc =3D list_last_entry_or_null(&fsl_chan->vchan.desc_issued, + struct virt_dma_desc, node); + if (!vdesc) + return; + + prev_desc =3D to_fsl_edma_desc(vdesc); + if (prev_desc->iscyclic) + return; + + last_tcd =3D prev_desc->tcd[prev_desc->n_tcds - 1].vtcd; + last_csr =3D fsl_edma_get_tcd_to_cpu(fsl_chan, last_tcd, csr); + + for (unsigned int i =3D 0; i < fsl_desc->n_tcds; i++) { + struct fsl_edma_hw_tcd *tcd =3D fsl_desc->tcd[i].vtcd; + + if (fsl_edma_get_tcd_to_cpu(fsl_chan, tcd, csr) & EDMA_TCD_CSR_E_LINK) + return; + } + + if (!(last_csr & EDMA_TCD_CSR_D_REQ) || + last_csr & EDMA_TCD_CSR_E_LINK || + list_count_nodes(&fsl_chan->vchan.desc_issued) >=3D FIELD_MAX(EDMA_TC= D_CSR_LINKCH)) + return; + + /* Set a non-zero linked SG identifier to all TCD of the new descriptor */ + fsl_chan->link_sg_id++; + if (fsl_chan->link_sg_id > FIELD_MAX(EDMA_TCD_CSR_LINKCH)) + fsl_chan->link_sg_id =3D 1; + + fsl_desc->link_sg_id =3D fsl_chan->link_sg_id; + + for (unsigned int i =3D 0; i < fsl_desc->n_tcds; i++) { + struct fsl_edma_hw_tcd *tcd =3D fsl_desc->tcd[i].vtcd; + u16 csr =3D fsl_edma_get_tcd_to_cpu(fsl_chan, tcd, csr); + + csr |=3D FIELD_PREP(EDMA_TCD_CSR_LINKCH, fsl_chan->link_sg_id); + fsl_edma_set_tcd_to_le(fsl_chan, tcd, csr, csr); + } + + /* + * Set DLAST_SGA before enabling E_SG in CSR: if the DMA engine + * only picks up the former, it updates DADDR at end of transfer, + * which is not reused. + */ + fsl_edma_set_tcd_to_le(fsl_chan, last_tcd, fsl_desc->tcd[0].ptcd, dlast_s= ga); + + dma_wmb(); + + last_csr &=3D ~EDMA_TCD_CSR_D_REQ; + last_csr |=3D EDMA_TCD_CSR_E_SG; + fsl_edma_set_tcd_to_le(fsl_chan, last_tcd, last_csr, csr); + + if (prev_desc =3D=3D fsl_chan->edesc && + prev_desc->n_tcds =3D=3D 1 && + !(flags & FSL_EDMA_DRV_CLEAR_DONE_E_SG)) { + edma_cp_tcd_to_reg(fsl_chan, last_tcd, dlast_sga); + edma_cp_tcd_to_reg(fsl_chan, last_tcd, csr); + } + + trace_edma_link_sg(fsl_chan, last_tcd); } =20 void fsl_edma_issue_pending(struct dma_chan *chan) { struct fsl_edma_chan *fsl_chan =3D to_fsl_edma_chan(chan); + struct virt_dma_desc *vdesc, *tmp; unsigned long flags; =20 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); @@ -949,7 +1055,12 @@ void fsl_edma_issue_pending(struct dma_chan *chan) return; } =20 - if (vchan_issue_pending(&fsl_chan->vchan) && !fsl_chan->edesc) + list_for_each_entry_safe(vdesc, tmp, &fsl_chan->vchan.desc_submitted, nod= e) { + fsl_edma_link_sg(fsl_chan, to_fsl_edma_desc(vdesc)); + list_move_tail(&vdesc->node, &fsl_chan->vchan.desc_issued); + } + + if (!list_empty(&fsl_chan->vchan.desc_issued) && !fsl_chan->edesc) fsl_edma_xfer_desc(fsl_chan); =20 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h index 0d028048701d..ab7ec43f93cf 100644 --- a/drivers/dma/fsl-edma-common.h +++ b/drivers/dma/fsl-edma-common.h @@ -42,6 +42,7 @@ #define EDMA_TCD_CSR_E_LINK BIT(5) #define EDMA_TCD_CSR_ACTIVE BIT(6) #define EDMA_TCD_CSR_DONE BIT(7) +#define EDMA_TCD_CSR_LINKCH GENMASK(12, 8) =20 #define EDMA_V3_TCD_NBYTES_MLOFF_NBYTES(x) ((x) & GENMASK(9, 0)) #define EDMA_V3_TCD_NBYTES_MLOFF(x) (x << 10) @@ -169,6 +170,7 @@ struct fsl_edma_chan { struct dma_slave_config cfg; u32 attr; bool is_sw; + u8 link_sg_id; struct dma_pool *tcd_pool; dma_addr_t dma_dev_addr; u32 dma_dev_size; @@ -199,6 +201,7 @@ struct fsl_edma_desc { struct virt_dma_desc vdesc; struct fsl_edma_chan *echan; bool iscyclic; + u8 link_sg_id; enum dma_transfer_direction dirn; unsigned int n_tcds; struct fsl_edma_sw_tcd tcd[]; diff --git a/drivers/dma/fsl-edma-trace.h b/drivers/dma/fsl-edma-trace.h index d3541301a247..ac319d2dbb90 100644 --- a/drivers/dma/fsl-edma-trace.h +++ b/drivers/dma/fsl-edma-trace.h @@ -119,6 +119,11 @@ DEFINE_EVENT(edma_log_tcd, edma_fill_tcd, TP_ARGS(chan, tcd) ); =20 +DEFINE_EVENT(edma_log_tcd, edma_link_sg, + TP_PROTO(struct fsl_edma_chan *chan, void *tcd), + TP_ARGS(chan, tcd) +); + #endif =20 /* this part must be outside header guard */ --=20 2.55.0