From nobody Fri Oct 2 09:21:58 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED97237F745 for ; Mon, 3 Aug 2026 10:31:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785753123; cv=none; b=LsQni8BgYy/OJW5AZwxKNGH8XkQWKFgllW/flbExxdLy00rU9W0S5brldXfiTHKrG7/5NWqFTJsfWAuaA3k2pxsTRaPX+UerSlRpj2ISGyPw5zttL9naWdpns/oGw/jl1Ak9QyLVnOyBSdsqeZp6wDhf+fTusF1khAErbGNI2oo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785753123; c=relaxed/simple; bh=F+fPjKe8NP3i0MZrbOhQmL14uCve9gQEON/srSIsDbM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ApdC7FNMIkp+QdkjQoUwk3c+Ku0Zvtv3YFSlrxCDr8znWjg7oPrQDU3hstcxT/kgxV4XFVBvz+dGz7ToIbvFGoDBi0JVoqGg8kV8WvtkcCoUg8czr+fBmHGj8puUXiJH3Hz/eaC+SEKHPtnzsgQZlAjm9CmB9gIU7Nj8Rrl2cB0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=GpMGoBKI; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=Pb8qJOT0; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="GpMGoBKI"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="Pb8qJOT0" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 6736SGcf250822 for ; Mon, 3 Aug 2026 10:31:59 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= /Rdiyohjbhr0H44YMyHYEoS5uhqb4cajhLofrK++hek=; b=GpMGoBKINU1FxXvE L8mo+yFZ7nKqvo9B/3uwE8NB+TWGgDLkhJdz8KylflQ2ugrhOZ0jjE5F6z4KzlJx x9KABTCQRyaNBhEVt5TJJ2A+xxoMjG+ciV+XOvqWcdaRH2j0O8/mw2jEDagAaakH rKVOXIq0sLQctsL35OKl+3k+zRgxMr7fB37AERVTkBQPvBGChsB7EjLJqigHOkD8 FwrTrCmmCFYBzCjpJYp4oojzqTKdec4atJKOyqUHbiA3p00JPEXVpkYmlQbnLwdL xkO8aBYAztXj4EApmNDrG1TBbE2zO2r+6bZtfH4sAyjVYoNeEwdyr5Kyr0tyAK3O TbQ9Nw== Received: from mail-pj1-f71.google.com (mail-pj1-f71.google.com [209.85.216.71]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ftnrd91v8-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 03 Aug 2026 10:31:58 +0000 (GMT) Received: by mail-pj1-f71.google.com with SMTP id 98e67ed59e1d1-38ce7fabf76so1235541a91.2 for ; Mon, 03 Aug 2026 03:31:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1785753118; x=1786357918; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=/Rdiyohjbhr0H44YMyHYEoS5uhqb4cajhLofrK++hek=; b=Pb8qJOT03S/gqoKeJxYzZSkrMFNnRAf9dhcEiBtMazvEw9i0taX5Zq1e3kMcg2Sj4X LY521iqT5t+QPaLuW60uzgvTA9mjgWJfzKzCe5Tb9d0WOmPGmoIE9n5SHmxh4R+7s0Gr 7IWj05Lqm7lYd1gY+I8roUAiaYkBTXvHmjOJwOzJ7v24PMbeSaIy5jcbV3T0KEr3ez0a LMFe2pLVHawFUy/dGvsfcdBwzfNKBnOzFlbxFxOYrxwDLXVH8NfrT/hdGhJqZy/Z58CM 9S+wsHkcs1UPSKDFlcf9gxas995C9a1EZ4cSyZKB3P6R2F0dpCAyK+tdvZ/kgPkFhnLY FGNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1785753118; x=1786357918; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=/Rdiyohjbhr0H44YMyHYEoS5uhqb4cajhLofrK++hek=; b=YfXYXbzqjO2simMSDk+JmGPu85E1WerkQHIIHoYCp/fBq/uYw27iaVIH5glCl3upLE G4udcnsb/VH4dRYw4kBTDUaQXTCmVArCg2X6jj9K4rqhrRtU745xczgI0nArtRja27W9 3QQP9u3VJWQSJLldVKEc3mzNDs3TUnTYZOG58dXO9nHXS7VlXaSQt4v442LLwZM0z/Bk 3KpnhzBkhQSQZKmiQ241/WJDAOAg1jBQieaGzmtiV/E1giLoW9QoB00u+t7ItjWRB900 RL0d/Wbo6UIZHo81REEYBaH06k/fqdZI2bm9mpF6Y6YgzCbkFIURUHtI4vge1tp6xiIs w8LA== X-Forwarded-Encrypted: i=1; AHgh+RrG+qhjDixTv7h/X4gtj+GkOzj/t0Bfo9c8Wv/oOWZuvgYllRywwBXIbp93m6DuQ6tKif/JFEJ53J//aM4=@vger.kernel.org X-Gm-Message-State: AOJu0YwjiXLIc5AW+yREEzhyifUPpX+JMZRafDi2khZC3xvbWwEj0qrL 0dbM2jaTibH9mVu33ufjVco7y5Z/Mfvx7TsJUCkJRjIPKSCS16Gx5/ItCYs+i+r4g9gjcoeZLXN Fw99xhU8Tgt8blIRJt+qJMhmFkUtlwS7460wuOG8+4CSJvAzI6DCvrrUqby3j3j0oGX6oZ6JSv0 A= X-Gm-Gg: AR+sD12IMg1W5ZEhMRUEsFabviOT1qSzf/P5r8ixqzEZwt7XNFXl05sgxmV1wke07ZA nF65YQGPxcxio64O3nzHC44G9/eNeeHFeEuxCgLpippDBhTDpQEm/IpFRxFYnIH3qaMnTNl0KgN gaUpXCI2tGdO8qDlnPOVmkXoBg7b/waHaw2FRNf4rpGyqtplF2iFQMBrxYYwHo5e/pVJDOQRE2b D4RrSxMqR/tgOZGvXF7Ovb3XxaQ7LygxqGVBOPEmXLTq554pT1Le9H/g73LAuyZz/+k2SpeJ1ze eLI+FsvCxc8/dqVP3CkJE/6DRgDjXU5yjm6WEjv0InPLl/yG4N28Wch0U2ZbVKEqxFfuFh3Nx6G CyYWdSQyieyqv+DDgtie6GjIzCg== X-Received: by 2002:a17:90b:2e06:b0:38e:ab33:9551 with SMTP id 98e67ed59e1d1-38fbc60a11emr8206079a91.42.1785753117910; Mon, 03 Aug 2026 03:31:57 -0700 (PDT) X-Received: by 2002:a17:90b:2e06:b0:38e:ab33:9551 with SMTP id 98e67ed59e1d1-38fbc60a11emr8206046a91.42.1785753117416; Mon, 03 Aug 2026 03:31:57 -0700 (PDT) Received: from hu-sumk-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38fb2b1244bsm3693427a91.0.2026.08.03.03.31.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 03:31:56 -0700 (PDT) From: Sumit Kumar Date: Mon, 03 Aug 2026 16:01:43 +0530 Subject: [PATCH v2 1/5] dmaengine: Add DMA_SG support for multi-buffer scatter-gather transfers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260803-dma_multi_sg-v2-1-c12bb05e42d6@oss.qualcomm.com> References: <20260803-dma_multi_sg-v2-0-c12bb05e42d6@oss.qualcomm.com> In-Reply-To: <20260803-dma_multi_sg-v2-0-c12bb05e42d6@oss.qualcomm.com> To: Vinod Koul , Frank Li , Jonathan Corbet , Shuah Khan , Manivannan Sadhasivam , Jeff Hugo , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Kishon Vijay Abraham I , Bjorn Helgaas Cc: dmaengine@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, mhi@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, Sumit Kumar X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1785753106; l=7025; i=sumit.kumar@oss.qualcomm.com; s=20250409; h=from:subject:message-id; bh=F+fPjKe8NP3i0MZrbOhQmL14uCve9gQEON/srSIsDbM=; b=BHFl2Lx7cmYBNT3LrRyXX+cViMAk98sV6yIvxrf3cYqAZMo6eXZU6N8lrQyU/DB/LId6lHcMI O26it2Vb/6iAaYzqSf4sAwug5Cw3nZ2nsfv7C6HGhpzJL0/rgAQYwvg X-Developer-Key: i=sumit.kumar@oss.qualcomm.com; a=ed25519; pk=3cys6srXqLACgA68n7n7KjDeM9JiMK1w6VxzMxr0dnM= X-Proofpoint-Spam-Info: AW1haW4tMjYwODAzMDA5NCBTYWx0ZWRfXwHYhHYrMwWDy 5Yce+j2Al4WSATvLk0EfYN2qURKCiTAKmvPl+1M6coMH5DaxSK/yMk+RzcN2lr6BcgQOgu+gny2 RqNEo8LtLmzMlRL/LxaXsOhSqbvWKAU= X-Authority-Analysis: v=2.4 cv=f/94wuyM c=1 sm=1 tr=0 ts=6a706e1e cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=0CPfFOknu0lYeC7QLpQA:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-GUID: ZzhIiAzAOysgfsUBHPVXsCnkl70DoWev X-Proofpoint-ORIG-GUID: ZzhIiAzAOysgfsUBHPVXsCnkl70DoWev X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODAzMDA5NCBTYWx0ZWRfXzO2gUKnSNeFR azs2CFf8LJiATgJhdDFNulNeAklShuE/iYaLjbxKOoLkt33yFbgV2tjE0WYtzmdARz/SNeZ3iTu H2PstMZUC6EzlNCeQkrKUVzv30NaWRwB3JfdtNcCfAmVC47yxvH94SyK/LhfEgG33E5ASVdIhJH QaBiT3WEKAjllCulnjNFC+z0Kal1qOjZ0sk5avd4PHl3/PjtwgGJxYy964RQAPjyGj3Cb2mHudx UZSb3zk5N2p+7YluzNpJQqN0JMBVyt3AZqFw1WliV2j+5rCyArkiag/8NCNnk6y+tEvJlVpVj1h h8XZNLBbEoZN6UGbtY8TegaB51yvKY1qIf8XQ0GU7CoephhTsjhnPigIMIr7Cb67l044uRmhHRR lqxcnv5f3iQjZdexh7dVX8dh2YnwPTsDXxTieeqKnEMqu4d6e3gqpmfFZhdysXeu74PtS4XytJ0 e46ua5w00lh4PpwlxLQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-02_06,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 malwarescore=0 spamscore=0 bulkscore=0 impostorscore=0 suspectscore=0 clxscore=1015 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608030094 A client that needs to copy several independent, non-contiguous memory regions in one operation currently has to submit one DMA_MEMCPY transaction per region, each with its own completion interrupt, even when every region is known up front and the copies could be described as a single hardware transaction. Partially reintroduce the DMA_SG transaction type and device_prep_dma_sg() API that was removed in commit c678fa66341c ("dmaengine: remove DMA_SG as it is dead code in kernel"). Only the core API is restored here. The API accepts separate source and destination scatter-gather lists, where entry i of the source list is transferred to entry i of the destination list. This allows multiple independent (src[i] -> dst[i]) transfers to be batched into a single DMA transaction instead of N separate submissions, reducing submission and interrupt overhead. DMA_SG is a memcpy-class operation: both endpoints are memory buffers, and neither DMA address is a FIFO-style peripheral register. The source and destination scatter-gather lists must contain the same number of entries; providers reject requests where the entry counts differ. Restore the DMA_SG entry in Documentation/driver-api/dmaengine/provider.rst and add CHECK_CAP(dma_sg, DMA_SG) to dma_async_device_register() to validate that drivers setting the capability provide the corresponding function pointer. Signed-off-by: Sumit Kumar --- Documentation/driver-api/dmaengine/provider.rst | 21 +++++++++++++++ drivers/dma/dmaengine.c | 1 + include/linux/dmaengine.h | 35 +++++++++++++++++++++= ++++ 3 files changed, 57 insertions(+) diff --git a/Documentation/driver-api/dmaengine/provider.rst b/Documentatio= n/driver-api/dmaengine/provider.rst index f4ed98f701c918ff81bc674845880f8d01efbf1d..638e4b83e9a2f90c056111dbdd7= 572a4ed0f536d 100644 --- a/Documentation/driver-api/dmaengine/provider.rst +++ b/Documentation/driver-api/dmaengine/provider.rst @@ -210,6 +210,27 @@ Currently, the types available are: - Used by the client drivers to register a callback that will be called on a regular basis through the DMA controller interrupt =20 +- DMA_SG + + - The device supports memory to memory scatter-gather transfers + using paired source and destination scatter-gather lists, where + entry ``i`` of the source list is transferred to entry ``i`` of + the destination list in a single DMA transaction. + + - The source and destination scatter-gather lists must contain the + same number of entries; providers reject (return NULL for) requests + where the entry counts differ. Providers that walk the two lists in + lockstep pair them entry-by-entry as passed in, so clients that + DMA-map the lists must ensure the mapped segmentation stays aligned + between the two lists (for example by not relying on the DMA layer + to merge entries of one list but not the other). + + - Unlike DMA_MEMCPY, neither the source nor destination is a + FIFO-style peripheral register; both are memory buffers. Multiple + independent (src[i] -> dst[i]) copies are submitted as a single + DMA transaction, reducing submission and interrupt overhead + compared to N separate DMA_MEMCPY operations. + - DMA_PRIVATE =20 - The devices only supports slave transfers, and as such isn't diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c index 6ffd8bd82154af2af2807d1c8b7ae7475eab56d3..9e790b9f165063d696438ace637= 0df98dffb8a32 100644 --- a/drivers/dma/dmaengine.c +++ b/drivers/dma/dmaengine.c @@ -1211,6 +1211,7 @@ int dma_async_device_register(struct dma_device *devi= ce) CHECK_CAP(dma_pq_val, DMA_PQ_VAL); CHECK_CAP(dma_memset, DMA_MEMSET); CHECK_CAP(dma_interrupt, DMA_INTERRUPT); + CHECK_CAP(dma_sg, DMA_SG); CHECK_CAP(dma_cyclic, DMA_CYCLIC); CHECK_CAP(interleaved_dma, DMA_INTERLEAVE); =20 diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index fe33a20abc6146d539670e0e6fe6c9d27d96aa2a..61aa72149f5d5cf1828b89d13d0= b35f1a12bb000 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -65,6 +65,7 @@ enum dma_transaction_type { DMA_COMPLETION_NO_ORDER, DMA_REPEAT, DMA_LOAD_EOT, + DMA_SG, /* last transaction type for creation of the capabilities mask */ DMA_TX_TYPE_END, }; @@ -848,6 +849,7 @@ struct dma_filter { * The function takes a buffer of size buf_len. The callback function will * be called after period_len bytes have been transferred. * @device_prep_interleaved_dma: Transfer expression in a generic way. + * @device_prep_dma_sg: prepares a memory to memory scatter-gather operati= on * @device_caps: May be used to override the generic DMA slave capabilities * with per-channel specific ones * @device_config: Pushes a new configuration to a channel, return 0 or an= error @@ -954,6 +956,11 @@ struct dma_device { struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)( struct dma_chan *chan, struct dma_interleaved_template *xt, unsigned long flags); + struct dma_async_tx_descriptor *(*device_prep_dma_sg) + (struct dma_chan *chan, + struct scatterlist *dst_sg, unsigned int dst_nents, + struct scatterlist *src_sg, unsigned int src_nents, + unsigned long flags); =20 void (*device_caps)(struct dma_chan *chan, struct dma_slave_caps *caps); int (*device_config)(struct dma_chan *chan, struct dma_slave_config *conf= ig); @@ -1194,6 +1201,34 @@ static inline struct dma_async_tx_descriptor *dmaeng= ine_prep_interleaved_dma( return chan->device->device_prep_interleaved_dma(chan, xt, flags); } =20 +/** + * dmaengine_prep_dma_sg() - Prepare a memory-to-memory scatter-gather DMA= descriptor. + * @chan: The channel to be used for this descriptor + * @dst_sg: Destination scatter list + * @dst_nents: Number of entries in destination scatter list + * @src_sg: Source scatter list + * @src_nents: Number of entries in source scatter list + * @flags: DMA engine flags + * + * Prepares a DMA transaction that copies data from multiple source memory + * regions to multiple destination memory regions in a single DMA transact= ion. + * Entry i of the source list is paired with entry i of the destination li= st, + * so both lists must contain the same number of entries; the call returns + * NULL otherwise. + */ +static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_sg + (struct dma_chan *chan, + struct scatterlist *dst_sg, unsigned int dst_nents, + struct scatterlist *src_sg, unsigned int src_nents, + unsigned long flags) +{ + if (!chan || !chan->device || !chan->device->device_prep_dma_sg) + return NULL; + + return chan->device->device_prep_dma_sg(chan, dst_sg, dst_nents, + src_sg, src_nents, flags); +} + /** * dmaengine_prep_dma_memset() - Prepare a DMA memset descriptor. * @chan: The channel to be used for this descriptor --=20 2.34.1 From nobody Fri Oct 2 09:21:58 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D420381AE3 for ; Mon, 3 Aug 2026 10:32:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785753126; cv=none; b=UT0I80B/5M97Z+mHoyv+3kFxNRnsbwfMTDn98ibHYjbsBrb4UY3gc6G4itYeU3eI5TNFaaXfEDugr1snyh/IMU5jg4+hTBZybQ57PPOl+Zvr5MxjeZK3hqqf3szaGVjABcrzrInc+tNZLRJ7K8IMdLIYwr1dbxIKOiM0c35mC8U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785753126; c=relaxed/simple; bh=Dt7uawwamGL5dzZbfwrTJusLP6o30EN5ycCd9lSUTTA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pufjep3s2YiAxuAuq83jYeSLS8v5EpMEKXfP00SzdVeYvvPf+SAjPAzFp507nE/0MOCi+3HMOLT8Noem0NkbhWBiXUgGkcy6zjPpmZNaq7WNaEkdlh8P/N/tanTqt78C8nHBbRiDYmIfJyhNdtN8pjmqBbd5/PmW/4VSy8e/gns= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=hAoOjh3E; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=P+8bTebB; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="hAoOjh3E"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="P+8bTebB" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 6736kpoo4123743 for ; Mon, 3 Aug 2026 10:32:04 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= cnKaf8soKtsfI46+7/IcDh6tbT8xlfKfVzMrrCqhrT0=; b=hAoOjh3E7f/wHN+1 M3aDHDlm2LGxlWFl8ZVuZzRSO8g7y0yP3x/gV9ZNnfE0P5JVomin8GLiIpcum0e3 gUEVmOevnW7h7pO9XZ5P64oJdtwkCul7d4KtYAmzjMZ/Hsmcxt+QusMaMLXcBfBT /4hctq5jt+ULxRspBZrkDZsfxdSfxrAj4ey/BC+MdrsRebdoyh8jRybFXbtnYoQo 3N3FuTolnWmE0TXebW2hKAmhM/QilCiV7HoQ6WJaNsCTbEpbjhxw/rgxIZSqHN5E x3S5qyGU/B2LRaj4YYcN0q/YNh7aj9xWLnKkzebRVzDTyW2B6AjV2ybswnOc0m3L uHCkRw== Received: from mail-pj1-f71.google.com (mail-pj1-f71.google.com [209.85.216.71]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ftp168y9v-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 03 Aug 2026 10:32:03 +0000 (GMT) Received: by mail-pj1-f71.google.com with SMTP id 98e67ed59e1d1-38e1118e4abso6017780a91.0 for ; Mon, 03 Aug 2026 03:32:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1785753123; x=1786357923; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=cnKaf8soKtsfI46+7/IcDh6tbT8xlfKfVzMrrCqhrT0=; b=P+8bTebBNK3ABnTI/DmMmVPJnAWOjJPddtUYFdM52mu2Q7ADGf+I6oJk//DCtX4iCQ AGtrsnqbbgBAJvdtw1/9cM9vJ1TC0QuccWJYfk/cRlM3Pv7vdbc/Y1cI3XHR3DXTD+zr ohxHhSf//c2L+dzQhnuYNUZnqagezeXyrL5wEgv1uMWfyycaoAxDsV3UdIqA8OopDd+N T7t7pUQ/E1b4UJjl573WoWKnqbyRVPifb1s9/ZlubzrvE3aI2oci7/aCGnN/cTNGyhxv s/bId4fxc+QmSx7gt5tit8XB5ubRhLntzVHQ37Kqy/MAtO8wkHce0PjlMs4eW+LZni3h QfCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1785753123; x=1786357923; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=cnKaf8soKtsfI46+7/IcDh6tbT8xlfKfVzMrrCqhrT0=; b=Sbk4SIaLaukjuKsAI/YD3r9RizYXY9eEitqNCdibaDZpW1hTVL8x8iHC0wzmCwMVu+ X1L9Up1SD3jgyUOpcF7ztgPnWAeRrDN+fNG2/R/UtHQiP9aXc3TKNSLHKzt+E+ub1N/u RrL3dTvzjIj2IMNkSJRibU562kIk11QxCK2Mp2zvU7n8jKBb6n9wIumKndhRbiZyczIQ lWNwPA7ig7hUJ2P4957lLotECMLkw+/t+NEiyg1mkwSmOqZ4Xl1+pYkt3plXsAjPEriP rt/hHIaWajUvmUpgvlZDZegHyWkG1DU3CLqtIQj10mXzsKAcSMfLw0BgsBHwj1Vr1dlB 3g1A== X-Forwarded-Encrypted: i=1; AHgh+RrYS6pJDfNr7hRPS1/gLmFRsuzHrPMmjxqkqJz5VOL5qVrUtggxX9jpsLNcOR9jEK6t9FP9ldv9PNn88Bw=@vger.kernel.org X-Gm-Message-State: AOJu0YyWJIlGBw5+WF3c+bfCZpJA/bigNT51j33g1jTG7kwT0sWvPigm +1uSrXYL+sEDkO1Ph2zWu7CXsoxaSh4WeU8pD4RLSWnnvxtn3f0R5976/VHd9p8//ivVMG+cIvs qTOgqh4qS0PczTtDzuF5uMhlwyu/iDRV5jWHnz4qrizDzyfqQwJDi8B3XL/FxP0sSXGk= X-Gm-Gg: AR+sD10mXgdze8nUbykZkOsaiFpsWdUVO/3sjgOlBB8AWmzANuNtXSw5IXeq5vi1Ez6 JE9wmnoegUTOUfpWQ7HqEkfeyFgYqSZ3mUOT08mxa7roXKQY2g2+3FenC6yPek4H/2x5VZJShMc JW7xo0GW3/CNKaST6n/IzekhL4oZQ7yXHUQdeosppLRHxcX/ekPWe3E0Pj4Un+Cjr3pztb8pnS3 wIW3Oo1sPv9VAwm4nuDXsEnFjtXaUKRGgAWKApL0yk34eVCzSEg+t+HsK+SZ2RByLwtK254doX6 l8CS8ddAo9zD7joBGzSO7RfTb4BSvU1aDGzXR2/t587njUOugigukTiL6/8gZWzoFJsWFShOAUE IuyV8ipTFFEjyRT86zAXmsmO2BA== X-Received: by 2002:a17:90b:280a:b0:381:a766:efcc with SMTP id 98e67ed59e1d1-38fbc45436bmr8414442a91.14.1785753123132; Mon, 03 Aug 2026 03:32:03 -0700 (PDT) X-Received: by 2002:a17:90b:280a:b0:381:a766:efcc with SMTP id 98e67ed59e1d1-38fbc45436bmr8414407a91.14.1785753122550; Mon, 03 Aug 2026 03:32:02 -0700 (PDT) Received: from hu-sumk-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38fb2b1244bsm3693427a91.0.2026.08.03.03.31.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 03:32:02 -0700 (PDT) From: Sumit Kumar Date: Mon, 03 Aug 2026 16:01:44 +0530 Subject: [PATCH v2 2/5] dmaengine: dw-edma: Add DMA_SG support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260803-dma_multi_sg-v2-2-c12bb05e42d6@oss.qualcomm.com> References: <20260803-dma_multi_sg-v2-0-c12bb05e42d6@oss.qualcomm.com> In-Reply-To: <20260803-dma_multi_sg-v2-0-c12bb05e42d6@oss.qualcomm.com> To: Vinod Koul , Frank Li , Jonathan Corbet , Shuah Khan , Manivannan Sadhasivam , Jeff Hugo , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Kishon Vijay Abraham I , Bjorn Helgaas Cc: dmaengine@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, mhi@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, Sumit Kumar X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1785753106; l=9314; i=sumit.kumar@oss.qualcomm.com; s=20250409; h=from:subject:message-id; bh=Dt7uawwamGL5dzZbfwrTJusLP6o30EN5ycCd9lSUTTA=; b=Nn4l0bMMov/mSFqw3meaBaoqHEtMDdiPvrx/ENQmNWAidJ1BQ1j6oH20wYCJqtwxhbUJVyoNV IyqdC0G627/CGiVmC4k+FZvC/APWNV1tor2WcbrXmTKStUezyzJwKLn X-Developer-Key: i=sumit.kumar@oss.qualcomm.com; a=ed25519; pk=3cys6srXqLACgA68n7n7KjDeM9JiMK1w6VxzMxr0dnM= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODAzMDA5NCBTYWx0ZWRfX4pZJ2K3a/ag+ KXz4+wvWyELpBRfrI1qPy1SvNZDh+fjB1po2yL0Py+8bhBUUhe3i90S+7jmDVVGdl01O2nNmHXe MAHMK/p4ppiCK1KaUR0qJFheJ7TdaNmF8WwXChV1rZtPaeebS1Yg6Z6KbNrrhzCrmowrtn676V5 8JvWj2F596qtMmiv4wtV1TVuotP0Vr/Aj1Jo8t7WAO9gjQXTPFePmbvN1ROGqO9WmR3h96tfHzT ZHn6mhtGiQFswZPkFpMQVlX6AroplUdRTw8sW19fzPLh1SerN0bybZjq79NGIMS1NNIXMoOscEo gmTqeZoEw7zh8yl5HSpK2cmz0/yX57fwsFexEJR2bncSGubRdHECaua3wDVUtBRFTThiU5mwtmN ifMKDvsL7xlJ+9SWgjX0ie9NVuzCWHczBcQ//zMlS3mD38fHXaNtB+rK34Zukc4+ncvGcHScfrY e6Jrl4mogX551h9Ly4A== X-Authority-Analysis: v=2.4 cv=Wpob99fv c=1 sm=1 tr=0 ts=6a706e23 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=3YK5jeb26AILRK50rYoA:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwODAzMDA5NCBTYWx0ZWRfX30eYPTZBLeTz cVu8n+JMW/IQMp44N6AbXa4rhD/wgZPUIhDFzB4usRTZjiTheIMWl5Jc9wrO7kSpVbKBS1anDzX 6KagE+w46M5r4gFaQJ3jPX1XgGFhBoU= X-Proofpoint-ORIG-GUID: dO7oud03w_z0r7mK3XaXn88VQ5tUsyOx X-Proofpoint-GUID: dO7oud03w_z0r7mK3XaXn88VQ5tUsyOx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-02_06,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 malwarescore=0 suspectscore=0 priorityscore=1501 impostorscore=0 spamscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608030094 Synopsys DesignWare eDMA supports a linked-list mode where each list item carries independent source and destination addresses, letting multiple independent memory transfers be described in one linked list and submitted to the hardware as a single DMA transaction. The IP processes list items strictly in order, so paired scatter-gather entries are never reordered. Implement the DMA_SG capability by adding a new EDMA_XFER_DUAL_SG transfer type and a corresponding struct dw_edma_dual_sg carrying the paired source and destination SG lists. dw_edma_device_transfer() walks both lists in lockstep, building a single hardware linked-list; a per-entry length mismatch or premature list end fails the whole request. The transfer direction is inferred from the channel hardware polarity (EDMA_DIR_READ/WRITE), not from dma_slave_config.direction: for local eDMA (DW_EDMA_CHIP_LOCAL) read channels handle DEV_TO_MEM and write channels handle MEM_TO_DEV; for remote eDMA the mapping is inverted. PCIe bus addresses are translated via dw_edma_get_pci_address() for the remote side of each transfer. dmaengine_slave_config() must still be called before dmaengine_prep_dma_sg() because dw_edma_device_transfer() gates transfers on chan->configured, even though the direction field itself is unused by the DMA_SG path. Signed-off-by: Sumit Kumar --- drivers/dma/dw-edma/dw-edma-core.c | 87 ++++++++++++++++++++++++++++++++++= +--- drivers/dma/dw-edma/dw-edma-core.h | 10 ++++- 2 files changed, 90 insertions(+), 7 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-ed= ma-core.c index 1f893dc54c7938a9c45bafd975a4f99fdc0acb38..9fbfa5ad65b5421b164d2ab9883= 233225e0269e4 100644 --- a/drivers/dma/dw-edma/dw-edma-core.c +++ b/drivers/dma/dw-edma/dw-edma-core.c @@ -372,6 +372,7 @@ dw_edma_device_transfer(struct dw_edma_transfer *xfer, struct dw_edma_chan *chan =3D dchan2dw_edma_chan(xfer->dchan); enum dma_transfer_direction dir =3D xfer->direction; struct scatterlist *sg =3D NULL; + struct scatterlist *dst_sg =3D NULL; struct dw_edma_burst *burst; struct dw_edma_desc *desc; u64 src_addr, dst_addr; @@ -429,6 +430,9 @@ dw_edma_device_transfer(struct dw_edma_transfer *xfer, return NULL; if (!xfer->xfer.il->src_inc || !xfer->xfer.il->dst_inc) return NULL; + } else if (xfer->type =3D=3D EDMA_XFER_DUAL_SG) { + if (xfer->xfer.dual_sg.len < 1) + return NULL; } else { return NULL; } @@ -441,16 +445,27 @@ dw_edma_device_transfer(struct dw_edma_transfer *xfer, dst_addr =3D config->dst_addr; } =20 - if (dir =3D=3D DMA_DEV_TO_MEM) - src_addr =3D dw_edma_get_pci_address(chan, (phys_addr_t)src_addr); - else - dst_addr =3D dw_edma_get_pci_address(chan, (phys_addr_t)dst_addr); + /* + * DUAL_SG translates each src/dst sg entry individually below + * (see the burst->sar/burst->dar assignment), so it is exempt + * from the single up-front translation used by other types. + */ + if (xfer->type !=3D EDMA_XFER_DUAL_SG) { + if (dir =3D=3D DMA_DEV_TO_MEM) + src_addr =3D dw_edma_get_pci_address(chan, (phys_addr_t)src_addr); + else + dst_addr =3D dw_edma_get_pci_address(chan, (phys_addr_t)dst_addr); + } =20 if (xfer->type =3D=3D EDMA_XFER_CYCLIC) { cnt =3D xfer->xfer.cyclic.cnt; } else if (xfer->type =3D=3D EDMA_XFER_SCATTER_GATHER) { cnt =3D xfer->xfer.sg.len; sg =3D xfer->xfer.sg.sgl; + } else if (xfer->type =3D=3D EDMA_XFER_DUAL_SG) { + cnt =3D xfer->xfer.dual_sg.len; + sg =3D xfer->xfer.dual_sg.src_sgl; + dst_sg =3D xfer->xfer.dual_sg.dst_sgl; } else if (xfer->type =3D=3D EDMA_XFER_INTERLEAVED) { cnt =3D xfer->xfer.il->numf * xfer->xfer.il->frame_size; fsz =3D xfer->xfer.il->frame_size; @@ -463,12 +478,23 @@ dw_edma_device_transfer(struct dw_edma_transfer *xfer, for (i =3D 0; i < cnt; i++) { if (xfer->type =3D=3D EDMA_XFER_SCATTER_GATHER && !sg) break; + /* + * DUAL_SG walks the source and destination lists in lockstep; + * a premature end or a per-entry length mismatch would leave + * the descriptor partially built, so fail the whole request. + */ + if (xfer->type =3D=3D EDMA_XFER_DUAL_SG && + (!sg || !dst_sg || sg_dma_len(sg) !=3D sg_dma_len(dst_sg))) { + kfree(desc); + return NULL; + } =20 burst =3D desc->burst + i; =20 if (xfer->type =3D=3D EDMA_XFER_CYCLIC) burst->sz =3D xfer->xfer.cyclic.len; - else if (xfer->type =3D=3D EDMA_XFER_SCATTER_GATHER) + else if (xfer->type =3D=3D EDMA_XFER_SCATTER_GATHER || + xfer->type =3D=3D EDMA_XFER_DUAL_SG) burst->sz =3D sg_dma_len(sg); else if (xfer->type =3D=3D EDMA_XFER_INTERLEAVED) burst->sz =3D xfer->xfer.il->sgl[i % fsz].size; @@ -492,6 +518,9 @@ dw_edma_device_transfer(struct dw_edma_transfer *xfer, */ } else if (xfer->type =3D=3D EDMA_XFER_INTERLEAVED) { burst->dar =3D dst_addr; + } else if (xfer->type =3D=3D EDMA_XFER_DUAL_SG) { + burst->sar =3D dw_edma_get_pci_address(chan, sg_dma_address(sg)); + burst->dar =3D sg_dma_address(dst_sg); } } else { burst->dar =3D dst_addr; @@ -507,13 +536,19 @@ dw_edma_device_transfer(struct dw_edma_transfer *xfer, * and destination addresses are increased * by the same portion (data length) */ - } else if (xfer->type =3D=3D EDMA_XFER_INTERLEAVED) { + } else if (xfer->type =3D=3D EDMA_XFER_INTERLEAVED) { burst->sar =3D src_addr; + } else if (xfer->type =3D=3D EDMA_XFER_DUAL_SG) { + burst->sar =3D sg_dma_address(sg); + burst->dar =3D dw_edma_get_pci_address(chan, sg_dma_address(dst_sg)); } } =20 if (xfer->type =3D=3D EDMA_XFER_SCATTER_GATHER) { sg =3D sg_next(sg); + } else if (xfer->type =3D=3D EDMA_XFER_DUAL_SG) { + sg =3D sg_next(sg); + dst_sg =3D sg_next(dst_sg); } else if (xfer->type =3D=3D EDMA_XFER_INTERLEAVED) { struct dma_interleaved_template *il =3D xfer->xfer.il; struct data_chunk *dc =3D &il->sgl[i % fsz]; @@ -613,6 +648,44 @@ static void dw_hdma_set_callback_result(struct virt_dm= a_desc *vd, res->residue =3D residue; } =20 +static struct dma_async_tx_descriptor * +dw_edma_device_prep_dma_sg(struct dma_chan *dchan, + struct scatterlist *dst_sg, unsigned int dst_nents, + struct scatterlist *src_sg, unsigned int src_nents, + unsigned long flags) +{ + struct dw_edma_chan *chan =3D dchan2dw_edma_chan(dchan); + struct dw_edma_transfer xfer; + enum dma_transfer_direction dir; + + if (src_nents !=3D dst_nents || !src_nents) + return NULL; + + if (!src_sg || !dst_sg) + return NULL; + + /* Determine direction from channel configuration */ + if (chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL) + dir =3D (chan->dir =3D=3D EDMA_DIR_READ) ? DMA_DEV_TO_MEM : DMA_MEM_TO_D= EV; + else + dir =3D (chan->dir =3D=3D EDMA_DIR_WRITE) ? DMA_DEV_TO_MEM : DMA_MEM_TO_= DEV; + + xfer.dchan =3D dchan; + xfer.direction =3D dir; + xfer.xfer.dual_sg.src_sgl =3D src_sg; + xfer.xfer.dual_sg.dst_sgl =3D dst_sg; + xfer.xfer.dual_sg.len =3D src_nents; + xfer.flags =3D flags; + xfer.type =3D EDMA_XFER_DUAL_SG; + + /* + * dw_edma_device_transfer() rejects unconfigured channels, so + * dmaengine_slave_config() must have been called on this channel + * beforehand even though the direction field is unused here. + */ + return dw_edma_device_transfer(&xfer, dw_edma_device_get_config(dchan, NU= LL)); +} + static void dw_edma_done_interrupt(struct dw_edma_chan *chan) { struct dw_edma_desc *desc; @@ -997,6 +1070,7 @@ static int dw_edma_channel_setup(struct dw_edma *dw, u= 32 wr_alloc, u32 rd_alloc) dma_cap_set(DMA_CYCLIC, dma->cap_mask); dma_cap_set(DMA_PRIVATE, dma->cap_mask); dma_cap_set(DMA_INTERLEAVE, dma->cap_mask); + dma_cap_set(DMA_SG, dma->cap_mask); dma->directions =3D BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); dma->src_addr_widths =3D BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); dma->dst_addr_widths =3D BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); @@ -1017,6 +1091,7 @@ static int dw_edma_channel_setup(struct dw_edma *dw, = u32 wr_alloc, u32 rd_alloc) dma->device_prep_config_sg =3D dw_edma_device_prep_config_sg; dma->device_prep_dma_cyclic =3D dw_edma_device_prep_dma_cyclic; dma->device_prep_interleaved_dma =3D dw_edma_device_prep_interleaved_dma; + dma->device_prep_dma_sg =3D dw_edma_device_prep_dma_sg; =20 dma_set_max_seg_size(dma->dev, U32_MAX); =20 diff --git a/drivers/dma/dw-edma/dw-edma-core.h b/drivers/dma/dw-edma/dw-ed= ma-core.h index f6a5ad31756723e6fd72f7d9d903a1204e25c0b0..e3219ae96d84f528fb7d77dbe3a= 0b3d7c1264f05 100644 --- a/drivers/dma/dw-edma/dw-edma-core.h +++ b/drivers/dma/dw-edma/dw-edma-core.h @@ -38,7 +38,8 @@ enum dw_edma_status { enum dw_edma_xfer_type { EDMA_XFER_SCATTER_GATHER =3D 0, EDMA_XFER_CYCLIC, - EDMA_XFER_INTERLEAVED + EDMA_XFER_INTERLEAVED, + EDMA_XFER_DUAL_SG, }; =20 struct dw_edma_chan; @@ -151,6 +152,12 @@ struct dw_edma_sg { unsigned int len; }; =20 +struct dw_edma_dual_sg { + struct scatterlist *src_sgl; + struct scatterlist *dst_sgl; + unsigned int len; +}; + struct dw_edma_cyclic { dma_addr_t paddr; size_t len; @@ -163,6 +170,7 @@ struct dw_edma_transfer { struct dw_edma_sg sg; struct dw_edma_cyclic cyclic; struct dma_interleaved_template *il; + struct dw_edma_dual_sg dual_sg; } xfer; enum dma_transfer_direction direction; unsigned long flags; --=20 2.34.1 From nobody Fri Oct 2 09:21:58 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E57C3803D3 for ; Mon, 3 Aug 2026 10:32:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785753133; cv=none; b=l3wX3NQsCo6f87nXL9j1wZV64nxuEU2w6r/L5MYP468Z9eDspLe4UZ4e79P6mjiBSBcis0gHW9msZU4AlKx9StlFCK/qhmIroV8vcIUWuLOj4gEOOjh5E9wirXhV3R0MS8+i2I6D2ul3S9h19baQFX1m1lw2A2HUm4h6sQi0mEY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785753133; c=relaxed/simple; bh=YQodrxLZXGti3XmvW8nwU9lpi/9j4ifCS2HxijUaHDk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=epZ3pXZNoTGpSco2nEV0zfo1JWBRVGDqWu4LZ/PrFPGXh1vWcbDXOkGIGaWiL3midkxYJpvPNqztmlvbQfdTTPqsEoRauUr4UjRbgryVi+9QrsY7FzayMz72VU5WKC1YQWvbi1MN0Pm7zcclPPRBHxMXmV3d/tC0IjW7K9z0as4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=Vu4Jb7gB; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=cbIdnpCd; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="Vu4Jb7gB"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="cbIdnpCd" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 6736bXVr3957265 for ; Mon, 3 Aug 2026 10:32:09 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= hhWKGvX0bNeNwHOozHVzgVNQHnYcAVFkH32Yo6rHh38=; b=Vu4Jb7gB3declPWK TI3ECB0a8FvuRnE+D/jzRkJmWnbzJac120CngS1IhSZayxc7b9m4tP74KA7HjzI0 +Hr4EmydHJ/DbcOv5kOQ83iOgtoNvmG06zuFKdriQHYHbp1PSU3aENjow4ucZbmg DOidSr8lKRiL8ntegXqq0+5mO0vfXX6G+6pZvhhQQO/38cQ+JB8Kht/drncw1GGJ +kWFiQuNIvA0+o773xfVNWk3oNepwb9E151S+Ji/WULvobiHMp7evIdT5hIBn+sx 4AjzSC2+A1KUEa0UKvSnu4sYplS7jMo07ulsrleYdoBQayosyJwfNMx8AlFfhFyo jHfApA== Received: from mail-pj1-f72.google.com (mail-pj1-f72.google.com [209.85.216.72]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ftnvnh16p-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 03 Aug 2026 10:32:09 +0000 (GMT) Received: by mail-pj1-f72.google.com with SMTP id 98e67ed59e1d1-38f283baf1fso3100857a91.3 for ; Mon, 03 Aug 2026 03:32:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1785753128; x=1786357928; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=hhWKGvX0bNeNwHOozHVzgVNQHnYcAVFkH32Yo6rHh38=; b=cbIdnpCdJdN60W+wVZCuB0cFQzbgYAr1ZjxF7W2lJuF3RhmJWtipwTtFi5jE2HkKEK NNbZb4DGAKPnf0/PBRLNXi8KQ5XvDl0KlMq4J6Wo9x1dAqt6s3d5mB05e8ib3AzIE33s qLLoWTMOdWqDkZm7yrgwmsrWc8mj5COoP4zLQo4miVdp9Kby9147Jv7inAnYhZaiTqQ0 iU+JJ/B7LorBsMw5W+4CU7XAvucxU4I843UlOBuzAOgMn/Z2amTX+LGTB8Lu2MtnTbOf MHlFYOzzsZn6xnW+itjyBt+PQkquoJtfywPbf+ALq9yueIr1DjWzWgvG2ijvZ4aNJf1K YmLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1785753128; x=1786357928; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=hhWKGvX0bNeNwHOozHVzgVNQHnYcAVFkH32Yo6rHh38=; b=X4fgKC26HoxLKzoRXyF0lJrZVW9XNmXGIN63ic65CGbD1anaSVEhDFiclEELdltjQt dvPI/1jOt2z/YyGocJe8zvRyYoSJtab/nvkzcnN9jDKesxUvyPsLI++IqgvvhzsjfAuN jVWv6XET5FI9mWdf0qvIspeh/Lj9srMz9elk+xjyJsN3QZEusTXcr1U67T40s3LfRNmL wKhaQ4P8q8tg5yxU5mSepJ1vESunAld8VII645h5RY/DZuWHGET+zVuVPC4c5EIMjt6A BATeIyTpio9RRwArS/cwXBT9wR+q3oMBzMkmeGbUw0ou2ImVFMyL/O9oFsd4ocx2lP8G BlPg== X-Forwarded-Encrypted: i=1; AHgh+Rr7WWsDBTaDNj5+qy8bsnfSrRjORFdJaKkqeNvAODEF1QDY5Tum4LUyKecPqLXnYE6laJKTyxeTDKer9As=@vger.kernel.org X-Gm-Message-State: AOJu0YyB3qHXsM3VaN1LcNsOcMQxVl65joAJU3WUoKittljhvdjq5Pf9 Jvv4PYSQI7Zx7Q5RP+qD7zzQxGRgW7qVpTwoX8vIicyg/T6BqqniDjmZQHMHnYjTuy8qJ2FlDlB GEofy5tSvXcevUNPLjvSIvkJsrRubMx0wtEpQ6OgZF4pENUVM5BKK3nbBP0Vxm6bVIXw= X-Gm-Gg: AR+sD11eLXBSFxkSbFN39aRPJjN8FXrDPwy/Fhp1KOXNtgBm62/jrVezdXIaEDXu4SK 8r1IHUWSsPDTCxvQ35g+D9aAVDzwXOTsYIT9gKI6J6G1hsBo5TSIWalAaPO3vH9vSldE1e8pfE9 24Ig1vleeKNTojmfL0FB2HhWo0+EHjGEyZHZi4RmXb9Yy/Y/CK107KQRlXEfdMA1PjabBcZRoKw EHIjE/VxAoEo5fj6FeIhTlubBeSTNEf2OOqHz36K1xccIvYa3KDwFriA8yJHatqOzaeaoSGN82r W78967NWkAKHnuTzIePiMxnOsQ0vN+a92pltZwiPwQPSftCbXmiHeMsq08R4/ojK1R0McpLBTbY nxWDF6krhyxnj3wC/Qz6U4hzcug== X-Received: by 2002:a17:90b:58c3:b0:389:8f6c:4d59 with SMTP id 98e67ed59e1d1-38fbc4bc3cbmr8623154a91.24.1785753128248; Mon, 03 Aug 2026 03:32:08 -0700 (PDT) X-Received: by 2002:a17:90b:58c3:b0:389:8f6c:4d59 with SMTP id 98e67ed59e1d1-38fbc4bc3cbmr8623122a91.24.1785753127669; Mon, 03 Aug 2026 03:32:07 -0700 (PDT) Received: from hu-sumk-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38fb2b1244bsm3693427a91.0.2026.08.03.03.32.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 03:32:07 -0700 (PDT) From: Sumit Kumar Date: Mon, 03 Aug 2026 16:01:45 +0530 Subject: [PATCH v2 3/5] PCI: epf-mhi: Use a define for the DMA transfer timeout Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260803-dma_multi_sg-v2-3-c12bb05e42d6@oss.qualcomm.com> References: <20260803-dma_multi_sg-v2-0-c12bb05e42d6@oss.qualcomm.com> In-Reply-To: <20260803-dma_multi_sg-v2-0-c12bb05e42d6@oss.qualcomm.com> To: Vinod Koul , Frank Li , Jonathan Corbet , Shuah Khan , Manivannan Sadhasivam , Jeff Hugo , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Kishon Vijay Abraham I , Bjorn Helgaas Cc: dmaengine@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, mhi@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, Sumit Kumar X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1785753106; l=1737; i=sumit.kumar@oss.qualcomm.com; s=20250409; h=from:subject:message-id; bh=YQodrxLZXGti3XmvW8nwU9lpi/9j4ifCS2HxijUaHDk=; b=rcBxb1zUyIP4s50AcsJ6tkSwDs7jalf+WtVec3AVWiM+5ZsHiNUzXBYpOlzh8jiw2Jacuj4Ec tl6wkE1qXPxBIdwVaF+mpN3ZJYM4JlQEETY7EYgWiO8hxuAAq1WXNMf X-Developer-Key: i=sumit.kumar@oss.qualcomm.com; a=ed25519; pk=3cys6srXqLACgA68n7n7KjDeM9JiMK1w6VxzMxr0dnM= X-Authority-Analysis: v=2.4 cv=aoaCzyZV c=1 sm=1 tr=0 ts=6a706e29 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=K2uzCxK3BSS_9ZXfCP0A:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-GUID: MnAOLPLxYN12lLujy9LFgFcsR0OO-5CI X-Proofpoint-ORIG-GUID: MnAOLPLxYN12lLujy9LFgFcsR0OO-5CI X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODAzMDA5NCBTYWx0ZWRfX9ApjU/UPQWAn /EvO87Lo32VcUUNpENaiDMJvdfJKKbMuF1r4gvCd1yNqxzlWgGU+NLG9MGL4+1YeIN5z3w5HXx9 dZ6fj09llSFeoT/Z2lKE6l8+R+7FFGRSSUSU4amxThlJhLgK2keGRwv4ng1f1ceQnxO4Q7tdNmk IRJQev9ASM9zcZ6RVcW6keh+JFRDBs/HHxHzlWi2aJBngHGbe3+CDTxrzp6Wj7evJ6QuAtqaURU B9AjVwg1u4jj1WMJCK9Gh8CZwft6lnA9UnI+wyvWnrabH+IBgq2xLBlQ/8OIHRrRWg4J4rImokI co0zPMVG2hAyPWyljwB7MFXS6QOgnQvF3RRK8bbx0uRERKEHu246n09YrS/wRWlmDE/iMR6IhOM qCwiWfDV6hQ2zWdP5x4Tvukql0XJLc02ELWZwIfG1n+QSWtjQfnddHeBYZTm0O5Jca4xCTfGnuB 4Wj407nOwAQVnWF307w== X-Proofpoint-Spam-Info: AW1haW4tMjYwODAzMDA5NCBTYWx0ZWRfXy2sduUpVT0PO Egs0XH6wECjV6+E1UaLqPy09H3wbU5my2w0qxG9a6De4uOJ9Iv+z3vANtKnr+IcCA98p286N3Xm if+lfP2nK5lgE5WLYM7tadxJQAoyrdk= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-02_06,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 bulkscore=0 suspectscore=0 priorityscore=1501 adultscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 phishscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608030094 The eDMA read and write paths open-code a 1000 ms completion timeout as a msecs_to_jiffies(1000) literal. Replace both with a PCI_EPF_MHI_DMA_TIMEOUT_MS define so the value is named and shared. No functional change. Signed-off-by: Sumit Kumar --- drivers/pci/endpoint/functions/pci-epf-mhi.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/pci/endpoint/functions/pci-epf-mhi.c b/drivers/pci/end= point/functions/pci-epf-mhi.c index c3e3b58fb86cd75e175b69ca45530610c500b99e..6bac69fc84b472c5f1abbeede2b= 441b5db73c784 100644 --- a/drivers/pci/endpoint/functions/pci-epf-mhi.c +++ b/drivers/pci/endpoint/functions/pci-epf-mhi.c @@ -21,6 +21,8 @@ /* Platform specific flags */ #define MHI_EPF_USE_DMA BIT(0) =20 +#define PCI_EPF_MHI_DMA_TIMEOUT_MS 1000 + struct pci_epf_mhi_dma_transfer { struct pci_epf_mhi *epf_mhi; struct mhi_ep_buf_info buf_info; @@ -357,7 +359,7 @@ static int pci_epf_mhi_edma_read(struct mhi_ep_cntrl *m= hi_cntrl, } =20 dma_async_issue_pending(chan); - ret =3D wait_for_completion_timeout(&complete, msecs_to_jiffies(1000)); + ret =3D wait_for_completion_timeout(&complete, msecs_to_jiffies(PCI_EPF_M= HI_DMA_TIMEOUT_MS)); if (!ret) { dev_err(dev, "DMA transfer timeout\n"); dmaengine_terminate_sync(chan); @@ -425,7 +427,7 @@ static int pci_epf_mhi_edma_write(struct mhi_ep_cntrl *= mhi_cntrl, } =20 dma_async_issue_pending(chan); - ret =3D wait_for_completion_timeout(&complete, msecs_to_jiffies(1000)); + ret =3D wait_for_completion_timeout(&complete, msecs_to_jiffies(PCI_EPF_M= HI_DMA_TIMEOUT_MS)); if (!ret) { dev_err(dev, "DMA transfer timeout\n"); dmaengine_terminate_sync(chan); --=20 2.34.1 From nobody Fri Oct 2 09:21:58 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 18AE438C410 for ; Mon, 3 Aug 2026 10:32:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785753137; cv=none; b=kB6sAjkGpTz/OELXJkVJkn3JlqdX5ZQCDJaqD/k+4G85m9qFwWSCdGAwHp6lRNoBeWwp+qb3VbPd79ujnSy/5sfXguW4y5RQNX+FHO7aT9h7+WuRxi7rOOa9FRiUwvRoTlCG9VTuSrS98GEdKQ5LhT4bqEvWiB6pkVIS9FFLf4c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785753137; c=relaxed/simple; bh=4QpWEADG4CkH+CP53+qDbiZyPNja9E4z4/xXmZqrsQU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lyvFaMY8DBhPVsPttWLqXV37oC7BA1PVz9J4qN0tbVKSi/7v4hUUkHZVs1XkpKwbYwY+Ezh19QOBILntvD1FLES4Nz4iJrjW/9SwnmX4Hr8E1c387gQhfmEyCNRX+DSvBEoh7x3ZFop500Pxkn3SYnaKpje+wu+dEvnITKtmKaA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=WYpkr6g1; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=NsV1GaW3; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="WYpkr6g1"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="NsV1GaW3" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 6736SkbM3759066 for ; Mon, 3 Aug 2026 10:32:14 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= kzu2DfTz3pF/jHcouD27Xpy/1af5e6d+vxLdTi60Gn8=; b=WYpkr6g1QMq82YYo CdlBk1aTNqaYeUMNk96gKNxLn6EkUz5C4QgXlxrZRY1xYi85RoAHZd1/0wSpCFWK zrZ8AJZFArRm3P24u1OWXqJFK/0Jq4QdvwREGe2yfw6W+ZTuP0qU5sfDAK5iify4 kpEfLIyrAeWPYfCbWPeyp9aGZyzajCGTDNLGfQi1IgWBv7x/UHLE4sI+DYYV5CLN +wIDSn2GsMyMak+0W+tfFSLyUYlnG6jkqeLvxOyW3mV5GNh/MtZBXf/cnDsNQf1C 1lNVWiwphlep6DtdEjcvdLgTDFeK2t4T6mVPsyWfxmFxhI8tGT5f/j4GhbRNGuPw HT8I2g== Received: from mail-pl1-f197.google.com (mail-pl1-f197.google.com [209.85.214.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ftnrns1nh-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 03 Aug 2026 10:32:14 +0000 (GMT) Received: by mail-pl1-f197.google.com with SMTP id d9443c01a7336-2d001671a54so67989645ad.2 for ; Mon, 03 Aug 2026 03:32:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1785753133; x=1786357933; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=kzu2DfTz3pF/jHcouD27Xpy/1af5e6d+vxLdTi60Gn8=; b=NsV1GaW36u+evTualsTMJXFD7ZB6XT0g3APM8HiZf+8ywa08zUA98+hTVwFK9/WmZj JScqdI2LTlsAg57YY0s+/fpniWwp9Rlmxpq+Wu68XQZtvoDf+3fS6RAfk47f7bOXpCre HFP2hTpBwLsO4wzhru6r8Q2WNWizFAWuUDKtrenlibvf/xpQ3of4WSes2OjHwCC1Y0S+ NgfEfwHMRewYuVUStiZmLLSKlI+k0b+GHtPHq6Y1eYbfdl96Yutyt2Xg/OTXdIluR1pU Fze1BpaOr/LvSQJANZ6ex/A2i1lIVMAWZ8Na3kP8kVrl0h1UIVnHVuVXlXw0S7zvJUjO FU5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1785753133; x=1786357933; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=kzu2DfTz3pF/jHcouD27Xpy/1af5e6d+vxLdTi60Gn8=; b=mPcaEU6e2944RY2YdLCgn7jvsUhk8tdPcXbTrnWm56xDUSghMKRbr+iBOfgvVk1ryE 1wW3TQx/4822mDkjSxhfNvmGBiRbhnMfwMh2MjYPJd4var4etUBwg/vJTlk9PdmuRvzo Zjxdpj8Fr3d4l5LzyPhd89h67LSkVJF9Vy85SDf/U6WI3ez2IcCtZIMmudO7blkTraka Gicmf928G6naimfxF2G6zL7qGc3ym4isV50c8BW588FpkwCJ3cttvZ3vSQj30Kxeom+G TzfW8Y7+VXv1RA2JKis2zLvKJ0UyEDXUfznSLx+G4bvSrYFmeyM4btpZ5K//LzwLqgVc Pz/w== X-Forwarded-Encrypted: i=1; AHgh+Rrfu468exfBMAKZxxhODn5c5JA3g2x+HjrhJPAMpIqqqnM/6B0qNn4CzMpDiUVEwlNps01dxIpOJpQHPqI=@vger.kernel.org X-Gm-Message-State: AOJu0YxEyxFACBuo84jfyQA35BhJ8C+V8qhIJMYVXP2IVtUyU+AJLY/h isbjlPVPuM4cbc7FAUqVvqGKNEhddxUJNuZa2vPQUhvXyJk0n2oyHggJN3RkDqfhIm8ZJ+zdwQb t8uq05JDp/WKdk+PnghOA7OA5CHgDr6R39+0WT6t9ENJyZrxOFwbcqe1roo/Qb0azMJY= X-Gm-Gg: AR+sD113mLhSfZD80s/Cgh9v5RRWXfHnWUA/iYp5AqCkIh4NUJSky2v0tQ6JdWZLNvy lYX0WOE3WMDJ4Ow5YZ4y+VwRWt6EV+kA9q/Yo5YsUJQlfdANLkwILzf5Q+PyuSuMKERi7eaOT/+ 4iyjgONoGv5lf3D59yo7bgrP1m9TI+MYgTer43ftd7UoWCyCmtI7wi1NkFfOjMk4NBpApvaWuEb OziL3qz1TsQbdPsvKvQaCGmt30DVKBh8OUqDBTw/2sdZBRNfNxvfZSUQV6xsfm9SibIKPiVWggi b0ep4DKSVOBjiNi4fuo2zXp+ynqn9ROraqRgflxBOschbuQPss7vfMvtQ8MijPaa1p5TN0LW/uO eApWZyjUs9yiJT/ry+jmN8BhU3w== X-Received: by 2002:a17:90b:1c06:b0:38e:ad9d:1161 with SMTP id 98e67ed59e1d1-38fbc0c9bd9mr8433521a91.0.1785753133435; Mon, 03 Aug 2026 03:32:13 -0700 (PDT) X-Received: by 2002:a17:90b:1c06:b0:38e:ad9d:1161 with SMTP id 98e67ed59e1d1-38fbc0c9bd9mr8433492a91.0.1785753132847; Mon, 03 Aug 2026 03:32:12 -0700 (PDT) Received: from hu-sumk-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38fb2b1244bsm3693427a91.0.2026.08.03.03.32.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 03:32:12 -0700 (PDT) From: Sumit Kumar Date: Mon, 03 Aug 2026 16:01:46 +0530 Subject: [PATCH v2 4/5] PCI: epf-mhi: Add batched DMA read support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260803-dma_multi_sg-v2-4-c12bb05e42d6@oss.qualcomm.com> References: <20260803-dma_multi_sg-v2-0-c12bb05e42d6@oss.qualcomm.com> In-Reply-To: <20260803-dma_multi_sg-v2-0-c12bb05e42d6@oss.qualcomm.com> To: Vinod Koul , Frank Li , Jonathan Corbet , Shuah Khan , Manivannan Sadhasivam , Jeff Hugo , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Kishon Vijay Abraham I , Bjorn Helgaas Cc: dmaengine@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, mhi@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, Sumit Kumar X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1785753106; l=9526; i=sumit.kumar@oss.qualcomm.com; s=20250409; h=from:subject:message-id; bh=4QpWEADG4CkH+CP53+qDbiZyPNja9E4z4/xXmZqrsQU=; b=ZWwBKKhxFxlU1y+hFSSNRfzdca0yerwMiZT59hD0GLb/a9RUBqcBLIw8RAerzrnXxnxqspfbn e+CVE/QIXHqCnPyltWZXuJbQvYvf1rZTufLFnkxZRjavIROgytwFvCy X-Developer-Key: i=sumit.kumar@oss.qualcomm.com; a=ed25519; pk=3cys6srXqLACgA68n7n7KjDeM9JiMK1w6VxzMxr0dnM= X-Proofpoint-Spam-Info: AW1haW4tMjYwODAzMDA5NCBTYWx0ZWRfX7Qt4gD7IjdYY ydC+5uL/Q1gbYG46g2UdAdyomVfqI7oWc+ENQvrKgeUtfU13cEEe9w3oBVyyllCsFMMgvInsjUQ oRIcbaJ7h06VNDl4xxVVCaFaHMrWOU4= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODAzMDA5NCBTYWx0ZWRfX0/v29FQpwXkr 9A2d5pqzBi4cWsGbqZEVrh4281clzqwt+BaADdKtC4/1adLEmj+XJqoF77g2UrTcWgcuhxsRS0G O9WS+7ZlFJtAAfi4uRbyXBT1Z8+Ify9LHdY/0ZfCtZY5QhTPGtuWxGJKnQ/hpgqaj/1uZxdRkwj JovHpSpjgadGVqMnqze5SmqW277S7k97JaKZzMhcs5bAoEBqxs/aS+CcaWEf8Vhi30ndQoJzNt5 rcWS/CgxXeUh2QR/WyNxl30488qUzjEIqTBGqXcOZBZZfe1lbrB8VW93ROVmlQN744M7aD48l7F VTNuMbfAWSTLRpTiPlpD3YQAVCre2NbpblJX0lwBimjkAt78tt2JYPX7Nw3XakCgN/DwgYsyCTJ 43+WmuCqRH4W/06g+U6Hnb1ZlxV+f0+x7Ds4i53IyvV7URN7IFMmG/Xmk/zXBD45pRxGowCeTRl E8iS5Dj/cVzRe3UCYpA== X-Authority-Analysis: v=2.4 cv=Zest8MVA c=1 sm=1 tr=0 ts=6a706e2e cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=DqDsU1vVsjqoWll3QmEA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-GUID: AqC8dQTmuD0PaPacDGbjkPUK1_LqvBnU X-Proofpoint-ORIG-GUID: AqC8dQTmuD0PaPacDGbjkPUK1_LqvBnU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-02_06,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 clxscore=1015 adultscore=0 lowpriorityscore=0 priorityscore=1501 bulkscore=0 suspectscore=0 malwarescore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608030094 Add support for batched DMA transfers in the PCI EPF MHI driver to improve performance when reading multiple buffers from the host. Implement two variants of the read_batch() callback: pci_epf_mhi_edma_read_batch() is a DMA-optimized implementation that uses dmaengine_prep_dma_sg() to transfer multiple buffers in a single DMA transaction, while pci_epf_mhi_iatu_read_batch() serves as a CPU-copy fallback for platforms without DMA support by sequentially processing each buffer via IATU mapping. Wire up read_batch() to the eDMA variant only when the RX DMA channel advertises the DMA_SG capability, falling back to the IATU variant otherwise. On a successful batch, notify completion for every buffer via its caller-supplied buf_info->cb, mirroring the read_sync/read_async completion semantics so the MHI stack can free each buffer and raise its transfer completion event. Make read_batch() a mandatory callback in mhi_ep_register_controller(), alongside read_sync/write_sync/read_async/ write_async. This enables the MHI endpoint stack to cache ring data efficiently, particularly for wraparound scenarios where ring data spans two non-contiguous memory regions. Signed-off-by: Sumit Kumar --- drivers/bus/mhi/ep/main.c | 3 +- drivers/pci/endpoint/functions/pci-epf-mhi.c | 159 +++++++++++++++++++++++= ++++ include/linux/mhi_ep.h | 7 ++ 3 files changed, 168 insertions(+), 1 deletion(-) diff --git a/drivers/bus/mhi/ep/main.c b/drivers/bus/mhi/ep/main.c index 21bc2c50170ff7f0181c0d0d4eefd51db30f34c8..c45240fc481dc3260a61b546c22= 3b6be8e105587 100644 --- a/drivers/bus/mhi/ep/main.c +++ b/drivers/bus/mhi/ep/main.c @@ -1459,7 +1459,8 @@ int mhi_ep_register_controller(struct mhi_ep_cntrl *m= hi_cntrl, return -EINVAL; =20 if (!mhi_cntrl->read_sync || !mhi_cntrl->write_sync || - !mhi_cntrl->read_async || !mhi_cntrl->write_async) + !mhi_cntrl->read_async || !mhi_cntrl->write_async || + !mhi_cntrl->read_batch) return -EINVAL; =20 ret =3D mhi_ep_chan_init(mhi_cntrl, config); diff --git a/drivers/pci/endpoint/functions/pci-epf-mhi.c b/drivers/pci/end= point/functions/pci-epf-mhi.c index 6bac69fc84b472c5f1abbeede2b441b5db73c784..ad245148de1462cffc950ba9a9e= 232405514dfb7 100644 --- a/drivers/pci/endpoint/functions/pci-epf-mhi.c +++ b/drivers/pci/endpoint/functions/pci-epf-mhi.c @@ -444,6 +444,162 @@ static int pci_epf_mhi_edma_write(struct mhi_ep_cntrl= *mhi_cntrl, return ret; } =20 +static int pci_epf_mhi_iatu_read_batch(struct mhi_ep_cntrl *mhi_cntrl, + struct mhi_ep_buf_info *buf_info_array, + u32 num_buffers) +{ + struct pci_epf_mhi *epf_mhi =3D to_epf_mhi(mhi_cntrl); + struct device *dev =3D &epf_mhi->epf->dev; + u32 i; + int ret; + + if (num_buffers =3D=3D 0) + return -EINVAL; + + for (i =3D 0; i < num_buffers; i++) { + ret =3D pci_epf_mhi_iatu_read(mhi_cntrl, &buf_info_array[i]); + if (ret < 0) { + dev_err(dev, "Failed to read buffer %u of %u in batch: %d\n", + i, num_buffers, ret); + return ret; + } + } + + return 0; +} + +static int pci_epf_mhi_edma_read_batch(struct mhi_ep_cntrl *mhi_cntrl, + struct mhi_ep_buf_info *buf_info_array, + u32 num_buffers) +{ + struct pci_epf_mhi *epf_mhi =3D to_epf_mhi(mhi_cntrl); + struct device *dma_dev =3D epf_mhi->epf->epc->dev.parent; + struct device *dev =3D &epf_mhi->epf->dev; + struct dma_async_tx_descriptor *desc; + struct dma_slave_config config =3D {}; + DECLARE_COMPLETION_ONSTACK(complete); + struct scatterlist *src_sg; + struct scatterlist *dst_sg; + unsigned long time_left; + struct dma_chan *chan; + dma_cookie_t cookie; + unsigned int i; + int mapped; + void *buf; + int ret; + + if (num_buffers =3D=3D 0) + return -EINVAL; + + /* + * Single allocation carved into two arrays: src_sg[], dst_sg[]. + * Reduces allocator round-trips on the ring-cache hot path. Done + * before taking the lock so direct reclaim cannot stall other + * transfers waiting on epf_mhi->lock. + */ + buf =3D kcalloc(num_buffers, 2 * sizeof(*src_sg), GFP_KERNEL); + if (!buf) + return -ENOMEM; + src_sg =3D buf; + dst_sg =3D src_sg + num_buffers; + + mutex_lock(&epf_mhi->lock); + + chan =3D epf_mhi->dma_chan_rx; + if (!chan) { + ret =3D -ENODEV; + goto err_unlock; + } + + sg_init_table(src_sg, num_buffers); + sg_init_table(dst_sg, num_buffers); + + for (i =3D 0; i < num_buffers; i++) { + /* + * src addresses are PCIe host bus addresses already visible to + * the eDMA engine; no dma_map_sg() is needed for the source list. + */ + sg_dma_address(&src_sg[i]) =3D buf_info_array[i].host_addr; + sg_dma_len(&src_sg[i]) =3D buf_info_array[i].size; + + sg_set_buf(&dst_sg[i], buf_info_array[i].dev_addr, buf_info_array[i].siz= e); + } + + mapped =3D dma_map_sg(dma_dev, dst_sg, num_buffers, DMA_FROM_DEVICE); + if (!mapped) { + dev_err(dev, "Failed to map destination buffers for %u-buffer batch read= \n", + num_buffers); + ret =3D -EIO; + goto err_unlock; + } + + config.direction =3D DMA_DEV_TO_MEM; + ret =3D dmaengine_slave_config(chan, &config); + if (ret) { + dev_err(dev, "Failed to configure DMA channel for %u-buffer batch read: = %d\n", + num_buffers, ret); + goto err_unmap; + } + + desc =3D dmaengine_prep_dma_sg(chan, dst_sg, num_buffers, + src_sg, num_buffers, + DMA_CTRL_ACK | DMA_PREP_INTERRUPT); + if (!desc) { + dev_err(dev, "Failed to prepare batch DMA\n"); + ret =3D -EIO; + goto err_unmap; + } + + desc->callback =3D pci_epf_mhi_dma_callback; + desc->callback_param =3D &complete; + + cookie =3D dmaengine_submit(desc); + ret =3D dma_submit_error(cookie); + if (ret) { + dev_err(dev, "Failed to submit DMA\n"); + if (dmaengine_terminate_sync(chan)) + dev_err(dev, "Failed to terminate DMA channel after submit failure\n"); + goto err_unmap; + } + + dma_async_issue_pending(chan); + + time_left =3D wait_for_completion_timeout(&complete, + msecs_to_jiffies(PCI_EPF_MHI_DMA_TIMEOUT_MS)); + if (!time_left) { + dev_err(dev, "DMA transfer timeout\n"); + if (dmaengine_terminate_sync(chan)) + dev_err(dev, "Failed to terminate DMA channel after timeout\n"); + ret =3D -ETIMEDOUT; + goto err_unmap; + } + + ret =3D 0; + +err_unmap: + /* dma_unmap_sg() must use the nents passed to dma_map_sg(), not its retu= rn value */ + dma_unmap_sg(dma_dev, dst_sg, num_buffers, DMA_FROM_DEVICE); +err_unlock: + mutex_unlock(&epf_mhi->lock); + + kfree(buf); + + /* + * On a successful batch, notify completion for every buffer via its + * caller-supplied callback so MHI can free the backing buffer and raise + * the transfer completion event per entry, matching the + * read_sync/read_async semantics. Done after dropping the lock as a + * callback may re-enter the driver and epf_mhi->lock is not reentrant. + */ + if (!ret) { + for (i =3D 0; i < num_buffers; i++) + if (buf_info_array[i].cb) + buf_info_array[i].cb(&buf_info_array[i]); + } + + return ret; +} + static void pci_epf_mhi_dma_worker(struct work_struct *work) { struct pci_epf_mhi *epf_mhi =3D container_of(work, struct pci_epf_mhi, dm= a_work); @@ -789,11 +945,14 @@ static int pci_epf_mhi_link_up(struct pci_epf *epf) mhi_cntrl->unmap_free =3D pci_epf_mhi_unmap_free; mhi_cntrl->read_sync =3D mhi_cntrl->read_async =3D pci_epf_mhi_iatu_read; mhi_cntrl->write_sync =3D mhi_cntrl->write_async =3D pci_epf_mhi_iatu_wri= te; + mhi_cntrl->read_batch =3D pci_epf_mhi_iatu_read_batch; if (info->flags & MHI_EPF_USE_DMA) { mhi_cntrl->read_sync =3D pci_epf_mhi_edma_read; mhi_cntrl->write_sync =3D pci_epf_mhi_edma_write; mhi_cntrl->read_async =3D pci_epf_mhi_edma_read_async; mhi_cntrl->write_async =3D pci_epf_mhi_edma_write_async; + if (dma_has_cap(DMA_SG, epf_mhi->dma_chan_rx->device->cap_mask)) + mhi_cntrl->read_batch =3D pci_epf_mhi_edma_read_batch; } =20 /* Register the MHI EP controller */ diff --git a/include/linux/mhi_ep.h b/include/linux/mhi_ep.h index 7b40fc8cbe77ab8419d167e89264b69a817b9fb1..51f66cae937a53a93e9ae76cdcf= aac7b1e08283f 100644 --- a/include/linux/mhi_ep.h +++ b/include/linux/mhi_ep.h @@ -107,6 +107,11 @@ struct mhi_ep_buf_info { * @write_sync: CB function for writing to host memory synchronously * @read_async: CB function for reading from host memory asynchronously * @write_async: CB function for writing to host memory asynchronously + * @read_batch: CB function for reading from host memory in batches synchr= onously. + * Callers must pass at least one buffer (num_buffers > 0); e= ach + * buf_info entry must have host_addr, dev_addr and size set. + * Each buffer's buf_info->cb, if set, is invoked once the ba= tch + * completes successfully, mirroring read_sync/read_async. * @mhi_state: MHI Endpoint state * @max_chan: Maximum channels supported by the endpoint controller * @mru: MRU (Maximum Receive Unit) value of the endpoint controller @@ -164,6 +169,8 @@ struct mhi_ep_cntrl { int (*write_sync)(struct mhi_ep_cntrl *mhi_cntrl, struct mhi_ep_buf_info = *buf_info); int (*read_async)(struct mhi_ep_cntrl *mhi_cntrl, struct mhi_ep_buf_info = *buf_info); int (*write_async)(struct mhi_ep_cntrl *mhi_cntrl, struct mhi_ep_buf_info= *buf_info); + int (*read_batch)(struct mhi_ep_cntrl *mhi_cntrl, struct mhi_ep_buf_info = *buf_info_array, + u32 num_buffers); =20 enum mhi_state mhi_state; =20 --=20 2.34.1 From nobody Fri Oct 2 09:21:58 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B7E4138DC4F for ; Mon, 3 Aug 2026 10:32:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785753142; cv=none; b=DHS9hOQFTzh0a/+kLwFBrA6/RMZSaXnCNanSE+YwpNMPzAVyScyjVor/rzXyhJyy6q2fmMtRO71FSYU/+RCUwZ9eQXKJeuvU52UqURTXZXOZRZ3giLVXKtYUlnFtcYantfnDPkvBHtatYSzwxR5RU+aYs395xBw/8aVVCdT/tbE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785753142; c=relaxed/simple; bh=kXJQnle2iy213AQWQj46cMV6D4x1j/TtR9P5Qzd56rA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=oUiF0sTQlu1u34UuglrQq+NjrzYCWIOvprcEZsm7pAVGrZUS4O3TiXsKhcpeW+t5XMr0OOR7YLqqKAzs9MAqxd4yMOK4Ml0OIiztdSCJwRTyjvegENPF6zWhRScKGX01iz+ANuSxvSK5NkLxkSTc6Pt2NRbgGxgqjetl/VMf2ew= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=TiU7BJpN; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=b1kuUadB; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="TiU7BJpN"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="b1kuUadB" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 6736sYQS3790798 for ; Mon, 3 Aug 2026 10:32:19 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= SsOg8BzHaZPjVzLWezCKuNFn2YJ6/+JPUNTdZcJCf2U=; b=TiU7BJpNpXEsU/y2 mhQjK4BU5En47PTImCEEAkJNY22Im2WfBGZQX8fxXy60Ey+O/ZD1BpvzsVcvRrG4 hCfA2aGDHQ11mL4FdQ3PXjLLka7SpyRcFoz1c6bcgKkvqGC0AplSCkIaajpvnAXk 6XIVevQZHrXA9y0NNqaBO3OYcC3MkleBsH9grp/jKVbpHuyd1St5mQ4CDJi8fZpy UdrpOccwOt+cQ6UVcH7ngtf7ldpNOzcfLDNUnnOnt3oCFyxJGXQcLXByDxSTsMgN 9pPRSm5YE3IBIw+Hgwitij1zsFEMaSnusV4rIjCE+K13nv6viAIX+d3d0uJyRwnM 1q5jDQ== Received: from mail-pj1-f69.google.com (mail-pj1-f69.google.com [209.85.216.69]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ftp4r0ycd-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 03 Aug 2026 10:32:19 +0000 (GMT) Received: by mail-pj1-f69.google.com with SMTP id 98e67ed59e1d1-38e475f83a2so5423760a91.1 for ; Mon, 03 Aug 2026 03:32:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1785753138; x=1786357938; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=SsOg8BzHaZPjVzLWezCKuNFn2YJ6/+JPUNTdZcJCf2U=; b=b1kuUadBN3He0pAkStNvDTt5dvOPCxDKWPIL7QkWFQGNGHR+RBWGmkwwypI2+XuLEL L7g4apLsAWKJl31Sva64Cq8zCHUkA/Wwn5Y6nckeLYB0+MdpQ8dt7sNbwQxhpG9fHx1c DsqQH9Z0yGvkLexyDngSrxmsfArnVv75uqsoiiFKva4D+TKUs1f+3NitzD81lUmmuVfs NvLF/4a/v17de5LiRln0wnj1hUVFsNretVACYwCmqnBJBKFIOhMzyebgYGIrxKRlael6 g7BhEgptI3m4h1UFgVj4dakCOe+5VteNRrKqUQsmf0yDaj2+OshLoBK0jdzckN5/LMaW ZyVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1785753138; x=1786357938; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=SsOg8BzHaZPjVzLWezCKuNFn2YJ6/+JPUNTdZcJCf2U=; b=dvUq88U32yg289syv3c0gQbkt/Vop2s+I/mg5DL5qbOGrY+2Qf3CAmF1rFBO+TmeBq LvzhthVM1Fg8gPQ7aIl9tHjxzKHT+CTpf5bJbT/96szrn7eTgZ/W5szNgCtHotm1IT8/ TRaBjR/UtA2Uesg4MrbiDe3ZIGjL1FdzxNrZNS/Xw1vclBo15rPapl4pz3GjQUJgEchq 2tRlh56ng1V/f/BJADVLOC4ZJ/tKUqkW9pW/seBQYJcMhMM0g+A1dg6BILEEZB5r51AS LZ6kpdnmhw5ZN8y7LQpIKQihqekPJXNk9oPz+sQV5mSMLSnfvRHQJKx6jmuFxt3jcZmE 0C7A== X-Forwarded-Encrypted: i=1; AHgh+RpjdnaXBQeegKL1SfBgRjh2NluzVP7fF+FK0Op0ctVfQhdgjmKXTrHD1QpRBf/keAjk6WxkKYfbo8k6ydQ=@vger.kernel.org X-Gm-Message-State: AOJu0YzlFh2PO4VcZsN0kOSJuVdXAxGHHQG+O9Z5ECQOm1AetAwphw57 5ipAL97T+c6CZ9wIZD3JJpXGDGB9zNeLCnCAEpwB4X/tc1XfGcHyVW3krE1CfIFTclZNCTfpNFk BRR1pYQFh1wKzbWpQWKn3m/Q09x1lMUJvnUoOFC8tS30GqkBYyzeRiQpL4JYN3G8Q91Q= X-Gm-Gg: AR+sD105D7NlobHSde0vV9sJNFknqWKnmPudEMPY+Io2A0s6wQQEd2DVKOXj+KJ+rI7 mHrYVTM89qx1GjCquC6z2q53ZWTh1mZ5ocy6BZPq/ZMQuzcQp4M0TiPnGYayIKhsb3cgx4qEpEN 7S9o3vNQNycbRBFRD96VnFmoTN1sL8y8QQ1jAZoS9M9hN5l799B3GdqZF3N/4dUCq2YwXgpiXam q/8RgD52ljY9e1WtcRZE2jX8+i7mMpklaPGhI59+FOdQ0OF6g0yFxvp+onaVEVVhoFI86KjRr/5 UiHIXqxjaZisBd/at83p6oNYRq6DhWPxGo0uYYHnwa374maY8dQjiwQ3h4QE3HSbqpW78Al5gnG dPdg0+UtkrXN10nvZ952pFKboOA== X-Received: by 2002:a17:90b:2588:b0:38e:712a:bb38 with SMTP id 98e67ed59e1d1-38fbc530fe4mr8942872a91.24.1785753138515; Mon, 03 Aug 2026 03:32:18 -0700 (PDT) X-Received: by 2002:a17:90b:2588:b0:38e:712a:bb38 with SMTP id 98e67ed59e1d1-38fbc530fe4mr8942831a91.24.1785753138002; Mon, 03 Aug 2026 03:32:18 -0700 (PDT) Received: from hu-sumk-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38fb2b1244bsm3693427a91.0.2026.08.03.03.32.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 03:32:17 -0700 (PDT) From: Sumit Kumar Date: Mon, 03 Aug 2026 16:01:47 +0530 Subject: [PATCH v2 5/5] bus: mhi: ep: Use batched read for ring caching Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260803-dma_multi_sg-v2-5-c12bb05e42d6@oss.qualcomm.com> References: <20260803-dma_multi_sg-v2-0-c12bb05e42d6@oss.qualcomm.com> In-Reply-To: <20260803-dma_multi_sg-v2-0-c12bb05e42d6@oss.qualcomm.com> To: Vinod Koul , Frank Li , Jonathan Corbet , Shuah Khan , Manivannan Sadhasivam , Jeff Hugo , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Kishon Vijay Abraham I , Bjorn Helgaas Cc: dmaengine@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, mhi@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, Sumit Kumar X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1785753106; l=3180; i=sumit.kumar@oss.qualcomm.com; s=20250409; h=from:subject:message-id; bh=kXJQnle2iy213AQWQj46cMV6D4x1j/TtR9P5Qzd56rA=; b=+8Fy0NjdzuFsiqbwvScTz4Xn76n/ysFSpxfGLANQlTO8kqhW/k29GAcN9IKv825+jmOn97fT4 OmfYqMfaJTzBIo5STgSVXs09zHTAA7nUzj1rknHfloExXKfrqI72JgI X-Developer-Key: i=sumit.kumar@oss.qualcomm.com; a=ed25519; pk=3cys6srXqLACgA68n7n7KjDeM9JiMK1w6VxzMxr0dnM= X-Authority-Analysis: v=2.4 cv=X9Ri7mTe c=1 sm=1 tr=0 ts=6a706e33 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=O-L2LWsoD7DDJCLd4zEA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-ORIG-GUID: p3AZI7MReFe0GN2ZnSyVBoFFo9tyL8GE X-Proofpoint-GUID: p3AZI7MReFe0GN2ZnSyVBoFFo9tyL8GE X-Proofpoint-Spam-Info: AW1haW4tMjYwODAzMDA5NCBTYWx0ZWRfX7vMnpDOlrqw3 dX5yMZ2+ycU/qMCwSREy3NrDPykxhw35f+2UkCiOsLm8lZZYjiHd2eU5xDFHQYtalZ2uVxGNTxa DclLqLOYkbYCIhmiB7eDR6wZUSIwecc= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODAzMDA5NCBTYWx0ZWRfX1fcQ5IfF0L15 0SUY8gT3eyq8CRnIbsl76KhS9STJyaVwFyF8Wf+0p73aBBxK17M+PTKl2Yl6Sxdbm/LNFlzkCmw P8gO8FEKEorISAvDt9e2CBp+imaSe96WWAEexfXxO7DPRWwmR5YJH1lbmYV6J78XBxSs/Et6KHT 3IGI1eQgmey1j8xox7mfZl56fr+6OZPv7MiKVKDmGecmoj4Kk/mBRsjkrZf4xeSz3HqO2VHHiKN St1NYhCWfvwCXMIko/g3PcDpjfGSg31yeTZBhT12mc8+nQKnuRW0XU2w+F7LtOMM98FuVGjL8SK 2wYPryWbCy0nEYd3jAxMSsIibY9nx+HOLzwj2+tJCX4oKi5f8KpLChZoBB9zmpsCMl8pIdtH/2V pXUW9DRe1mI96b4txfjM/vP5XNxTvY/MOFzKMTF1FDBKSXLytR0IVP3V7fR7WFwjrfqf/A2b7Rq eFAzJNAtqe+kc93CXTA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-02_06,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 impostorscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 phishscore=0 adultscore=0 spamscore=0 lowpriorityscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608030094 Optimise ring caching in __mhi_ep_cache_ring(). For the non-wraparound case, use read_sync(); for the wraparound case where ring data spans two non-contiguous host memory regions, both the tail portion (start -> ring_size) and head portion (0 -> end) are submitted using the new read_batch() API in a single operation. On DMA-capable platforms this transfers both segments in one DMA transaction. Signed-off-by: Sumit Kumar --- drivers/bus/mhi/ep/ring.c | 36 ++++++++++++++++++++---------------- 1 file changed, 20 insertions(+), 16 deletions(-) diff --git a/drivers/bus/mhi/ep/ring.c b/drivers/bus/mhi/ep/ring.c index 405ce16c02a89ea2268ea1033ff5c1c26b1c81bd..a369c1eb0c0b849d7ced01b9989= 8ca461cf680b9 100644 --- a/drivers/bus/mhi/ep/ring.c +++ b/drivers/bus/mhi/ep/ring.c @@ -30,7 +30,6 @@ static int __mhi_ep_cache_ring(struct mhi_ep_ring *ring, = size_t end) { struct mhi_ep_cntrl *mhi_cntrl =3D ring->mhi_cntrl; struct device *dev =3D &mhi_cntrl->mhi_dev->dev; - struct mhi_ep_buf_info buf_info =3D {}; size_t start; int ret; =20 @@ -44,6 +43,8 @@ static int __mhi_ep_cache_ring(struct mhi_ep_ring *ring, = size_t end) =20 start =3D ring->wr_offset; if (start < end) { + struct mhi_ep_buf_info buf_info =3D {}; + buf_info.size =3D (end - start) * sizeof(struct mhi_ring_element); buf_info.host_addr =3D ring->rbase + (start * sizeof(struct mhi_ring_ele= ment)); buf_info.dev_addr =3D &ring->ring_cache[start]; @@ -51,27 +52,30 @@ static int __mhi_ep_cache_ring(struct mhi_ep_ring *ring= , size_t end) ret =3D mhi_cntrl->read_sync(mhi_cntrl, &buf_info); if (ret) return ret; + + dev_dbg(dev, "Cached ring: start %zu end %zu size %zu\n", start, end, + buf_info.size); } else { - buf_info.size =3D (ring->ring_size - start) * sizeof(struct mhi_ring_ele= ment); - buf_info.host_addr =3D ring->rbase + (start * sizeof(struct mhi_ring_ele= ment)); - buf_info.dev_addr =3D &ring->ring_cache[start]; + struct mhi_ep_buf_info buf_info[2] =3D {}; + u32 count =3D 1; =20 - ret =3D mhi_cntrl->read_sync(mhi_cntrl, &buf_info); - if (ret) - return ret; + buf_info[0].size =3D (ring->ring_size - start) * sizeof(struct mhi_ring_= element); + buf_info[0].host_addr =3D ring->rbase + (start * sizeof(struct mhi_ring_= element)); + buf_info[0].dev_addr =3D &ring->ring_cache[start]; =20 if (end) { - buf_info.host_addr =3D ring->rbase; - buf_info.dev_addr =3D &ring->ring_cache[0]; - buf_info.size =3D end * sizeof(struct mhi_ring_element); - - ret =3D mhi_cntrl->read_sync(mhi_cntrl, &buf_info); - if (ret) - return ret; + buf_info[1].size =3D end * sizeof(struct mhi_ring_element); + buf_info[1].host_addr =3D ring->rbase; + buf_info[1].dev_addr =3D &ring->ring_cache[0]; + count =3D 2; } - } + ret =3D mhi_cntrl->read_batch(mhi_cntrl, buf_info, count); + if (ret) + return ret; =20 - dev_dbg(dev, "Cached ring: start %zu end %zu size %zu\n", start, end, buf= _info.size); + dev_dbg(dev, "Cached ring (batched): start %zu end %zu tail_size %zu hea= d_size %zu count %u\n", + start, end, buf_info[0].size, end ? buf_info[1].size : 0, count); + } =20 return 0; } --=20 2.34.1