From nobody Fri Oct 2 07:45:35 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 32B1636CE19; Mon, 3 Aug 2026 23:13:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785798831; cv=none; b=c1M8bQnatvHz9mXBmXA4kKjqYmG0r5BaDbA1S/O4NlS2DwVIevs8olDBs9GSFiVsfRmfWJLzOn4qIoWQd8ieIMfXgFNSH6FvIqkuwVsXTo+GbvvCamfmthxk6rqsouPIeYNPqYCQAal5enXVFVQsgvAK+q6rEcLaHgZf8v8lUCk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785798831; c=relaxed/simple; bh=DZmwxJP+W8fGWvn/wOKVMifNip3avlrIAIcelKvVs+o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lt92YJYtQgri4NEHRIi2trqio3NmehTQGroAu4gxCnyvV6hSNIwnBpIHmZGu3RyvKu+8qXKeHLPiHzAXjIuqdojggEC1J5XtH+4kiS+bTUwMpnqiNhg1VsTueUtTtxvLxkl7czAgqj8bQKVHOGpw85hjnkMbp6ARfuUldQIFtgM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=bMmg+SyI; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="bMmg+SyI" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 61E861F00A3D; Mon, 3 Aug 2026 23:13:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1785798828; bh=MWKdz3JjvBdWuvOM6XAtmb0QINEsI1qn45G5e91+shs=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=bMmg+SyIYkQotwqndKPnGAM5LzydfefBsa7HQ6mWc4Nqa+55HgPBPObG7Zr8bnuPt eo18e+JEDq8jyhmEvk0zhrblYNjRFiHC5n/sG3iIxs5tH9voJeHEBC050mMowAI3sI fkZt0wDRz1aRY/K/WNPE+iqp4tyPRXc56Nc47yfk7cljj3+CLr07QtVzPHPerc2HZL bxVmDK16nogajsTkcIN+Tkb4J9wlo4Oo3aT8aXIEL9pHNlYMWnFpHheAWXE+jk2ETZ elY8vlXTx7ILOVaex6QcBtjIhGrSwH1mbYJ+/LC86XnB5nZRodoq1PhjkUX/cg+6tV Yrpp+sI6NCuQQ== From: Mark Brown Date: Mon, 03 Aug 2026 23:56:46 +0100 Subject: [PATCH v18 01/14] arm64/gcs: Ensure FGTs for EL1 GCS instructions are disabled Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260803-arm64-gcs-v18-1-fd8c40f5ad88@kernel.org> References: <20260803-arm64-gcs-v18-0-fd8c40f5ad88@kernel.org> In-Reply-To: <20260803-arm64-gcs-v18-0-fd8c40f5ad88@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Joey Gouly , Suzuki K Poulose , Shuah Khan , Fuad Tabba , Oliver Upton Cc: Peter Maydell , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=906; i=broonie@kernel.org; h=from:subject:message-id; bh=DZmwxJP+W8fGWvn/wOKVMifNip3avlrIAIcelKvVs+o=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqcSCaY5vmoCebOz+50MafMkleZZx0nmawOTK6f WZjtGmb/meJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCanEgmgAKCRAk1otyXVSH 0ObQB/4rLPRCuyyEUJqVXMlIJCDtlyScXBoSu42kR26SMPfPpzjW67SeYMd7/jJucvagyxeDESt ydaNDDgzEr9sgMINY1YbAXjzTQu7zn6FmuQ7vS9v0hVpzgU4mdOpxpqFuZ1yq+97G30XufY6xap gwtYiomMJc63RZ7fECW7utdhNGeCwHrq+atUjZYpLKpj+j4MrZMm2QHfyBCuoM7LXMCV8XEqKxt wBtlH5C9XKnbFuUa1X7G3IvX0x150pwcA4nFUb7zMlrU082hjKbonn+QsPj6tXBlARnX+an3orG k0CvfWEUIzhmvwVQ19ux4o4kJvLCTdhf1+YsDmS7aTNma6b2 X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB The initial EL2 setup for GCS did not include disabling of EL1 usage of GCS instructions, also disable these traps. Fixes: ff5181d8a2a8 ("arm64/gcs: Provide basic EL2 setup to allow GCS usage= at EL0 and EL1") Signed-off-by: Mark Brown --- arch/arm64/include/asm/el2_setup.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el= 2_setup.h index aa8ec9df8024..d308c6e6757d 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -393,6 +393,11 @@ orr x0, x0, #HFGRTR_EL2_nGCS_EL1_MASK orr x0, x0, #HFGRTR_EL2_nGCS_EL0_MASK =20 + /* Disable traps of GCS instructions at EL1 */ + orr x2, x2, #HFGITR_EL2_nGCSEPP_MASK + orr x2, x2, #HFGITR_EL2_nGCSSTR_EL1_MASK + orr x2, x2, #HFGITR_EL2_nGCSPUSHM_EL1_MASK + .Lskip_gce_fgt_\@: =20 .Lset_fgt_\@: --=20 2.47.3 From nobody Fri Oct 2 07:45:35 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 56905371D02; Mon, 3 Aug 2026 23:13:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785798834; cv=none; b=KHYpRvKOyj0ucSoFIVN/rx4n/afwnEwwmtfG6rchCjJ1EvaNPsIPfI9YCZ9KnaQkY4QsRgpTRDcQgzzbAzvuw1ybmhUytpeLMpaEV7TNAuytKMUYTzFyc82tWn4LYIjIAeRerHkK1MoBQwmx76hTfsEt+aramIBUmwPCz0Cn2SM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785798834; c=relaxed/simple; bh=cmvAQBxB4SuCRvDZjmRe7yIsmwDDWXuwPP1P7cDHpHg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=k8kVN5qqvEQ1BzN93yP127Bvcaa1f2mNMi60KWGxmJJztrAJdzAQWUl4BblZPoafM/ouwHuRjqnUwGxpnB5ib+XaDcJgFbZH9dJfk+mbEZe1xVLxfYa8Kj7Qa91euJvL62TeRbD+ll1xsQiFxRGZOFBFoEHTgznHpqPd5sduIVY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=n1B1ZB7N; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="n1B1ZB7N" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8F49A1F00A3A; Mon, 3 Aug 2026 23:13:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1785798831; bh=YWlLd/PWbYINVwpXcYMDnYu5TnVLNXcprwUMzPtexF8=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=n1B1ZB7NZk/zoYIXJLELhvaOM9ee9r5LVdnVLFMQMZsrlnvmIdWA+QekBRoe3mAld wP8pfbEDj80MlaUqf7PJI5to074itwnVO+jFmV0VJrRF06BnHYy1VH2v0Zq2JHYW11 VB9d352PsFVMr74/vovZl17L9KshF7Wd/TuxDLQ2c5ur2To0jmdIMYMeuDKp+uRtWV zBXoGsy1zV0hu5UDplg/4twF1AI2CUGde8uqEUHTUUPV6sGINervfzYzN71HSqITe5 T/KEUrGie3wI1HZ71MxeNFGXkjyN4d6LOhVP0CX1jx5x9/KNA291EAt6LqEtDWPOhq 7bReHO3mfm8ig== From: Mark Brown Date: Mon, 03 Aug 2026 23:56:47 +0100 Subject: [PATCH v18 02/14] KVM: arm64: Fix FGT mapping for HFGITR_EL2.nGCSEPP Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260803-arm64-gcs-v18-2-fd8c40f5ad88@kernel.org> References: <20260803-arm64-gcs-v18-0-fd8c40f5ad88@kernel.org> In-Reply-To: <20260803-arm64-gcs-v18-0-fd8c40f5ad88@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Joey Gouly , Suzuki K Poulose , Shuah Khan , Fuad Tabba , Oliver Upton Cc: Peter Maydell , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=1184; i=broonie@kernel.org; h=from:subject:message-id; bh=cmvAQBxB4SuCRvDZjmRe7yIsmwDDWXuwPP1P7cDHpHg=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqcSCbkagjMfsbLEpGUmar5p5Ty1V7CBLnEKnXQ ra30SaQdMOJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCanEgmwAKCRAk1otyXVSH 0PAhB/9mBKlZ9sVJgzTIjaFaUlLo2gm1JQgfsLOHRI6C9ty/0BN1X7qgdk6ZxWd3wzBBIPCYqrj IkzEXO5sLn18xJK+vWZxGakaHibAVq8z/fDea75/tAKJyMW3jK1i5Ypo218kwnr7TMA9crMVpV2 x2H8Hxj9pFwJyoOrDU22vdQnfjMB8UhlTesrZaTvGn4IkKzHKGizQQ241EoRZz4o+vMsJ//EDsH ffcB2O+ppdot5+e/1l9sbdToya2Chjq0TTMyvSEJMMmqL/iJVNqPXLQmx8qpA0ni6iciKzN4+cN YTh1cd8OWdeVI7abMF8P7TUTR51VzLQa0mcGkLjbzWt6ViL+ X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB The encoding to trap mapping currently maps a FGT on OP_GCSPOPX to HFGITR_EL2.nGCSEPP but as per DDI0601 2026-06 this FGT controls trapping of GCSPUSHX and GCSPOPCX, and not the separate GCSPOPX instruction. Update the mapping to reflect the architecture. Fixes: 863ac38984a82 ("KVM: arm64: Add missing HFGITR_EL2 FGT entries to ne= sted virt") Signed-off-by: Mark Brown --- arch/arm64/kvm/emulate-nested.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-neste= d.c index 3c82f392845d..b32742d9dd73 100644 --- a/arch/arm64/kvm/emulate-nested.c +++ b/arch/arm64/kvm/emulate-nested.c @@ -1432,7 +1432,7 @@ static const struct encoding_to_trap_config encoding_= to_fgt[] __initconst =3D { SR_FGT(OP_AT_S1E1A, HFGITR, ATS1E1A, 1), SR_FGT(OP_COSP_RCTX, HFGITR, COSPRCTX, 1), SR_FGT(OP_GCSPUSHX, HFGITR, nGCSEPP, 0), - SR_FGT(OP_GCSPOPX, HFGITR, nGCSEPP, 0), + SR_FGT(OP_GCSPOPCX, HFGITR, nGCSEPP, 0), SR_FGT(OP_GCSPUSHM, HFGITR, nGCSPUSHM_EL1, 0), SR_FGT(OP_BRB_IALL, HFGITR, nBRBIALL, 0), SR_FGT(OP_BRB_INJ, HFGITR, nBRBINJ, 0), --=20 2.47.3 From nobody Fri Oct 2 07:45:35 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C618637882E; Mon, 3 Aug 2026 23:13:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785798838; cv=none; b=n7o7z2+byeeCsi2ME8dykSanuSql+QwlYDd+ByDyGp5e/CJQIYPb//5lL+RLS4g3VwQrJhRYYsWaTcdPbS3NgiEroESWthje+Di5x79rM9bP3zXjemW9Ty2uSTOvNI0G1wPMj7huODM5uJYKT4K28LJrhJhrSffM4mlteYh5muA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785798838; c=relaxed/simple; bh=NdLP1VKUTKphBm8suHoAvrHrkIlKFHR/bT2XY3QxNuY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=tWxGDtl3wwyUhGl4LC2bAMKpV93kUI7AwHfg5TRiSth9aUie0LIWRGfZo7XI8xDNGzK4Yow5cXkL2vzxsrDvHToUqlQT/4m895byGnhtw+vNjIJ8ojzUxJgx+FpZoGDAFgd3B7hmHpByiKtui0F4bwAspPOECe+sWXYzJaAMswA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=S7kb2514; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="S7kb2514" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B7F341F00A3D; Mon, 3 Aug 2026 23:13:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1785798834; bh=cwJwDWxDGap6PB96rMqBbA8hyXSVukR7/phZa1dgKtE=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=S7kb2514lcPp1aqCYeVqsYK4w9CaTKu3pl0vveZjSuOWAdOZLtR1OjeSMVgXUluNI J5dxPZPqgNRb7Hek3azizCVt5rKvbCAWDRJOazCGPkdaNUJCI5srF2cff12wzjqnbX sALD4/FF6Geflu8rymcRYvHikZ7SarSC867kKhvT+N2TmQ7KpWGDnsoGk/poVFpMvz MLreonJdzbAhQ08C296GnCUVEuDWGYZb1gO3OokX+G3k1aWFmd55/JytlMjI3OsEaf SDDdeXJ1g00EhjxG2lhS3xQeWc5AL7jidrL34BRWutFlCrQMeE+Q/WyFGJCEmc/UKZ ilB0qPvqbBDYA== From: Mark Brown Date: Mon, 03 Aug 2026 23:56:48 +0100 Subject: [PATCH v18 03/14] KVM: arm64: Manage GCS access and registers for guests Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260803-arm64-gcs-v18-3-fd8c40f5ad88@kernel.org> References: <20260803-arm64-gcs-v18-0-fd8c40f5ad88@kernel.org> In-Reply-To: <20260803-arm64-gcs-v18-0-fd8c40f5ad88@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Joey Gouly , Suzuki K Poulose , Shuah Khan , Fuad Tabba , Oliver Upton Cc: Peter Maydell , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=12563; i=broonie@kernel.org; h=from:subject:message-id; bh=NdLP1VKUTKphBm8suHoAvrHrkIlKFHR/bT2XY3QxNuY=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqcSCc7aCHFAF/YvFEKG2yQ9+bcVVzz7BC/rc5B P0MrSLlxS2JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCanEgnAAKCRAk1otyXVSH 0NTQB/9cHzGBOSQhg8tWCX1nbuv46iLjBrd7s3bPokWbWnZCi6jpl4Lu199ieJEYiMRnrAS9hvG +f4iPksp/fmCVoCtzCTMyv2TxsYjyT5syxITseguM7nFCnHxScQQ/Ok+v6xLlTV+UivMc+KjTqa 5jvY4vx1baJw670M9j7xFXUZp2Wwk1hMRUdH0KJUfL18Uxy6/pqcMin3+mcS5ng2Qp0eTMS1vV/ 6YWCvUuwm2cSsPXQFYcmlRjYOapo+yEKXUAv2OpT5w9YTituYqIckQeD42QgsDb9Uws8V9v/iCt YDzujY8MGrDbAqj/XoEYZyktJGHutFdhyssxo9Pf1m0KcHt+ X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB GCS introduces a number of system registers, on systems with GCS we need to context switch them and expose them to VMMs to allow guests to use GCS. In order to allow guests to use GCS we also need to configure HCRX_EL2.GCSEn, if this is not set GCS instructions will be noops and CHKFEAT will report GCS as disabled. Signed-off-by: Mark Brown --- arch/arm64/include/asm/kvm_emulate.h | 3 +++ arch/arm64/include/asm/kvm_host.h | 14 ++++++++++ arch/arm64/include/asm/vncr_mapping.h | 2 ++ arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h | 31 ++++++++++++++++++++++ arch/arm64/kvm/hyp/vhe/sysreg-sr.c | 10 +++++++ arch/arm64/kvm/sys_regs.c | 42 ++++++++++++++++++++++++++= ++++ 6 files changed, 102 insertions(+) diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/= kvm_emulate.h index 5bf3d7e1d92c..ee774c3b8dcd 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -686,6 +686,9 @@ static inline void vcpu_set_hcrx(struct kvm_vcpu *vcpu) =20 if (kvm_has_feat(kvm, ID_AA64ISAR1_EL1, LS64, LS64_V)) vcpu->arch.hcrx_el2 |=3D HCRX_EL2_EnASR; + + if (kvm_has_gcs(kvm)) + vcpu->arch.hcrx_el2 |=3D HCRX_EL2_GCSEn; } } #endif /* __ARM64_KVM_EMULATE_H__ */ diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index bae2c4f92ef5..1f0da8988961 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -497,6 +497,10 @@ enum vcpu_sysreg { =20 POR_EL0, /* Permission Overlay Register 0 (EL0) */ =20 + /* Guarded Control Stack registers */ + GCSCRE0_EL1, /* Guarded Control Stack Control (EL0) */ + GCSPR_EL0, /* Guarded Control Stack Pointer (EL0) */ + /* FP/SIMD/SVE */ SVCR, FPMR, @@ -517,6 +521,8 @@ enum vcpu_sysreg { PIRE0_EL2, /* Permission Indirection Register 0 (EL2) */ PIR_EL2, /* Permission Indirection Register 1 (EL2) */ POR_EL2, /* Permission Overlay Register 2 (EL2) */ + GCSCR_EL2, /* Guarded Control Stack Control Register (EL2) */ + GCSPR_EL2, /* Guarded Control Stack Pointer Register (EL2) */ SPSR_EL2, /* EL2 saved program status register */ ELR_EL2, /* EL2 exception link register */ AFSR0_EL2, /* Auxiliary Fault Status Register 0 (EL2) */ @@ -588,6 +594,10 @@ enum vcpu_sysreg { VNCR(VDISR_EL2), VNCR(VSESR_EL2), =20 + /* Guarded Control Stack registers */ + VNCR(GCSPR_EL1), /* Guarded Control Stack Pointer (EL1) */ + VNCR(GCSCR_EL1), /* Guarded Control Stack Control (EL1) */ + VNCR(HFGRTR_EL2), VNCR(HFGWTR_EL2), VNCR(HFGITR_EL2), @@ -1648,6 +1658,10 @@ void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64= val); #define kvm_has_sctlr2(k) \ (kvm_has_feat((k), ID_AA64MMFR3_EL1, SCTLRX, IMP)) =20 +#define kvm_has_gcs(k) \ + (system_supports_gcs() && \ + kvm_has_feat((k), ID_AA64PFR1_EL1, GCS, IMP)) + static inline bool kvm_arch_has_irq_bypass(void) { return true; diff --git a/arch/arm64/include/asm/vncr_mapping.h b/arch/arm64/include/asm= /vncr_mapping.h index 14366d35ce82..b260008c5e3e 100644 --- a/arch/arm64/include/asm/vncr_mapping.h +++ b/arch/arm64/include/asm/vncr_mapping.h @@ -97,6 +97,8 @@ #define VNCR_PMSNEVFR_EL1 0x850 #define VNCR_PMSDSFR_EL1 0x858 #define VNCR_TRFCR_EL1 0x880 +#define VNCR_GCSPR_EL1 0x8C0 +#define VNCR_GCSCR_EL1 0x8D0 #define VNCR_MPAM1_EL1 0x900 #define VNCR_MPAMHCR_EL2 0x930 #define VNCR_MPAMVPMV_EL2 0x938 diff --git a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h b/arch/arm64/kvm/hy= p/include/hyp/sysreg-sr.h index a17cbe7582de..053d7b3c5104 100644 --- a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h +++ b/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h @@ -17,6 +17,7 @@ #include =20 static inline bool ctxt_has_s1poe(struct kvm_cpu_context *ctxt); +static inline bool ctxt_has_gcs(struct kvm_cpu_context *ctxt); =20 static inline struct kvm_vcpu *ctxt_to_vcpu(struct kvm_cpu_context *ctxt) { @@ -67,6 +68,11 @@ static inline void __sysreg_save_user_state(struct kvm_c= pu_context *ctxt) { ctxt_sys_reg(ctxt, TPIDR_EL0) =3D read_sysreg(tpidr_el0); ctxt_sys_reg(ctxt, TPIDRRO_EL0) =3D read_sysreg(tpidrro_el0); + + if (ctxt_has_gcs(ctxt)) { + ctxt_sys_reg(ctxt, GCSPR_EL0) =3D read_sysreg_s(SYS_GCSPR_EL0); + ctxt_sys_reg(ctxt, GCSCRE0_EL1) =3D read_sysreg_s(SYS_GCSCRE0_EL1); + } } =20 static inline bool ctxt_has_mte(struct kvm_cpu_context *ctxt) @@ -131,6 +137,17 @@ static inline bool ctxt_has_sctlr2(struct kvm_cpu_cont= ext *ctxt) return kvm_has_sctlr2(kern_hyp_va(vcpu->kvm)); } =20 +static inline bool ctxt_has_gcs(struct kvm_cpu_context *ctxt) +{ + struct kvm_vcpu *vcpu; + + if (!cpus_have_final_cap(ARM64_HAS_GCS)) + return false; + + vcpu =3D ctxt_to_vcpu(ctxt); + return kvm_has_feat(kern_hyp_va(vcpu->kvm), ID_AA64PFR1_EL1, GCS, IMP); +} + static inline void __sysreg_save_el1_state(struct kvm_cpu_context *ctxt) { ctxt_sys_reg(ctxt, SCTLR_EL1) =3D read_sysreg_el1(SYS_SCTLR); @@ -144,6 +161,10 @@ static inline void __sysreg_save_el1_state(struct kvm_= cpu_context *ctxt) if (ctxt_has_s1pie(ctxt)) { ctxt_sys_reg(ctxt, PIR_EL1) =3D read_sysreg_el1(SYS_PIR); ctxt_sys_reg(ctxt, PIRE0_EL1) =3D read_sysreg_el1(SYS_PIRE0); + if (ctxt_has_gcs(ctxt)) { + ctxt_sys_reg(ctxt, GCSPR_EL1) =3D read_sysreg_el1(SYS_GCSPR); + ctxt_sys_reg(ctxt, GCSCR_EL1) =3D read_sysreg_el1(SYS_GCSCR); + } } =20 if (ctxt_has_s1poe(ctxt)) @@ -206,6 +227,11 @@ static inline void __sysreg_restore_user_state(struct = kvm_cpu_context *ctxt) { write_sysreg(ctxt_sys_reg(ctxt, TPIDR_EL0), tpidr_el0); write_sysreg(ctxt_sys_reg(ctxt, TPIDRRO_EL0), tpidrro_el0); + if (ctxt_has_gcs(ctxt)) { + write_sysreg_s(ctxt_sys_reg(ctxt, GCSPR_EL0), SYS_GCSPR_EL0); + write_sysreg_s(ctxt_sys_reg(ctxt, GCSCRE0_EL1), + SYS_GCSCRE0_EL1); + } } =20 static inline void __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt, @@ -239,6 +265,11 @@ static inline void __sysreg_restore_el1_state(struct k= vm_cpu_context *ctxt, if (ctxt_has_s1pie(ctxt)) { write_sysreg_el1(ctxt_sys_reg(ctxt, PIR_EL1), SYS_PIR); write_sysreg_el1(ctxt_sys_reg(ctxt, PIRE0_EL1), SYS_PIRE0); + + if (ctxt_has_gcs(ctxt)) { + write_sysreg_el1(ctxt_sys_reg(ctxt, GCSPR_EL1), SYS_GCSPR); + write_sysreg_el1(ctxt_sys_reg(ctxt, GCSCR_EL1), SYS_GCSCR); + } } =20 if (ctxt_has_s1poe(ctxt)) diff --git a/arch/arm64/kvm/hyp/vhe/sysreg-sr.c b/arch/arm64/kvm/hyp/vhe/sy= sreg-sr.c index be685b63e8cf..2431c18f5792 100644 --- a/arch/arm64/kvm/hyp/vhe/sysreg-sr.c +++ b/arch/arm64/kvm/hyp/vhe/sysreg-sr.c @@ -61,6 +61,9 @@ static void __sysreg_save_vel2_state(struct kvm_vcpu *vcp= u) =20 if (ctxt_has_s1poe(&vcpu->arch.ctxt)) __vcpu_assign_sys_reg(vcpu, POR_EL2, read_sysreg_el1(SYS_POR)); + + if (ctxt_has_gcs(&vcpu->arch.ctxt)) + __vcpu_assign_sys_reg(vcpu, GCSCR_EL2, read_sysreg_el1(SYS_GCSCR)); } =20 /* @@ -77,6 +80,8 @@ static void __sysreg_save_vel2_state(struct kvm_vcpu *vcp= u) __vcpu_assign_sys_reg(vcpu, SP_EL2, read_sysreg(sp_el1)); __vcpu_assign_sys_reg(vcpu, ELR_EL2, read_sysreg_el1(SYS_ELR)); __vcpu_assign_sys_reg(vcpu, SPSR_EL2, read_sysreg_el1(SYS_SPSR)); + if (ctxt_has_gcs(&vcpu->arch.ctxt)) + __vcpu_assign_sys_reg(vcpu, GCSPR_EL2, read_sysreg_el1(SYS_GCSPR)); =20 if (ctxt_has_sctlr2(&vcpu->arch.ctxt)) __vcpu_assign_sys_reg(vcpu, SCTLR2_EL2, read_sysreg_el1(SYS_SCTLR2)); @@ -133,6 +138,11 @@ static void __sysreg_restore_vel2_state(struct kvm_vcp= u *vcpu) =20 if (ctxt_has_s1poe(&vcpu->arch.ctxt)) write_sysreg_el1(__vcpu_sys_reg(vcpu, POR_EL2), SYS_POR); + + if (ctxt_has_gcs(&vcpu->arch.ctxt)) { + write_sysreg_el1(__vcpu_sys_reg(vcpu, GCSCR_EL2), SYS_GCSCR); + write_sysreg_el1(__vcpu_sys_reg(vcpu, GCSPR_EL2), SYS_GCSPR); + } } =20 write_sysreg_el1(__vcpu_sys_reg(vcpu, ESR_EL2), SYS_ESR); diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 5d5c579d4579..d18ada283809 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -109,6 +109,10 @@ static enum sr_loc_attr locate_direct_register(const s= truct kvm_vcpu *vcpu, case PIR_EL1: case PIRE0_EL1: case POR_EL1: + case GCSCRE0_EL1: + case GCSPR_EL0: + case GCSCR_EL1: + case GCSPR_EL1: case ESR_EL1: case AFSR0_EL1: case AFSR1_EL1: @@ -200,6 +204,8 @@ static void locate_register(const struct kvm_vcpu *vcpu= , enum vcpu_sysreg reg, MAPPED_EL2_SYSREG(PIR_EL2, PIR_EL1, NULL ); MAPPED_EL2_SYSREG(PIRE0_EL2, PIRE0_EL1, NULL ); MAPPED_EL2_SYSREG(POR_EL2, POR_EL1, NULL ); + MAPPED_EL2_SYSREG(GCSCR_EL2, GCSCR_EL1, NULL ); + MAPPED_EL2_SYSREG(GCSPR_EL2, GCSPR_EL1, NULL ); MAPPED_EL2_SYSREG(AMAIR_EL2, AMAIR_EL1, NULL ); MAPPED_EL2_SYSREG(ELR_EL2, ELR_EL1, NULL ); MAPPED_EL2_SYSREG(SPSR_EL2, SPSR_EL1, NULL ); @@ -228,6 +234,10 @@ static u64 read_sr_from_cpu(enum vcpu_sysreg reg) case TCR2_EL1: val =3D read_sysreg_s(SYS_TCR2_EL12); break; case PIR_EL1: val =3D read_sysreg_s(SYS_PIR_EL12); break; case PIRE0_EL1: val =3D read_sysreg_s(SYS_PIRE0_EL12); break; + case GCSPR_EL0: val =3D read_sysreg_s(SYS_GCSPR_EL0); break; + case GCSCRE0_EL1: val =3D read_sysreg_s(SYS_GCSCRE0_EL1); break; + case GCSCR_EL1: val =3D read_sysreg_s(SYS_GCSCR_EL12); break; + case GCSPR_EL1: val =3D read_sysreg_s(SYS_GCSPR_EL12); break; case POR_EL1: val =3D read_sysreg_s(SYS_POR_EL12); break; case ESR_EL1: val =3D read_sysreg_s(SYS_ESR_EL12); break; case AFSR0_EL1: val =3D read_sysreg_s(SYS_AFSR0_EL12); break; @@ -267,6 +277,10 @@ static void write_sr_to_cpu(enum vcpu_sysreg reg, u64 = val) case PIR_EL1: write_sysreg_s(val, SYS_PIR_EL12); break; case PIRE0_EL1: write_sysreg_s(val, SYS_PIRE0_EL12); break; case POR_EL1: write_sysreg_s(val, SYS_POR_EL12); break; + case GCSCRE0_EL1: write_sysreg_s(val, SYS_GCSCRE0_EL1); break; + case GCSPR_EL0: write_sysreg_s(val, SYS_GCSPR_EL0); break; + case GCSCR_EL1: write_sysreg_s(val, SYS_GCSCR_EL12); break; + case GCSPR_EL1: write_sysreg_s(val, SYS_GCSPR_EL12); break; case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break; case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break; case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break; @@ -2995,6 +3009,21 @@ static unsigned int cnthv_visibility(const struct kv= m_vcpu *vcpu, return REG_HIDDEN; } =20 +static unsigned int gcs_visibility(const struct kvm_vcpu *vcpu, + const struct sys_reg_desc *r) +{ + if (kvm_has_gcs(vcpu->kvm)) + return 0; + + return REG_HIDDEN; +} + +static unsigned int gcs_el2_visibility(const struct kvm_vcpu *vcpu, + const struct sys_reg_desc *rd) +{ + return __el2_visibility(vcpu, rd, gcs_visibility); +} + static bool access_mdcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) @@ -3399,6 +3428,13 @@ static const struct sys_reg_desc sys_reg_descs[] =3D= { PTRAUTH_KEY(APDB), PTRAUTH_KEY(APGA), =20 + { SYS_DESC(SYS_GCSCR_EL1), NULL, reset_val, GCSCR_EL1, 0, + .visibility =3D gcs_visibility }, + { SYS_DESC(SYS_GCSPR_EL1), NULL, reset_unknown, GCSPR_EL1, + .visibility =3D gcs_visibility }, + { SYS_DESC(SYS_GCSCRE0_EL1), NULL, reset_val, GCSCRE0_EL1, 0, + .visibility =3D gcs_visibility }, + { SYS_DESC(SYS_SPSR_EL1), access_spsr}, { SYS_DESC(SYS_ELR_EL1), access_elr}, =20 @@ -3523,6 +3559,8 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { CTR_EL0_DminLine_MASK | CTR_EL0_L1Ip_MASK | CTR_EL0_IminLine_MASK), + { SYS_DESC(SYS_GCSPR_EL0), NULL, reset_unknown, GCSPR_EL0, + .visibility =3D gcs_visibility }, { SYS_DESC(SYS_SVCR), undef_access, reset_val, SVCR, 0, .visibility =3D s= me_visibility }, { SYS_DESC(SYS_FPMR), undef_access, reset_val, FPMR, 0, .visibility =3D f= p8_visibility }, =20 @@ -3764,6 +3802,10 @@ static const struct sys_reg_desc sys_reg_descs[] =3D= { EL2_REG_FILTERED(VNCR_EL2, bad_vncr_trap, reset_val, 0, vncr_el2_visibility), =20 + EL2_REG_FILTERED(GCSCR_EL2, access_rw, reset_val, 0, + gcs_el2_visibility), + EL2_REG_FILTERED(GCSPR_EL2, access_rw, reset_val, 0, + gcs_el2_visibility), { SYS_DESC(SYS_DACR32_EL2), undef_access, reset_unknown, DACR32_EL2 }, EL2_REG_VNCR_FILT(HDFGRTR2_EL2, fgt2_visibility), EL2_REG_VNCR_FILT(HDFGWTR2_EL2, fgt2_visibility), --=20 2.47.3 From nobody Fri Oct 2 07:45:35 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E90B374178; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260803-arm64-gcs-v18-4-fd8c40f5ad88@kernel.org> References: <20260803-arm64-gcs-v18-0-fd8c40f5ad88@kernel.org> In-Reply-To: <20260803-arm64-gcs-v18-0-fd8c40f5ad88@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Joey Gouly , Suzuki K Poulose , Shuah Khan , Fuad Tabba , Oliver Upton Cc: Peter Maydell , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=2294; i=broonie@kernel.org; h=from:subject:message-id; bh=bEpjQNbOqRXEgxmuuFHddb+wqn5p6+xc/jGJ7dQCByg=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqcSCcvNjLB4tkEjb/xUFQG1hdPElFCuRE4NDXo PbihH5N34mJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCanEgnAAKCRAk1otyXVSH 0OFhB/94zXmoRtkIdaIqQ0+NWyxasfo5LNxSjiS4EmEjobzqgEto+1z7mMO7w7Yguq02tALAYLQ EWuUu6sp+mRa89RJ8KMkWoLzKu6dz5Eyshc3g2V/0yUQOX9WnhU8pwqCaINqdXsdO4xwfMmj1IY AvVVrmIxkQuyu9tC2Od4syd6HG8EdRBosoW7ACdTnsOrgk8SDfusTdlGMqqZuY36YlJ2P7ajeEE Nan/zyd70GGaIBg3yRyK6v4Usc0HmO2y/8miRxbWQEzLvwcYdldXZuLrvokAPvuzht1zgDsl+QZ myqmBEvVh/O9XWzy9fiNfHgIMwm3BLR0AMK7I+Hfdt0cy9Sb X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB In order to allow efficient implementation of GCS implementations are permitted to do GCS specific caching, with barriers implicit in stack switch operations and GCSB DSYNC as an explicit barrier. Since we do not use GCS in the hypervisor or host kernel the hypervisor cannot rely on any barriers being present in vCPU context switches other than those it explicitly inserts. Add explicit barriers when loading and saving vCPU state. Signed-off-by: Mark Brown Reviewed-by: Yuan Yao --- arch/arm64/kvm/hyp/nvhe/switch.c | 13 +++++++++++++ arch/arm64/kvm/hyp/vhe/sysreg-sr.c | 14 ++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/arch/arm64/kvm/hyp/nvhe/switch.c b/arch/arm64/kvm/hyp/nvhe/swi= tch.c index 7318e3e6a5f3..fe8727bf2833 100644 --- a/arch/arm64/kvm/hyp/nvhe/switch.c +++ b/arch/arm64/kvm/hyp/nvhe/switch.c @@ -301,6 +301,12 @@ int __kvm_vcpu_run(struct kvm_vcpu *vcpu) */ dsb(nsh); =20 + /* + * Ensure any GCS memory effects are visible to this CPU. + */ + if (ctxt_has_gcs(guest_ctxt)) + gcsb_dsync(); + __kvm_adjust_pc(vcpu); =20 /* @@ -345,6 +351,13 @@ int __kvm_vcpu_run(struct kvm_vcpu *vcpu) */ dsb(nsh); =20 + /* + * Ensure any GCS memory effects from the outgoing vCPU are + * visible elsewhere. + */ + if (ctxt_has_gcs(guest_ctxt)) + gcsb_dsync(); + __deactivate_traps(vcpu); __load_host_stage2(); =20 diff --git a/arch/arm64/kvm/hyp/vhe/sysreg-sr.c b/arch/arm64/kvm/hyp/vhe/sy= sreg-sr.c index 2431c18f5792..4594992b008c 100644 --- a/arch/arm64/kvm/hyp/vhe/sysreg-sr.c +++ b/arch/arm64/kvm/hyp/vhe/sysreg-sr.c @@ -239,6 +239,13 @@ void __vcpu_load_switch_sysregs(struct kvm_vcpu *vcpu) if (vcpu_has_nv(vcpu)) dsb(nsh); =20 + /* + * Ensure any GCS memory effects are visible to the incoming + * vCPU. + */ + if (ctxt_has_gcs(guest_ctxt)) + gcsb_dsync(); + /* * Load guest EL1 and user state * @@ -299,5 +306,12 @@ void __vcpu_put_switch_sysregs(struct kvm_vcpu *vcpu) /* Restore host user state */ __sysreg_restore_user_state(host_ctxt); =20 + /* + * Ensure any GCS memory effects from the outgoing vCPU are + * visible elsewhere. + */ + if (ctxt_has_gcs(guest_ctxt)) + gcsb_dsync(); + vcpu_clear_flag(vcpu, SYSREGS_ON_CPU); } --=20 2.47.3 From nobody Fri Oct 2 07:45:35 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F2DD4378D7D; Mon, 3 Aug 2026 23:14:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Mon, 3 Aug 2026 23:13:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1785798840; bh=2SztSUpbsqfIgO005x2FPAmHBQNw5E5n0LUq/NdA0HU=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=QOd1UUAuA0wysoBcq8FqfSKC2Se2YLbkKhOEL08FZ85CrNr8EC2g9zfYT8Vtj+Ex6 oop1fwUYFrKHlMu+5rqGa8PBnl4PhrEijse4ombi7g6Z1i9NNvT8maELylZqzUsb48 1jUXul74YiNI+c49SnP3h0ZFuxhp4T2JAsAqdX2XuLIUo1cZGVQ/Cs84o9aWBGfMNa FWysRxBGeWMed3mpMIM4wUGNu7VeWrBuDayjeOfA5TOevxi4MAVS8/y12LmzrCS421 CP5z+T38fjAwKALoX8d1H6kpo8ub+7WbqUkSltwBgaOxXmtnAk/yitV4v62KVDaaaZ 92uHFTxv/w1Sw== From: Mark Brown Date: Mon, 03 Aug 2026 23:56:50 +0100 Subject: [PATCH v18 05/14] KVM: arm64: Set PSTATE.EXLOCK when entering an exception Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260803-arm64-gcs-v18-5-fd8c40f5ad88@kernel.org> References: <20260803-arm64-gcs-v18-0-fd8c40f5ad88@kernel.org> In-Reply-To: <20260803-arm64-gcs-v18-0-fd8c40f5ad88@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Joey Gouly , Suzuki K Poulose , Shuah Khan , Fuad Tabba , Oliver Upton Cc: Peter Maydell , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=2696; i=broonie@kernel.org; h=from:subject:message-id; bh=rvtRV62usxvYDabRiDuT5QzOKER095ZOoLBRwH9Xwsc=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqcSCd6PEHl3QFHLPPxtobM1uSd2n0Wo8YAbYo7 O5LFRktw0aJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCanEgnQAKCRAk1otyXVSH 0HK/B/0aeWDR87DHcNDUqhWkFohvbpfdwxSXXg9pT4seEAp2+Szhs3jmJyiv9iVpmFbxKRHkjGq ktTIQ+HtgP1TV7PzQJ4qimkqDl1DWuvQVrNcv5nxsbLnRYuGxCyDBwagBag/23J1Yn+OcAEr0SM UqZsxgnPj6fn+CtgGbmrvhnglCbu66Kw1lN+7AwUYkJxhFyAQQGJvDpwHeUwt1FFkKL4XjrSQRy Tev05VETk7uLLZfziD7sFKio8tQzz4CjesIad65cZtN2FFUTm6cFXheiBcdBk7grUjf5Dse4/qV ywLXs9NYEoksIwYZMQskGDcPBjYqsekSJSKCg39220B7V3G8 X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB As per DDI 0487 R_WTXBY we need to manage PSTATE.EXLOCK when entering an exception, when the exception is entered from a lower EL the bit is cleared while if entering from the same EL it is set to GCSCR_ELx.EXLOCKEN. Implement this behaviour in enter_exception64(). Signed-off-by: Mark Brown Reviewed-by: Yuan Yao --- arch/arm64/include/uapi/asm/ptrace.h | 1 + arch/arm64/kvm/hyp/exception.c | 37 ++++++++++++++++++++++++++++++++= ++++ 2 files changed, 38 insertions(+) diff --git a/arch/arm64/include/uapi/asm/ptrace.h b/arch/arm64/include/uapi= /asm/ptrace.h index 6fed93fb2536..6113b9f9771b 100644 --- a/arch/arm64/include/uapi/asm/ptrace.h +++ b/arch/arm64/include/uapi/asm/ptrace.h @@ -56,6 +56,7 @@ #define PSR_C_BIT 0x20000000 #define PSR_Z_BIT 0x40000000 #define PSR_N_BIT 0x80000000 +#define PSR_EXLOCK_BIT 0x400000000 =20 #define PSR_BTYPE_SHIFT 10 =20 diff --git a/arch/arm64/kvm/hyp/exception.c b/arch/arm64/kvm/hyp/exception.c index bef40ddb16db..15b00e0ee1ec 100644 --- a/arch/arm64/kvm/hyp/exception.c +++ b/arch/arm64/kvm/hyp/exception.c @@ -65,6 +65,38 @@ static void __vcpu_write_spsr_und(struct kvm_vcpu *vcpu,= u64 val) vcpu->arch.ctxt.spsr_und =3D val; } =20 +static unsigned long compute_exlock(struct kvm_vcpu *vcpu, + unsigned long mode, + unsigned long target_mode) +{ + u64 gcscr; + + if (!kvm_has_gcs(kern_hyp_va(vcpu->kvm))) + return 0; + + /* GCS can't be enabled for 32 bit */ + if (mode & PSR_MODE32_BIT) + return 0; + + /* When taking an exception to a higher EL EXLOCK is cleared. */ + if ((mode | PSR_MODE_THREAD_BIT) !=3D target_mode) + return 0; + + /* + * When taking an exception to the same EL EXLOCK is set to + * the effective value of GCSR_ELx.EXLOCKEN. + */ + if (is_hyp_ctxt(vcpu)) + gcscr =3D __vcpu_read_sys_reg(vcpu, GCSCR_EL2); + else + gcscr =3D __vcpu_read_sys_reg(vcpu, GCSCR_EL1); + + if (gcscr & GCSCR_ELx_EXLOCKEN) + return PSR_EXLOCK_BIT; + + return 0; +} + /* * This performs the exception entry at a given EL (@target_mode), stashin= g PC * and PSTATE into ELR and SPSR respectively, and compute the new PC/PSTAT= E. @@ -154,6 +186,11 @@ static void enter_exception64(struct kvm_vcpu *vcpu, u= nsigned long target_mode, // PSTATE.BTYPE is set to zero upon any exception to AArch64 // See ARM DDI 0487E.a, pages D1-2293 to D1-2294. =20 + // PSTATE.EXLOCK is set to 0 upon any exception to a higher + // EL, or to GCSCR_ELx.EXLOCKEN for an exception to the same + // exception level. See ARM DDI 0487 R_WTXBY. + new |=3D compute_exlock(vcpu, mode, target_mode); + new |=3D PSR_D_BIT; new |=3D PSR_A_BIT; new |=3D PSR_I_BIT; --=20 2.47.3 From nobody Fri Oct 2 07:45:35 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 38BD437C108; Mon, 3 Aug 2026 23:14:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785798849; cv=none; b=Iz7WUmuTDlpWVidIghcUtCeq6ZPtMa8M4qQdFOOOqB4NNHtvQkgRX/Tl1uQNbtRTwSiFUPvZGSdFpNRp/xLwBMV7IjjfF4QX6HKivJGiK2pSZjlnvn4yVEhCPs9/7e+2ZuZU9emmESIzlWetlEO+O/yhbqs9r4SwO9Sr29/ajg8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785798849; c=relaxed/simple; bh=ZU9mNb8TUUW8fTZnFvfc37aP+mNNUc8as/YCprUO5Nc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=dJOV9wS6LdyE88HzG0qPTY9Gq6rFlgaIe8VO60NrnMX36Z7rip0mVYjHoGyUpZUO6lHR7+f+WrBmlxwkS2h1MyRpdQuvyGoTDjwso7pIUnxe15Tsw1lvRQ88prTR+dbwEKWQ4mZvxaIFDtDz5uqwbiJio8/fyoedsa1pD0BYLco= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TtI1EZ45; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TtI1EZ45" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4A7131F00A3A; Mon, 3 Aug 2026 23:14:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1785798844; bh=DulmpQOh2UwOXi3qlin3hjgVoAUJhkyK/puVXl2lmtE=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=TtI1EZ454Sle8DrWdHjlktGs9gAblCXWealtta2X8IbB91P/T42f1lQ3fq2R4mYgw aRRJsN8OXhIlr5md9kgI6JfRM3kAbH7I0C9SiWAyDDlS4nvK79glHA9yTkj0IQjXWr os6jo9pJB7yBwch5z1ioURE3S2GxeKMKz6F08jvonnpgu8C9ZP+lk5KecJpK4ib642 3sNkr2cyG/6Wp/YXnaNAExT/FUqlJ9XtpCtZapUVZYzo8cCCp6M/Lu37EN4xKtGUYz k8fijf3wpWNLkUG1xUAolOZt/WHEEwIQjCWppSbFP2tScsuCaBqEDT59MIanAQGgM8 3ydWb1H8WF9yg== From: Mark Brown Date: Mon, 03 Aug 2026 23:56:51 +0100 Subject: [PATCH v18 06/14] KVM: arm64: Validate GCS exception lock when emulating ERET Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260803-arm64-gcs-v18-6-fd8c40f5ad88@kernel.org> References: <20260803-arm64-gcs-v18-0-fd8c40f5ad88@kernel.org> In-Reply-To: <20260803-arm64-gcs-v18-0-fd8c40f5ad88@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Joey Gouly , Suzuki K Poulose , Shuah Khan , Fuad Tabba , Oliver Upton Cc: Peter Maydell , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=3924; i=broonie@kernel.org; h=from:subject:message-id; bh=ZU9mNb8TUUW8fTZnFvfc37aP+mNNUc8as/YCprUO5Nc=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqcSCe9LWKDOOy/w6LJ24GOuVZrMRkAuvQyfwya ZQ8U/jQ2reJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCanEgngAKCRAk1otyXVSH 0IR/CACDgp9eOXL4EhgWzixMCUIIWislVrhGoffwqK+a5vQQ/C8FKJvk/vKbto4Idh0/T/rgGFu au755xtVWtMpnDPoxIX6lNcSe7KtiAw9Ug9tEYjVV9U1lD6a0G1fFrzYi/8MkocoUKGJEWoN/OL lzlZN/EXewoWiF0BfkKOgHtZTyYFg8TxjyJgEAN9PYMLXPflCncWoLDARsS4nTq5JsjfniYxbAm Ev9uJ/njyH6KkGm7kWU5AHxcU7hfDf5CDPUcxZHv/o2ps3VfcHFiTENyUkmGJBmW9yJkVWWWPFQ DblgDA7yLD1f/kzbNyMzlKfio3t+DkxCve5YvAe9ZwP4j4h8 X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB As per DDI0487 R_TYTWB GCS adds an additional case where an illegal exception return can be generated. If all of: - PSTATE.EXLOCK is 0. - The EL is not being changed by the ERET. - GCSCR_ELx.EXLOCKEN is 1. are true then the return is illegal. Emulate this behaviour when emulating ERET for nested guests, while we're at it using the symbolic definition for EXLOCK in SPSR. Signed-off-by: Mark Brown --- arch/arm64/include/asm/kvm_nested.h | 39 +++++++++++++++++++++++++++++++++= ++++ arch/arm64/kvm/emulate-nested.c | 5 ++++- arch/arm64/kvm/hyp/vhe/switch.c | 4 ++++ 3 files changed, 47 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/kvm_nested.h b/arch/arm64/include/asm/k= vm_nested.h index 012d711034d1..b2343f67d15b 100644 --- a/arch/arm64/include/asm/kvm_nested.h +++ b/arch/arm64/include/asm/kvm_nested.h @@ -240,6 +240,45 @@ static inline bool kvm_auth_eretax(struct kvm_vcpu *vc= pu, u64 *elr) } #endif =20 +#ifdef CONFIG_ARM64_GCS +/* + * A subset of the pseudocode ELFromSPSR(), validity checks are + * assumed to have been done in code that is not GCS specific. + */ +static inline int exlock_el_from_spsr(u64 spsr) +{ + return FIELD_GET(GENMASK(3, 2), spsr); +} + +/* See IllegalExceptionReturn() pseudocode */ +static inline bool kvm_check_illegal_exlock_return(struct kvm_vcpu *vcpu, + u64 spsr) +{ + u64 cur_el, target_el; + + if (!kvm_has_gcs(vcpu->kvm)) + return false; + + if (vcpu->arch.ctxt.regs.pstate & PSR_EXLOCK_BIT) + return false; + + cur_el =3D exlock_el_from_spsr(vcpu->arch.ctxt.regs.pstate); + target_el =3D exlock_el_from_spsr(spsr); + + if (cur_el !=3D target_el) + return false; + + return read_sysreg_el1(SYS_GCSCR) & GCSCR_ELx_EXLOCKEN; +} + +#else +static inline bool kvm_check_illegal_exlock_return(struct kvm_vcpu *vcpu, + u64 spsr) +{ + return false; +} +#endif + #define KVM_NV_GUEST_MAP_SZ (KVM_PGTABLE_PROT_SW1 | KVM_PGTABLE_PROT_SW0) =20 static inline u64 kvm_encode_nested_level(struct kvm_s2_trans *trans) diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-neste= d.c index b32742d9dd73..0f0723f22000 100644 --- a/arch/arm64/kvm/emulate-nested.c +++ b/arch/arm64/kvm/emulate-nested.c @@ -2740,10 +2740,13 @@ static u64 kvm_check_illegal_exception_return(struc= t kvm_vcpu *vcpu, u64 spsr) * - trying to return to an illegal M value * - trying to return to a 32bit EL * - trying to return to EL1 with HCR_EL2.TGE set + * - GCSCR_ELx.EXLOCKEN is 1 and PSTATE.EXLOCK is 0 when attempting + * to return from ELx the same EL. */ if (mode =3D=3D PSR_MODE_EL3t || mode =3D=3D PSR_MODE_EL3h || mode =3D=3D 0b00001 || (mode & BIT(1)) || (spsr & PSR_MODE32_BIT) || + kvm_check_illegal_exlock_return(vcpu, spsr) || (vcpu_el2_tge_is_set(vcpu) && (mode =3D=3D PSR_MODE_EL1t || mode =3D=3D PSR_MODE_EL1h))) { u64 mask; @@ -2770,7 +2773,7 @@ static u64 kvm_check_illegal_exception_return(struct = kvm_vcpu *vcpu, u64 spsr) =20 mask =3D PSR_MODE_MASK | PSR_MODE32_BIT; if (kvm_has_feat(vcpu->kvm, ID_AA64PFR1_EL1, GCS, IMP)) - mask |=3D BIT_ULL(34); /* PSTATE.EXLOCK */ + mask |=3D PSR_EXLOCK_BIT; =20 spsr |=3D *vcpu_cpsr(vcpu) & mask; spsr |=3D PSR_IL_BIT; diff --git a/arch/arm64/kvm/hyp/vhe/switch.c b/arch/arm64/kvm/hyp/vhe/switc= h.c index bbe9cebd3d9d..e09d9a425689 100644 --- a/arch/arm64/kvm/hyp/vhe/switch.c +++ b/arch/arm64/kvm/hyp/vhe/switch.c @@ -371,6 +371,10 @@ static bool kvm_hyp_handle_eret(struct kvm_vcpu *vcpu,= u64 *exit_code) return false; } =20 + /* Push GCS exception lock failures into the slow path */ + if (kvm_check_illegal_exlock_return(vcpu, spsr)) + return false; + /* If ERETAx fails, take the slow path */ if (esr_iss_is_eretax(esr)) { if (!(vcpu_has_ptrauth(vcpu) && kvm_auth_eretax(vcpu, &elr))) --=20 2.47.3 From nobody Fri Oct 2 07:45:35 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 04D7C37DAD5; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260803-arm64-gcs-v18-7-fd8c40f5ad88@kernel.org> References: <20260803-arm64-gcs-v18-0-fd8c40f5ad88@kernel.org> In-Reply-To: <20260803-arm64-gcs-v18-0-fd8c40f5ad88@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Joey Gouly , Suzuki K Poulose , Shuah Khan , Fuad Tabba , Oliver Upton Cc: Peter Maydell , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=1286; i=broonie@kernel.org; h=from:subject:message-id; bh=fG68MfhkwRfSg1W6YX0cbN8/yZcNS3S2f4yLKb+2+CU=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqcSCfDFrrJu6EBWatsQlkDL5fLdxzD6q+uZ194 xEX8/bZYV+JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCanEgnwAKCRAk1otyXVSH 0P4eB/9zHfXUwqA3slkhU8zpWiO6oeFu2MR+OB2dN1p5kY4ZG138rVq10mYyWQU8QNQ6v1G0jpW In9wLKEM2acaBUUiCKckWBNkOJOlCGrneiptUyFmVfn5pmNv6S+KztRxd3gnCJODMFvftwMTFh6 FJ3CsmvV5hPa1G1Z5/KttX1zHQ/qsbBPkeNgmfmt1iAzurlgrSIKreSMTByopRgvu56croTYSik FBMaDy/0JcX9R9KdFmT+fV99wDcVF8BDhzFO5Zmz9I9bOuIxMQfmfEh2+0xULOvImlxQb/oPIw0 r05PfCDqy41xH/3wlnenzd6JxGRRauMN+CmPtGqR5toa2jxc X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB For nested guests where HFGITR_EL2.nGCSSTR_EL1 is clear or when there are L2 GCS data check exceptions we need to forward the exception to the guest. Add handling to do so. Signed-off-by: Mark Brown --- arch/arm64/kvm/handle_exit.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c index 54aedf93c78b..63dcc4a0e69a 100644 --- a/arch/arm64/kvm/handle_exit.c +++ b/arch/arm64/kvm/handle_exit.c @@ -304,12 +304,24 @@ static int handle_svc(struct kvm_vcpu *vcpu) return 1; } =20 +/* + * We might get GCS exceptions that need to be forwarded to the + * hypervisor when a nested guest has HFGITR_EL2.nGCSSTR_EL1 clear, or + * for a GCS data check exception for a L2 guest. + */ static int kvm_handle_gcs(struct kvm_vcpu *vcpu) { - /* We don't expect GCS, so treat it with contempt */ - if (kvm_has_feat(vcpu->kvm, ID_AA64PFR1_EL1, GCS, IMP)) - WARN_ON_ONCE(1); + if (!kvm_has_gcs(vcpu->kvm)) { + kvm_inject_undefined(vcpu); + return 1; + } =20 + if (vcpu_has_nv(vcpu)) { + kvm_inject_nested_sync(vcpu, kvm_vcpu_get_esr(vcpu)); + return 1; + } + + WARN_ON_ONCE(1); kvm_inject_undefined(vcpu); return 1; } --=20 2.47.3 From nobody Fri Oct 2 07:45:35 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 892613815E3; Mon, 3 Aug 2026 23:14:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785798854; cv=none; b=hC0jqSHpIv7mh3zIR5pMRD8OSS7VUJrfG8yest2S4gMaKd3j4tdZwH54byoVfSSEncE+r+URafdtIAJT4nDCxMH4hZ1eWsx9F4NqyZ+RV30U6U0cajxf8u4DXOuyD0z6jgI0Nl8aPf95SPBIA8KWABn5V68+/BjtGyhuZtYaU70= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785798854; c=relaxed/simple; bh=dYXTcrQgfnk8FxnmgXg6ADstB4n1DYUswquMHXPAUUY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=dhfWGS+scKEWuQLCm7u7vQnUe1jEtg9YCKAI6s/nN78RZpsoOOcD5I+x0Ke6vu0Ke3yX/p9VbtweudTk8TUGegdvBacs1jWl37nyohlZHgliTOGPAadSPBumwEYIzLxl8R34lFv/zW7sgulyuK0BOaMhMfiRM+3J/fmoD8Z8cxQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ioiICQYp; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ioiICQYp" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A8CD21F000E9; Mon, 3 Aug 2026 23:14:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1785798850; bh=zoyq8Inen+VAWRiWz/um6XRtPFDfayF6DG7fxVMTx/o=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=ioiICQYpyvdsUZNRXOM2rAHl31xYTBontCQMRP1yN9JruPVThooXeBQk7z8eIUCAI 7/+jEOxzE4Fz1RBngaY78EZAzTSRnVFRHt8h8duZ9OhXvb0iwP7914dmcKcSYGoEMc ERLskkc+RJZ806KHNeYi8WG7PMayK8YN3nxg7CnT9Q6P3qy7C4gsdjPskFFjLH2vw9 SJdHRAWKa44LSpkBAZ5AQ1hD3ts88rsye4nSHns8KDhbWYudKSmw7SauajTQNcpMJL Y9O7/RKVv5WA6hjY43EaVJAN9zsIvJ3jsxoiRx2w/Xpa4BejHSAdAy13lYhhIa8T7B my83Ioy9JtFiQ== From: Mark Brown Date: Mon, 03 Aug 2026 23:56:53 +0100 Subject: [PATCH v18 08/14] KVM: arm64: Enforce EXLOCK for SPSR and ELR Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260803-arm64-gcs-v18-8-fd8c40f5ad88@kernel.org> References: <20260803-arm64-gcs-v18-0-fd8c40f5ad88@kernel.org> In-Reply-To: <20260803-arm64-gcs-v18-0-fd8c40f5ad88@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Joey Gouly , Suzuki K Poulose , Shuah Khan , Fuad Tabba , Oliver Upton Cc: Peter Maydell , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=3010; i=broonie@kernel.org; h=from:subject:message-id; bh=dYXTcrQgfnk8FxnmgXg6ADstB4n1DYUswquMHXPAUUY=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqcSCgZxL3vnMN/fdXvvlTWz7G2jUymHEbk80nG VGlBh/oOo6JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCanEgoAAKCRAk1otyXVSH 0AfCB/994WaXrj0FxhuZLpXWKMkoWnuJzBwOu2c5GkJcdKi3+WqEe94KqUqJGMq4L5LsrGGmj66 rmOQoLZ7n/Zfe2AHNiEi6BLNDwlRcMm94pcaJmWXD7wjOVlyrGm3aLKmXQNNwpaP9CmkQ/ePZM7 VHJaLWib1K/WYDMhmycFJW041eFXVFYEnOzTWKycKJYb9gXPleLX8LOv4XMSsfTy835sOftUaa4 OIItrP8OYOANc6y7xMDxiL9rtH7CcaF7NOAqfmu9OEpnxBHJkq9KwqRkSEy37covX0WebB/PZUV eOaePDOxENwfTA5E+MxHnJm/hlh+mVzEV7/XSBItTbxYJLvB X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB As per I_CFFNS and the pseudocode for the SPSR_ELx and ELR_ELx registers a GCS exception with ExType 1 is generated for attempts to write to those registers when both GCSCR_ELx.EXLOCKEN and PSTATE.EXLOCK are set. Ensure that this is enforced for guests if access to these registers from the guest is handled by the hypervisor. Signed-off-by: Mark Brown --- arch/arm64/include/asm/kvm_emulate.h | 8 +++++++ arch/arm64/kvm/sys_regs.c | 42 ++++++++++++++++++++++++++++++++= ---- 2 files changed, 46 insertions(+), 4 deletions(-) diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/= kvm_emulate.h index ee774c3b8dcd..bc012c86fcd6 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -81,6 +81,14 @@ int kvm_inject_nested_irq(struct kvm_vcpu *vcpu); int kvm_inject_nested_sea(struct kvm_vcpu *vcpu, bool iabt, u64 addr); int kvm_inject_nested_serror(struct kvm_vcpu *vcpu, u64 esr); =20 +static inline void kvm_inject_exlock(struct kvm_vcpu *vcpu) +{ + u64 esr =3D FIELD_PREP(ESR_ELx_EC_MASK, ESR_ELx_EC_GCS) | ESR_ELx_IL | + FIELD_PREP(ESR_ELx_ExType_MASK, ESR_ELx_ExType_EXLOCK); + + kvm_inject_sync(vcpu, esr); +} + static inline void kvm_inject_nested_sve_trap(struct kvm_vcpu *vcpu) { u64 esr =3D FIELD_PREP(ESR_ELx_EC_MASK, ESR_ELx_EC_SVE) | diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index d18ada283809..387c14a33524 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2782,14 +2782,42 @@ static bool access_sp_el1(struct kvm_vcpu *vcpu, return true; } =20 +static inline bool sysregs_exlocked(struct kvm_vcpu *vcpu) +{ + u64 gcscr; + + if (!kvm_has_gcs(vcpu->kvm)) + return false; + + if (!(vcpu->arch.ctxt.regs.pstate & PSR_EXLOCK_BIT)) + return false; + + /* + * Note that the EXLOCKEN for the running EL is checked + * regardless of the register written to. + */ + if (is_hyp_ctxt(vcpu)) + gcscr =3D vcpu_read_sys_reg(vcpu, GCSCR_EL2); + else + gcscr =3D vcpu_read_sys_reg(vcpu, GCSCR_EL1); + + return gcscr & GCSCR_ELx_EXLOCKEN; +} + static bool access_elr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) { - if (p->is_write) + if (p->is_write) { + if (sysregs_exlocked(vcpu)) { + kvm_inject_exlock(vcpu); + return false; + } + vcpu_write_sys_reg(vcpu, p->regval, ELR_EL1); - else + } else { p->regval =3D vcpu_read_sys_reg(vcpu, ELR_EL1); + } =20 return true; } @@ -2798,10 +2826,16 @@ static bool access_spsr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) { - if (p->is_write) + if (p->is_write) { + if (sysregs_exlocked(vcpu)) { + kvm_inject_exlock(vcpu); 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a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Now that required functionality for GCS is in place expose ID_AA64PFR1_EL1.GCS, allowing guests to be given the feature. Signed-off-by: Mark Brown --- arch/arm64/kvm/nested.c | 3 +-- arch/arm64/kvm/sys_regs.c | 5 +++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c index dfb96edbdc43..e588820b1be7 100644 --- a/arch/arm64/kvm/nested.c +++ b/arch/arm64/kvm/nested.c @@ -1632,11 +1632,10 @@ u64 limit_nv_id_reg(struct kvm *kvm, u32 reg, u64 v= al) break; =20 case SYS_ID_AA64PFR1_EL1: - /* Only support BTI, SSBS, CSV2_frac */ + /* Only support GCS, BTI, SSBS, CSV2_frac */ val &=3D ~(ID_AA64PFR1_EL1_PFAR | ID_AA64PFR1_EL1_MTEX | ID_AA64PFR1_EL1_THE | - ID_AA64PFR1_EL1_GCS | ID_AA64PFR1_EL1_MTE_frac | ID_AA64PFR1_EL1_NMI | ID_AA64PFR1_EL1_SME | diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 387c14a33524..7105f42a63ae 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2109,10 +2109,12 @@ static u64 sanitise_id_aa64pfr1_el1(const struct kv= m_vcpu *vcpu, u64 val) SYS_FIELD_GET(ID_AA64PFR0_EL1, RAS, pfr0) =3D=3D ID_AA64PFR0_EL1_RA= S_IMP)) val &=3D ~ID_AA64PFR1_EL1_RAS_frac; =20 + if (!system_supports_gcs()) + val &=3D ~ID_AA64PFR1_EL1_GCS; + val &=3D ~ID_AA64PFR1_EL1_SME; val &=3D ~ID_AA64PFR1_EL1_RNDR_trap; val &=3D ~ID_AA64PFR1_EL1_NMI; - val &=3D ~ID_AA64PFR1_EL1_GCS; val &=3D ~ID_AA64PFR1_EL1_THE; val &=3D ~ID_AA64PFR1_EL1_MTEX; val &=3D ~ID_AA64PFR1_EL1_PFAR; @@ -3350,7 +3352,6 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { ~(ID_AA64PFR1_EL1_PFAR | ID_AA64PFR1_EL1_MTEX | ID_AA64PFR1_EL1_THE | - ID_AA64PFR1_EL1_GCS | ID_AA64PFR1_EL1_MTE_frac | ID_AA64PFR1_EL1_NMI | ID_AA64PFR1_EL1_RNDR_trap | --=20 2.47.3 From nobody Fri Oct 2 07:45:35 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A36BE382F07; Mon, 3 Aug 2026 23:14:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; 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Mon, 3 Aug 2026 23:14:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1785798857; bh=dJCqL2eqPlwjEMli5RhMxuoH1kWXulj7dYwiP95H9BM=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=AHAKRtz72OkQjQlbao/1hq6WwkRjhIDkecv8IOk6GnmrqBYluogRWKYDGVo89/kvi DYMsu8ORMLnAWMo4L59wgOQ2n4hVqdRPAmFe+fdH7akrwftyalR1KGFiMyhAgblWbS H6I1+2twLfqc0ndQK0Iap4oUUDa2ICQjaHmoggkfjzfW88zVf/A2mMfzgcmGixYKk8 wEOcw4YYbFHDMK+yfU9pVps/1D3eMJn4TTP6Tyko8iwPnvAS1EeQ2S0g+EJdY4Qx6L IVCW9Z0Mm3qZPS0aA03GHPvsR6MQoGiIE40kXiOJ20fZl9W+XOpcZCn6D5FSIa3Y1/ 6yomboabZB9Sw== From: Mark Brown Date: Mon, 03 Aug 2026 23:56:55 +0100 Subject: [PATCH v18 10/14] KVM: selftests: arm64: Add GCS registers to get-reg-list Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260803-arm64-gcs-v18-10-fd8c40f5ad88@kernel.org> References: <20260803-arm64-gcs-v18-0-fd8c40f5ad88@kernel.org> In-Reply-To: <20260803-arm64-gcs-v18-0-fd8c40f5ad88@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Joey Gouly , Suzuki K Poulose , Shuah Khan , Fuad Tabba , Oliver Upton Cc: Peter Maydell , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown , Thiago Jung Bauermann X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; 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Add these to those validated by get-reg-list. Reviewed-by: Thiago Jung Bauermann Signed-off-by: Mark Brown --- tools/testing/selftests/kvm/arm64/get-reg-list.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/tools/testing/selftests/kvm/arm64/get-reg-list.c b/tools/testi= ng/selftests/kvm/arm64/get-reg-list.c index 0a3a94c4cca1..6a93136d153f 100644 --- a/tools/testing/selftests/kvm/arm64/get-reg-list.c +++ b/tools/testing/selftests/kvm/arm64/get-reg-list.c @@ -42,6 +42,12 @@ struct feature_id_reg { static struct feature_id_reg feat_id_regs[] =3D { REG_FEAT(TCR2_EL1, ID_AA64MMFR3_EL1, TCRX, IMP), REG_FEAT(TCR2_EL2, ID_AA64MMFR3_EL1, TCRX, IMP), + REG_FEAT(GCSPR_EL0, ID_AA64PFR1_EL1, GCS, IMP), + REG_FEAT(GCSPR_EL1, ID_AA64PFR1_EL1, GCS, IMP), + REG_FEAT(GCSPR_EL2, ID_AA64PFR1_EL1, GCS, IMP), + REG_FEAT(GCSCRE0_EL1, ID_AA64PFR1_EL1, GCS, IMP), + REG_FEAT(GCSCR_EL1, ID_AA64PFR1_EL1, GCS, IMP), + REG_FEAT(GCSCR_EL2, ID_AA64PFR1_EL1, GCS, IMP), REG_FEAT(PIRE0_EL1, ID_AA64MMFR3_EL1, S1PIE, IMP), REG_FEAT(PIRE0_EL2, ID_AA64MMFR3_EL1, S1PIE, IMP), REG_FEAT(PIR_EL1, ID_AA64MMFR3_EL1, S1PIE, IMP), @@ -502,6 +508,9 @@ static __u64 base_regs[] =3D { ARM64_SYS_REG(3, 0, 2, 0, 1), /* TTBR1_EL1 */ ARM64_SYS_REG(3, 0, 2, 0, 2), /* TCR_EL1 */ ARM64_SYS_REG(3, 0, 2, 0, 3), /* TCR2_EL1 */ + ARM64_SYS_REG(3, 0, 2, 5, 0), /* GCSCR_EL1 */ + ARM64_SYS_REG(3, 0, 2, 5, 1), /* GCSPR_EL1 */ + ARM64_SYS_REG(3, 0, 2, 5, 2), /* GCSCRE0_EL1 */ ARM64_SYS_REG(3, 0, 5, 1, 0), /* AFSR0_EL1 */ ARM64_SYS_REG(3, 0, 5, 1, 1), /* AFSR1_EL1 */ ARM64_SYS_REG(3, 0, 5, 2, 0), /* ESR_EL1 */ @@ -518,6 +527,7 @@ static __u64 base_regs[] =3D { ARM64_SYS_REG(3, 0, 13, 0, 4), /* TPIDR_EL1 */ ARM64_SYS_REG(3, 0, 14, 1, 0), /* CNTKCTL_EL1 */ ARM64_SYS_REG(3, 2, 0, 0, 0), /* CSSELR_EL1 */ + ARM64_SYS_REG(3, 3, 2, 5, 1), /* GCSPR_EL0 */ ARM64_SYS_REG(3, 3, 10, 2, 4), /* POR_EL0 */ ARM64_SYS_REG(3, 3, 13, 0, 2), /* TPIDR_EL0 */ ARM64_SYS_REG(3, 3, 13, 0, 3), /* TPIDRRO_EL0 */ @@ -738,6 +748,8 @@ static __u64 el2_regs[] =3D { SYS_REG(VTTBR_EL2), SYS_REG(VTCR_EL2), SYS_REG(VNCR_EL2), + SYS_REG(GCSPR_EL2), + SYS_REG(GCSCR_EL2), SYS_REG(HDFGRTR2_EL2), SYS_REG(HDFGWTR2_EL2), SYS_REG(HFGRTR2_EL2), --=20 2.47.3 From nobody Fri Oct 2 07:45:35 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF6A937EFFC; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260803-arm64-gcs-v18-11-fd8c40f5ad88@kernel.org> References: <20260803-arm64-gcs-v18-0-fd8c40f5ad88@kernel.org> In-Reply-To: <20260803-arm64-gcs-v18-0-fd8c40f5ad88@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Joey Gouly , Suzuki K Poulose , Shuah Khan , Fuad Tabba , Oliver Upton Cc: Peter Maydell , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=987; i=broonie@kernel.org; h=from:subject:message-id; bh=d3SxEv6RjSY+xiyxMK7Zi+tIruIS+RbgPdYjX8k0TSU=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqcSCi4NyQnb7b/tt4qcu29pwgrmnYuE5kleL9V znPjXt5eEyJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCanEgogAKCRAk1otyXVSH 0BxtB/4/6luayAMUFSCj1h8ayU90trD1gtsnwpc9Jg90GfpoYAJ02Nf7Oi+80Hugc3S5Jc3i42C wlPWlsr3pUTBTT7kkWDIEnHcOgnZyZ+Cgxys5aLGFGJNHZCHxUYgRW76VqLyFLFoNgnGohPGNot 3Vqd8G3ZWFJoRkarpxGARudaHJZMbcQKou6piUDYiywtkei8B3JRdH/RZoL37X1ELGD/xIeEUIK Tg857HkXAYHcRqfeuLep7DgVQZEEsA2oAfZHE5sHlHHGhR+/qUz+Ml4MS1umdwpMssghV+LOouN MjuBwro40e1IaakiwOPrTec2uQhZeEG+UBSom6/66jjNjFd/ X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Now that GCS is configurable via the ID registers update set_id_regs to cover ID_AA64PFR1_EL1.GCS. Signed-off-by: Mark Brown --- tools/testing/selftests/kvm/arm64/set_id_regs.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/testing/selftests/kvm/arm64/set_id_regs.c b/tools/testin= g/selftests/kvm/arm64/set_id_regs.c index 7429a1055df5..34e59fbbbe89 100644 --- a/tools/testing/selftests/kvm/arm64/set_id_regs.c +++ b/tools/testing/selftests/kvm/arm64/set_id_regs.c @@ -154,6 +154,7 @@ static const struct reg_ftr_bits ftr_id_aa64pfr0_el1[] = =3D { =20 static const struct reg_ftr_bits ftr_id_aa64pfr1_el1[] =3D { REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, DF2, 0), + REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, GCS, 0), REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, CSV2_frac, 0), REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, SSBS, ID_AA64PFR1_EL1_SSBS_= NI), REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, BT, 0), --=20 2.47.3 From nobody Fri Oct 2 07:45:35 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B21573859D3; Mon, 3 Aug 2026 23:14:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785798868; cv=none; b=OFIdf+CP6rSg2xACZiXyHnfxUnX2TOLy8/ie9DH6gP7xGH0MWlTi46iDEcyCfTrsnYeunoW0K3yxyxicx8V8S5mnK13D4R1CRZYNZ/2p+AY7x6FSFKrZlkbgAJTpZJPPq7bJ39hAQwMk0qgdT/tqmqs4sGixAQAKtf9PmeTKAdY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785798868; c=relaxed/simple; bh=kq5inm4XLV9y3q0emrqMvgSlwP7yu7PrdQSzkYGOWPo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=XCK2f0nnEvQs2VARz7UkWPM51ww+7bFKQ/PzYVQdjejovfrKzTk5xh+o3ig3irK2GhS0e7f6ZB79c6btXYpSUxd7r4599cnXeH0+EZPbmjEVRwxXwErpg0nCfxgsS5uXqXcCdZ9xlY1+uorh38WrK07zePMdR0uK23Zq9A3o1F8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=UUJfR+7I; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="UUJfR+7I" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9A9651F000E9; Mon, 3 Aug 2026 23:14:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1785798863; bh=nW2uwG3VWmqTYBYq5oWNcIeaMFqReX/mfTA7yT0Lz8Q=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=UUJfR+7IHMsqGfyZM1V72vBi6n1cTfpx09aKjJy1cews2EQ8MJzTECoyN49Qxb4w8 LeZ2AC0vfl8Laqclee/QDXA70OWPOLviLGywYHxWiLminr8YW4ZXlUVYNsyUyHDz8J HxJboeTNvZhMNEFFYSwBBQJoPgkE+jXjVgDPDYmPAIop8CnLs64U+BxTUNv9X0hkUu G5c5PDTJnVe0ufNCdfsaH8dwfIpBNGazQFYB7yo6t9NWSx8tE5gffpNHk2QyDy5s8H Opop/pl/a2n49NWVH+1wyFAL0ruVbZPoOOjKwyXFnXlVHLs8bmrMezCW0Q9hFkMO5i XXjDONKXU9IFQ== From: Mark Brown Date: Mon, 03 Aug 2026 23:56:57 +0100 Subject: [PATCH v18 12/14] KVM: selftests: arm64: Only restore SPSR_EL1 and ELR_EL1 if they change Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260803-arm64-gcs-v18-12-fd8c40f5ad88@kernel.org> References: <20260803-arm64-gcs-v18-0-fd8c40f5ad88@kernel.org> In-Reply-To: <20260803-arm64-gcs-v18-0-fd8c40f5ad88@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Joey Gouly , Suzuki K Poulose , Shuah Khan , Fuad Tabba , Oliver Upton Cc: Peter Maydell , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=1508; i=broonie@kernel.org; h=from:subject:message-id; bh=kq5inm4XLV9y3q0emrqMvgSlwP7yu7PrdQSzkYGOWPo=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqcSCjvNz7/djhQRkSZti3j2aUYjpk2yW/YBJMi OsYTqXIpiGJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCanEgowAKCRAk1otyXVSH 0NdXB/4pR/GcsXnAvSiiTy8IGiyTvuwng5ZpqiFk+rDDrfer18Mw/vryphyfqsiI7x5uutZ/Ol9 oQBe4HbT+LsmZmA95XxaOcsDnjhfgttYBU4XgOFBNXsed/7xYxODbku9jPDD9a+2IxThVulLW1u ty9GLeB1u9o3iwfljQwg5T5M8AUKlzovEpYiYXVUA3eO15DQxjE3mCvp6Xqx4xuh1pH6ejzdk/o +6+q+wEnC//QForuKEjDuZ7h/aOrD2cvLe1eMbxGoULioE2Qpr87cqF4FPvTwrZ1QeZ1+vzr3KQ LnGk6EA4pmi5CekhtSXkuHcNUf0b3ErDHYCSauYHZsfNPU5u X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB When EXLOCK is enabled for ELx writes to SPSR_ELx and ELR_ELx generate GCS exceptions. Currently the selftest helpers unconditionally reload the saved values for these registers regardless of if the handler didn't change them. This gets in the way of EXLOCK testing, making it hard to generate contexts which will generate an invalid ERET since we never get as far as doing an exception return while EXLOCK is enabled. In order to facilitate testing of nested virtualisation emulation of EXLOCK change our reloads into read/modify/write cycles, suppressing the writes when they would not change the value in the register. Signed-off-by: Mark Brown --- tools/testing/selftests/kvm/lib/arm64/handlers.S | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/tools/testing/selftests/kvm/lib/arm64/handlers.S b/tools/testi= ng/selftests/kvm/lib/arm64/handlers.S index 0e443eadfac6..367c22d61cba 100644 --- a/tools/testing/selftests/kvm/lib/arm64/handlers.S +++ b/tools/testing/selftests/kvm/lib/arm64/handlers.S @@ -33,8 +33,18 @@ =20 .macro restore_registers ldp x1, x2, [sp, #16 * 16] /* PC, PSTATE */ + + /* Suppress redundant writes to support GCS exception lock testing */ + mrs x3, elr_el1 + cmp x1, x3 + beq .Lskip_elr_\@ msr elr_el1, x1 +.Lskip_elr_\@: + mrs x3, spsr_el1 + cmp x2, x3 + beq .Lskip_spsr_\@ msr spsr_el1, x2 +.Lskip_spsr_\@: =20 /* sp is not restored */ ldp x30, xzr, [sp, #16 * 15] /* x30, SP */ --=20 2.47.3 From nobody Fri Oct 2 07:45:35 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E400D384CF0; Mon, 3 Aug 2026 23:14:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785798873; cv=none; b=VmR0yTSOlxaorImCJdf5FPm/BXpBzo77h+SxQxIy1Myti3eU2fn7UaEIHNZhs8J/wqlWWDJuXchJdWCREc+p5raxcWixtfjk8/+IbhYkLWtehc+JImZGa3ROkilM+lMYHRDPVkLKfYz4W3bimL8Tper08jPL2q+zngb1ZgEqD2o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785798873; c=relaxed/simple; bh=sIWieTk4WURR6tewmd4CqdDOGodIh/nx0/zJZ1rNZT8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hE9bDXtmK4JqQVHlb8vQJWbk27OQzCBECN8KaD1nvWTTNyhxoYST5a9evlR/IjvAJGU6B4dQswTd5DF9ONGvFdovoxPx4pqU7RbpJt7SGyoxgnyRHMH9sNNYHB4Er85rp5+D7y89eFFRdbjEUtZb5aRWpnSVXFTD7CAcG6ZW33o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=fOvlpMoc; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="fOvlpMoc" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C3AF21F00A3D; Mon, 3 Aug 2026 23:14:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1785798866; bh=0g4KetOtT1QniGH3lYu0d4Ii94UczTzbZTbGp4YhhKU=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=fOvlpMocHn1y0aanjbvVGXQNf/tJP1b7+DpCsPyyLZ1+RhIfXcUz+9AmLDWxlOCTf 6MZ/yxNy9Y/eBSg+Z1gCn4R6J6RfeBPcdK7UMiJZjXsfpOYV/OMXNTae+s01emf5Ba +QWWLjTEHXRCAHZfH7zcK/6ljxBU68mHTQ/egHu8WX8XOE8nFFokVTUM1tEAfig6CZ 9oJHSrGTGGyyerL9Psv458ie+FAq2vtvKrihj4GPpnWIY57VppvjbHDvOC5xggig/a OBJHCibh8YeGakff7Cix9GMXzkMcQmcHM71HTzAmC2g16Zh1qXr/vsiXwUsvYw7OqF g0ayeDyYo6Gcg== From: Mark Brown Date: Mon, 03 Aug 2026 23:56:58 +0100 Subject: [PATCH v18 13/14] tools: Synchronise the kernel esr.h Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260803-arm64-gcs-v18-13-fd8c40f5ad88@kernel.org> References: <20260803-arm64-gcs-v18-0-fd8c40f5ad88@kernel.org> In-Reply-To: <20260803-arm64-gcs-v18-0-fd8c40f5ad88@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Joey Gouly , Suzuki K Poulose , Shuah Khan , Fuad Tabba , Oliver Upton Cc: Peter Maydell , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=7181; i=broonie@kernel.org; h=from:subject:message-id; bh=sIWieTk4WURR6tewmd4CqdDOGodIh/nx0/zJZ1rNZT8=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqcSCkCRfaQjaD7jACQCeX5Lg3QpLZ8ULiT4HAg wmZf+J+T7+JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCanEgpAAKCRAk1otyXVSH 0BqWB/9mCnrhmIefg8+FELVFYNUWdH+nf07j8iX0/2V63FW5DBLsSkumMQJxIgeg2n8ZnvcVLe1 yfobn2xoDEdFPvgx3rGwbY005l+Gz9q/mbMBZW4a7i899FcsDtHHA/I/Q6rHl/Jx3bv1hF/2gn5 jqKwaBH6qY3/3x+pegnOojuBbSwSlmCnhDGi7xSX0FXVsHjlhoKvMw3DHAxWj3ZChYFUTYiBqPw VxCfG/G40HpTEOxBUuVA+IfgEtDjE0sMOkSChDUnBosRFIXl5FGakMfM+ujY5C3pW6FJdZbO+d+ wdJHE+gpA977+n658jD/RhvBAirzCm21ZrsU3hQRq+VIpIvr X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB To pick up definitions for GCS. Signed-off-by: Mark Brown --- tools/arch/arm64/include/asm/esr.h | 113 +++++++++++++++++++++++++++++++++= ---- 1 file changed, 102 insertions(+), 11 deletions(-) diff --git a/tools/arch/arm64/include/asm/esr.h b/tools/arch/arm64/include/= asm/esr.h index f3c6403e5ef2..24c6ebe3fd41 100644 --- a/tools/arch/arm64/include/asm/esr.h +++ b/tools/arch/arm64/include/asm/esr.h @@ -19,7 +19,8 @@ #define ESR_ELx_EC_FP_ASIMD UL(0x07) #define ESR_ELx_EC_CP10_ID UL(0x08) /* EL2 only */ #define ESR_ELx_EC_PAC UL(0x09) /* EL2 and above */ -/* Unallocated EC: 0x0A - 0x0B */ +#define ESR_ELx_EC_OTHER UL(0x0A) +/* Unallocated EC: 0x0B */ #define ESR_ELx_EC_CP14_64 UL(0x0C) #define ESR_ELx_EC_BTI UL(0x0D) #define ESR_ELx_EC_ILL UL(0x0E) @@ -50,7 +51,8 @@ #define ESR_ELx_EC_FP_EXC32 UL(0x28) /* Unallocated EC: 0x29 - 0x2B */ #define ESR_ELx_EC_FP_EXC64 UL(0x2C) -/* Unallocated EC: 0x2D - 0x2E */ +#define ESR_ELx_EC_GCS UL(0x2D) +/* Unallocated EC: 0x2E */ #define ESR_ELx_EC_SERROR UL(0x2F) #define ESR_ELx_EC_BREAKPT_LOW UL(0x30) #define ESR_ELx_EC_BREAKPT_CUR UL(0x31) @@ -97,6 +99,8 @@ #define ESR_ELx_AET_CE (UL(6) << ESR_ELx_AET_SHIFT) =20 /* Shared ISS field definitions for Data/Instruction aborts */ +#define ESR_ELx_VNCR_SHIFT (13) +#define ESR_ELx_VNCR (UL(1) << ESR_ELx_VNCR_SHIFT) #define ESR_ELx_SET_SHIFT (11) #define ESR_ELx_SET_MASK (UL(3) << ESR_ELx_SET_SHIFT) #define ESR_ELx_FnV_SHIFT (10) @@ -119,6 +123,16 @@ #define ESR_ELx_FSC_SEA_TTW(n) (0x14 + (n)) #define ESR_ELx_FSC_SECC (0x18) #define ESR_ELx_FSC_SECC_TTW(n) (0x1c + (n)) +#define ESR_ELx_FSC_EXCL_ATOMIC (0x35) +#define ESR_ELx_FSC_ADDRSZ (0x00) + +/* + * Annoyingly, the negative levels for Address size faults aren't laid out + * contiguously (or in the desired order) + */ +#define ESR_ELx_FSC_ADDRSZ_nL(n) ((n) =3D=3D -1 ? 0x25 : 0x2C) +#define ESR_ELx_FSC_ADDRSZ_L(n) ((n) < 0 ? ESR_ELx_FSC_ADDRSZ_nL(n) : \ + (ESR_ELx_FSC_ADDRSZ + (n))) =20 /* Status codes for individual page table levels */ #define ESR_ELx_FSC_ACCESS_L(n) (ESR_ELx_FSC_ACCESS + (n)) @@ -141,12 +155,12 @@ #define ESR_ELx_SF (UL(1) << ESR_ELx_SF_SHIFT) #define ESR_ELx_AR_SHIFT (14) #define ESR_ELx_AR (UL(1) << ESR_ELx_AR_SHIFT) -#define ESR_ELx_VNCR_SHIFT (13) -#define ESR_ELx_VNCR (UL(1) << ESR_ELx_VNCR_SHIFT) #define ESR_ELx_CM_SHIFT (8) #define ESR_ELx_CM (UL(1) << ESR_ELx_CM_SHIFT) =20 /* ISS2 field definitions for Data Aborts */ +#define ESR_ELx_HDBSSF_SHIFT (11) +#define ESR_ELx_HDBSSF (UL(1) << ESR_ELx_HDBSSF_SHIFT) #define ESR_ELx_TnD_SHIFT (10) #define ESR_ELx_TnD (UL(1) << ESR_ELx_TnD_SHIFT) #define ESR_ELx_TagAccess_SHIFT (9) @@ -161,8 +175,6 @@ #define ESR_ELx_Xs_MASK (GENMASK_ULL(4, 0)) =20 /* ISS field definitions for exceptions taken in to Hyp */ -#define ESR_ELx_FSC_ADDRSZ (0x00) -#define ESR_ELx_FSC_ADDRSZ_L(n) (ESR_ELx_FSC_ADDRSZ + (n)) #define ESR_ELx_CV (UL(1) << 24) #define ESR_ELx_COND_SHIFT (20) #define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT) @@ -174,6 +186,13 @@ #define ESR_ELx_WFx_ISS_WFE (UL(1) << 0) #define ESR_ELx_xVC_IMM_MASK ((UL(1) << 16) - 1) =20 +/* ISS definitions for LD64B/ST64B/{T,P}SBCSYNC instructions */ +#define ESR_ELx_ISS_OTHER_ST64BV (0) +#define ESR_ELx_ISS_OTHER_ST64BV0 (1) +#define ESR_ELx_ISS_OTHER_LDST64B (2) +#define ESR_ELx_ISS_OTHER_TSBCSYNC (3) +#define ESR_ELx_ISS_OTHER_PSBCSYNC (4) + #define DISR_EL1_IDS (UL(1) << 24) /* * DISR_EL1 and ESR_ELx share the bottom 13 bits, but the RES0 bits may me= an @@ -371,12 +390,14 @@ /* * ISS values for SME traps */ +#define ESR_ELx_SME_ISS_SMTC_MASK GENMASK(2, 0) +#define ESR_ELx_SME_ISS_SMTC(esr) ((esr) & ESR_ELx_SME_ISS_SMTC_MASK) =20 -#define ESR_ELx_SME_ISS_SME_DISABLED 0 -#define ESR_ELx_SME_ISS_ILL 1 -#define ESR_ELx_SME_ISS_SM_DISABLED 2 -#define ESR_ELx_SME_ISS_ZA_DISABLED 3 -#define ESR_ELx_SME_ISS_ZT_DISABLED 4 +#define ESR_ELx_SME_ISS_SMTC_SME_DISABLED 0 +#define ESR_ELx_SME_ISS_SMTC_ILL 1 +#define ESR_ELx_SME_ISS_SMTC_SM_DISABLED 2 +#define ESR_ELx_SME_ISS_SMTC_ZA_DISABLED 3 +#define ESR_ELx_SME_ISS_SMTC_ZT_DISABLED 4 =20 /* ISS field definitions for MOPS exceptions */ #define ESR_ELx_MOPS_ISS_MEM_INST (UL(1) << 24) @@ -387,6 +408,31 @@ #define ESR_ELx_MOPS_ISS_SRCREG(esr) (((esr) & (UL(0x1f) << 5)) >> 5) #define ESR_ELx_MOPS_ISS_SIZEREG(esr) (((esr) & (UL(0x1f) << 0)) >> 0) =20 +/* ISS field definitions for GCS */ +#define ESR_ELx_ExType_SHIFT (20) +#define ESR_ELx_ExType_MASK GENMASK(23, 20) +#define ESR_ELx_Raddr_SHIFT (10) +#define ESR_ELx_Raddr_MASK GENMASK(14, 10) +#define ESR_ELx_Rn_SHIFT (5) +#define ESR_ELx_Rn_MASK GENMASK(9, 5) +#define ESR_ELx_Rvalue_SHIFT 5 +#define ESR_ELx_Rvalue_MASK GENMASK(9, 5) +#define ESR_ELx_IT_SHIFT (0) +#define ESR_ELx_IT_MASK GENMASK(4, 0) + +#define ESR_ELx_ExType_DATA_CHECK 0 +#define ESR_ELx_ExType_EXLOCK 1 +#define ESR_ELx_ExType_STR 2 + +#define ESR_ELx_IT_RET 0 +#define ESR_ELx_IT_GCSPOPM 1 +#define ESR_ELx_IT_RET_KEYA 2 +#define ESR_ELx_IT_RET_KEYB 3 +#define ESR_ELx_IT_GCSSS1 4 +#define ESR_ELx_IT_GCSSS2 5 +#define ESR_ELx_IT_GCSPOPCX 6 +#define ESR_ELx_IT_GCSPOPX 7 + #ifndef __ASSEMBLER__ #include =20 @@ -408,6 +454,11 @@ static inline bool esr_is_cfi_brk(unsigned long esr) (esr_brk_comment(esr) & ~CFI_BRK_IMM_MASK) =3D=3D CFI_BRK_IMM_BASE; } =20 +static inline bool esr_is_ubsan_brk(unsigned long esr) +{ + return (esr_brk_comment(esr) & ~UBSAN_BRK_MASK) =3D=3D UBSAN_BRK_IMM; +} + static inline bool esr_fsc_is_translation_fault(unsigned long esr) { esr =3D esr & ESR_ELx_FSC; @@ -439,6 +490,46 @@ static inline bool esr_fsc_is_access_flag_fault(unsign= ed long esr) (esr =3D=3D ESR_ELx_FSC_ACCESS_L(0)); } =20 +static inline bool esr_fsc_is_excl_atomic_fault(unsigned long esr) +{ + esr =3D esr & ESR_ELx_FSC; + + return esr =3D=3D ESR_ELx_FSC_EXCL_ATOMIC; +} + +static inline bool esr_fsc_is_addr_sz_fault(unsigned long esr) +{ + esr &=3D ESR_ELx_FSC; + + return (esr =3D=3D ESR_ELx_FSC_ADDRSZ_L(3)) || + (esr =3D=3D ESR_ELx_FSC_ADDRSZ_L(2)) || + (esr =3D=3D ESR_ELx_FSC_ADDRSZ_L(1)) || + (esr =3D=3D ESR_ELx_FSC_ADDRSZ_L(0)) || + (esr =3D=3D ESR_ELx_FSC_ADDRSZ_L(-1)); +} + +static inline bool esr_fsc_is_sea_ttw(unsigned long esr) +{ + esr =3D esr & ESR_ELx_FSC; + + return (esr =3D=3D ESR_ELx_FSC_SEA_TTW(3)) || + (esr =3D=3D ESR_ELx_FSC_SEA_TTW(2)) || + (esr =3D=3D ESR_ELx_FSC_SEA_TTW(1)) || + (esr =3D=3D ESR_ELx_FSC_SEA_TTW(0)) || + (esr =3D=3D ESR_ELx_FSC_SEA_TTW(-1)); +} + +static inline bool esr_fsc_is_secc_ttw(unsigned long esr) +{ + esr =3D esr & ESR_ELx_FSC; + + return (esr =3D=3D ESR_ELx_FSC_SECC_TTW(3)) || + (esr =3D=3D ESR_ELx_FSC_SECC_TTW(2)) || + (esr =3D=3D ESR_ELx_FSC_SECC_TTW(1)) || + (esr =3D=3D ESR_ELx_FSC_SECC_TTW(0)) || + (esr =3D=3D ESR_ELx_FSC_SECC_TTW(-1)); +} + /* Indicate whether ESR.EC=3D=3D0x1A is for an ERETAx instruction */ static inline bool esr_iss_is_eretax(unsigned long esr) { --=20 2.47.3 From nobody Fri Oct 2 07:45:35 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E27D6381AE5; Mon, 3 Aug 2026 23:14:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785798875; cv=none; b=i4gbK9WhnSsr7K66fy4TxQEuazNsql+2Fb877QL+eUbgTFrg690O24cIhbv98jAAGSTXYGDoPxSTbL/Eli3jDX5lWlm/icj1Pf1SO8EI5VVxJDl2H63GAw+AaklAZK4yFMORJ3wrG89IAnKKikeUTt+U6UmI21Kkf+vM23Ad/Jw= ARC-Message-Signature: i=1; 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b=S6Cgizc/xuEu3XPUrMCe8dJhDOEf3e8WJr0K0iePNYmTVx6WaGc4XtBsGyu4qdZe5 heOyVxteeYXwQu1tVPO/CWh8qWYH8OWsVf/4dNtZ4XgzvGmtVsPmpIdkV6sVvo8kip tnvT8UqGxAx5LU/+DM8JTGA7U1F00w4Y7GPG2+ZNX/eGsxEIB/atOhQbhyHA4Z/y9i XhtWD0FaNiF1A5KoB6kECsAa/k76WuvzCZKCUoM1hsMrTS8htd2qq8TeJlxdz71RZn kHs9nHE2EH1UUnBm6YIeB3PQEUSfjMsG4Cl6kqkZS7GMDDDQXlf01UmjrCTLENmg9y MqgwwgI4tN1rg== From: Mark Brown Date: Mon, 03 Aug 2026 23:56:59 +0100 Subject: [PATCH v18 14/14] KVM: selftests: arm64: Add GCS EXLOCK exception emulation test Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260803-arm64-gcs-v18-14-fd8c40f5ad88@kernel.org> References: <20260803-arm64-gcs-v18-0-fd8c40f5ad88@kernel.org> In-Reply-To: <20260803-arm64-gcs-v18-0-fd8c40f5ad88@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Joey Gouly , Suzuki K Poulose , Shuah Khan , Fuad Tabba , Oliver Upton Cc: Peter Maydell , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=11852; i=broonie@kernel.org; h=from:subject:message-id; bh=DwJtjT1vSlZeZxuU+9RDgebOB5WNzjn6/ElXQEH8V8M=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqcSCk4kCYwz6yfjuB2x3RXs3Sy7VZa4/+VjKXJ bbDK+mMk7CJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCanEgpAAKCRAk1otyXVSH 0ElcB/sEnyxe2G2Js4rRGKRrrnYGFBC57xu9oCaEnTnIWDaNPIu8fkYcjoDm3WFdjOV9J8bvuaR u+0k3Sl+GMhpsV2u1JK3pkLYG75LVbHLZJ7QZwgqvef3UX16cG1AlU7oaC5W3SonJVgqDAZJGS9 VVqd8NcMzt1AwtrPntE+HIiDtkUUR/b6CK3Vu8Xri1buEqljIoHTi1+E1roRoW+bFzk2VfhcR8K dsSDnLaWcqbyU476eJ7VpkYVxG3FT+WR+q8pGxv5EQWswZFcJf9KshY3Ng64llX97d1ZjF5hkyA fM1kBioIF5jNuLtVS2swlO6DhaPOpKsaxTRXJVgjF0wULOYd X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB When running in vEL2 ERET is emulated, this means that we must emulate the behaviour of GCSCR_EL2.EXLOCKEN. Add a test that validates the behaviour. As per DDI0487 R_WTXBY PSTATE.EXLOCK is set to the value of GCSCR_ELx.EXLOCKEN when taking an exception to the same exception level. As per DDI0487 R_TYTWB if on exception return to the same EL GCSCR_ELx.EXLOCKEN is 1 and PSTATE.EXLOCK is not 1 then the exception return is illegal. We nest handling of two UDFs to allow us to both observe and modify PSTATE.EXLOCK, checking that expected exceptions are generated for ERET. We also repeat the UDF tests having enabled fine grained traps for ERET to try to ensure that the slow paths are taken. We also attempt to write to both SPSR_ELx and ELR_ELx, again using a UDF handler to control PSTATE.EXLOCK. We do all this both with and without having enabled EXLOCKEN, though only for code running at EL2 due to framework limitations. For completeness we also inject a data abort from EL0 to EL2 with GCSCR_EL2.EXLOCKEN set, ensuring that PSTATE.EXLOCK is not set. Signed-off-by: Mark Brown --- tools/testing/selftests/kvm/Makefile.kvm | 1 + tools/testing/selftests/kvm/arm64/gcs_exceptions.c | 346 +++++++++++++++++= ++++ 2 files changed, 347 insertions(+) diff --git a/tools/testing/selftests/kvm/Makefile.kvm b/tools/testing/selft= ests/kvm/Makefile.kvm index 6fc34e9bf8e1..0200dd477ffe 100644 --- a/tools/testing/selftests/kvm/Makefile.kvm +++ b/tools/testing/selftests/kvm/Makefile.kvm @@ -174,6 +174,7 @@ TEST_GEN_PROGS_arm64 +=3D arm64/hello_el2 TEST_GEN_PROGS_arm64 +=3D arm64/host_sve TEST_GEN_PROGS_arm64 +=3D arm64/hypercalls TEST_GEN_PROGS_arm64 +=3D arm64/external_aborts +TEST_GEN_PROGS_arm64 +=3D arm64/gcs_exceptions TEST_GEN_PROGS_arm64 +=3D arm64/mmio_sign_ext TEST_GEN_PROGS_arm64 +=3D arm64/page_fault_test TEST_GEN_PROGS_arm64 +=3D arm64/psci_test diff --git a/tools/testing/selftests/kvm/arm64/gcs_exceptions.c b/tools/tes= ting/selftests/kvm/arm64/gcs_exceptions.c new file mode 100644 index 000000000000..de5bc6590727 --- /dev/null +++ b/tools/testing/selftests/kvm/arm64/gcs_exceptions.c @@ -0,0 +1,346 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Test KVM's handling of Guarded Control Stack exception state. + */ + +#include "kvm_util.h" +#include "processor.h" +#include "test_util.h" +#include "ucall.h" + +#include +#include + +#define PSTATE_IL_BIT BIT(20) + +static void require_guest_gcs(struct kvm_vcpu *vcpu) +{ + u64 pfr1 =3D vcpu_get_reg(vcpu, + KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1)); + + TEST_REQUIRE(SYS_FIELD_GET(ID_AA64PFR1_EL1, GCS, pfr1) >=3D + ID_AA64PFR1_EL1_GCS_IMP); +} + +static bool expect_exlock; +static unsigned int undef_count; +static unsigned int illegal_count; +static unsigned int gcs_count; +static u64 handler_pstate; +static u64 illegal_pstate; + +static u64 expected_illegal_pc; +static enum udf_mode { + UDF_COLLECT, /* Initial UDF we collect PSTATE from */ + UDF_VALIDATE, /* Secondary UDF that collects and validates */ + UDF_REPAIR, /* UDF to clear EXLOCK */ + UDF_ELR_EL1, /* Write to ELR_EL1 with EXLOCK */ + UDF_ELR_EL2, /* Write to ELR_EL2 with EXLOCK */ + UDF_SPSR_EL1, /* Write to SPSR_EL1 with EXLOCK */ + UDF_SPSR_EL2, /* Write to SPSR_EL2 with EXLOCK */ +} udf_mode; + +static void guest_undef_handler(struct ex_regs *regs) +{ + u64 esr =3D read_sysreg(esr_el2); + u64 val; + + undef_count++; + + /* Just skip the instruction either way. */ + GUEST_ASSERT_EQ(esr, ESR_ELx_IL); + regs->pc +=3D 4; + + switch (udf_mode) { + case UDF_COLLECT: + GUEST_ASSERT_EQ(read_sysreg_s(SYS_GCSCR_EL2) & GCSCR_ELx_EXLOCKEN, + expect_exlock ? GCSCR_ELx_EXLOCKEN : 0); + + /* + * If we want the nested exception handler to change + * PSTATE it can't have EXLOCK set. + */ + write_sysreg_s(0, SYS_GCSCR_EL2); + isb(); + + /* + * Take another exception without returning so we can + * collect the EXLOCK state we're seeing here and make + * our return illegal. + */ + expected_illegal_pc =3D regs->pc; + udf_mode =3D UDF_VALIDATE; + asm volatile("udf #0" ::: "memory"); + + /* Reenable so PSTATE.EXLOCK is checked */ + write_sysreg_s(expect_exlock ? GCSCR_ELx_EXLOCKEN : 0, + SYS_GCSCR_EL2); + isb(); + break; + + case UDF_VALIDATE: + GUEST_ASSERT_EQ(read_sysreg_s(SYS_GCSCR_EL2) & GCSCR_ELx_EXLOCKEN, + 0); + + /* Validate the EXLOCK of the original exception. */ + handler_pstate =3D regs->pstate; + GUEST_ASSERT_EQ(!!(regs->pstate & PSR_EXLOCK_BIT), + expect_exlock); + + /* Clearing PSTATE.EXLOCK triggers an illegal ERET. */ + regs->pstate &=3D ~PSR_EXLOCK_BIT; + break; + + case UDF_REPAIR: + GUEST_ASSERT_EQ(read_sysreg_s(SYS_GCSCR_EL2) & GCSCR_ELx_EXLOCKEN, + 0); + + /* Disable EXLOCK for the requesting context */ + regs->pstate &=3D ~PSR_EXLOCK_BIT; + break; + + case UDF_ELR_EL1: + GUEST_ASSERT_EQ(read_sysreg_s(SYS_GCSCR_EL2) & GCSCR_ELx_EXLOCKEN, + expect_exlock ? GCSCR_ELx_EXLOCKEN : 0); + + asm volatile("mrs %0, elr_el1 \n\ + msr elr_el1, %0" + : "=3Dr"(val) :: "memory"); + break; + + case UDF_ELR_EL2: + GUEST_ASSERT_EQ(read_sysreg_s(SYS_GCSCR_EL2) & GCSCR_ELx_EXLOCKEN, + expect_exlock ? GCSCR_ELx_EXLOCKEN : 0); + + asm volatile("mrs %0, elr_el2 \n\ + msr elr_el2, %0" + : "=3Dr"(val) :: "memory"); + break; + + case UDF_SPSR_EL1: + GUEST_ASSERT_EQ(read_sysreg_s(SYS_GCSCR_EL2) & GCSCR_ELx_EXLOCKEN, + expect_exlock ? GCSCR_ELx_EXLOCKEN : 0); + + asm volatile("mrs %0, spsr_el1 \n\ + msr spsr_el1, %0" + : "=3Dr"(val) :: "memory"); + break; + + case UDF_SPSR_EL2: + GUEST_ASSERT_EQ(read_sysreg_s(SYS_GCSCR_EL2) & GCSCR_ELx_EXLOCKEN, + expect_exlock ? GCSCR_ELx_EXLOCKEN : 0); + + asm volatile("mrs %0, spsr_el2 \n\ + msr spsr_el2, %0" + : "=3Dr"(val) :: "memory"); + break; + + default: + GUEST_FAIL("Invalid udf_mode"); + } +} + +static void guest_illegal_handler(struct ex_regs *regs) +{ + u64 esr =3D read_sysreg(esr_el2); + + illegal_count++; + illegal_pstate =3D regs->pstate; + + GUEST_ASSERT_EQ(ESR_ELx_EC(esr), ESR_ELx_EC_ILL); + GUEST_ASSERT(esr & ESR_ELx_IL); + GUEST_ASSERT(regs->pstate & PSTATE_IL_BIT); + GUEST_ASSERT(!(regs->pstate & PSR_EXLOCK_BIT)); + GUEST_ASSERT_EQ(regs->pc, expected_illegal_pc); + + /* Disable exception locking so we can repair the return state. */ + write_sysreg_s(0, SYS_GCSCR_EL2); + isb(); + + /* We need our own EXLOCK clearing so we can repair the original */ + udf_mode =3D UDF_REPAIR; + asm volatile("udf #0" ::: "memory"); + + /* Disable EXLOCK for the generating context, making things legal */ + regs->pstate &=3D ~(PSTATE_IL_BIT | PSR_EXLOCK_BIT); +} + +static void guest_gcs_handler(struct ex_regs *regs) +{ + u64 esr =3D read_sysreg(esr_el2); + + gcs_count++; + + GUEST_ASSERT_EQ(ESR_ELx_EC(esr), ESR_ELx_EC_GCS); + GUEST_ASSERT_EQ(FIELD_GET(ESR_ELx_ExType_MASK, esr), + ESR_ELx_ExType_EXLOCK); + + /* Disabling EXLOCKEN makes sysreg writes legal. */ + write_sysreg_s(0, SYS_GCSCR_EL2); + isb(); +} + +static noinline void test_udf_exception(bool enable_exlock) +{ + unsigned int initial_undef =3D undef_count; + unsigned int initial_illegal =3D illegal_count; + unsigned int initial_gcs =3D gcs_count; + + expect_exlock =3D enable_exlock; + write_sysreg_s(enable_exlock ? GCSCR_ELx_EXLOCKEN : 0, + SYS_GCSCR_EL2); + isb(); + + udf_mode =3D UDF_COLLECT; + asm volatile("udf #0" ::: "memory"); + + /* Leave GCS disabled even if a broken ERET skipped the ILL handler. */ + write_sysreg_s(0, SYS_GCSCR_EL2); + isb(); + + GUEST_ASSERT_EQ(undef_count, initial_undef + 2 + enable_exlock); + GUEST_ASSERT_EQ(illegal_count, initial_illegal + enable_exlock); + GUEST_ASSERT_EQ(!!(handler_pstate & PSR_EXLOCK_BIT), enable_exlock); + if (enable_exlock) + GUEST_ASSERT(illegal_pstate & PSTATE_IL_BIT); + GUEST_ASSERT_EQ(initial_gcs, gcs_count); +} + +static noinline void test_sysreg(enum udf_mode reg, bool enable_exlock) +{ + unsigned int initial_undef =3D undef_count; + unsigned int initial_gcs =3D gcs_count; + + expect_exlock =3D enable_exlock; + + write_sysreg_s(enable_exlock ? GCSCR_ELx_EXLOCKEN : 0, + SYS_GCSCR_EL2); + isb(); + + udf_mode =3D reg; + asm volatile("udf #0" ::: "memory"); + + /* Ensure EXLOCK is disabled */ + write_sysreg_s(0, SYS_GCSCR_EL2); + isb(); + + GUEST_ASSERT_EQ(gcs_count, initial_gcs + expect_exlock); + GUEST_ASSERT_EQ(undef_count, initial_undef + 1); +} + +static void guest_code(void) +{ + GUEST_ASSERT_EQ(get_current_el(), 2); + + /* + * Try straightforwardly generating an exception without and + * with EXLOCK. + */ + test_udf_exception(false); + test_sysreg(UDF_ELR_EL1, false); + test_sysreg(UDF_ELR_EL2, false); + test_sysreg(UDF_SPSR_EL1, false); + test_sysreg(UDF_SPSR_EL2, false); + + test_udf_exception(true); + test_sysreg(UDF_ELR_EL1, true); + test_sysreg(UDF_ELR_EL2, true); + test_sysreg(UDF_SPSR_EL1, true); + test_sysreg(UDF_SPSR_EL2, true); + + /* Force ERET directly through the slow emulation path as well. */ + sysreg_clear_set_s(SYS_HFGITR_EL2, 0, HFGITR_EL2_ERET); + isb(); + + test_udf_exception(false); + + test_udf_exception(true); + + sysreg_clear_set_s(SYS_HFGITR_EL2, HFGITR_EL2_ERET, 0); + isb(); + GUEST_DONE(); +} + +static void test_exception_from_same_el(void) +{ + struct kvm_vcpu_init init; + struct kvm_vcpu *vcpu; + struct kvm_vm *vm; + struct ucall uc; + + vm =3D vm_create(1); + kvm_get_default_vcpu_target(vm, &init); + init.features[0] |=3D BIT(KVM_ARM_VCPU_HAS_EL2); + vcpu =3D aarch64_vcpu_add(vm, 0, &init, guest_code); + require_guest_gcs(vcpu); + + vm_init_descriptor_tables(vm); + vcpu_init_descriptor_tables(vcpu); + vm_install_sync_handler(vm, VECTOR_SYNC_CURRENT, + ESR_ELx_EC_UNKNOWN, guest_undef_handler); + vm_install_sync_handler(vm, VECTOR_SYNC_CURRENT, + ESR_ELx_EC_ILL, guest_illegal_handler); + vm_install_sync_handler(vm, VECTOR_SYNC_CURRENT, + ESR_ELx_EC_GCS, guest_gcs_handler); + kvm_arch_vm_finalize_vcpus(vm); + + vcpu_run(vcpu); + switch (get_ucall(vcpu, &uc)) { + case UCALL_DONE: + break; + case UCALL_ABORT: + REPORT_GUEST_ASSERT(uc); + break; + default: + TEST_FAIL("Unhandled ucall: %ld", uc.cmd); + } + + kvm_vm_free(vm); +} + +static void test_exception_from_lower_el(void) +{ + struct kvm_vcpu_events events =3D {}; + struct kvm_vcpu_init init; + struct kvm_vcpu *vcpu; + struct kvm_vm *vm; + u64 pstate; + + vm =3D vm_create(1); + kvm_get_default_vcpu_target(vm, &init); + init.features[0] |=3D BIT(KVM_ARM_VCPU_HAS_EL2); + vcpu =3D aarch64_vcpu_add(vm, 0, &init, NULL); + require_guest_gcs(vcpu); + kvm_arch_vm_finalize_vcpus(vm); + + /* + * Inject an EL0 data abort to vEL2 with EXLOCK enabled for + * vEL2. + */ + vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_HCR_EL2), + vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_HCR_EL2)) | + HCR_EL2_TGE); + vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_GCSCR_EL2), + GCSCR_ELx_EXLOCKEN); + vcpu_set_reg(vcpu, ARM64_CORE_REG(regs.pstate), + PSR_MODE_EL0t | PSR_EXLOCK_BIT); + + events.exception.ext_dabt_pending =3D true; + vcpu_events_set(vcpu, &events); + + pstate =3D vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pstate)); + TEST_ASSERT_EQ(pstate & PSR_MODE_MASK, PSR_MODE_EL2h); + TEST_ASSERT(!(pstate & PSR_EXLOCK_BIT), + "EXLOCK set on exception from a lower EL"); + + kvm_vm_free(vm); +} + +int main(void) +{ + TEST_REQUIRE(kvm_check_cap(KVM_CAP_ARM_EL2)); + test_exception_from_same_el(); + test_exception_from_lower_el(); + + return 0; +} --=20 2.47.3