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b=I71r8HVkZOP7bToJMB6bpPE69cGKKAvOxMgzeLsyJYoqsoEC3XgeK4m3gLJkMGvmQ9UQonJW4bRPeS2hJHLYQ2lrCeM2AhbydG/Xg/gj1ct5tFwc5JrWuTchkXIoRRPKFah8NGtIi8HgSF5uU3AZu9SYdPM5NaxQFepdmiqj4zo= Received: from SEZPR04MB5651.apcprd04.prod.outlook.com (2603:1096:101:48::7) by KU4PR04MB9320.apcprd04.prod.outlook.com (2603:1096:d10:7b::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.292.13; Sun, 2 Aug 2026 13:25:42 +0000 Received: from SEZPR04MB5651.apcprd04.prod.outlook.com ([fe80::b864:dca8:c2ed:e5cc]) by SEZPR04MB5651.apcprd04.prod.outlook.com ([fe80::b864:dca8:c2ed:e5cc%2]) with mapi id 15.21.0292.012; Sun, 2 Aug 2026 13:25:42 +0000 From: Pu Hu To: "peterz@infradead.org" , "mingo@redhat.com" , "acme@kernel.org" , "namhyung@kernel.org" , "mark.rutland@arm.com" , "alexander.shishkin@linux.intel.com" , "jolsa@kernel.org" , "irogers@google.com" , "adrian.hunter@intel.com" , "james.clark@linaro.org" , Pu Hu , "linux-perf-users@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Jiazi Li Subject: [RFC] perf pmu-events: Fix typo in idle-cycles-frontend description Thread-Topic: [RFC] perf pmu-events: Fix typo in idle-cycles-frontend description Thread-Index: AQHdIoJqRUODVN/Z6kS8V68nAzHvPA== Date: Sun, 2 Aug 2026 13:25:42 +0000 Message-ID: <20260802132536.4635-1-hupu@transsion.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=transsion.com; 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charset="utf-8" From: Pu Hu The brief description of the idle-cycles-frontend legacy hardware event refers to its alias as "stalled-cycles-fronted", but there is no such event. The correct event name is "stalled-cycles-frontend". This typo is visible in the output of "perf list", for example: idle-cycles-frontend [Stalled cycles during issue [This event is an alias of stalled-cycles-fronted]. Unit: armv8_pmuv3] Fix the spelling so that the description points to the valid event name. Signed-off-by: Pu Hu --- .../arch/common/common/legacy-hardware.json | 2 +- tools/perf/pmu-events/empty-pmu-events.c | 362 +++++++++--------- 2 files changed, 182 insertions(+), 182 deletions(-) diff --git a/tools/perf/pmu-events/arch/common/common/legacy-hardware.json = b/tools/perf/pmu-events/arch/common/common/legacy-hardware.json index 71700647f19b..ee9f4247e8ae 100644 --- a/tools/perf/pmu-events/arch/common/common/legacy-hardware.json +++ b/tools/perf/pmu-events/arch/common/common/legacy-hardware.json @@ -51,7 +51,7 @@ }, { "EventName": "idle-cycles-frontend", - "BriefDescription": "Stalled cycles during issue [This event is an ali= as of stalled-cycles-fronted].", + "BriefDescription": "Stalled cycles during issue [This event is an ali= as of stalled-cycles-frontend].", "LegacyConfigCode": "7" }, { diff --git a/tools/perf/pmu-events/empty-pmu-events.c b/tools/perf/pmu-even= ts/empty-pmu-events.c index 2af4865713be..7df1552403e7 100644 --- a/tools/perf/pmu-events/empty-pmu-events.c +++ b/tools/perf/pmu-events/empty-pmu-events.c @@ -2474,186 +2474,186 @@ static const char *const big_c_string =3D /* offset=3D122795 */ "stalled-cycles-frontend\000legacy hardware\000Stalled cycles during issue= [This event is an alias of idle-cycles-frontend]\000legacy-hardware-config= =3D7\000\00000\000\000\000\000\000" /* offset=3D122945 */ -"idle-cycles-frontend\000legacy hardware\000Stalled cycles during issue [T= his event is an alias of stalled-cycles-fronted]\000legacy-hardware-config= =3D7\000\00000\000\000\000\000\000" -/* offset=3D123094 */ +"idle-cycles-frontend\000legacy hardware\000Stalled cycles during issue [T= his event is an alias of stalled-cycles-frontend]\000legacy-hardware-config= =3D7\000\00000\000\000\000\000\000" +/* offset=3D123095 */ "stalled-cycles-backend\000legacy hardware\000Stalled cycles during retire= ment [This event is an alias of idle-cycles-backend]\000legacy-hardware-con= fig=3D8\000\00000\000\000\000\000\000" -/* offset=3D123247 */ +/* offset=3D123248 */ "idle-cycles-backend\000legacy hardware\000Stalled cycles during retiremen= t [This event is an alias of stalled-cycles-backend]\000legacy-hardware-con= fig=3D8\000\00000\000\000\000\000\000" -/* offset=3D123400 */ +/* offset=3D123401 */ "ref-cycles\000legacy hardware\000Total cycles; not affected by CPU freque= ncy scaling\000legacy-hardware-config=3D9\000\00000\000\000\000\000\000" -/* offset=3D123512 */ +/* offset=3D123513 */ "software\000" -/* offset=3D123521 */ +/* offset=3D123522 */ "cpu-clock\000software\000Per-CPU high-resolution timer based event\000con= fig=3D0\000\000001e-6msec\000\000\000\000\000" -/* offset=3D123607 */ +/* offset=3D123608 */ "task-clock\000software\000Per-task high-resolution timer based event\000c= onfig=3D1\000\000001e-6msec\000\000\000\000\000" -/* offset=3D123695 */ +/* offset=3D123696 */ "faults\000software\000Number of page faults [This event is an alias of pa= ge-faults]\000config=3D2\000\00000\000\000\000\000\000" -/* offset=3D123790 */ +/* offset=3D123791 */ "page-faults\000software\000Number of page faults [This event is an alias = of faults]\000config=3D2\000\00000\000\000\000\000\000" -/* offset=3D123885 */ +/* offset=3D123886 */ "context-switches\000software\000Number of context switches [This event is= an alias of cs]\000config=3D3\000\00000\000\000\000\000\000" -/* offset=3D123986 */ +/* offset=3D123987 */ "cs\000software\000Number of context switches [This event is an alias of c= ontext-switches]\000config=3D3\000\00000\000\000\000\000\000" -/* offset=3D124087 */ +/* offset=3D124088 */ "cpu-migrations\000software\000Number of times a process has migrated to a= new CPU [This event is an alias of migrations]\000config=3D4\000\00000\000= \000\000\000\000" -/* offset=3D124219 */ +/* offset=3D124220 */ "migrations\000software\000Number of times a process has migrated to a new= CPU [This event is an alias of cpu-migrations]\000config=3D4\000\00000\000= \000\000\000\000" -/* offset=3D124351 */ +/* offset=3D124352 */ "minor-faults\000software\000Number of minor page faults. Minor faults don= 't require I/O to handle\000config=3D5\000\00000\000\000\000\000\000" -/* offset=3D124460 */ +/* offset=3D124461 */ "major-faults\000software\000Number of major page faults. Major faults req= uire I/O to handle\000config=3D6\000\00000\000\000\000\000\000" -/* offset=3D124563 */ +/* offset=3D124564 */ "alignment-faults\000software\000Number of kernel handled memory alignment= faults\000config=3D7\000\00000\000\000\000\000\000" -/* offset=3D124655 */ +/* offset=3D124656 */ "emulation-faults\000software\000Number of kernel handled unimplemented in= struction faults handled through emulation\000config=3D8\000\00000\000\000\= 000\000\000" -/* offset=3D124782 */ +/* offset=3D124783 */ "dummy\000software\000A placeholder event that doesn't count anything\000c= onfig=3D9\000\00000\000\000\000\000\000" -/* offset=3D124862 */ +/* offset=3D124863 */ "bpf-output\000software\000An event used by BPF programs to write to the p= erf ring buffer\000config=3D0xa\000\00000\000\000\000\000\000" -/* offset=3D124964 */ +/* offset=3D124965 */ "cgroup-switches\000software\000Number of context switches to a task in a = different cgroup\000config=3D0xb\000\00000\000\000\000\000\000" -/* offset=3D125067 */ +/* offset=3D125068 */ "tool\000" -/* offset=3D125072 */ +/* offset=3D125073 */ "duration_time\000tool\000Wall clock interval time in nanoseconds\000confi= g=3D1\000\00000\000\000\000\000\000" -/* offset=3D125148 */ +/* offset=3D125149 */ "user_time\000tool\000User (non-kernel) time in nanoseconds\000config=3D2\= 000\00000\000\000\000\000\000" -/* offset=3D125218 */ +/* offset=3D125219 */ "system_time\000tool\000System/kernel time in nanoseconds\000config=3D3\00= 0\00000\000\000\000\000\000" -/* offset=3D125286 */ +/* offset=3D125287 */ "has_pmem\000tool\0001 if persistent memory installed otherwise 0\000confi= g=3D4\000\00000\000\000\000\000\000" -/* offset=3D125362 */ +/* offset=3D125363 */ "num_cores\000tool\000Number of cores. A core consists of 1 or more thread= , with each thread being associated with a logical Linux CPU\000config=3D5\= 000\00000\000\000\000\000\000" -/* offset=3D125507 */ +/* offset=3D125508 */ "num_cpus\000tool\000Number of logical Linux CPUs. There may be multiple s= uch CPUs on a core\000config=3D6\000\00000\000\000\000\000\000" -/* offset=3D125610 */ +/* offset=3D125611 */ "num_cpus_online\000tool\000Number of online logical Linux CPUs. There may= be multiple such CPUs on a core\000config=3D7\000\00000\000\000\000\000\00= 0" -/* offset=3D125727 */ +/* offset=3D125728 */ "num_dies\000tool\000Number of dies. Each die has 1 or more cores\000confi= g=3D8\000\00000\000\000\000\000\000" -/* offset=3D125803 */ +/* offset=3D125804 */ "num_packages\000tool\000Number of packages. Each package has 1 or more di= e\000config=3D9\000\00000\000\000\000\000\000" -/* offset=3D125889 */ +/* offset=3D125890 */ "slots\000tool\000Number of functional units that in parallel can execute = parts of an instruction\000config=3D0xa\000\00000\000\000\000\000\000" -/* offset=3D125999 */ +/* offset=3D126000 */ "smt_on\000tool\0001 if simultaneous multithreading (aka hyperthreading) i= s enable otherwise 0\000config=3D0xb\000\00000\000\000\000\000\000" -/* offset=3D126106 */ +/* offset=3D126107 */ "system_tsc_freq\000tool\000The amount a Time Stamp Counter (TSC) increase= s per second\000config=3D0xc\000\00000\000\000\000\000\000" -/* offset=3D126205 */ +/* offset=3D126206 */ "core_wide\000tool\0001 if not SMT, if SMT are events being gathered on al= l SMT threads 1 otherwise 0\000config=3D0xd\000\00000\000\000\000\000\000" -/* offset=3D126319 */ +/* offset=3D126320 */ "target_cpu\000tool\0001 if CPUs being analyzed, 0 if threads/processes\00= 0config=3D0xe\000\00000\000\000\000\000\000" -/* offset=3D126403 */ +/* offset=3D126404 */ "bp_l1_btb_correct\000branch\000L1 BTB Correction\000event=3D0x8a\000\0000= 0\000\000\000\000\000" -/* offset=3D126465 */ +/* offset=3D126466 */ "bp_l2_btb_correct\000branch\000L2 BTB Correction\000event=3D0x8b\000\0000= 0\000\000\000\000\000" -/* offset=3D126527 */ +/* offset=3D126528 */ "l3_cache_rd\000cache\000L3 cache access, read\000event=3D0x40\000\00000\0= 00\000\000\000Attributable Level 3 cache access, read\000" -/* offset=3D126625 */ +/* offset=3D126626 */ "segment_reg_loads.any\000other\000Number of segment register loads\000eve= nt=3D6,period=3D200000,umask=3D0x80\000\00000\000\000\000\000\000" -/* offset=3D126727 */ +/* offset=3D126728 */ "dispatch_blocked.any\000other\000Memory cluster signals to block micro-op= dispatch for any reason\000event=3D9,period=3D200000,umask=3D0x20\000\0000= 0\000\000\000\000\000" -/* offset=3D126860 */ +/* offset=3D126861 */ "eist_trans\000other\000Number of Enhanced Intel SpeedStep(R) Technology (= EIST) transitions\000event=3D0x3a,period=3D200000\000\00000\000\000\000\000= \000" -/* offset=3D126978 */ +/* offset=3D126979 */ "hisi_sccl,ddrc\000" -/* offset=3D126993 */ +/* offset=3D126994 */ "uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write commands\000event=3D2\= 000\00000\000\000\000\000\000" -/* offset=3D127063 */ +/* offset=3D127064 */ "uncore_cbox\000" -/* offset=3D127075 */ +/* offset=3D127076 */ "unc_cbo_xsnp_response.miss_eviction\000uncore\000A cross-core snoop resul= ted from L3 Eviction which misses in some processor core\000event=3D0x22,um= ask=3D0x81\000\00000\000\000\000\000\000" -/* offset=3D127229 */ +/* offset=3D127230 */ "event-hyphen\000uncore\000UNC_CBO_HYPHEN\000event=3D0xe0\000\00000\000\00= 0\000\000\000" -/* offset=3D127283 */ +/* offset=3D127284 */ "event-two-hyph\000uncore\000UNC_CBO_TWO_HYPH\000event=3D0xc0\000\00000\00= 0\000\000\000\000" -/* offset=3D127341 */ +/* offset=3D127342 */ "hisi_sccl,l3c\000" -/* offset=3D127355 */ +/* offset=3D127356 */ "uncore_hisi_l3c.rd_hit_cpipe\000uncore\000Total read hits\000event=3D7\00= 0\00000\000\000\000\000\000" -/* offset=3D127423 */ +/* offset=3D127424 */ "uncore_imc_free_running\000" -/* offset=3D127447 */ +/* offset=3D127448 */ "uncore_imc_free_running.cache_miss\000uncore\000Total cache misses\000eve= nt=3D0x12\000\00000\000\000\000\000\000" -/* offset=3D127527 */ +/* offset=3D127528 */ "uncore_imc\000" -/* offset=3D127538 */ +/* offset=3D127539 */ "uncore_imc.cache_hits\000uncore\000Total cache hits\000event=3D0x34\000\0= 0000\000\000\000\000\000" -/* offset=3D127603 */ +/* offset=3D127604 */ "uncore_sys_ddr_pmu\000" -/* offset=3D127622 */ +/* offset=3D127623 */ "sys_ddr_pmu.write_cycles\000uncore\000ddr write-cycles event\000event=3D0= x2b\000v8\00000\000\000\000\000\000" -/* offset=3D127698 */ +/* offset=3D127699 */ "uncore_sys_ccn_pmu\000" -/* offset=3D127717 */ +/* offset=3D127718 */ "sys_ccn_pmu.read_cycles\000uncore\000ccn read-cycles event\000config=3D0x= 2c\0000x01\00000\000\000\000\000\000" -/* offset=3D127794 */ +/* offset=3D127795 */ "uncore_sys_cmn_pmu\000" -/* offset=3D127813 */ +/* offset=3D127814 */ "sys_cmn_pmu.hnf_cache_miss\000uncore\000Counts total cache misses in firs= t lookup result (high priority)\000eventid=3D1,type=3D5\000(434|436|43c|43a= ).*\00000\000\000\000\000\000" -/* offset=3D127956 */ +/* offset=3D127957 */ "CPUs_utilized\000Default\000(software@cpu\\-clock\\,name\\=3Dcpu\\-clock@= if #target_cpu else software@task\\-clock\\,name\\=3Dtask\\-clock@) / (dur= ation_time * 1e9)\000\000Average CPU utilization\000\0001CPUs\000\000\000\0= 00011" -/* offset=3D128142 */ +/* offset=3D128143 */ "cs_per_second\000Default\000software@context\\-switches\\,name\\=3Dcontex= t\\-switches@ * 1e9 / (software@cpu\\-clock\\,name\\=3Dcpu\\-clock@ if #tar= get_cpu else software@task\\-clock\\,name\\=3Dtask\\-clock@)\000\000Context= switches per CPU second\000\0001cs/sec\000\000\000\000011" -/* offset=3D128375 */ +/* offset=3D128376 */ "migrations_per_second\000Default\000software@cpu\\-migrations\\,name\\=3D= cpu\\-migrations@ * 1e9 / (software@cpu\\-clock\\,name\\=3Dcpu\\-clock@ if = #target_cpu else software@task\\-clock\\,name\\=3Dtask\\-clock@)\000\000Pro= cess migrations to a new CPU per CPU second\000\0001migrations/sec\000\000\= 000\000011" -/* offset=3D128635 */ +/* offset=3D128636 */ "page_faults_per_second\000Default\000software@page\\-faults\\,name\\=3Dpa= ge\\-faults@ * 1e9 / (software@cpu\\-clock\\,name\\=3Dcpu\\-clock@ if #targ= et_cpu else software@task\\-clock\\,name\\=3Dtask\\-clock@)\000\000Page fau= lts per CPU second\000\0001faults/sec\000\000\000\000011" -/* offset=3D128866 */ +/* offset=3D128867 */ "insn_per_cycle\000Default\000instructions / cpu\\-cycles\000insn_per_cycl= e < 1\000Instructions Per Cycle\000\0001instructions\000\000\000\000001" -/* offset=3D128979 */ +/* offset=3D128980 */ "stalled_cycles_per_instruction\000Default\000(max(stalled\\-cycles\\-fron= tend, stalled\\-cycles\\-backend) / instructions if has_event(stalled\\-cyc= les\\-frontend) & has_event(stalled\\-cycles\\-backend) else (stalled\\-cyc= les\\-frontend / instructions if has_event(stalled\\-cycles\\-frontend) els= e (stalled\\-cycles\\-backend / instructions if has_event(stalled\\-cycles\= \-backend) else 0)))\000\000Max front or backend stalls per instruction\000= \000\000\000\000\000001" -/* offset=3D129404 */ +/* offset=3D129405 */ "frontend_cycles_idle\000Default\000(stalled\\-cycles\\-frontend / cpu\\-c= ycles if has_event(stalled\\-cycles\\-frontend) else 0)\000frontend_cycles_= idle > 0.1\000Frontend stalls per cycle\000\000\000\000\000\000001" -/* offset=3D129583 */ +/* offset=3D129584 */ "backend_cycles_idle\000Default\000(stalled\\-cycles\\-backend / cpu\\-cyc= les if has_event(stalled\\-cycles\\-backend) else 0)\000backend_cycles_idle= > 0.2\000Backend stalls per cycle\000\000\000\000\000\000001" -/* offset=3D129757 */ +/* offset=3D129758 */ "cycles_frequency\000Default\000cpu\\-cycles / (software@cpu\\-clock\\,nam= e\\=3Dcpu\\-clock@ if #target_cpu else software@task\\-clock\\,name\\=3Dtas= k\\-clock@)\000\000Cycles per CPU second\000\0001GHz\000\000\000\000011" -/* offset=3D129933 */ +/* offset=3D129934 */ "branch_frequency\000Default\000branches / (software@cpu\\-clock\\,name\\= =3Dcpu\\-clock@ if #target_cpu else software@task\\-clock\\,name\\=3Dtask\\= -clock@)\000\000Branches per CPU second\000\0001000M/sec\000\000\000\000011" -/* offset=3D130113 */ +/* offset=3D130114 */ "branch_miss_rate\000Default\000branch\\-misses / branches\000branch_miss_= rate > 0.05\000Branch miss rate\000\000100%\000\000\000\000001" -/* offset=3D130217 */ +/* offset=3D130218 */ "l1d_miss_rate\000Default2\000L1\\-dcache\\-load\\-misses / L1\\-dcache\\-= loads\000l1d_miss_rate > 0.05\000L1D miss rate\000\000100%\000\000\000\000= 001" -/* offset=3D130333 */ +/* offset=3D130334 */ "llc_miss_rate\000Default2\000LLC\\-load\\-misses / LLC\\-loads\000llc_mis= s_rate > 0.05\000LLC miss rate\000\000100%\000\000\000\000001" -/* offset=3D130434 */ +/* offset=3D130435 */ "l1i_miss_rate\000Default3\000L1\\-icache\\-load\\-misses / L1\\-icache\\-= loads\000l1i_miss_rate > 0.05\000L1I miss rate\000\000100%\000\000\000\0000= 01" -/* offset=3D130549 */ +/* offset=3D130550 */ "dtlb_miss_rate\000Default3\000dTLB\\-load\\-misses / dTLB\\-loads\000dtlb= _miss_rate > 0.05\000dTLB miss rate\000\000100%\000\000\000\000001" -/* offset=3D130655 */ +/* offset=3D130656 */ "itlb_miss_rate\000Default3\000iTLB\\-load\\-misses / iTLB\\-loads\000itlb= _miss_rate > 0.05\000iTLB miss rate\000\000100%\000\000\000\000001" -/* offset=3D130761 */ +/* offset=3D130762 */ "l1_prefetch_miss_rate\000Default4\000L1\\-dcache\\-prefetch\\-misses / L1= \\-dcache\\-prefetches\000l1_prefetch_miss_rate > 0.05\000L1 prefetch miss = rate\000\000100%\000\000\000\000001" -/* offset=3D130909 */ +/* offset=3D130910 */ "CPI\000\0001 / IPC\000\000\000\000\000\000\000\000000" -/* offset=3D130932 */ +/* offset=3D130933 */ "IPC\000group1\000inst_retired.any / cpu_clk_unhalted.thread\000\000\000\0= 00\000\000\000\000000" -/* offset=3D130996 */ +/* offset=3D130997 */ "Frontend_Bound_SMT\000\000idq_uops_not_delivered.core / (4 * (cpu_clk_unh= alted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalt= ed.ref_xclk)))\000\000\000\000\000\000\000\000000" -/* offset=3D131163 */ +/* offset=3D131164 */ "dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_retired.any\000\000\00= 0\000\000\000\000\000000" -/* offset=3D131228 */ +/* offset=3D131229 */ "icache_miss_cycles\000\000l1i\\-loads\\-misses / inst_retired.any\000\000= \000\000\000\000\000\000000" -/* offset=3D131296 */ +/* offset=3D131297 */ "cache_miss_cycles\000group1\000dcache_miss_cpi + icache_miss_cycles\000\0= 00\000\000\000\000\000\000000" -/* offset=3D131368 */ +/* offset=3D131369 */ "DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_hit + l2_rqsts.pf_hit += l2_rqsts.rfo_hit\000\000\000\000\000\000\000\000000" -/* offset=3D131463 */ +/* offset=3D131464 */ "DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_data_rd - l2_rqsts.dema= nd_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss\000\000\000\000\0= 00\000\000\000000" -/* offset=3D131598 */ +/* offset=3D131599 */ "DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2_All_Miss\000\000\000\= 000\000\000\000\000000" -/* offset=3D131663 */ +/* offset=3D131664 */ "DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, DCache_L2_All)\000\000\= 000\000\000\000\000\000000" -/* offset=3D131732 */ +/* offset=3D131733 */ "DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss, DCache_L2_All)\000\00= 0\000\000\000\000\000\000000" -/* offset=3D131803 */ +/* offset=3D131804 */ "M1\000\000ipc + M2\000\000\000\000\000\000\000\000000" -/* offset=3D131826 */ +/* offset=3D131827 */ "M2\000\000ipc + M1\000\000\000\000\000\000\000\000000" -/* offset=3D131849 */ +/* offset=3D131850 */ "M3\000\0001 / M3\000\000\000\000\000\000\000\000000" -/* offset=3D131870 */ +/* offset=3D131871 */ "L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9 / duration_time\000\0= 00\000\000\000\000\000\000000" ; =20 @@ -3469,7 +3469,7 @@ static const struct compact_pmu_event pmu_events__com= mon_default_core[] =3D { /* i-tlb-refs\000legacy cache\000Instruction TLB read accesses\000legacy-= cache-conf... */ { 97543 }, /* idle-cycles-backend\000legacy hardware\000Stalled cycles during retire= ment [This... */ - { 123247 }, + { 123248 }, /* idle-cycles-frontend\000legacy hardware\000Stalled cycles during issue= [This eve... */ { 122945 }, /* instruction-tlb\000legacy cache\000Instruction TLB read accesses\000le= gacy-cache... */ @@ -5113,73 +5113,73 @@ static const struct compact_pmu_event pmu_events__c= ommon_default_core[] =3D { /* node-write-refs\000legacy cache\000Local memory write accesses\000lega= cy-cache-c... */ { 117401 }, /* ref-cycles\000legacy hardware\000Total cycles; not affected by CPU fre= quency sca... */ - { 123400 }, + { 123401 }, /* stalled-cycles-backend\000legacy hardware\000Stalled cycles during ret= irement [T... */ - { 123094 }, + { 123095 }, /* stalled-cycles-frontend\000legacy hardware\000Stalled cycles during is= sue [This ... */ { 122795 }, }; static const struct compact_pmu_event pmu_events__common_software[] =3D { /* alignment-faults\000software\000Number of kernel handled memory alignm= ent faults... */ - { 124563 }, + { 124564 }, /* bpf-output\000software\000An event used by BPF programs to write to th= e perf rin... */ - { 124862 }, + { 124863 }, /* cgroup-switches\000software\000Number of context switches to a task in= a differe... */ - { 124964 }, + { 124965 }, /* context-switches\000software\000Number of context switches [This event= is an ali... */ - { 123885 }, + { 123886 }, /* cpu-clock\000software\000Per-CPU high-resolution timer based event\000= config=3D0\0... */ - { 123521 }, + { 123522 }, /* cpu-migrations\000software\000Number of times a process has migrated t= o a new CP... */ - { 124087 }, + { 124088 }, /* cs\000software\000Number of context switches [This event is an alias o= f context-... */ - { 123986 }, + { 123987 }, /* dummy\000software\000A placeholder event that doesn't count anything\0= 00config=3D9... */ - { 124782 }, + { 124783 }, /* emulation-faults\000software\000Number of kernel handled unimplemented= instructi... */ - { 124655 }, + { 124656 }, /* faults\000software\000Number of page faults [This event is an alias of= page-faul... */ - { 123695 }, + { 123696 }, /* major-faults\000software\000Number of major page faults. Major faults = require I/... */ - { 124460 }, + { 124461 }, /* migrations\000software\000Number of times a process has migrated to a = new CPU [T... */ - { 124219 }, + { 124220 }, /* minor-faults\000software\000Number of minor page faults. Minor faults = don't requ... */ - { 124351 }, + { 124352 }, /* page-faults\000software\000Number of page faults [This event is an ali= as of faul... */ - { 123790 }, + { 123791 }, /* task-clock\000software\000Per-task high-resolution timer based event\0= 00config=3D1... */ - { 123607 }, + { 123608 }, }; static const struct compact_pmu_event pmu_events__common_tool[] =3D { /* core_wide\000tool\0001 if not SMT, if SMT are events being gathered on= all SMT t... */ - { 126205 }, + { 126206 }, /* duration_time\000tool\000Wall clock interval time in nanoseconds\000co= nfig=3D1\000... */ - { 125072 }, + { 125073 }, /* has_pmem\000tool\0001 if persistent memory installed otherwise 0\000co= nfig=3D4\000... */ - { 125286 }, + { 125287 }, /* num_cores\000tool\000Number of cores. A core consists of 1 or more thr= ead, with ... */ - { 125362 }, + { 125363 }, /* num_cpus\000tool\000Number of logical Linux CPUs. There may be multipl= e such CPU... */ - { 125507 }, + { 125508 }, /* num_cpus_online\000tool\000Number of online logical Linux CPUs. There = may be mul... */ - { 125610 }, + { 125611 }, /* num_dies\000tool\000Number of dies. Each die has 1 or more cores\000co= nfig=3D8\000... */ - { 125727 }, + { 125728 }, /* num_packages\000tool\000Number of packages. Each package has 1 or more= die\000co... */ - { 125803 }, + { 125804 }, /* slots\000tool\000Number of functional units that in parallel can execu= te parts o... */ - { 125889 }, + { 125890 }, /* smt_on\000tool\0001 if simultaneous multithreading (aka hyperthreading= ) is enabl... */ - { 125999 }, + { 126000 }, /* system_time\000tool\000System/kernel time in nanoseconds\000config=3D3= \000\00000\0... */ - { 125218 }, + { 125219 }, /* system_tsc_freq\000tool\000The amount a Time Stamp Counter (TSC) incre= ases per s... */ - { 126106 }, + { 126107 }, /* target_cpu\000tool\0001 if CPUs being analyzed, 0 if threads/processes= \000config... */ - { 126319 }, + { 126320 }, /* user_time\000tool\000User (non-kernel) time in nanoseconds\000config= =3D2\000\00000... */ - { 125148 }, + { 125149 }, =20 }; =20 @@ -5192,50 +5192,50 @@ static const struct pmu_table_entry pmu_events__com= mon[] =3D { { .entries =3D pmu_events__common_software, .num_entries =3D ARRAY_SIZE(pmu_events__common_software), - .pmu_name =3D { 123512 /* software\000 */ }, + .pmu_name =3D { 123513 /* software\000 */ }, }, { .entries =3D pmu_events__common_tool, .num_entries =3D ARRAY_SIZE(pmu_events__common_tool), - .pmu_name =3D { 125067 /* tool\000 */ }, + .pmu_name =3D { 125068 /* tool\000 */ }, }, }; =20 static const struct compact_pmu_event pmu_metrics__common_default_core[] = =3D { /* CPUs_utilized\000Default\000(software@cpu\\-clock\\,name\\=3Dcpu\\-clo= ck@ if #targ... */ - { 127956 }, + { 127957 }, /* backend_cycles_idle\000Default\000(stalled\\-cycles\\-backend / cpu\\-= cycles if ... */ - { 129583 }, + { 129584 }, /* branch_frequency\000Default\000branches / (software@cpu\\-clock\\,name= \\=3Dcpu\\-c... */ - { 129933 }, + { 129934 }, /* branch_miss_rate\000Default\000branch\\-misses / branches\000branch_mi= ss_rate > ... */ - { 130113 }, + { 130114 }, /* cs_per_second\000Default\000software@context\\-switches\\,name\\=3Dcon= text\\-switc... */ - { 128142 }, + { 128143 }, /* cycles_frequency\000Default\000cpu\\-cycles / (software@cpu\\-clock\\,= name\\=3Dcpu... */ - { 129757 }, + { 129758 }, /* dtlb_miss_rate\000Default3\000dTLB\\-load\\-misses / dTLB\\-loads\000d= tlb_miss_r... */ - { 130549 }, + { 130550 }, /* frontend_cycles_idle\000Default\000(stalled\\-cycles\\-frontend / cpu\= \-cycles i... */ - { 129404 }, + { 129405 }, /* insn_per_cycle\000Default\000instructions / cpu\\-cycles\000insn_per_c= ycle < 1\0... */ - { 128866 }, + { 128867 }, /* itlb_miss_rate\000Default3\000iTLB\\-load\\-misses / iTLB\\-loads\000i= tlb_miss_r... */ - { 130655 }, + { 130656 }, /* l1_prefetch_miss_rate\000Default4\000L1\\-dcache\\-prefetch\\-misses /= L1\\-dcac... */ - { 130761 }, + { 130762 }, /* l1d_miss_rate\000Default2\000L1\\-dcache\\-load\\-misses / L1\\-dcache= \\-loads\0... */ - { 130217 }, + { 130218 }, /* l1i_miss_rate\000Default3\000L1\\-icache\\-load\\-misses / L1\\-icache= \\-loads\0... */ - { 130434 }, + { 130435 }, /* llc_miss_rate\000Default2\000LLC\\-load\\-misses / LLC\\-loads\000llc_= miss_rate ... */ - { 130333 }, + { 130334 }, /* migrations_per_second\000Default\000software@cpu\\-migrations\\,name\\= =3Dcpu\\-mig... */ - { 128375 }, + { 128376 }, /* page_faults_per_second\000Default\000software@page\\-faults\\,name\\= =3Dpage\\-faul... */ - { 128635 }, + { 128636 }, /* stalled_cycles_per_instruction\000Default\000(max(stalled\\-cycles\\-f= rontend, s... */ - { 128979 }, + { 128980 }, =20 }; =20 @@ -5249,41 +5249,41 @@ static const struct pmu_table_entry pmu_metrics__co= mmon[] =3D { =20 static const struct compact_pmu_event pmu_events__test_soc_cpu_default_cor= e[] =3D { /* bp_l1_btb_correct\000branch\000L1 BTB Correction\000event=3D0x8a\000\0= 0000\000\000... */ - { 126403 }, + { 126404 }, /* bp_l2_btb_correct\000branch\000L2 BTB Correction\000event=3D0x8b\000\0= 0000\000\000... */ - { 126465 }, + { 126466 }, /* dispatch_blocked.any\000other\000Memory cluster signals to block micro= -op dispat... */ - { 126727 }, + { 126728 }, /* eist_trans\000other\000Number of Enhanced Intel SpeedStep(R) Technolog= y (EIST) t... */ - { 126860 }, + { 126861 }, /* l3_cache_rd\000cache\000L3 cache access, read\000event=3D0x40\000\0000= 0\000\000\00... */ - { 126527 }, + { 126528 }, /* segment_reg_loads.any\000other\000Number of segment register loads\000= event=3D6,pe... */ - { 126625 }, + { 126626 }, }; static const struct compact_pmu_event pmu_events__test_soc_cpu_hisi_sccl_d= drc[] =3D { /* uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write commands\000event= =3D2\000\00000... */ - { 126993 }, + { 126994 }, }; static const struct compact_pmu_event pmu_events__test_soc_cpu_hisi_sccl_l= 3c[] =3D { /* uncore_hisi_l3c.rd_hit_cpipe\000uncore\000Total read hits\000event=3D7= \000\00000\0... */ - { 127355 }, + { 127356 }, }; static const struct compact_pmu_event pmu_events__test_soc_cpu_uncore_cbox= [] =3D { /* event-hyphen\000uncore\000UNC_CBO_HYPHEN\000event=3D0xe0\000\00000\000= \000\000\000... */ - { 127229 }, + { 127230 }, /* event-two-hyph\000uncore\000UNC_CBO_TWO_HYPH\000event=3D0xc0\000\00000= \000\000\000... */ - { 127283 }, + { 127284 }, /* unc_cbo_xsnp_response.miss_eviction\000uncore\000A cross-core snoop re= sulted fro... */ - { 127075 }, + { 127076 }, }; static const struct compact_pmu_event pmu_events__test_soc_cpu_uncore_imc[= ] =3D { /* uncore_imc.cache_hits\000uncore\000Total cache hits\000event=3D0x34\00= 0\00000\000\... */ - { 127538 }, + { 127539 }, }; static const struct compact_pmu_event pmu_events__test_soc_cpu_uncore_imc_= free_running[] =3D { /* uncore_imc_free_running.cache_miss\000uncore\000Total cache misses\000= event=3D0x12... */ - { 127447 }, + { 127448 }, =20 }; =20 @@ -5296,61 +5296,61 @@ static const struct pmu_table_entry pmu_events__tes= t_soc_cpu[] =3D { { .entries =3D pmu_events__test_soc_cpu_hisi_sccl_ddrc, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_cpu_hisi_sccl_ddrc), - .pmu_name =3D { 126978 /* hisi_sccl,ddrc\000 */ }, + .pmu_name =3D { 126979 /* hisi_sccl,ddrc\000 */ }, }, { .entries =3D pmu_events__test_soc_cpu_hisi_sccl_l3c, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_cpu_hisi_sccl_l3c), - .pmu_name =3D { 127341 /* hisi_sccl,l3c\000 */ }, + .pmu_name =3D { 127342 /* hisi_sccl,l3c\000 */ }, }, { .entries =3D pmu_events__test_soc_cpu_uncore_cbox, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_cpu_uncore_cbox), - .pmu_name =3D { 127063 /* uncore_cbox\000 */ }, + .pmu_name =3D { 127064 /* uncore_cbox\000 */ }, }, { .entries =3D pmu_events__test_soc_cpu_uncore_imc, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_cpu_uncore_imc), - .pmu_name =3D { 127527 /* uncore_imc\000 */ }, + .pmu_name =3D { 127528 /* uncore_imc\000 */ }, }, { .entries =3D pmu_events__test_soc_cpu_uncore_imc_free_running, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_cpu_uncore_imc_free_run= ning), - .pmu_name =3D { 127423 /* uncore_imc_free_running\000 */ }, + .pmu_name =3D { 127424 /* uncore_imc_free_running\000 */ }, }, }; =20 static const struct compact_pmu_event pmu_metrics__test_soc_cpu_default_co= re[] =3D { /* CPI\000\0001 / IPC\000\000\000\000\000\000\000\000000 */ - { 130909 }, + { 130910 }, /* DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2_All_Miss\000\000\0= 00\000\000... */ - { 131598 }, + { 131599 }, /* DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_hit + l2_rqsts.pf_hi= t + l2_rqs... */ - { 131368 }, + { 131369 }, /* DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_data_rd - l2_rqsts.d= emand_data... */ - { 131463 }, + { 131464 }, /* DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, DCache_L2_All)\000\0= 00\000\000... */ - { 131663 }, + { 131664 }, /* DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss, DCache_L2_All)\000= \000\000\0... */ - { 131732 }, + { 131733 }, /* Frontend_Bound_SMT\000\000idq_uops_not_delivered.core / (4 * (cpu_clk_= unhalted.t... */ - { 130996 }, + { 130997 }, /* IPC\000group1\000inst_retired.any / cpu_clk_unhalted.thread\000\000\00= 0\000\000\... */ - { 130932 }, + { 130933 }, /* L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9 / duration_time\00= 0\000\000\... */ - { 131870 }, + { 131871 }, /* M1\000\000ipc + M2\000\000\000\000\000\000\000\000000 */ - { 131803 }, + { 131804 }, /* M2\000\000ipc + M1\000\000\000\000\000\000\000\000000 */ - { 131826 }, + { 131827 }, /* M3\000\0001 / M3\000\000\000\000\000\000\000\000000 */ - { 131849 }, + { 131850 }, /* cache_miss_cycles\000group1\000dcache_miss_cpi + icache_miss_cycles\00= 0\000\000\... */ - { 131296 }, + { 131297 }, /* dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_retired.any\000\000= \000\000\0... */ - { 131163 }, + { 131164 }, /* icache_miss_cycles\000\000l1i\\-loads\\-misses / inst_retired.any\000\= 000\000\00... */ - { 131228 }, + { 131229 }, =20 }; =20 @@ -5364,15 +5364,15 @@ static const struct pmu_table_entry pmu_metrics__te= st_soc_cpu[] =3D { =20 static const struct compact_pmu_event pmu_events__test_soc_sys_uncore_sys_= ccn_pmu[] =3D { /* sys_ccn_pmu.read_cycles\000uncore\000ccn read-cycles event\000config= =3D0x2c\0000x0... */ - { 127717 }, + { 127718 }, }; static const struct compact_pmu_event pmu_events__test_soc_sys_uncore_sys_= cmn_pmu[] =3D { /* sys_cmn_pmu.hnf_cache_miss\000uncore\000Counts total cache misses in f= irst looku... */ - { 127813 }, + { 127814 }, }; static const struct compact_pmu_event pmu_events__test_soc_sys_uncore_sys_= ddr_pmu[] =3D { /* sys_ddr_pmu.write_cycles\000uncore\000ddr write-cycles event\000event= =3D0x2b\000v8... */ - { 127622 }, + { 127623 }, =20 }; =20 @@ -5380,17 +5380,17 @@ static const struct pmu_table_entry pmu_events__tes= t_soc_sys[] =3D { { .entries =3D pmu_events__test_soc_sys_uncore_sys_ccn_pmu, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_sys_uncore_sys_ccn_pmu), - .pmu_name =3D { 127698 /* uncore_sys_ccn_pmu\000 */ }, + .pmu_name =3D { 127699 /* uncore_sys_ccn_pmu\000 */ }, }, { .entries =3D pmu_events__test_soc_sys_uncore_sys_cmn_pmu, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_sys_uncore_sys_cmn_pmu), - .pmu_name =3D { 127794 /* uncore_sys_cmn_pmu\000 */ }, + .pmu_name =3D { 127795 /* uncore_sys_cmn_pmu\000 */ }, }, { .entries =3D pmu_events__test_soc_sys_uncore_sys_ddr_pmu, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_sys_uncore_sys_ddr_pmu), - .pmu_name =3D { 127603 /* uncore_sys_ddr_pmu\000 */ }, + .pmu_name =3D { 127604 /* uncore_sys_ddr_pmu\000 */ }, }, }; =20 --=20 2.43.0