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Sun, 02 Aug 2026 13:34:06 -0700 (PDT) From: =?utf-8?q?Stefan_D=C3=B6singer?= Date: Sun, 02 Aug 2026 23:33:33 +0300 Subject: [PATCH v9 01/12] dt-bindings: clk: zte: Add zx297520v3 top clock and reset controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260802-zx29clk-v9-1-d05530d85d28@gmail.com> References: <20260802-zx29clk-v9-0-d05530d85d28@gmail.com> In-Reply-To: <20260802-zx29clk-v9-0-d05530d85d28@gmail.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Brian Masney , Vinod Koul , Neil Armstrong , Russell King , Lee Jones Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, mfd@lists.linux.dev, =?utf-8?q?Stefan_D=C3=B6singer?= X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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a=openpgp; fpr=4F9C2C8728019633893EBBB98CB81F9A72BBA155 These SoCs have 3 clock and reset controllers: Top, Matrix and LSP. Clocks go from oscillator -> top -> matrix -> LSP, with a register in top controlling most clocks that get passed to matrix and a register in matrix controlling all the clocks that get passed to LSP. Generally every device has two clocks (one work clock, and one that connects it to the bus, I call it PCLK), two reset bits (I don't know what the difference is - sometimes asserting one is enough to reset the device, sometimes both need to be asserted). PCLK and WCLK are controlled by individual gates. Some devices have a mux and/or a divider for their work clock. Some devices, like the GPIO controller, only have reset bits and no clocks. The top clock controller is fed by a 26 MHz external oscillator and has 4 PLLs to generate other clock rates. ZTE's kernel mostly relies on the boot ROM to set up PLLs, but one LTE-related PLL is not configured on some boards. Therefore my driver contains code to program PLLs. It produces identical settings as the boot ROM for the pre-programmed frequencies. Not all clocks will have an explicit user in the end. I am defining a lot of them simply to shut them off. The boot loader sets up a few of the proprietary timers, which will send regular IRQs (although the kernel of course doesn't need to listen to them). I don't plan to add a driver for the proprietary timer as I see no use for them - the ARM arch timer works just fine. I will add a driver for the very similar proprietary watchdog though. The clock list in this patch is pretty complete but not exhaustive. There are other bits that are enabled, but I couldn't deduce what they are controlling by trial and error. Some of them seem to do nothing. Others cause an instant hang of the board when disabled. It is quite likely that a handful more clocks will be added in the future, but not a large number. Signed-off-by: Stefan D=C3=B6singer Reviewed-by: Krzysztof Kozlowski --- Changes v8->v9: *) "unevaluatedProperties: false" for the syscon child node (Krzysztof) *) "additionalProperties: false" for the binding itself (Krzysztof) *) Remove USB PHY resets, but USB controller resets remain unchanged (Krzysztof) *) Rename syscon reboot node to "reboot". While both "reboot" and "syscon-reboot" are common in actual device trees, syscon-reboot.yaml's own example uses "reboot". DT's Generic Names Recommendation contains neither (Sashiko, patch 12) Changes v7->v8 (all Krzysztof): *) Fold the PHY into the top-level node *) Start clock indices at 0 *) Rename the phy include file to zte,zx297520v3-topcrm.h. And a non-change despite/because of new discoveries: USB has more PHY and DWC controls in a different controller at 0x140000. ZTE calls this controller SOC_SYS, and it is a textbook case for syscon: It has a lot of different controls: A remap flag for boot ROM, a control to bring the A53 up in arm32 vs aarch64 mode, the entrypoint of the LTE DSP, SDIO, I2S, ... USB-wise it has a register with PHY and DWC controls: Endianness for the DWC2 registers, PHY clock adjustments, PHY and DWC host/device switch. In spite of this I think topcrm is the better home for #phy-cells: The USB ready flags in topcrm are essential for bringing up the USB devices whereas the soc_sys controls are a curiosity. Host mode only works if I externally inject VBUS. Clock adjustment is too inflexible to be of real value. Flipping the DWC registers to big endian works, but what for? If I find a use case for changing the default USB values in soc_sys it can be handled via syscon. soc_sys also has power controls for a few devices, including USB. This will be handled via #power-domain-cells. The self-referencing reset property causes the following boot messages: /soc/clock-controller@13b000: Fixed dependency cycle(s) with /soc/clock-controller@13b000 /soc/clock-controller@13b000: Fixed dependency cycle(s) with /soc/clock-controller@13b000 Do I need to add post-init-providers? As far as I understand it, this message is informational and not a problem that needs to be addressed. Changes v6->v7: *) Moved the bindings back into clock/ (Krzysztof). Use clock-controller@ in example and in the later DTSI patch. *) With a lucky find in strings in LTE's cpko.ko blob I could make sense of the register that controls which clocks get passed from PLLs into the clock distribution inside topcrm. Importantly that also narrows which clocks can possibly be passed to Matrix, so I could slim down the bindings considerably. *) Add a usb phy child node with the phy schema added in the previous patch. I don't expect the USB status register to ever be in another place, so the binding expresses the @84 expectation. Changes v5->v6: Set value for syscon-reboot example (Sashiko). It was my intention to set only the lowest bit, and I think Sashiko is right that without 'value' being set, all other bits are actively set to 0. It shouldn't matter given my understanding of the hardware (afaics all other bits are ignored), but actively clearing bits was not my intention. I haven't changed the name match for "syscon-reboot". I see plenty of examples of hardcoding this string as opposed to having a regex for syscon-reboot@12345678 in other bindings. Changes v4->v5: Rename from zte,zx297520v3-topclk to zte,zx297520v3-topcrm and move to soc/zte Fix path in MAINTAINERS Add syscon-reboot node to the binding Give the USB and HSIC PHY resets their own reset control --- .../bindings/clock/zte,zx297520v3-topcrm.yaml | 122 +++++++++++++++++= ++++ MAINTAINERS | 4 + include/dt-bindings/clock/zte,zx297520v3-clk.h | 66 +++++++++++ include/dt-bindings/phy/zte,zx297520v3-topcrm.h | 12 ++ include/dt-bindings/reset/zte,zx297520v3-reset.h | 30 +++++ 5 files changed, 234 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/zte,zx297520v3-topcrm.= yaml b/Documentation/devicetree/bindings/clock/zte,zx297520v3-topcrm.yaml new file mode 100644 index 000000000000..ecd332f421b9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/zte,zx297520v3-topcrm.yaml @@ -0,0 +1,122 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/zte,zx297520v3-topcrm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ZTE zx297520v3 SoC top clock and reset controller + +maintainers: + - Stefan D=C3=B6singer + +description: | + The zx297520v3 top clock and reset controller generates clocks for core + devices on the board like the main bus, USB and timers. In addition to c= locks + it has reset controls for peripherals, a global board reset, watchdog re= set + controls and a USB status register. + + The controller has two clock inputs: a 26 MHz and a 32 kHz external + oscillator. They need to be provided as input clocks. The controller pro= vides + PLL output frequencies to downstream clock controllers. + + The USB PHY is exposed as two PHYs, one for USB and another for HSIC. No= te + that while the controls for both PHYs are always present, the PHYs thems= elves + may be absent. If this is the case the controller never signals that the + missing PHY is ready. + + All available clocks are defined as preprocessor macros in the + "include/dt-bindings/clock/zte,zx297520v3-clk.h" header. The resets are + defined in the "include/dt-bindings/reset/zte,zx297520v3-reset.h" header= . PHY + defines are found in "include/dt-bindings/phy/zte,zx297520v3-topcrm.h". + +properties: + compatible: + items: + - const: zte,zx297520v3-topcrm + - const: syscon + + reg: + maxItems: 1 + + clocks: + items: + - description: 26 MHz external oscillator + - description: 32 kHz external oscillator + + clock-names: + items: + - const: osc26m + - const: osc32k + + interrupts: + items: + - description: IRQ reporting USB connection + - description: IRQ reporting USB disconnection + - description: IRQ reporting HSIC connection + - description: IRQ reporting HSIC disconnection + + interrupt-names: + items: + - const: usb-up + - const: usb-down + - const: hsic-up + - const: hsic-down + + "#clock-cells": + const: 1 + + "#phy-cells": + const: 1 + + "#reset-cells": + const: 1 + + reboot: + type: object + $ref: /schemas/power/reset/syscon-reboot.yaml# + unevaluatedProperties: false + description: + Reboot method for the SoC. + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - interrupt-names + - reboot + - "#clock-cells" + - "#phy-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + topcrm: clock-controller@13b000 { + compatible =3D "zte,zx297520v3-topcrm", "syscon"; + reg =3D <0x0013b000 0x400>; + clocks =3D <&osc26m>, <&osc32k>; + clock-names =3D "osc26m", "osc32k"; + interrupts =3D , + , + , + ; + interrupt-names =3D "usb-up", "usb-down", "hsic-up", "hsic-down"; + #clock-cells =3D <1>; + #phy-cells =3D <1>; + #reset-cells =3D <1>; + + reboot { + compatible =3D "syscon-reboot"; + offset =3D <0x0>; + mask =3D <0x1>; + value =3D <0x1>; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 92a2167f1eb8..d53c0a2c7d9b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3910,8 +3910,12 @@ L: linux-arm-kernel@lists.infradead.org (moderated f= or non-subscribers) S: Odd fixes F: Documentation/arch/arm/zte/ F: Documentation/devicetree/bindings/arm/zte.yaml +F: Documentation/devicetree/bindings/clock/zte,zx297520v3-topcrm.yaml F: arch/arm/boot/dts/zte/ F: arch/arm/mach-zte/ +F: include/dt-bindings/clock/zte,zx297520v3-clk.h +F: include/dt-bindings/phy/zte,zx297520v3-topcrm.h +F: include/dt-bindings/reset/zte,zx297520v3-reset.h =20 ARM/ZYNQ ARCHITECTURE M: Michal Simek diff --git a/include/dt-bindings/clock/zte,zx297520v3-clk.h b/include/dt-bi= ndings/clock/zte,zx297520v3-clk.h new file mode 100644 index 000000000000..3aed94ccc26f --- /dev/null +++ b/include/dt-bindings/clock/zte,zx297520v3-clk.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) Stefan D=C3=B6singer. + */ + +#ifndef __DT_BINDINGS_CLOCK_ZX297520V3_H +#define __DT_BINDINGS_CLOCK_ZX297520V3_H + +#define ZX297520V3_M0_WCLK 0 +#define ZX297520V3_SRAM1_PCLK 1 +#define ZX297520V3_SRAM2_PCLK 2 +#define ZX297520V3_UART0_WCLK 3 +#define ZX297520V3_UART0_PCLK 4 +#define ZX297520V3_I2C0_WCLK 5 +#define ZX297520V3_I2C0_PCLK 6 +#define ZX297520V3_RTC_WCLK 7 +#define ZX297520V3_RTC_PCLK 8 +#define ZX297520V3_LPM_GSM_WCLK 9 +#define ZX297520V3_LPM_GSM_PCLK 10 +#define ZX297520V3_LPM_LTE_WCLK 11 +#define ZX297520V3_LPM_LTE_PCLK 12 +#define ZX297520V3_LPM_TD_WCLK 13 +#define ZX297520V3_LPM_TD_PCLK 14 +#define ZX297520V3_LPM_W_WCLK 15 +#define ZX297520V3_LPM_W_PCLK 16 +#define ZX297520V3_TIMER_T08_WCLK 17 +#define ZX297520V3_TIMER_T08_PCLK 18 +#define ZX297520V3_TIMER_T09_WCLK 19 +#define ZX297520V3_TIMER_T09_PCLK 20 +#define ZX297520V3_MPLL 21 +#define ZX297520V3_MPLL_D5 22 +#define ZX297520V3_DPLL 23 +#define ZX297520V3_GPLL 24 +#define ZX297520V3_GPLL_D2 25 +#define ZX297520V3_GATED_OSC26M 26 +#define ZX297520V3_PMM_WCLK 27 +#define ZX297520V3_PMM_PCLK 28 +#define ZX297520V3_OUT0_WCLK 29 +#define ZX297520V3_OUT1_WCLK 30 +#define ZX297520V3_OUT2_WCLK 31 +#define ZX297520V3_OUT32K_WCLK 32 +#define ZX297520V3_RMIIPHY_WCLK 33 +#define ZX297520V3_TIMER_T12_WCLK 34 +#define ZX297520V3_TIMER_T12_PCLK 35 +#define ZX297520V3_TIMER_T13_WCLK 36 +#define ZX297520V3_TIMER_T13_PCLK 37 +#define ZX297520V3_TIMER_T14_WCLK 38 +#define ZX297520V3_TIMER_T14_PCLK 39 +#define ZX297520V3_TIMER_T15_WCLK 40 +#define ZX297520V3_TIMER_T15_PCLK 41 +#define ZX297520V3_TIMER_T16_WCLK 42 +#define ZX297520V3_TIMER_T16_PCLK 43 +#define ZX297520V3_TIMER_T17_WCLK 44 +#define ZX297520V3_TIMER_T17_PCLK 45 +#define ZX297520V3_WDT_T18_WCLK 46 +#define ZX297520V3_WDT_T18_PCLK 47 +#define ZX297520V3_USIM1_WCLK 48 +#define ZX297520V3_USIM1_PCLK 49 +#define ZX297520V3_AHB_WCLK 50 +#define ZX297520V3_AHB_PCLK 51 +#define ZX297520V3_USB_WCLK 52 +#define ZX297520V3_USB_PCLK 53 +#define ZX297520V3_HSIC_WCLK 54 +#define ZX297520V3_HSIC_PCLK 55 + +#endif /* __DT_BINDINGS_CLOCK_ZX297520V3_H */ diff --git a/include/dt-bindings/phy/zte,zx297520v3-topcrm.h b/include/dt-b= indings/phy/zte,zx297520v3-topcrm.h new file mode 100644 index 000000000000..b36ccf2f54ef --- /dev/null +++ b/include/dt-bindings/phy/zte,zx297520v3-topcrm.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) Stefan D=C3=B6singer. + */ + +#ifndef __DT_BINDINGS_PHY_ZTE_ZX297520V3_TOPCRM_H +#define __DT_BINDINGS_PHY_ZTE_ZX297520V3_TOPCRM_H + +#define ZX297520V3_USB_PHY 0 +#define ZX297520V3_HSIC_PHY 1 + +#endif /* __DT_BINDINGS_PHY_ZTE_ZX297520V3_TOPCRM_H */ diff --git a/include/dt-bindings/reset/zte,zx297520v3-reset.h b/include/dt-= bindings/reset/zte,zx297520v3-reset.h new file mode 100644 index 000000000000..f60aaccf0f4d --- /dev/null +++ b/include/dt-bindings/reset/zte,zx297520v3-reset.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) Stefan D=C3=B6singer. + */ + +#ifndef __DT_BINDINGS_RESET_ZX297520V3_H +#define __DT_BINDINGS_RESET_ZX297520V3_H + +#define ZX297520V3_ZSP_RESET 0 +#define ZX297520V3_UART0_RESET 1 +#define ZX297520V3_I2C0_RESET 2 +#define ZX297520V3_RTC_RESET 3 +#define ZX297520V3_TIMER_T08_RESET 4 +#define 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ESMTPSA id 5b1f17b1804b1-49807bb45ebsm118499905e9.4.2026.08.02.13.34.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Aug 2026 13:34:12 -0700 (PDT) From: =?utf-8?q?Stefan_D=C3=B6singer?= Date: Sun, 02 Aug 2026 23:33:34 +0300 Subject: [PATCH v9 02/12] dt-bindings: clk: zte: Add zx297520v3 matrix clock and reset controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260802-zx29clk-v9-2-d05530d85d28@gmail.com> References: <20260802-zx29clk-v9-0-d05530d85d28@gmail.com> In-Reply-To: <20260802-zx29clk-v9-0-d05530d85d28@gmail.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Brian Masney , Vinod Koul , Neil Armstrong , Russell King , Lee Jones Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, mfd@lists.linux.dev, =?utf-8?q?Stefan_D=C3=B6singer?= , Krzysztof Kozlowski X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=10475; i=stefandoesinger@gmail.com; h=from:subject:message-id; bh=teIthTUZUUG27g6rTGA+Gnp1H6xnG5Y2mXlLPS6PaqE=; b=owEBiQJ2/ZANAwAIAT0TvMhUTxoiAcsmYgBqb6myeRhCvp2m/eQhdoPkAuo//XXbiyrj1eN2K gQTzkw3Sk+JAk8EAAEIADkWIQRDFvS2qgVbJ5UyXWw9E7zIVE8aIgUCam+pshsUgAAAAAAEAA5t YW51MiwyLjUrMS4xMiwyLDIACgkQPRO8yFRPGiKyBA/7BNffsgTp4U9tzGEFqjt39ml+DVHG1sb CKoOaulIyXtOrNcTNAPgqfm403IfLR7v5EhNynZj9vJGRpl65Y0wMCDZ48zyYVfWFENenVa5vyX Wz/rNI6YpSJB8QXKU98OLikUG8zgGXDCi0jAj3W9CCVDF304w0lSm0rj5uKNZ9C7oxy8bt/7W5N PSx88zKl82iEQhVshAN9QDclYIj+QTJBZ6ymi0nm5U6bxSodVyKjOEoYt9UjO12GNu5bFIxYqOc ZDssh27/cUesG7KBrYMjo1kvaygEpkIQXc35y/I9Kam2BJ6jUR0lzHSWL8bxNY7l+aaD0Esk6cv BMibbJN7y7z5OAvyNubr/nswM0Nnj6a544pmkt+to6pLr5Y9FgH7FWSdVnMdwPM4ncP4KdRVcLy 9T/s447eNkBLT5qM/k/y/k9cZqdMPJ3xRsHaR+5Lq7s/HxAyceRq+4TsmuRhAgokqpH+OXcxEel cBquuIPJWWcrvqO94Hh7305AN9gG+98Wv6mjPWDRMdjWE/vsbynJVlTarBnwvLhS7Tlcwd4hzn0 YKdzCoTnRDSwv32nqMic7ULpI6YB84+qREh+kFHbkqiV/7nriFntoT1pCPCFaKddeAX98RR8WsG +lyX6v+H3ax7TTe1hW2mWMjf7VLxYkPOx/pvhetIXSj1ljQP4L5M= X-Developer-Key: i=stefandoesinger@gmail.com; a=openpgp; fpr=4F9C2C8728019633893EBBB98CB81F9A72BBA155 This controller contains clocks and resets for high speed devices on the zx297520v3 board and hardware spinlocks that I expect will be necessary to communicate correctly with the LTE DSP firmware blob. I don't know much about the hwlocks yet other than that they exist, so there is no header yet adding meaning to their indices. Presumably that meaning doesn't exist in hardware and is de facto defined by ZTE's firmware blobs running on the rprocs. The zte-zx297520v3-crm driver will instantiate separate MFD children for clocks and resets, which are handled by separate clock and reset drivers. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Stefan D=C3=B6singer --- v8->v9: *) The SDIO controllers and GMAC depend on topcrm's ahb clock for register access / dma operation. Add the input to the binding. v7->v8: *) Start clock indices at 0 *) Fix indentation *) Add a prose note about discovered registers that allow writing CNTVAL. I am not exposing them in any way because for now I see no need to use this functionality. It is possible that the counter resets to 0 during standby, which means someone needs to fix it up using those registers. Nevertheless, no syscon yet for these reasons: I have no idea how CNTVAL behaves during standby. It might be just fine. Standby very likely needs firmware handling running on the Cortex M0, which can restore CNTVAL if necessary. If Linux needs to do it, it can probably be done by the clock or MFD parent driver. Given what I've learned so far I'd rather add syscon later than put it in place without a clear user. Details of how to manipulate CNTVAL will be in the matrix clk driver. *) A non-change in the binding text, but worth mentioning: Register 0x118 contains gates that gate off matrix-synthesized PLL fixed dividers. They reinforce the understanding of the top->matrix interface and the adequacy of the bindings. v6->v7: *) Moved it back to clock/ *) Remove syscon compatible again. I looked into remaining unknown registers and I am convinced that there is no odd misc register left that can't be exposed as a proper subsystem provider. The controls in 0x100 that ZTE's DRAM reading code exercises are auto clock gating controls and the actual mailbox is in a different controller. Unknown registers in 0x120-0x12c are a frequency voting mechanism for the AXI bus clock. The driver will participate in that voting rather than set the frequency via 0x0. If need be it could be exposed as #interconnect-cells, but it won't necessitate "syscon". *) Reduce the number of input clocks to match register controls in topclk's input control that affect matrix and LSP. *) Add DDR mux and gates. Not to change them, but to make sure CCF knows about which PLL is feeding the sysmem memory Changes v5->v6: Add syscon compatible - Conor suggested this after v4 and I forgot it in v5. v4->v5: Move binding to soc/zte Remove topclk from the example Add #hwlock-cells for hw spinlock registers Add more clocks I stumbled into: sram0 and another LTE related device v3->v4: Split matrixclk into its own controller again because syscon/regmap deals poorly with device nodes that have more than one memory region. As a consequence I am passing all PLL outputs generated on Topclk down to Matrixclk. --- .../bindings/clock/zte,zx297520v3-matrixcrm.yaml | 98 ++++++++++++++++++= ++++ MAINTAINERS | 1 + include/dt-bindings/clock/zte,zx297520v3-clk.h | 41 +++++++++ include/dt-bindings/reset/zte,zx297520v3-reset.h | 12 +++ 4 files changed, 152 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/zte,zx297520v3-matrixc= rm.yaml b/Documentation/devicetree/bindings/clock/zte,zx297520v3-matrixcrm.= yaml new file mode 100644 index 000000000000..bb7df02c8a0f --- /dev/null +++ b/Documentation/devicetree/bindings/clock/zte,zx297520v3-matrixcrm.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/zte,zx297520v3-matrixcrm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ZTE zx297520v3 SoC matrix clock and reset controller + +maintainers: + - Stefan D=C3=B6singer + +description: | + This controller contains clock and reset controls for high speed devices= on + the zx297520v3 board: The CPU, RAM, SDIO and Ethernet clocks and resets = are + found here. This controller requires PLL-generated clocks from Topcrm as= well + as the fixed 26 MHz and 32 kHz oscillators found on this board. + + This controller also contains hardware mutex registers for synchronizati= on + with different processors on this board. + + An additional curiosity are registers that allow setting (but not readin= g) the + ARM architected timer's CNTVAL. This is not exposed in the binding becau= se + there shouldn't be a need to access it. + + All available clocks are defined as preprocessor macros in the + "include/dt-bindings/clock/zte,zx297520v3-clk.h" header. Resets are defi= ned in + the "include/dt-bindings/reset/zte,zx297520v3-reset.h" header. + +properties: + compatible: + const: zte,zx297520v3-matrixcrm + + reg: + maxItems: 1 + + clocks: + items: + - description: 26 MHz external oscillator + - description: 32 kHz external oscillator + - description: AHB clock from topcrm + - description: Main PLL output from topcrm (usually 624 MHz) + - description: Main PLL subdivision factor 5 + - description: Dpll output from topcrm (usually 491.52 MHz) + - description: Gpll output from topcrm (usually 200 MHz) + - description: Gpll subdivision factor 2 + - description: osc26m work clock from topcrm + + clock-names: + items: + - const: osc26m + - const: osc32k + - const: ahb + - const: mpll + - const: mpll-d5 + - const: dpll + - const: gpll + - const: gpll-d2 + - const: wclk-osc26m + + "#clock-cells": + const: 1 + + "#hwlock-cells": + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + - "#hwlock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + #include + #include + + clock-controller@1306000 { + compatible =3D "zte,zx297520v3-matrixcrm"; + reg =3D <0x01306000 0x400>; + clocks =3D <&osc26m>, <&osc32k>, <&topcrm ZX297520V3_AHB_PCLK>, + <&topcrm ZX297520V3_MPLL>, <&topcrm ZX297520V3_MPLL_D5>, + <&topcrm ZX297520V3_DPLL>, <&topcrm ZX297520V3_GPLL>, + <&topcrm ZX297520V3_GPLL_D2>, + <&topcrm ZX297520V3_GATED_OSC26M>; + clock-names =3D "osc26m", "osc32k", "ahb", "mpll", "mpll-d5", "dpl= l", + "gpll", "gpll-d2", "wclk-osc26m"; + #clock-cells =3D <1>; + #hwlock-cells =3D <1>; + #reset-cells =3D <1>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index d53c0a2c7d9b..9a919e60254a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3910,6 +3910,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated fo= r non-subscribers) S: Odd fixes F: Documentation/arch/arm/zte/ F: Documentation/devicetree/bindings/arm/zte.yaml +F: Documentation/devicetree/bindings/clock/zte,zx297520v3-matrixcrm.yaml F: Documentation/devicetree/bindings/clock/zte,zx297520v3-topcrm.yaml F: arch/arm/boot/dts/zte/ F: arch/arm/mach-zte/ diff --git a/include/dt-bindings/clock/zte,zx297520v3-clk.h b/include/dt-bi= ndings/clock/zte,zx297520v3-clk.h index 3aed94ccc26f..a8477e9b2a14 100644 --- a/include/dt-bindings/clock/zte,zx297520v3-clk.h +++ b/include/dt-bindings/clock/zte,zx297520v3-clk.h @@ -63,4 +63,45 @@ #define ZX297520V3_HSIC_WCLK 54 #define ZX297520V3_HSIC_PCLK 55 =20 +#define ZX297520V3_SYS_TIMER_WCLK 0 +#define ZX297520V3_CPU_WCLK 1 +#define ZX297520V3_CPU_PCLK 2 +#define ZX297520V3_ZSP_WCLK 3 +#define ZX297520V3_DDR_CTRL_PCLK 4 +#define ZX297520V3_DDR_CTRL_WCLK 5 +#define ZX297520V3_EDCP_WCLK 6 +#define ZX297520V3_EDCP_PCLK 7 +#define ZX297520V3_SD0_WCLK 8 +#define ZX297520V3_SD0_PCLK 9 +#define ZX297520V3_SD0_CDET 10 +#define ZX297520V3_SD1_WCLK 11 +#define ZX297520V3_SD1_PCLK 12 +#define ZX297520V3_SD1_CDET 13 +#define ZX297520V3_NAND_WCLK 14 +#define ZX297520V3_NAND_PCLK 15 +#define ZX297520V3_DMA_PCLK 16 +#define ZX297520V3_MBOX_PCLK 17 +#define ZX297520V3_PDCFG_WCLK 18 +#define ZX297520V3_PDCFG_PCLK 19 +#define ZX297520V3_SSC_WCLK 20 +#define ZX297520V3_SSC_PCLK 21 +#define ZX297520V3_AXI_WCLK 22 +#define ZX297520V3_GMAC_WCLK 23 +#define ZX297520V3_GMAC_PCLK 24 +#define ZX297520V3_GMAC_AHB 25 +#define ZX297520V3_VOU_WCLK 26 +#define ZX297520V3_VOU_PCLK 27 +#define ZX297520V3_LSP_MPLL_D5_WCLK 28 +#define ZX297520V3_LSP_MPLL_D4_WCLK 29 +#define ZX297520V3_LSP_MPLL_D6_WCLK 30 +#define ZX297520V3_LSP_MPLL_D8_WCLK 31 +#define ZX297520V3_LSP_MPLL_D12_WCLK 32 +#define ZX297520V3_LSP_OSC26M_WCLK 33 +#define ZX297520V3_LSP_OSC32K_WCLK 34 +#define ZX297520V3_LSP_PCLK 35 +#define ZX297520V3_LSP_TDM_WCLK 36 +#define ZX297520V3_LSP_DPLL_D4_WCLK 37 +#define ZX297520V3_SRAM0_PCLK 38 +#define ZX297520V3_GSM_CFG_PCLK 39 + #endif /* __DT_BINDINGS_CLOCK_ZX297520V3_H */ diff --git a/include/dt-bindings/reset/zte,zx297520v3-reset.h b/include/dt-= bindings/reset/zte,zx297520v3-reset.h index f60aaccf0f4d..d79fa601afa6 100644 --- a/include/dt-bindings/reset/zte,zx297520v3-reset.h +++ b/include/dt-bindings/reset/zte,zx297520v3-reset.h @@ -27,4 +27,16 @@ #define ZX297520V3_USB_RESET 18 #define ZX297520V3_HSIC_RESET 19 =20 +#define ZX297520V3_CPU_RESET 0 +#define ZX297520V3_DDR_CTRL_RESET 1 +#define ZX297520V3_EDCP_RESET 2 +#define ZX297520V3_SD0_RESET 3 +#define ZX297520V3_SD1_RESET 4 +#define ZX297520V3_NAND_RESET 5 +#define ZX297520V3_PDCFG_RESET 6 +#define ZX297520V3_SSC_RESET 7 +#define ZX297520V3_GMAC_RESET 8 +#define ZX297520V3_VOU_RESET 9 +#define ZX297520V3_LSP_RESET 10 + #endif /* __DT_BINDINGS_RESET_ZX297520V3_H */ --=20 2.54.0 From nobody Fri Oct 2 10:08:32 2026 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3007833C182 for ; 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a=openpgp; fpr=4F9C2C8728019633893EBBB98CB81F9A72BBA155 The clock controller of the zx297520v3 Low Speed Peripherals is relatively clean. One register per device with gates, muxes and resets and for some devices a divider. There are even bits in the matrix controller to control propagation of clock lines down to LSP. The clocks are sorted by register address and I am convinced that the device list is complete. There are, however, a few more registers that are likely extra dividers for TDM and I2S devices. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Stefan D=C3=B6singer --- Patch changelog: v8: *) Start clock indices at 0 *) A minor grammar fix in the second paragraph of the binding prose v5: Rename from lspclk to lspcrm Remove matrixcrm from example v4: Order properties compatible->reg->clocks->clock->names->#cells --- .../bindings/clock/zte,zx297520v3-lspcrm.yaml | 101 +++++++++++++++++= ++++ MAINTAINERS | 1 + include/dt-bindings/clock/zte,zx297520v3-clk.h | 37 ++++++++ include/dt-bindings/reset/zte,zx297520v3-reset.h | 19 ++++ 4 files changed, 158 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/zte,zx297520v3-lspcrm.= yaml b/Documentation/devicetree/bindings/clock/zte,zx297520v3-lspcrm.yaml new file mode 100644 index 000000000000..cfad0e0372f4 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/zte,zx297520v3-lspcrm.yaml @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/zte,zx297520v3-lspcrm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ZTE zx297520v3 SoC LSP clock and reset controller + +maintainers: + - Stefan D=C3=B6singer + +description: | + This clock and reset controller controls low speed peripherals on the bo= ard. + This is a relatively isolated subsystem containing UART, I2C, I2S and SPI + devices. The controller is responsible for bringing the devices out of r= eset + and enabling their clocks as needed. + + The controller receives its clock signals from the matrix controller, and + these signals need to be declared as clock inputs. + + All available clocks are defined as preprocessor macros in the + "include/dt-bindings/clock/zte,zx297520v3-clk.h" header. Resets are defi= ned in + the "include/dt-bindings/reset/zte,zx297520v3-reset.h" header. + +properties: + compatible: + const: zte,zx297520v3-lspcrm + + reg: + maxItems: 1 + + clocks: + items: + - description: Main PLL divided by 5 output from matrixcrm (124.8 MH= z) + - description: Main PLL divided by 4 output from matrixcrm (156 MHz) + - description: Main PLL divided by 6 output from matrixcrm (104 MHz) + - description: Main PLL divided by 8 output from matrixcrm (78 MHz) + - description: Main PLL divided by 12 output from matrixcrm (52 MHz) + - description: Main oscillator output from matrixcrm (26 MHz) + - description: Timer oscillator output from matrixcrm (32 kHz) + - description: LSP pclk output from matrixcrm (26 MHz) + - description: TDM wclk mux output from matrixcrm + - description: DPLL divided by 4 output from matrixcrm (122.88 MHz) + + clock-names: + items: + - const: mpll-d5 + - const: mpll-d4 + - const: mpll-d6 + - const: mpll-d8 + - const: mpll-d12 + - const: osc26m + - const: osc32k + - const: pclk + - const: tdm-wclk + - const: dpll-d4 + + resets: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + #include + #include + + clock-controller@1400000 { + compatible =3D "zte,zx297520v3-lspcrm"; + reg =3D <0x01400000 0x100>; + clocks =3D <&matrixcrm ZX297520V3_LSP_MPLL_D5_WCLK>, + <&matrixcrm ZX297520V3_LSP_MPLL_D4_WCLK>, + <&matrixcrm ZX297520V3_LSP_MPLL_D6_WCLK>, + <&matrixcrm ZX297520V3_LSP_MPLL_D8_WCLK>, + <&matrixcrm ZX297520V3_LSP_MPLL_D12_WCLK>, + <&matrixcrm ZX297520V3_LSP_OSC26M_WCLK>, + <&matrixcrm ZX297520V3_LSP_OSC32K_WCLK>, + <&matrixcrm ZX297520V3_LSP_PCLK>, + <&matrixcrm ZX297520V3_LSP_TDM_WCLK>, + <&matrixcrm ZX297520V3_LSP_DPLL_D4_WCLK>; + clock-names =3D "mpll-d5", "mpll-d4", "mpll-d6", "mpll-d8", "mpll-= d12", + "osc26m", "osc32k", "pclk", "tdm-wclk", "dpll-d4"; + resets =3D <&matrixcrm ZX297520V3_LSP_RESET>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 9a919e60254a..e01ef014c110 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3910,6 +3910,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated fo= r non-subscribers) S: Odd fixes F: Documentation/arch/arm/zte/ F: Documentation/devicetree/bindings/arm/zte.yaml +F: Documentation/devicetree/bindings/clock/zte,zx297520v3-lspcrm.yaml F: Documentation/devicetree/bindings/clock/zte,zx297520v3-matrixcrm.yaml F: Documentation/devicetree/bindings/clock/zte,zx297520v3-topcrm.yaml F: arch/arm/boot/dts/zte/ diff --git a/include/dt-bindings/clock/zte,zx297520v3-clk.h b/include/dt-bi= ndings/clock/zte,zx297520v3-clk.h index a8477e9b2a14..8824740468a3 100644 --- a/include/dt-bindings/clock/zte,zx297520v3-clk.h +++ b/include/dt-bindings/clock/zte,zx297520v3-clk.h @@ -104,4 +104,41 @@ #define ZX297520V3_SRAM0_PCLK 38 #define ZX297520V3_GSM_CFG_PCLK 39 =20 +#define ZX297520V3_TIMER_L1_WCLK 0 +#define ZX297520V3_TIMER_L1_PCLK 1 +#define ZX297520V3_WDT_L2_WCLK 2 +#define ZX297520V3_WDT_L2_PCLK 3 +#define ZX297520V3_WDT_L3_WCLK 4 +#define ZX297520V3_WDT_L3_PCLK 5 +#define ZX297520V3_PWM_WCLK 6 +#define ZX297520V3_PWM_PCLK 7 +#define ZX297520V3_I2S0_WCLK 8 +#define ZX297520V3_I2S0_PCLK 9 +#define ZX297520V3_I2S1_WCLK 10 +#define ZX297520V3_I2S1_PCLK 11 +#define ZX297520V3_QSPI_WCLK 12 +#define ZX297520V3_QSPI_PCLK 13 +#define ZX297520V3_UART1_WCLK 14 +#define ZX297520V3_UART1_PCLK 15 +#define ZX297520V3_I2C1_WCLK 16 +#define ZX297520V3_I2C1_PCLK 17 +#define ZX297520V3_SPI0_WCLK 18 +#define ZX297520V3_SPI0_PCLK 19 +#define ZX297520V3_TIMER_LB_WCLK 20 +#define ZX297520V3_TIMER_LB_PCLK 21 +#define ZX297520V3_TIMER_LC_WCLK 22 +#define ZX297520V3_TIMER_LC_PCLK 23 +#define ZX297520V3_UART2_WCLK 24 +#define ZX297520V3_UART2_PCLK 25 +#define ZX297520V3_WDT_LE_WCLK 26 +#define ZX297520V3_WDT_LE_PCLK 27 +#define ZX297520V3_TIMER_LF_WCLK 28 +#define ZX297520V3_TIMER_LF_PCLK 29 +#define ZX297520V3_SPI1_WCLK 30 +#define ZX297520V3_SPI1_PCLK 31 +#define ZX297520V3_TIMER_L11_WCLK 32 +#define ZX297520V3_TIMER_L11_PCLK 33 +#define ZX297520V3_TDM_WCLK 34 +#define ZX297520V3_TDM_PCLK 35 + #endif /* __DT_BINDINGS_CLOCK_ZX297520V3_H */ diff --git a/include/dt-bindings/reset/zte,zx297520v3-reset.h b/include/dt-= bindings/reset/zte,zx297520v3-reset.h index d79fa601afa6..303fbef12a42 100644 --- a/include/dt-bindings/reset/zte,zx297520v3-reset.h +++ b/include/dt-bindings/reset/zte,zx297520v3-reset.h @@ -39,4 +39,23 @@ #define ZX297520V3_VOU_RESET 9 #define ZX297520V3_LSP_RESET 10 =20 +#define ZX297520V3_TIMER_L1_RESET 0 +#define ZX297520V3_WDT_L2_RESET 1 +#define ZX297520V3_WDT_L3_RESET 2 +#define ZX297520V3_PWM_RESET 3 +#define ZX297520V3_I2S0_RESET 4 +#define ZX297520V3_I2S1_RESET 5 +#define ZX297520V3_QSPI_RESET 6 +#define ZX297520V3_UART1_RESET 7 +#define ZX297520V3_I2C1_RESET 8 +#define ZX297520V3_SPI0_RESET 9 +#define ZX297520V3_TIMER_LB_RESET 10 +#define ZX297520V3_TIMER_LC_RESET 11 +#define ZX297520V3_UART2_RESET 12 +#define ZX297520V3_WDT_LE_RESET 13 +#define ZX297520V3_TIMER_LF_RESET 14 +#define ZX297520V3_SPI1_RESET 15 +#define ZX297520V3_TIMER_L11_RESET 16 +#define ZX297520V3_TDM_RESET 17 + #endif /* __DT_BINDINGS_RESET_ZX297520V3_H */ --=20 2.54.0 From nobody Fri Oct 2 10:08:32 2026 Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 026872F1FED for ; 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a=openpgp; fpr=4F9C2C8728019633893EBBB98CB81F9A72BBA155 This driver registers child devices for the zx297520v3 clock and reset controllers. The clk-zx297520v3 and reset-zte-zx297520v3 submitted in the next patches will drive the respective functionalities. Signed-off-by: Stefan D=C3=B6singer --- What I am still unsure about: How much sense does it make to have this module-capable and able to unbind: In practice, the board doesn't work without this driver and its clock and reset children. Changes v9: Deassert the LSP reset and enable the LSP pclk here. In practice the boot rom needs to do that because it prints to an LSP-connected UART and reads the boot policy from the LSP connected flash chip. In doing so, I migrated the match data to an enum as mfd.md suggests. Changes v8: *) Remove .of_compatible from PHY mfd child *) Move to drivers/mfd (Sashiko) For me either soc/zte or mfd/ is fine. Note though that this MFD parent is very specific to the zx297520v3 SoC. I don't expect this to be reused anywhere else. There are two more MFD-ish devices in there: soc_sys at 0x140000, which I plan to handle in the same driver, and an i2c PMIC, which would get its own host driver. *) Use PLATFORM_DEVID_AUTO (Sashiko). NONE was intentional as I only ever expect one instance, but I don't see any harm in doing the standard thing and use AUTO *) On the suggestion not to put the link to mfd_cells[] into match data: I see that it is spelled out in Sashiko's mfd.md, written by Lee Jones, the MFD maintainer. I would appreciate some education on the rationale behind it: Putting a pointer into the void *data is a common pattern in the kernel. I don't understand in which situation this can possibly break? Both structs are static const in the same compilation unit. data is a const void *, not a uintptr_t or kernel_ulong_t, so it seems passing a pointer is the intended use. What am I missing? Changes v7: Add phy MFD child Changes v6: Make the ZTE SoC driver section depend on HAS_IOMEM (Sashiko). The entire MFD section, which contains MFD_CORE, depends on HAS_IOMEM even with COMPILE_TEST. Add a NULL ptr check for of_device_get_match_data (Sashiko). While not uniform, rave-sp, rohm-bd9576, atc260x, da9052-i2c protect against incorrect manual attachment that way. Add lspclk here as well in an attempt to satisfy both Conor Dooley, who asks for MFD for top and matrix, and Philipp Zabel, who prefers aux but at least wants the reset driver limited to one driver type. Changes v5: Use MFD instead of Aux bus for top and matrix crm because of extra functionality: Reboot in top, hwlock in Matrix. LSP clocks stay with the aux bus and are thus not handled in this driver. The clk driver will bind directly to the lspcrm node. --- MAINTAINERS | 1 + drivers/mfd/Kconfig | 11 ++++ drivers/mfd/Makefile | 2 + drivers/mfd/zte-zx297520v3-crm.c | 117 +++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 131 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e01ef014c110..b9f96455bca7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3915,6 +3915,7 @@ F: Documentation/devicetree/bindings/clock/zte,zx2975= 20v3-matrixcrm.yaml F: Documentation/devicetree/bindings/clock/zte,zx297520v3-topcrm.yaml F: arch/arm/boot/dts/zte/ F: arch/arm/mach-zte/ +F: drivers/mfd/zte-zx297520v3-crm.c F: include/dt-bindings/clock/zte,zx297520v3-clk.h F: include/dt-bindings/phy/zte,zx297520v3-topcrm.h F: include/dt-bindings/reset/zte,zx297520v3-reset.h diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 35f6e9b76d05..c0c7e83487f4 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -2572,5 +2572,16 @@ config MFD_MAX7360 additional drivers must be enabled in order to use the functionality of the device. =20 +config MFD_ZTE_ZX297520V3_CRM + tristate "ZTE zx297520v3 Clock and Reset Manager" + select MFD_CORE + default SOC_ZX297520V3 + help + Say yes here to enable the driver for the ZTE zx297520v3 clock and + reset manager MFD driver. This driver provides the host device for + the clock and reset drivers and is required to boot the SoC. You + will also need to enable CLK_ZTE_ZX297520V3 and RESET_ZTE_ZX297520V3 + to build the actual clock and reset child drivers. + endmenu endif diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index dd4bb7e77c33..4f6a78170ac5 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -303,3 +303,5 @@ obj-$(CONFIG_MFD_RSMU_SPI) +=3D rsmu_spi.o rsmu_core.o obj-$(CONFIG_MFD_UPBOARD_FPGA) +=3D upboard-fpga.o =20 obj-$(CONFIG_MFD_LOONGSON_SE) +=3D loongson-se.o + +obj-$(CONFIG_MFD_ZTE_ZX297520V3_CRM) +=3D zte-zx297520v3-crm.o diff --git a/drivers/mfd/zte-zx297520v3-crm.c b/drivers/mfd/zte-zx297520v3-= crm.c new file mode 100644 index 000000000000..37cd0c14680e --- /dev/null +++ b/drivers/mfd/zte-zx297520v3-crm.c @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026 Stefan D=C3=B6singer + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +enum zx297520v3_mfd_type { + ZX297520V3_MFD_INVALID =3D 0, + ZX297520V3_MFD_TOPCRM, + ZX297520V3_MFD_MATRIXCRM, + ZX297520V3_MFD_LSPCRM, +}; + +static const struct mfd_cell zx297520v3_topcrm_cells[] =3D { + { + .name =3D "zx297520v3-topclk", + }, + { + .name =3D "zx297520v3-topreset", + }, + { + .name =3D "reboot", + .of_compatible =3D "syscon-reboot", + }, + { + .name =3D "zx297520v3-usb-phy", + }, +}; + +static const struct mfd_cell zx297520v3_matrixcrm_cells[] =3D { + { + .name =3D "zx297520v3-matrixclk", + }, + { + .name =3D "zx297520v3-matrixreset", + }, + /* A set of hwlock controllers is found here as well, but no driver is im= plemented yet */ +}; + +static const struct mfd_cell zx297520v3_lspcrm_cells[] =3D { + { + .name =3D "zx297520v3-lspclk", + }, + { + .name =3D "zx297520v3-lspreset", + }, +}; + +static int zx297520v3_crm_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + enum zx297520v3_mfd_type type; + const struct mfd_cell *cells; + struct reset_control *rst; + unsigned int num_cells; + struct clk *pclk; + + type =3D (enum zx297520v3_mfd_type)of_device_get_match_data(dev); + switch (type) { + case ZX297520V3_MFD_TOPCRM: + cells =3D zx297520v3_topcrm_cells; + num_cells =3D ARRAY_SIZE(zx297520v3_topcrm_cells); + break; + + case ZX297520V3_MFD_MATRIXCRM: + cells =3D zx297520v3_matrixcrm_cells; + num_cells =3D ARRAY_SIZE(zx297520v3_matrixcrm_cells); + break; + + case ZX297520V3_MFD_LSPCRM: + cells =3D zx297520v3_lspcrm_cells; + num_cells =3D ARRAY_SIZE(zx297520v3_lspcrm_cells); + + pclk =3D devm_clk_get_enabled(dev, "pclk"); + if (IS_ERR(pclk)) + return dev_err_probe(dev, PTR_ERR(pclk), "Could not get pclk\n"); + + rst =3D devm_reset_control_get_exclusive_deasserted(dev, NULL); + if (IS_ERR(rst)) + return dev_err_probe(dev, PTR_ERR(rst), "Could not get reset\n"); + break; + + default: + return -ENODEV; + } + + return devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, cells, num_cells, N= ULL, 0, NULL); +} + +static const struct of_device_id of_match_zx297520v3_crm[] =3D { + { .compatible =3D "zte,zx297520v3-topcrm", .data =3D (void *)ZX297520V3_M= FD_TOPCRM }, + { .compatible =3D "zte,zx297520v3-matrixcrm", .data =3D (void *)ZX297520V= 3_MFD_MATRIXCRM }, + { .compatible =3D "zte,zx297520v3-lspcrm", .data =3D (void *)ZX297520V3_M= FD_LSPCRM }, + { } +}; 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a=openpgp; fpr=4F9C2C8728019633893EBBB98CB81F9A72BBA155 The next patches will implement the regmap clocks and PLL driver. The actual hardware specific clock listing will live in a separate module. Signed-off-by: Stefan D=C3=B6singer --- Version 9: Rework parent matching and clock export control. Most of the changes will be in the next patches. The visible change here is that the clock array is unified with single clocks having a type rather than one array per type. Depend on HAS_IOMEM, similarly to Sashiko's flagged issue in the Reset patch ZX297520V3_CLK_NO_EXPORT is gone again. The explicit clock input array and enabling of LSP's pclk is removed from the clock driver. The MFD parent takes care of this instead. The clock driver does some sanity checking on the static clock data though. Version 8: Use ZX297520V3_CLK_NO_EXPORT=3D(~0u) for unexported clocks. While using 0, and starting clock indices at 1, is a common pattern in existing drivers, it exposes a driver implementation detail in the hardware binding interface. If desired, I can change the special index to a separate field in the structs. Fix the return value if the ->init() callback fails. (Sashiko) Version 7: *) Add fixed dividers to handle PLL subdivisions *) Never register PLLs directly as exported clocks - everything on this SoC goes through a gate before it leaves a controller. Version 6: *) Remove auxdev now that LSP clocks also use MFD *) Error codepath fixes pointed out by Sashiko. Version 5: *) Pass the static clk data instead of calling get_match_data to prepare for operating as an MFD child. *) Don't use devm_kzalloc to allocate the auxiliary_device structure. I guess Sashiko is right, and that's what "Because once the device is placed on the bus the parent driver can not tell what other code may have a reference to this data" is trying to tell me. *) Fix error check for device_node_to_regmap. --- MAINTAINERS | 1 + drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/zte/Kconfig | 17 ++++ drivers/clk/zte/Makefile | 5 ++ drivers/clk/zte/clk-regmap.c | 32 ++++++++ drivers/clk/zte/clk-zx.c | 189 +++++++++++++++++++++++++++++++++++++++= ++++ drivers/clk/zte/clk-zx.h | 142 ++++++++++++++++++++++++++++++++ drivers/clk/zte/pll-zx.c | 18 +++++ 9 files changed, 406 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index b9f96455bca7..77fa86c671b8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3915,6 +3915,7 @@ F: Documentation/devicetree/bindings/clock/zte,zx2975= 20v3-matrixcrm.yaml F: Documentation/devicetree/bindings/clock/zte,zx297520v3-topcrm.yaml F: arch/arm/boot/dts/zte/ F: arch/arm/mach-zte/ +F: drivers/clk/zte/ F: drivers/mfd/zte-zx297520v3-crm.c F: include/dt-bindings/clock/zte,zx297520v3-clk.h F: include/dt-bindings/phy/zte,zx297520v3-topcrm.h diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 1717ce75a907..6f0a863951ca 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -545,6 +545,7 @@ source "drivers/clk/uniphier/Kconfig" source "drivers/clk/visconti/Kconfig" source "drivers/clk/x86/Kconfig" source "drivers/clk/xilinx/Kconfig" +source "drivers/clk/zte/Kconfig" source "drivers/clk/zynqmp/Kconfig" =20 # Kunit test cases diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 6899e32e14aa..651fe866ddad 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -167,5 +167,6 @@ ifeq ($(CONFIG_COMMON_CLK), y) obj-$(CONFIG_X86) +=3D x86/ endif obj-y +=3D xilinx/ +obj-$(CONFIG_COMMON_CLK_ZTE) +=3D zte/ obj-$(CONFIG_ARCH_ZYNQ) +=3D zynq/ obj-$(CONFIG_COMMON_CLK_ZYNQMP) +=3D zynqmp/ diff --git a/drivers/clk/zte/Kconfig b/drivers/clk/zte/Kconfig new file mode 100644 index 000000000000..152c2423b8f0 --- /dev/null +++ b/drivers/clk/zte/Kconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# ZTE Clock Drivers +# + +config COMMON_CLK_ZTE + tristate "Clock driver for ZTE SoCs" + depends on HAS_IOMEM + depends on ARCH_ZTE || COMPILE_TEST + default ARCH_ZTE + select MFD_SYSCON + help + This option selects common clock infrastructure for ZTE based SoCs. + You will need to enable one or more SoC specific drivers to make use + of this. + + Enable this if you are building a kernel for a ZTE designed board. diff --git a/drivers/clk/zte/Makefile b/drivers/clk/zte/Makefile new file mode 100644 index 000000000000..27db07293165 --- /dev/null +++ b/drivers/clk/zte/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-$(CONFIG_COMMON_CLK_ZTE) +=3D clk-zte.o + +clk-zte-y +=3D clk-zx.o pll-zx.o clk-regmap.o diff --git a/drivers/clk/zte/clk-regmap.c b/drivers/clk/zte/clk-regmap.c new file mode 100644 index 000000000000..80332dba97f6 --- /dev/null +++ b/drivers/clk/zte/clk-regmap.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2026 Stefan D=C3=B6singer + */ + +#include +#include +#include +#include + +#include "clk-zx.h" + +struct clk_hw *zx_clk_register_gate(struct device *dev, struct regmap *reg= map, + const struct zx_gate_desc *desc, + struct clk_hw * const *clocks) +{ + return ERR_PTR(-ENODEV); +} + +struct clk_hw *zx_clk_register_divider(struct device *dev, struct regmap *= regmap, + const struct zx_div_desc *desc, + struct clk_hw * const *clocks) +{ + return ERR_PTR(-ENODEV); +} + +struct clk_hw *zx_clk_register_mux(struct device *dev, struct regmap *regm= ap, + const struct zx_mux_desc *desc, + struct clk_hw * const *clocks) +{ + return ERR_PTR(-ENODEV); +} diff --git a/drivers/clk/zte/clk-zx.c b/drivers/clk/zte/clk-zx.c new file mode 100644 index 000000000000..27bbafd8ce4d --- /dev/null +++ b/drivers/clk/zte/clk-zx.c @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026 Stefan D=C3=B6singer + */ + +#include +#include +#include +#include +#include +#include + +#include "clk-zx.h" + +static struct clk_hw *zx_clk_register_fixed_div(struct device *dev, + const struct zx_fixed_divider_desc *desc, + struct clk_hw * const *clocks) +{ + const struct zx_parent_desc *p =3D &desc->parent; + + switch (p->type) { + case ZX_PARENT_FW: + return devm_clk_hw_register_fixed_factor_fwname(dev, NULL, desc->name, p= ->fw_name, + CLK_SET_RATE_PARENT, 1, desc->div); + + case ZX_PARENT_ID: + return devm_clk_hw_register_fixed_factor_parent_hw(dev, desc->name, cloc= ks[p->id], + CLK_SET_RATE_PARENT, 1, + desc->div); + } + WARN_ON_ONCE(1); + return ERR_PTR(-EINVAL); +} + +static int zx_clk_validate(struct device *dev, struct device_node *of_node, + const struct zx_clk_data *data) +{ + const struct zx_parent_desc *parents; + unsigned int i, p, num_parents; + struct clk *clk; + + /* + * Sanity check: Make sure all parents are there and write a clear messag= e rather than + * leave potential orphans. + */ + for (i =3D 0; i < data->num_clocks; ++i) { + switch (data->clocks[i].type) { + case ZX_CLOCK_PLL: + parents =3D data->clocks[i].pll.parents; + num_parents =3D data->clocks[i].pll.num_parents; + break; + + case ZX_CLOCK_FIXED_DIV: + parents =3D &data->clocks[i].fixed_div.parent; + num_parents =3D 1; + break; + + case ZX_CLOCK_MUX: + parents =3D data->clocks[i].mux.parents; + num_parents =3D data->clocks[i].mux.num_parents; + break; + + case ZX_CLOCK_DIV: + parents =3D &data->clocks[i].div.parent; + num_parents =3D 1; + break; + + case ZX_CLOCK_GATE: + parents =3D &data->clocks[i].gate.parent; + num_parents =3D 1; + break; + + default: + return dev_err_probe(dev, -EINVAL, "Invalid clock entry %u\n", i); + } + + for (p =3D 0; p < num_parents; ++p) { + switch (parents[p].type) { + case ZX_PARENT_FW: + clk =3D of_clk_get_by_name(of_node, parents[p].fw_name); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), + "Input clk %s failure\n", + parents[p].fw_name); + clk_put(clk); + break; + + case ZX_PARENT_ID: + if (parents[p].id >=3D i) + return dev_err_probe(dev, -EINVAL, + "Clock %u has parent %u\n", + i, parents[p].id); + break; + + default: + return dev_err_probe(dev, -EINVAL, + "Clock %u has unexpected parent of type %u\n", + i, parents[p].type); + } + } + } + + return 0; +} + +int zx_clk_common_probe(struct device *dev, struct device_node *of_node, + const struct zx_clk_data *data) +{ + struct clk_hw_onecell_data *exports; + struct clk_hw **clocks; + struct regmap *map; + unsigned int i; + int res; + + res =3D zx_clk_validate(dev, of_node, data); + if (res) + return res; + + map =3D device_node_to_regmap(of_node); + if (IS_ERR(map)) + return PTR_ERR(map); + + clocks =3D devm_kcalloc(dev, data->num_clocks, sizeof(*clocks), GFP_KERNE= L); + if (!clocks) + return -ENOMEM; + + if (data->init) { + res =3D data->init(map); + if (res) + return res; + } + + for (i =3D 0; i < data->num_clocks; ++i) { + struct clk_hw *hw; + + switch (data->clocks[i].type) { + case ZX_CLOCK_PLL: + hw =3D zx_clk_register_pll(dev, map, &data->clocks[i].pll, clocks); + break; + + case ZX_CLOCK_FIXED_DIV: + hw =3D zx_clk_register_fixed_div(dev, &data->clocks[i].fixed_div, clock= s); + break; + + case ZX_CLOCK_MUX: + hw =3D zx_clk_register_mux(dev, map, &data->clocks[i].mux, clocks); + break; + + case ZX_CLOCK_DIV: + hw =3D zx_clk_register_divider(dev, map, &data->clocks[i].div, clocks); + break; + + case ZX_CLOCK_GATE: + hw =3D zx_clk_register_gate(dev, map, &data->clocks[i].gate, clocks); + break; + + default: + return -EINVAL; + } + + if (IS_ERR(hw)) + return dev_err_probe(dev, PTR_ERR(hw), "Failed to register clk %u\n", i= ); + + clocks[i] =3D hw; + } + + exports =3D devm_kzalloc(dev, struct_size(exports, hws, data->num_exports= ), GFP_KERNEL); + if (!exports) + return -ENOMEM; + exports->num =3D data->num_exports; + + for (i =3D 0; i < data->num_exports; ++i) { + if (data->exports[i] >=3D data->num_clocks) + return dev_err_probe(dev, -EINVAL, + "Export %u points to out of range clock %u\n", + i, data->exports[i]); + + exports->hws[i] =3D clocks[data->exports[i]]; + } + + devm_kfree(dev, clocks); + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, exports); +} +EXPORT_SYMBOL_NS_GPL(zx_clk_common_probe, "ZTE_CLK"); + +MODULE_AUTHOR("Stefan D=C3=B6singer "); +MODULE_DESCRIPTION("ZTE common clock driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/zte/clk-zx.h b/drivers/clk/zte/clk-zx.h new file mode 100644 index 000000000000..175fbba3e0b3 --- /dev/null +++ b/drivers/clk/zte/clk-zx.h @@ -0,0 +1,142 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2026 Stefan D=C3=B6singer + */ + +#ifndef __DRV_CLK_ZX_H +#define __DRV_CLK_ZX_H + +#include +#include +#include +#include + +#define CLK_ZX_PLL_PREPARE_IS_ENABLE 1 +#define CLK_ZX_MAX_PARENTS 8 + +enum zx_parent_type { + ZX_PARENT_FW, + ZX_PARENT_ID, +}; + +struct zx_parent_desc { + enum zx_parent_type type; + union { + const char *fw_name; + unsigned int id; + }; +}; + +#define PARENT_FW(_name) { .type =3D ZX_PARENT_FW, .fw_name =3D (_name) } + +#define PARENT_ID(_id) { .type =3D ZX_PARENT_ID, .id =3D (_id) } + +static inline struct clk_parent_data zx_get_parent(const struct zx_parent_= desc *p, + struct clk_hw * const *clocks) +{ + struct clk_parent_data ret =3D {}; + + switch (p->type) { + case ZX_PARENT_FW: + ret.fw_name =3D p->fw_name; + ret.index =3D -1; + return ret; + + case ZX_PARENT_ID: + ret.hw =3D clocks[p->id]; + ret.index =3D -1; + return ret; + }; + + WARN_ON_ONCE(1); + return ret; +} + +struct zx_pll_desc { + const char *name; + const struct zx_parent_desc *parents; + unsigned int num_parents; + unsigned long rate; + u16 reg; + u16 flags; +}; + +struct zx_fixed_divider_desc { + const char *name; + struct zx_parent_desc parent; + unsigned int div; +}; + +struct zx_mux_desc { + const char *name; + const struct zx_parent_desc *parents; + unsigned int num_parents; + u16 reg; + u8 shift, size; +}; + +struct zx_div_desc { + const char *name; + struct zx_parent_desc parent; + u16 reg; + u8 shift, size; +}; + +struct zx_gate_desc { + const char *name; + struct zx_parent_desc parent; + unsigned long flags; + u16 reg; + u8 shift; +}; + +enum zx_clock_type { + ZX_CLOCK_INVALID =3D 0, + ZX_CLOCK_PLL, + ZX_CLOCK_FIXED_DIV, + ZX_CLOCK_MUX, + ZX_CLOCK_DIV, + ZX_CLOCK_GATE, +}; + +struct zx_clock { + enum zx_clock_type type; + union { + struct zx_pll_desc pll; + struct zx_fixed_divider_desc fixed_div; + struct zx_mux_desc mux; + struct zx_div_desc div; + struct zx_gate_desc gate; + }; +}; + +struct clk_hw *zx_clk_register_pll(struct device *dev, struct regmap *regm= ap, + const struct zx_pll_desc *desc, + struct clk_hw * const *clocks); +struct clk_hw *zx_clk_register_mux(struct device *dev, struct regmap *regm= ap, + const struct zx_mux_desc *desc, + struct clk_hw * const *clocks); +struct clk_hw *zx_clk_register_divider(struct device *dev, struct regmap *= regmap, + const struct zx_div_desc *desc, + struct clk_hw * const *clocks); +struct clk_hw *zx_clk_register_gate(struct device *dev, struct regmap *reg= map, + const struct zx_gate_desc *desc, + struct clk_hw * const *clocks); + +struct zx_clk_export { + unsigned int priv; + unsigned int binding; +}; + +struct zx_clk_data { + int (*init)(struct regmap *map); + const struct zx_clock *clocks; + unsigned int num_clocks; + unsigned int *exports; + unsigned int num_exports; +}; + +int zx_clk_common_probe(struct device *dev, struct device_node *of_node, + const struct zx_clk_data *data); + +#endif /* __DRV_CLK_ZX_H */ diff --git a/drivers/clk/zte/pll-zx.c b/drivers/clk/zte/pll-zx.c new file mode 100644 index 000000000000..fc76c6524a16 --- /dev/null +++ b/drivers/clk/zte/pll-zx.c @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026 Stefan D=C3=B6singer + */ + +#include +#include +#include +#include + +#include "clk-zx.h" + +struct clk_hw *zx_clk_register_pll(struct device *dev, struct regmap *regm= ap, + const struct zx_pll_desc *desc, + struct clk_hw * const *clocks) +{ + return ERR_PTR(-ENODEV); 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Sun, 02 Aug 2026 13:34:33 -0700 (PDT) From: =?utf-8?q?Stefan_D=C3=B6singer?= Date: Sun, 02 Aug 2026 23:33:38 +0300 Subject: [PATCH v9 06/12] clk: zte: Add regmap-based clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260802-zx29clk-v9-6-d05530d85d28@gmail.com> References: <20260802-zx29clk-v9-0-d05530d85d28@gmail.com> In-Reply-To: <20260802-zx29clk-v9-0-d05530d85d28@gmail.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Brian Masney , Vinod Koul , Neil Armstrong , Russell King , Lee Jones Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, mfd@lists.linux.dev, =?utf-8?q?Stefan_D=C3=B6singer?= X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; 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a=openpgp; fpr=4F9C2C8728019633893EBBB98CB81F9A72BBA155 This is based on meson/clk-regmap.c, although slightly simplified. I have kept the copyright lines at the top of the file to indicate its origin. I see that numerous clock drivers have their own incarnation of regmap- based mux/div/gate clocks. If there is any version of it that is likely to be elevated to shared code like clk-gate.c I'll copy that and try to use it as unmodified as possible. Signed-off-by: Stefan D=C3=B6singer Reviewed-by: Brian Masney --- Version 9: Register single clocks per function invocation, remove ZX297520V3_CLK_NO_EXPORT again Version 8: Use ZX297520V3_CLK_NO_EXPORT instead of 0 for unexported clocks. Version 6: Remove stray regmap (Sashiko) Version 5: Use regmap_test_bits in zte_clk_regmap_gate_is_enabled --- drivers/clk/zte/clk-regmap.c | 219 +++++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 212 insertions(+), 7 deletions(-) diff --git a/drivers/clk/zte/clk-regmap.c b/drivers/clk/zte/clk-regmap.c index 80332dba97f6..022b2be7bb3d 100644 --- a/drivers/clk/zte/clk-regmap.c +++ b/drivers/clk/zte/clk-regmap.c @@ -1,32 +1,237 @@ // SPDX-License-Identifier: GPL-2.0 /* + * Copyright (c) 2018 BayLibre, SAS. * Copyright (c) 2026 Stefan D=C3=B6singer */ =20 +#include #include +#include #include +#include #include #include +#include =20 #include "clk-zx.h" =20 +struct zte_clk_regmap { + struct clk_hw hw; + struct regmap *map; + u16 reg; + u8 shift; + u8 size; +}; + +static inline struct zte_clk_regmap *to_zte_clk_regmap(struct clk_hw *hw) +{ + return container_of(hw, struct zte_clk_regmap, hw); +} + +static int zte_clk_regmap_gate_enable(struct clk_hw *hw) +{ + struct zte_clk_regmap *clk =3D to_zte_clk_regmap(hw); + + return regmap_set_bits(clk->map, clk->reg, BIT(clk->shift)); +} + +static void zte_clk_regmap_gate_disable(struct clk_hw *hw) +{ + struct zte_clk_regmap *clk =3D to_zte_clk_regmap(hw); + + regmap_clear_bits(clk->map, clk->reg, BIT(clk->shift)); +} + +static int zte_clk_regmap_gate_is_enabled(struct clk_hw *hw) +{ + struct zte_clk_regmap *clk =3D to_zte_clk_regmap(hw); + + return regmap_test_bits(clk->map, clk->reg, BIT(clk->shift)); +} + +static const struct clk_ops zte_clk_regmap_gate_ops =3D { + .enable =3D zte_clk_regmap_gate_enable, + .disable =3D zte_clk_regmap_gate_disable, + .is_enabled =3D zte_clk_regmap_gate_is_enabled, +}; + struct clk_hw *zx_clk_register_gate(struct device *dev, struct regmap *reg= map, - const struct zx_gate_desc *desc, - struct clk_hw * const *clocks) + const struct zx_gate_desc *desc, struct clk_hw * const *clocks) +{ + struct clk_parent_data parent =3D zx_get_parent(&desc->parent, clocks); + struct clk_init_data init =3D {}; + struct zte_clk_regmap *clk; + int res; + + clk =3D devm_kzalloc(dev, sizeof(*clk), GFP_KERNEL); + if (!clk) + return ERR_PTR(-ENOMEM); + + init.name =3D desc->name; + init.ops =3D &zte_clk_regmap_gate_ops; + init.parent_data =3D &parent; + init.num_parents =3D 1; + init.flags =3D CLK_SET_RATE_PARENT | desc->flags; + clk->hw.init =3D &init; + clk->map =3D regmap; + clk->reg =3D desc->reg; + clk->shift =3D desc->shift; + clk->size =3D 1; + + res =3D devm_clk_hw_register(dev, &clk->hw); + if (res) + return ERR_PTR(res); + + return &clk->hw; +} + +static unsigned long zte_clk_regmap_div_recalc_rate(struct clk_hw *hw, + unsigned long prate) +{ + struct zte_clk_regmap *clk =3D to_zte_clk_regmap(hw); + unsigned int val; + int ret; + + ret =3D regmap_read(clk->map, clk->reg, &val); + if (ret) + return 0; /* Gives a hint that something is wrong */ + + val >>=3D clk->shift; + val &=3D clk_div_mask(clk->size); + + return divider_recalc_rate(hw, prate, val, NULL, 0, clk->size); +} + +static int zte_clk_regmap_div_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct zte_clk_regmap *clk =3D to_zte_clk_regmap(hw); + + return divider_determine_rate(hw, req, NULL, clk->size, 0); +} + +static int zte_clk_regmap_div_set_rate(struct clk_hw *hw, unsigned long ra= te, + unsigned long parent_rate) { - return ERR_PTR(-ENODEV); + struct zte_clk_regmap *clk =3D to_zte_clk_regmap(hw); + unsigned int val; + int ret; + + ret =3D divider_get_val(rate, parent_rate, NULL, clk->size, 0); + if (ret < 0) + return ret; + + val =3D (unsigned int)ret << clk->shift; + + return regmap_update_bits(clk->map, clk->reg, clk_div_mask(clk->size) << = clk->shift, val); } =20 +static const struct clk_ops zte_clk_regmap_divider_ops =3D { + .recalc_rate =3D zte_clk_regmap_div_recalc_rate, + .determine_rate =3D zte_clk_regmap_div_determine_rate, + .set_rate =3D zte_clk_regmap_div_set_rate, +}; + struct clk_hw *zx_clk_register_divider(struct device *dev, struct regmap *= regmap, const struct zx_div_desc *desc, struct clk_hw * const *clocks) { - return ERR_PTR(-ENODEV); + struct clk_parent_data parent =3D zx_get_parent(&desc->parent, clocks); + struct clk_init_data init =3D {}; + struct zte_clk_regmap *clk; + int res; + + clk =3D devm_kzalloc(dev, sizeof(*clk), GFP_KERNEL); + if (!clk) + return ERR_PTR(-ENOMEM); + + init.name =3D desc->name; + init.ops =3D &zte_clk_regmap_divider_ops; + init.parent_data =3D &parent; + init.num_parents =3D 1; + init.flags =3D CLK_SET_RATE_PARENT; + clk->hw.init =3D &init; + clk->map =3D regmap; + clk->reg =3D desc->reg; + clk->shift =3D desc->shift; + clk->size =3D desc->size; + + res =3D devm_clk_hw_register(dev, &clk->hw); + if (res) + return ERR_PTR(res); + + return &clk->hw; } =20 +static u8 zte_clk_regmap_mux_get_parent(struct clk_hw *hw) +{ + struct zte_clk_regmap *clk =3D to_zte_clk_regmap(hw); + unsigned int val; + int ret; + + ret =3D regmap_read(clk->map, clk->reg, &val); + if (ret) + return 0xff; + + val >>=3D clk->shift; + val &=3D GENMASK(clk->size - 1, 0); + + return clk_mux_val_to_index(hw, NULL, 0, val); +} + +static int zte_clk_regmap_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct zte_clk_regmap *clk =3D to_zte_clk_regmap(hw); + unsigned int val =3D clk_mux_index_to_val(NULL, 0, index); + + return regmap_update_bits(clk->map, clk->reg, + GENMASK(clk->size - 1, 0) << clk->shift, + val << clk->shift); +} + +static int zte_clk_regmap_mux_determine_rate(struct clk_hw *hw, struct clk= _rate_request *req) +{ + return clk_mux_determine_rate_flags(hw, req, 0); +} + +static const struct clk_ops zte_clk_regmap_mux_ops =3D { + .get_parent =3D zte_clk_regmap_mux_get_parent, + .set_parent =3D zte_clk_regmap_mux_set_parent, + .determine_rate =3D zte_clk_regmap_mux_determine_rate, +}; + struct clk_hw *zx_clk_register_mux(struct device *dev, struct regmap *regm= ap, - const struct zx_mux_desc *desc, - struct clk_hw * const *clocks) + const struct zx_mux_desc *desc, struct clk_hw * const *clocks) { - return ERR_PTR(-ENODEV); + struct clk_parent_data parents[CLK_ZX_MAX_PARENTS]; + struct clk_init_data init =3D {}; + struct zte_clk_regmap *clk; + unsigned int i; + int res; + + if (WARN_ON(desc->num_parents > ARRAY_SIZE(parents))) + return ERR_PTR(-EINVAL); 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a=openpgp; fpr=4F9C2C8728019633893EBBB98CB81F9A72BBA155 I am guessing how much of this is reusable among other zx chips or even differently named ZTE platforms (if there are any). From reading the old zx2967 code, I think the PLL code would be reusable there, maybe with platform-specific bitmasks but otherwise the same logic. Signed-off-by: Stefan D=C3=B6singer --- Version 9: *) Take req->min_rate and req->max_rate into account when looking for possible PLL configurations (sashiko). In practice the code will still only ever encounter a fixed request to set dpll to 491.52 MHz. *) The same code style changes Brian requested on the other clk patches. Version 8: *) Document the behavior of unlocked PLLs better: They don't pass through their reference/parent, but pass through the fixed clock-26m oscillator, even if their reference clock is something else. *) dpll has working fractionals. Add this in the comment, but there is no actual code support for it - the LTE hardware doesn't need it. As for Sashiko's comments on the .set_rate implementation: In practice .set_rate will only ever set one rate, 491.52 MHz for dpll. All other PLLs are bootloader configured. Dpll could be handled by writing a magic constant into its config. I want to have the rate finding code as documentation, and maybe there is more elaborate future use for it (e.g. more flexible underclocking), but attempts to handle eventualities like rate searches or misconfigured bootloader values would be dead code. Version 7: *) Always keep unknownpll enabled when prepared so dpll can acquire a lock in its prepare() function. *) Clean up error reporting a bit (Sashiko) Version 6: *) Use abs_diff to compare target and candidate PLL rate (Sashiko). *) Use req->best_parent_rate in zx29_pll_determine_rate. Add a TODO comment about the parent rate flexibility. Version 5: Fix some issues pointed out by Sashiko: NULL dev, zx29_pll_recalc_rate error handling, disable PLL again on enable error. --- drivers/clk/zte/pll-zx.c | 568 +++++++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 565 insertions(+), 3 deletions(-) diff --git a/drivers/clk/zte/pll-zx.c b/drivers/clk/zte/pll-zx.c index fc76c6524a16..e61b462ec0b4 100644 --- a/drivers/clk/zte/pll-zx.c +++ b/drivers/clk/zte/pll-zx.c @@ -4,15 +4,577 @@ */ =20 #include +#include +#include #include +#include #include +#include +#include #include +#include +#include =20 #include "clk-zx.h" =20 +/* + * This code has only been tested with zx297520v3 PLLs, but from reading t= he zx296718 clock code it + * looks like PLL registers are similar. ZTE's sources explain the PLL reg= ister contents only in a + * .cmm file (A Lauterbach TRACE32 script) and some unused headers in thei= r U-Boot code dump, which + * may not be accurate. When calculating the frequencies from the default = PLL configuration the + * results match the fixed rate clocks from their clock driver. + * + * The 26 MHz and 32 kHz clocks can be easily observed with the timers. Th= e 104 MHz output can be + * observed through the UART. One 122.88 MHz clock can be observed through= the TDM device. All + * others can only be indirectly inferred, e.g. by comparing CPU speed or = SDIO transfer rate between + * the fixed 26 MHz oscillator and the provided PLL frequency. + * + * The formula to calculate the clock is ((ref / refdiv) * fbdiv) / postdi= v1 / postdiv2. The masks + * are given below. There are a few control flags: + * + * Bit 31: Disables the PLL, but passes clock-26m through unmodified. Whet= her POSTDIV_OUT_DISABLE + * still matters is different between PLLs. + * Bit 30: Returns if the PLL is locked + * Bit 29: Not named in ZTE's code, but can be set. There is no obvious im= pact. Lock times are + * unchanged, so it doesn't influence or bypass lock detection. It= doesn't raise any IRQs or + * influence GPIOs. + * Bit 27: Given its name it likely disables the Delta-Sigma Modulator, if= one exists at all. The + * boot ROM sets it on every PLL. Unsetting it marginally decrease= s the time it takes to + * lock to the reference clock (from ~400 us to ~300 us). + * Bit 24: Bypasses the VCO, but still applies refdiv and postdiv. Doesn't= matter if PLL_DISABLE=3D1. + * + * NB: Some PLLs have an automatic bypass logic that forwards clock-26m (R= EGARDLESS of reference) + * when they don't have a lock, regardless of reason. This can be triggere= d by disabling the PLL, + * setting an out-of-spec VCO frequency or disabling the parent. This shou= ldn't matter in regular + * operation, but caused me some confusion when reverse engineering the cl= ock tree. E.g. clock-26m-> + * unknownpll(disabled) -> dpll(enabled) counterintuitively results in a 2= 6 MHz output clock. + */ + +#define ZX29_PLL_DISABLE BIT(31) +#define ZX29_PLL_LOCKED BIT(30) +#define ZX29_PLL_LOCK_FILTER BIT(29) +#define ZX29_PLL_DSM_DISABLE BIT(27) +#define ZX29_PLL_PARENT_MASK GENMASK(26, 25) +#define ZX29_PLL_PARENT_SHIFT 25 +#define ZX29_PLL_BYPASS BIT(24) +#define ZX29_PLL_REFDIV_MASK GENMASK(23, 18) +#define ZX29_PLL_REFDIV_SHIFT 18 +#define ZX29_PLL_FBDIV_MASK GENMASK(17, 6) +#define ZX29_PLL_FBDIV_SHIFT 6 +#define ZX29_PLL_POSTDIV1_MASK GENMASK(5, 3) +#define ZX29_PLL_POSTDIV1_SHIFT 3 +#define ZX29_PLL_POSTDIV2_MASK GENMASK(2, 0) +#define ZX29_PLL_POSTDIV2_SHIFT 0 + +/* + * The second register has a 24 bit fractional value, which only matters w= hen ZX29_PLL_DSM_DISABLE + * is not set, and only seems to matter for dpll. ZTE's firmware does not = make use of the fractional + * and it is unimplemented in this driver. Experimental testing confirms t= hat it has an impact on + * dpll. + * + * Bits 27:24 contain more flags: + * + * Bit 27: Setting ZX29_PLL_DACAP slows down the lock time and obviates th= e speed gained from + * !DSM_DISABLE. No other effect observed. + * + * Bit 26: ZX29_PLL_4PHASE_OUT_DISABLE is set on some PLLs on boot but not= on others. It is set on + * boot on mpll and upll, but not gpll, dpll or unknownpll. I am n= ot sure what it does + * either. The SDIO devices break if they are fed from gpll with t= his flag set, but they + * work OK if they are fed from mpll without this flag set. + * + * Bit 25: ZX29_PLL_POSTDIV_OUT_DISABLE seems to disable the PLL output en= tirely. Whether it is + * bypassed by PLL_DISABLE differs between PLLs. gpll still produc= es an output clock if + * PLL_DISABLE =3D 1 and POSTDIV_DISABLE =3D 1, but produces no ou= tput if PLL_DISABLE =3D 0 and + * POSTDIV_DISABLE =3D 1. The dpll feeder ("unknownpll") at 0x100 = produces no output clock if + * both PLL_DISABLE and POSTDIV_DISABLE are set to 1. + * + * Bit 24: ZX29_PLL_VCO_OUT_DISABLE probably disables the output of the VC= O clock without + * post-VCO-dividers, but the raw VCO output is not a possible par= ent of any consumer clock, + * so I could not confirm this. It does not disable the VCO entire= ly - that's what + * PLL_DISABLE does. + * + * A spinlock should not be needed. PLLs don't share their registers with = anything else and the + * global prepare mutex and enable spinlock should be enough. Beware of co= nflicts in reg2 between + * POSTDIV_OUT_DISABLE and the fractional value in case you find out how f= ractional dividers work + * and add support for them. + */ +#define ZX29_PLL_REG2_OFFSET 4 +#define ZX29_PLL_DACAP BIT(27) +#define ZX29_PLL_4PHASE_OUT_DISABLE BIT(26) +#define ZX29_PLL_POSTDIV_OUT_DISABLE BIT(25) +#define ZX29_PLL_VCO_OUT_DISABLE BIT(24) +#define ZX29_PLL_FRACT GENMASK(23, 0) + +/* + * The VCO's frequency range is limited. The stock settings run the VCO be= tween 960 and 1248 MHz. + * Ad-hoc testing with gpll suggests that at least this PLL remains stable= down to about 7 MHz and + * up to 2 GHz and produces a clock that can be used by the SDIO controlle= r. Attempting to run the + * mpll VCO at 624 MHz and setting postdiv1 =3D postdiv2 =3D 1 - which sho= uld result in the same output + * frequency - or running it at 1872 MHz with an effective post divider of= 3 crashes the CPU. Most + * likely the PLLs become unstable outside their core range and the SDIO c= ontroller is much more + * forgiving than CPU and DRAM are. + */ +#define ZX29_PLL_VCO_MAX_FREQ (1300 * HZ_PER_MHZ) +#define ZX29_PLL_VCO_MIN_FREQ (900 * HZ_PER_MHZ) + +struct zx29_clk_pll { + struct clk_hw hw; + struct device *dev; + struct regmap *map; + u16 reg; +}; + +static inline struct zx29_clk_pll *to_zx29_clk_pll(struct clk_hw *hw) +{ + return container_of(hw, struct zx29_clk_pll, hw); +} + +static int zx29_pll_is_prepared(struct clk_hw *hw) +{ + struct zx29_clk_pll *pll =3D to_zx29_clk_pll(hw); + int res; + + res =3D regmap_test_bits(pll->map, pll->reg, ZX29_PLL_DISABLE); + if (res < 0) + return res; + + return !res; +} + +static int zx29_pll_prepare(struct clk_hw *hw) +{ + struct zx29_clk_pll *pll =3D to_zx29_clk_pll(hw); + u32 val =3D 0; + int res; + + res =3D regmap_clear_bits(pll->map, pll->reg, ZX29_PLL_DISABLE); + if (res < 0) + return res; + + /* Lock duration is usually between 300 us and 500 us */ + res =3D regmap_read_poll_timeout(pll->map, pll->reg, val, val & ZX29_PLL_= LOCKED, 50, 2000); + if (res) { + regmap_set_bits(pll->map, pll->reg, ZX29_PLL_DISABLE); + dev_err(pll->dev, "%s: PLL prepare failed: %d. Config value 0x%08x\n", + clk_hw_get_name(&pll->hw), res, val); + } + return res; +} + +static void zx29_pll_unprepare(struct clk_hw *hw) +{ + struct zx29_clk_pll *pll =3D to_zx29_clk_pll(hw); + + regmap_set_bits(pll->map, pll->reg, ZX29_PLL_DISABLE); +} + +static int zx29_pll_is_enabled(struct clk_hw *hw) +{ + struct zx29_clk_pll *pll =3D to_zx29_clk_pll(hw); + int res; + + res =3D regmap_test_bits(pll->map, pll->reg + ZX29_PLL_REG2_OFFSET, + ZX29_PLL_POSTDIV_OUT_DISABLE); + if (res < 0) + return res; + + return !res; +} + +static int zx29_pll_enable(struct clk_hw *hw) +{ + struct zx29_clk_pll *pll =3D to_zx29_clk_pll(hw); + + return regmap_clear_bits(pll->map, pll->reg + ZX29_PLL_REG2_OFFSET, + ZX29_PLL_POSTDIV_OUT_DISABLE); +} + +static void zx29_pll_disable(struct clk_hw *hw) +{ + struct zx29_clk_pll *pll =3D to_zx29_clk_pll(hw); + + regmap_set_bits(pll->map, pll->reg + ZX29_PLL_REG2_OFFSET, + ZX29_PLL_POSTDIV_OUT_DISABLE); +} + +static unsigned long zx29_pll_get_rate(const struct zx29_clk_pll *pll, uns= igned long parent_rate, + u32 setting) +{ + unsigned long refdiv, fbdiv, postdiv1, postdiv2, freq; + const char *name =3D clk_hw_get_name(&pll->hw); + u64 vco; + + refdiv =3D (setting & ZX29_PLL_REFDIV_MASK) >> ZX29_PLL_REFDIV_SHIFT; + fbdiv =3D (setting & ZX29_PLL_FBDIV_MASK) >> ZX29_PLL_FBDIV_SHIFT; + postdiv1 =3D (setting & ZX29_PLL_POSTDIV1_MASK) >> ZX29_PLL_POSTDIV1_SHIF= T; + postdiv2 =3D (setting & ZX29_PLL_POSTDIV2_MASK) >> ZX29_PLL_POSTDIV2_SHIF= T; + dev_dbg(pll->dev, "%s: reference clock %lu Hz, PLL setting 0x%08x\n", + name, parent_rate, setting); + + if (!refdiv || !postdiv1 || !postdiv2) { + dev_err(pll->dev, "%s: divide by zero (%lu, %lu, %lu)\n", name, refdiv, = postdiv1, + postdiv2); + return 0; + } + + vco =3D div_u64((u64)parent_rate * fbdiv, refdiv); + freq =3D div_u64(div_u64(vco, postdiv1), postdiv2); + dev_dbg(pll->dev, "%s: refdiv %lu fbdiv %lu\n", name, refdiv, fbdiv); + dev_dbg(pll->dev, "%s: postdiv1 %lu postdiv2 %lu\n", name, postdiv1, post= div2); + + dev_dbg(pll->dev, "%s: %lu MHz\n", name, freq / HZ_PER_MHZ); + + return freq; +} + +static unsigned long zx29_pll_recalc_rate(struct clk_hw *hw, unsigned long= parent_rate) +{ + struct zx29_clk_pll *pll =3D to_zx29_clk_pll(hw); + u32 val; + int res; + + res =3D regmap_read(pll->map, pll->reg, &val); + if (res < 0) { + dev_err(pll->dev, "%s: Failed to read PLL settings\n", clk_hw_get_name(&= pll->hw)); + return 0; + } + + return zx29_pll_get_rate(pll, parent_rate, val); +} + +static u32 zx29_pll_calc_values(const struct zx29_clk_pll *pll, unsigned l= ong parent_rate, + unsigned long rate, unsigned long min_rate, unsigned long max_rate) +{ + const unsigned int postdiv1_max =3D (1 << hweight32(ZX29_PLL_POSTDIV1_MAS= K)) - 1; + const unsigned int postdiv2_max =3D (1 << hweight32(ZX29_PLL_POSTDIV2_MAS= K)) - 1; + unsigned long fbdiv, refdiv, best_fbdiv =3D 0, best_refdiv =3D 0; + u32 postdiv1 =3D 0, postdiv2 =3D 0, i, j, setting; + const char *name =3D clk_hw_get_name(&pll->hw); + long best =3D LONG_MAX; + + /* + * This code produces the same VCO settings that the boot loader and stoc= k firmware use for + * the standard frequencies. It has seen only very little manual testing = beyond that. + * + * The goal is to find a VCO setting that gets us as close as possible to= the desired output + * rate, while being within the VCO's operating limits and achievable wit= h the input value + * range. It is iterating over possible post-VCO divider values (1-7)*(1-= 7) to look for + * valid VCO target frequencies and then looks for refdiv and fbdiv value= s to achieve the + * VCO frequency from the reference frequency. + */ + for (j =3D 1; j <=3D postdiv2_max; j++) { + for (i =3D 1; i <=3D postdiv1_max; i++) { + u64 vco =3D (u64)rate * i * j; + unsigned long out; + + if (vco > ZX29_PLL_VCO_MAX_FREQ || vco < ZX29_PLL_VCO_MIN_FREQ) + continue; + + rational_best_approximation(vco, parent_rate, + (1 << hweight32(ZX29_PLL_FBDIV_MASK)) - 1, + (1 << hweight32(ZX29_PLL_REFDIV_MASK)) - 1, + &fbdiv, &refdiv); + setting =3D fbdiv << ZX29_PLL_FBDIV_SHIFT; + setting |=3D refdiv << ZX29_PLL_REFDIV_SHIFT; + setting |=3D i << ZX29_PLL_POSTDIV1_SHIFT; + setting |=3D j << ZX29_PLL_POSTDIV2_SHIFT; + out =3D zx29_pll_get_rate(pll, parent_rate, setting); + + if (out < min_rate || out > max_rate) + continue; + + if (abs_diff(out, rate) > best) + continue; + + if (abs_diff(out, rate) < best) { + postdiv1 =3D i; + postdiv2 =3D j; + best_fbdiv =3D fbdiv; + best_refdiv =3D refdiv; + best =3D abs_diff(out, rate); + + if (!best) + goto search_done; + } + } + } +search_done: + + if (!postdiv1) { + dev_err(pll->dev, "Did not find a setting for %lu Hz, parent %lu Hz\n", + rate, parent_rate); + return 0; + } + + dev_dbg(pll->dev, "%s: parent rate %lu\n", name, parent_rate); + dev_dbg(pll->dev, "%s: found VCO dividers %u and %u\n", name, postdiv1, p= ostdiv2); + dev_dbg(pll->dev, "%s: VCO target rate %lu\n", name, rate * postdiv1 * po= stdiv2); + + dev_dbg(pll->dev, "%s: Got fbdiv =3D %lu refdiv =3D %lu\n", name, best_fb= div, best_refdiv); + + setting =3D best_fbdiv << ZX29_PLL_FBDIV_SHIFT; + setting |=3D best_refdiv << ZX29_PLL_REFDIV_SHIFT; + setting |=3D postdiv1 << ZX29_PLL_POSTDIV1_SHIFT; + setting |=3D postdiv2 << ZX29_PLL_POSTDIV2_SHIFT; + dev_dbg(pll->dev, "%s: Final setting 0x%08x\n", name, setting); + + return setting; +} + +static int zx29_pll_determine_rate(struct clk_hw *hw, struct clk_rate_requ= est *req) +{ + struct zx29_clk_pll *pll =3D to_zx29_clk_pll(hw); + unsigned long new_rate; + u32 setting; + + /* + * TODO: DPLL can switch between two parents, one of which is another PLL= . Take this into + * account when searching the config space and set req->best_parent_rate. + * + * In practice it shouldn't matter though. Dpll is always configured to a= fixed frequency + * and is the only clock with a switchable parent. + */ + if (!req->best_parent_rate) { + dev_err(pll->dev, "Did not expect best_parent_rate=3D0\n"); + return -EINVAL; + } + + setting =3D zx29_pll_calc_values(pll, req->best_parent_rate, req->rate, r= eq->min_rate, + req->max_rate); + if (!setting) + return -EINVAL; + + new_rate =3D zx29_pll_get_rate(pll, req->best_parent_rate, setting); + if (new_rate !=3D req->rate) { + dev_warn(pll->dev, "Did not find an exact match. Want %lu, got %lu\n", + req->rate, new_rate); + req->rate =3D new_rate; + } + + return 0; +} + +static int zx29_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct zx29_clk_pll *pll =3D to_zx29_clk_pll(hw); + u32 setting; + + /* + * TODO: Implement gradual PLL rate change. PLLs can be changed while the= y are running and + * downstream hardware is generally fine with that. The exception is DRAM= , which reads + * incorrect values if changed too fast. + * + * Changing the mpll rate is potentially useful for over/underclocking. G= ating mpll is + * unrealistic because too many devices depend on it. + */ + setting =3D zx29_pll_calc_values(pll, parent_rate, rate, rate, rate); + if (!setting) + return -EINVAL; + + dev_info(pll->dev, "%s: Setting new configuration: 0x%08x\n", clk_hw_get_= name(hw), setting); + + return regmap_update_bits(pll->map, pll->reg, 0x00ffffff, setting); +} + +static u8 zx29_pll_get_parent(struct clk_hw *hw) +{ + struct zx29_clk_pll *pll =3D to_zx29_clk_pll(hw); + u32 val; + int res; + + res =3D regmap_read(pll->map, pll->reg, &val); + if (res < 0) + return 0xff; + + val =3D (val & ZX29_PLL_PARENT_MASK) >> ZX29_PLL_PARENT_SHIFT; + dev_dbg(pll->dev, "%s: Parent 0x%x\n", clk_hw_get_name(hw), val); + + return val; +} + +static int zx29_pll_set_parent(struct clk_hw *hw, u8 index) +{ + struct zx29_clk_pll *pll =3D to_zx29_clk_pll(hw); + u32 idx_shift =3D index << ZX29_PLL_PARENT_SHIFT; + int res; + u32 val; + + res =3D regmap_update_bits(pll->map, pll->reg, ZX29_PLL_PARENT_MASK, idx_= shift); + if (res < 0) + return res; + + res =3D regmap_read(pll->map, pll->reg, &val); + if (res < 0) + return res; + + if ((val & ZX29_PLL_PARENT_MASK) !=3D idx_shift) { + dev_err(pll->dev, "Hardware rejected PLL parent %u\n", index); + return -EINVAL; + } + + return 0; +} + +static int zx29_pll_init(struct clk_hw *hw) +{ + struct zx29_clk_pll *pll =3D to_zx29_clk_pll(hw); + const char *name =3D clk_hw_get_name(hw); + int res; + u32 val; + + dev_dbg(pll->dev, "%s: initializing\n", name); + + /* + * The fractional value is not yet implemented. It works at least with dp= ll, but I have + * never seen it used on actual hardware. + */ + res =3D regmap_read(pll->map, pll->reg + ZX29_PLL_REG2_OFFSET, &val); + if (res < 0) + return res; + + if (val & ZX29_PLL_FRACT) { + dev_warn(pll->dev, "%s: unsupported nonzero fractional value 0x%08lx\n", + name, val & ZX29_PLL_FRACT); + } + + /* + * Remove the bypass flag so we don't have to bother with it in enable/di= sable. I have never + * seen it set by the earlier boot stages anyhow. + */ + res =3D regmap_clear_bits(pll->map, pll->reg, ZX29_PLL_BYPASS); + if (res < 0) + return res; + + res =3D regmap_test_bits(pll->map, pll->reg, ZX29_PLL_DISABLE); + if (res > 0) { + /* + * Set ZX29_PLL_POSTDIV_OUT_DISABLE for PLLs that have ZX29_PLL_DISABLE = for + * consistency with .enable and .prepare. This ensures that .prepare doe= sn't + * inadvertently enable PLLs without .enable being called. + */ + res =3D regmap_set_bits(pll->map, pll->reg + ZX29_PLL_REG2_OFFSET, + ZX29_PLL_POSTDIV_OUT_DISABLE); + } + + return res; +} + +static const struct clk_ops zx29_pll_ops =3D { + .init =3D zx29_pll_init, + .is_prepared =3D zx29_pll_is_prepared, + .prepare =3D zx29_pll_prepare, + .unprepare =3D zx29_pll_unprepare, + .is_enabled =3D zx29_pll_is_enabled, + .enable =3D zx29_pll_enable, + .disable =3D zx29_pll_disable, + .recalc_rate =3D zx29_pll_recalc_rate, + .determine_rate =3D zx29_pll_determine_rate, + .get_parent =3D zx29_pll_get_parent, + .set_parent =3D zx29_pll_set_parent, + .set_rate =3D zx29_pll_set_rate, +}; + +/* + * A PLL that can be a parent of another PLL needs to produce an output si= gnal when prepared, + * otherwise the downstream PLL's prepare() will fail to acquire a lock. + */ +static int zx29_pll_nodisable_init(struct clk_hw *hw) +{ + struct zx29_clk_pll *pll =3D to_zx29_clk_pll(hw); + const char *name =3D clk_hw_get_name(hw); + int res; + u32 val; + + dev_dbg(pll->dev, "%s: initializing, prepare-is-enabled\n", name); + + res =3D regmap_read(pll->map, pll->reg + ZX29_PLL_REG2_OFFSET, &val); + if (res < 0) + return res; + + if (val & ZX29_PLL_FRACT) { + dev_warn(pll->dev, "%s: unsupported nonzero fractional value 0x%08lx\n", + name, val & ZX29_PLL_FRACT); + } + + res =3D regmap_clear_bits(pll->map, pll->reg, ZX29_PLL_BYPASS); + if (res < 0) + return res; + + return regmap_clear_bits(pll->map, pll->reg + ZX29_PLL_REG2_OFFSET, + ZX29_PLL_POSTDIV_OUT_DISABLE); +} + +static const struct clk_ops zx29_pll_nodisable_ops =3D { + .init =3D zx29_pll_nodisable_init, + .is_prepared =3D zx29_pll_is_prepared, + .prepare =3D zx29_pll_prepare, + .unprepare =3D zx29_pll_unprepare, + .recalc_rate =3D zx29_pll_recalc_rate, + .determine_rate =3D zx29_pll_determine_rate, + .get_parent =3D zx29_pll_get_parent, + .set_parent =3D zx29_pll_set_parent, + .set_rate =3D zx29_pll_set_rate, +}; + struct clk_hw *zx_clk_register_pll(struct device *dev, struct regmap *regm= ap, - const struct zx_pll_desc *desc, - struct clk_hw * const *clocks) + const struct zx_pll_desc *desc, struct clk_hw * const *clocks) { - return ERR_PTR(-ENODEV); + struct clk_parent_data parents[CLK_ZX_MAX_PARENTS]; + struct clk_init_data init =3D {}; + struct zx29_clk_pll *pll; + unsigned int i; + int res; + + pll =3D devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + if (desc->flags & CLK_ZX_PLL_PREPARE_IS_ENABLE) + init.ops =3D &zx29_pll_nodisable_ops; + else + init.ops =3D &zx29_pll_ops; + + if (WARN_ON(desc->num_parents > ARRAY_SIZE(parents))) + return ERR_PTR(-EINVAL); + + for (i =3D 0; i < desc->num_parents; ++i) + parents[i] =3D zx_get_parent(&desc->parents[i], clocks); + + init.name =3D desc->name; + init.parent_data =3D parents; + init.num_parents =3D desc->num_parents; + + /* + * Disallow live reparent, but allow rate changes. PLLs can handle gradua= l changes fine, but + * large ones cause a temporary incorrect output, which can break downstr= eam devices. + * See zx29_pll_set_rate for considerations on that. + */ + init.flags =3D CLK_SET_PARENT_GATE; + pll->hw.init =3D &init; + pll->dev =3D dev; + pll->map =3D regmap; + pll->reg =3D desc->reg; + + res =3D devm_clk_hw_register(dev, &pll->hw); + if (res) + return ERR_PTR(res); + + /* + * Set the PLL rate only if the bootloader left it disabled. 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Sun, 02 Aug 2026 13:34:45 -0700 (PDT) Received: from [192.168.0.2] ([197.250.226.155]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49807bb45ebsm118499905e9.4.2026.08.02.13.34.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Aug 2026 13:34:44 -0700 (PDT) From: =?utf-8?q?Stefan_D=C3=B6singer?= Date: Sun, 02 Aug 2026 23:33:40 +0300 Subject: [PATCH v9 08/12] clk: zte: Introduce a driver for zx297520v3 top clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260802-zx29clk-v9-8-d05530d85d28@gmail.com> References: <20260802-zx29clk-v9-0-d05530d85d28@gmail.com> In-Reply-To: <20260802-zx29clk-v9-0-d05530d85d28@gmail.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Brian Masney , Vinod Koul , Neil Armstrong , Russell King , Lee Jones Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, mfd@lists.linux.dev, =?utf-8?q?Stefan_D=C3=B6singer?= X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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a=openpgp; fpr=4F9C2C8728019633893EBBB98CB81F9A72BBA155 This register space controls core devices: PLLs, the AHB bus, a lot of timers, the USB controller, the Cortex M0 processor that boots the board and a few other devices. For some reason the LTE coprocessor is also partially controlled by it. The main application processor and DDR memory are not found here though. The register to reboot the board is found here, as well as a register to control whether watchdog expiries cause a board reset. Signed-off-by: Stefan D=C3=B6singer --- Version 9: Link internal parents by an (internal) clock ID rather than names. There should be no difference in the built clock tree compared to Version 8. Version 8: Rename the expected clock name of the fixed oscillators to clock-26m and clock-32k. Sashiko pointed out that "oscXXm" is deprecated, although widespread in existing drivers. Add a define indirection for the AXI candidate=3Dcritical protection. While it holds true in a system with running rprocs, I find it useful for stress testing the clock tree to disable it. Double-checked pclk and wclk bits, fixed incorrect assignments in register 0x54. Version 7: The register at top+0x140 contains a series of gates that control PLL input into the top controller and PLL and osc26m work clock forward into matrix. This allowed further insight into the clock tree. The PLL subdivision list was replaced with fixed factor clocks that divide PLLs before and after the input gate (and some fixed factor divs go into matrix in the next patch). The number of clocks exported to Matrix is actually relatively small. As for Sashiko's suggestion about out of bound parents for dpll and unknownpll: I have never seen a parent !=3D 0. If that happens on a device I want to know about it. At this stage of development I'd rather have clearly visible orphaned clock than silently continuing at an unexpected frequency. "osc26m" -> "clock-26m" as "oscXX", although widespread, is deprecated. In doing so, change underscores in clock names to dashes (Sashiko). Version 5: *) Make it a MFD child driver instead of binding to the node directly *) Correct parents for dpll *) Correct HSIC work clock parent --- drivers/clk/zte/Kconfig | 11 + drivers/clk/zte/Makefile | 1 + drivers/clk/zte/clk-zx297520v3.c | 803 +++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 815 insertions(+) diff --git a/drivers/clk/zte/Kconfig b/drivers/clk/zte/Kconfig index 152c2423b8f0..0ccc6edf3c5b 100644 --- a/drivers/clk/zte/Kconfig +++ b/drivers/clk/zte/Kconfig @@ -15,3 +15,14 @@ config COMMON_CLK_ZTE of this. =20 Enable this if you are building a kernel for a ZTE designed board. + +config CLK_ZTE_ZX297520V3 + tristate "Clock driver for ZTE zx297520v3 based SoCs" + depends on COMMON_CLK_ZTE && (MFD_ZTE_ZX297520V3_CRM || COMPILE_TEST) + default SOC_ZX297520V3 + help + This driver supports ZTE zx297520v3 basic clocks. + + Enable this if you want to build a kernel that is able to run on + boards based on this SoC. You can safely enable multiple clock + drivers. The one(s) matching the device tree will be used. diff --git a/drivers/clk/zte/Makefile b/drivers/clk/zte/Makefile index 27db07293165..2c073512e919 100644 --- a/drivers/clk/zte/Makefile +++ b/drivers/clk/zte/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only =20 obj-$(CONFIG_COMMON_CLK_ZTE) +=3D clk-zte.o +obj-$(CONFIG_CLK_ZTE_ZX297520V3) +=3D clk-zx297520v3.o =20 clk-zte-y +=3D clk-zx.o pll-zx.o clk-regmap.o diff --git a/drivers/clk/zte/clk-zx297520v3.c b/drivers/clk/zte/clk-zx29752= 0v3.c new file mode 100644 index 000000000000..f9915582f261 --- /dev/null +++ b/drivers/clk/zte/clk-zx297520v3.c @@ -0,0 +1,803 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026 Stefan D=C3=B6singer + * + * There are no public datasheets for zx297520v3. The controls on this clo= ck controller have been + * extracted from ZTE's kernel and U-Boot sources and a LOT of manual test= ing. Some clocks can be + * found in the power management (evb_cpurpm.img) and LTE (cpko.ko) blobs = shipped with the routers. + * + * Because ZTE's sources are wrong or misleading in some parts and testing= can be misinterpreted, + * this file contains a LOT of comments on how particular clocks were test= ed and how the impact of + * changes to them can be observed. + */ + +#include +#include +#include +#include +#include +#include + +#include "clk-zx.h" + +MODULE_IMPORT_NS("ZTE_CLK"); + +/* + * AXI speed is either determined by a fixed selection in matrix+0x0, bits= 0:2 or by a voting system + * with ballots in matrix+0x120, 0x124, 0x128. The voting system is enable= d by setting matrix 0x12c + * to 1. Otherwise the selection in 0x0 applies. + * + * The fastest selected speed wins. This holds true for values 0 (26 MHz) = and 7 (6.5 MHz) too, so it + * isn't a case of lowest selector wins. I haven't tested what happens if = mpll is changed to output + * 5x the normal clock, so 7 beats 0. Presumably value 0 would still win t= he election. + * + * AXI speed 6.5 is a child of matrix-osc26m, not a PLL. This can be seen = by gating it off in + * topcrm+0x140. + * + * The system initializes with voting disabled and all preferences set to = the lowest setting, 7. + * The zx297520v3_matrix_init function transfers the global mux to our vot= e and enables voting. + * + * Because rprocs may change their selection without notice, all possible = parents of the AXI mux are + * marked critical. This can however obscure bugs in the clock tree. Defin= e ZX297520V3_AXI_CANDIDATE + * to 0 to disable this protection for testing and either not run anything= on the rprocs or make + * sure Linux votes for the fastest rate. + */ +#define ZX297520V3_AXI_CANDIDATE CLK_IS_CRITICAL + +/* + * Top and matrix clocks are chaotic - I haven't found a consistent patter= n behind their register + * and bit locations. Generally there are two gates (pclk, wclk), one mux,= two resets and sometimes + * one divider, but exceptions apply. For some devices there is only a res= et and some general + * (parent) clocks need setup. This structure plus macro handles the somew= hat regular parts. + * + * There are some patterns that can be observed. + * mux 0x3c, div 0x48, gate 0x54 + * mux 0x40, div 0x4c, gate 0x5c + * mux 0x44, div 0x50, gate 0x60 + * + * For a 0 - 0xc - 0x18 pattern. Muxes from 0x3c to 0x44, dividers from 0x= 48 to 0x50, gates 0x54 to + * 0x60. The pattern is broken for timer t17 though. + * + * Gates have 4 bits per clock - usually, but not always, bit 0 for wclk, = bit 1 for pclk, bit 2 for + * something the ZTE kernel calls "gate" (the bits we use here are called = "en"), which presumably + * enables automatic clock gating. Bit 3, if settable, seems unused. E.g. = offset 0x54 accepts all + * bits in 0xF77F7F7F - suggesting RTC, I2C0 have an extra gate bit. + * + * The default mpll settings multiply the 26 MHz reference clock times 24.= A mux selection of 26 MHz + * could mean using the 26 MHz oscillator directly, or passing it through = the PLL and divide by 24. + * + * If a UART is set to mpll-d6 (default 104 MHz), changing the mpll multip= liers does affect UART + * timing as it should. This does not happen when the UART is set to 26 MH= z input or timers that + * read 26 MHz input. This suggests 26 MHz clocks use the reference clock = directly. + * + * The general clock flow on this board goes from osc26m into the PLLs. Th= e PLL output is + * branched into a small number of divided frequencies (mpll, mpll-d4, mpl= l-d5, mpll-d6, mpll-d8, + * gpll, gpll-d2, gpll-d4) at a high level. These divided frequencies as w= ell as osc26m go + * through a series of gates at offset 0x140 in topcrm. The output of thes= e gates provide wclks for + * everything. + * + * At least 3 of those gate outputs (mpll, dpll, gpll-d2) are further divi= ded behind those gates, + * presumably in the matrix controller. There are multiple paths how 104 a= nd 78 MHz are derived, + * some specific to topcrm (0x140 bits 1 and 4), some specific to matrix (= 0x140 bit 9). There are + * likely 3 "copies" of the 78 MHz clock and two 50 MHz ones. + * + * Pclk is not gated by the 0x140 gates at all. Likewise osc32k is fed to = the timers without + * passing through this gate, even for consumers on matrix/LSP. Topcrm osc= 26m wclks are not gated + * either, but top-consumed PLL clocks are. + */ + +enum top_clock_ids { + ZX_CLK_MPLL, + ZX_CLK_UPLL, + ZX_CLK_DPLL2, + ZX_CLK_DPLL2_D2, + ZX_CLK_DPLL, + ZX_CLK_GPLL, + + ZX_CLK_OSC26M_D2, + ZX_CLK_TOP_MPLL_D2_PREGATE, + ZX_CLK_TOP_MPLL_D5_PREGATE, + ZX_CLK_TOP_MPLL_D6_PREGATE, + ZX_CLK_TOP_MPLL_D8_PREGATE, + ZX_CLK_TOP_UPLL_D12_PREGATE, + ZX_CLK_TOP_GPLL_D2_PREGATE, + ZX_CLK_TOP_GPLL_D4_PREGATE, + + ZX_CLK_TOP_MPLL_D2, + ZX_CLK_TOP_MPLL_D8, + ZX_CLK_TOP_MPLL_D6, + ZX_CLK_TOMATRIX_MPLL_D5, + ZX_CLK_TOMATRIX_MPLL, + ZX_CLK_TOMATRIX_DPLL, + ZX_CLK_TOP_UPLL_D12, + ZX_CLK_TOP_UPLL, + ZX_CLK_TOP_GPLL_D4, + ZX_CLK_TOMATRIX_GPLL_D2, + ZX_CLK_TOMATRIX_GPLL, + ZX_CLK_TOMATRIX_OSC26M, + + ZX_CLK_TOP_MPLL_D2_D4, + ZX_CLK_TOP_MPLL_D2_D13, + ZX_CLK_TOP_UPLL_D12_D2, + ZX_CLK_TOP_GPLL_D4_D2, + + ZX_CLK_M0_MUX, + ZX_CLK_AHB_MUX, + ZX_CLK_TIMER_T08_MUX, + ZX_CLK_TIMER_T09_MUX, + ZX_CLK_TIMER_T12_MUX, + ZX_CLK_TIMER_T13_MUX, + ZX_CLK_TIMER_T14_MUX, + ZX_CLK_TIMER_T15_MUX, + ZX_CLK_TIMER_T16_MUX, + ZX_CLK_TIMER_T17_MUX, + ZX_CLK_WDT_T18_MUX, + ZX_CLK_I2C0_MUX, + ZX_CLK_UART0_MUX, + ZX_CLK_OUT0_MUX, + ZX_CLK_OUT1_MUX, + ZX_CLK_OUT2_MUX, + ZX_CLK_RMIIPHY_MUX, + + ZX_CLK_TIMER_T08_DIV, + ZX_CLK_TIMER_T09_DIV, + ZX_CLK_TIMER_T12_DIV, + ZX_CLK_TIMER_T13_DIV, + ZX_CLK_TIMER_T14_DIV, + ZX_CLK_TIMER_T15_DIV, + ZX_CLK_TIMER_T16_DIV, + ZX_CLK_TIMER_T17_DIV, + ZX_CLK_WDT_T18_DIV, + ZX_CLK_USIM1_DIV, + + ZX_CLK_AHB_PCLK, + ZX_CLK_AHB_WCLK, + ZX_CLK_SRAM1_PCLK, + ZX_CLK_SRAM2_PCLK, + ZX_CLK_PMM_WCLK, + ZX_CLK_PMM_PCLK, + ZX_CLK_TIMER_T08_WCLK, + ZX_CLK_TIMER_T08_PCLK, + ZX_CLK_TIMER_T09_WCLK, + ZX_CLK_TIMER_T09_PCLK, + ZX_CLK_TIMER_T12_WCLK, + ZX_CLK_TIMER_T12_PCLK, + ZX_CLK_TIMER_T13_WCLK, + ZX_CLK_TIMER_T13_PCLK, + ZX_CLK_TIMER_T14_WCLK, + ZX_CLK_TIMER_T14_PCLK, + ZX_CLK_TIMER_T15_WCLK, + ZX_CLK_TIMER_T15_PCLK, + ZX_CLK_TIMER_T16_WCLK, + ZX_CLK_TIMER_T16_PCLK, + ZX_CLK_TIMER_T17_WCLK, + ZX_CLK_TIMER_T17_PCLK, + ZX_CLK_WDT_T18_WCLK, + ZX_CLK_WDT_T18_PCLK, + ZX_CLK_I2C0_WCLK, + ZX_CLK_I2C0_PCLK, + ZX_CLK_UART0_WCLK, + ZX_CLK_UART0_PCLK, + ZX_CLK_USB_WCLK, + ZX_CLK_USB_PCLK, + ZX_CLK_HSIC_WCLK, + ZX_CLK_HSIC_PCLK, + ZX_CLK_RTC_WCLK, + ZX_CLK_RTC_PCLK, + ZX_CLK_USIM1_WCLK, + ZX_CLK_USIM1_PCLK, + ZX_CLK_LPM_GSM_WCLK, + ZX_CLK_LPM_GSM_PCLK, + ZX_CLK_LPM_LTE_WCLK, + ZX_CLK_LPM_LTE_PCLK, + ZX_CLK_LPM_TD_WCLK, + ZX_CLK_LPM_TD_PCLK, + ZX_CLK_LPM_W_WCLK, + ZX_CLK_LPM_W_PCLK, + ZX_CLK_OUT0_WCLK, + ZX_CLK_OUT1_WCLK, + ZX_CLK_OUT2_WCLK, + ZX_CLK_OUT32K_WCLK, + ZX_CLK_RMIIPHY_WCLK, +}; + +/* Used for gates where we don't know the parent input(s). Assume general = oscillator */ +static const struct zx_parent_desc clk_unknown =3D PARENT_FW("osc26m"); + +/* For clocks that are known to use the ungated osc26m input */ +static const struct zx_parent_desc clk_main[] =3D { + PARENT_FW("osc26m"), +}; + +static const struct zx_parent_desc dpll_parents[] =3D { + PARENT_ID(ZX_CLK_DPLL2_D2), + PARENT_FW("osc26m"), +}; + +/* + * AHB: The clock mux works and impact can be tested e.g. with iperf speed= testing of the USB + * network connection. Values 2 and 3 give the same speed and depend on th= e same bit (3) in 0x140. + * The mpll-d6 rate is gated off by the same bit in 0x140 as m0's mpll-d6,= but the d8 is different. + * This may indicate that one of the two uses a different clock rate than = documented in ZTE's + * kernel. The M0 speed is easy to measure, so I am confident in the M0's = 78 MHz rate. AHB looks + * like 78 rather than 52, but confidence is lower because RAM read tests = are influenced by CPU + * overhead too. + */ + +static const struct zx_parent_desc ahb_sel[] =3D { + PARENT_FW("osc26m"), + PARENT_ID(ZX_CLK_TOP_MPLL_D6), /* 104 MHz */ + PARENT_ID(ZX_CLK_TOP_MPLL_D8), /* 78 MHz */ + PARENT_ID(ZX_CLK_TOP_MPLL_D8), /* 78 MHz */ +}; + +static const struct zx_parent_desc timer_top_sel[] =3D { + PARENT_FW("osc32k"), + PARENT_FW("osc26m"), +}; + +static const struct zx_parent_desc uart_top_sel[] =3D { + PARENT_FW("osc26m"), + PARENT_ID(ZX_CLK_TOP_MPLL_D6), /* 104 MHz, sharing M0's and ahb's 0x140 g= ate */ +}; + +/* + * The Cortex M0 coprocessor. It is responsible for booting the board and = runs some power management + * helper code on the stock firmware. The M0 rproc itself is not critical,= but most of topcrm's + * registers become unreadable if this is gated off or become slow when cl= ocked at 32 kHz, e.g. GPIO + * becomes borderline unusable at 32 kHz. + * + * There is no dedicated M0 gate. Disabling ahb-wclk looks like the M0 sto= ps from A53's point of + * view, but it merely breaks the A53's ability to communicate with it, an= d M0's ability to + * communicate with the standard UART on LSP. M0 keeps running with both a= hb-wclk and ahb-pclk + * gated off and can re-enable the gates. + */ +static const struct zx_parent_desc m0_sel[] =3D { + PARENT_FW("osc26m"), + PARENT_ID(ZX_CLK_TOP_MPLL_D6), /* 104 MHz */ + PARENT_ID(ZX_CLK_TOP_MPLL_D2_D4), /* 78 MHz, but different gate than the = ahb 78 MHz */ + PARENT_FW("osc32k"), /* Yes, tested. It is SLLLLOOOOOWWW. */ +}; + +/* + * Clk-out0/1/2/32k: These clocks are exposed on GPIOs 15, 16, 17 and 18 r= espectively. They are used + * in ZTE's camera and sound code, by directly poking into the clock regis= ters from the device + * drivers. Until the respective devices are supported they can safely be = switched off. + * + * For clk-out1 ZTE's camera code says the following: + * + * 0 -> 20 MHz + * 1 -> 40 MHz + * 2 -> 13 MHz + * 3 -> 26 MHz + * + * 0 and 1 read from upll. I confirmed their rates (upll-d24 and upll-d12)= by setting upll to a very + * low frequency and sampling the clock by GPIO reads. The outputs of 2 an= d 3 are way too high to + * test that way. Neither is reading from any PLL, they keep oscillating w= hen all PLLs are disabled. + * I am fairly sure that 3 is just direct osc26m because it perfectly matc= hes what out2 is + * showing in its 26 MHz setting. + * + * Clk-out2 is similar, but it has only one control bit in top 0x34 bit 8.= Neither setting selects + * a PLL output. When setting *0x34 =3D 0x080, clk-out1 and clk-out2 are i= n lockstep, presumably + * running at 13 MHz. 0x1c0 also runs in lockstep, presumably 26 MHz. + * + * clk-out0 has a mux in bit 5. Value 0 most likely selects osc26m. I am n= ot entirely sure about + * value 1 (which is the default), but the m0 mux has an impact on it. It = looks like a debug pin + * that exposes some core clock. + */ +static const struct zx_parent_desc out0_sel[] =3D { + PARENT_FW("osc26m"), + PARENT_ID(ZX_CLK_M0_MUX), +}; + +static const struct zx_parent_desc out1_sel[] =3D { + PARENT_ID(ZX_CLK_TOP_UPLL_D12_D2), /* 20 MHz */ + PARENT_ID(ZX_CLK_TOP_UPLL_D12), /* 40 MHz */ + PARENT_ID(ZX_CLK_OSC26M_D2), /* 13 MHz */ + PARENT_FW("osc26m"), +}; + +static const struct zx_parent_desc out2_sel[] =3D { + PARENT_ID(ZX_CLK_OSC26M_D2), /* 13 MHz */ + PARENT_FW("osc26m"), +}; + +/* + * Clk-o is similar to clk-out*, providing a clock on GPIO 20, presumably = for driving a (R)MII phy. + * The 50 MHz value is documented in a stray comment in ZTE's GMAC driver.= I tested it similarly to + * the above pins. Mux setting 0 gives half the count as setting 1 and set= ting 1 gives gpll divided + * by 4 - matching the 50 MHz suggested by the ZTE comment at the default = gpll settings. Gating gpll + * stops the clock for values 0 and 1. + * + * Settings 2 and 3 are possible, but seem to return garbage. It is genera= lly pulsing up and down, + * except if both gpll and upll are stopped. I suspect it just reads rando= m electrical fluctuation + * from other places in the board. Yes, I had a pull-down enabled when tes= ting this. + * + * I am not aware of any board that uses this though. The Ethernet-equippe= d ones I have all run the + * PHY with its own oscillator. + */ +static const struct zx_parent_desc rmii_sel[] =3D { + PARENT_ID(ZX_CLK_TOP_GPLL_D4_D2), /* 25 MHz */ + PARENT_ID(ZX_CLK_TOP_GPLL_D4), /* 50 MHz */ +}; + +#define PLL(_name, _parents, _rate, _reg, _flags) \ + { \ + .type =3D ZX_CLOCK_PLL, \ + .pll =3D { \ + .name =3D _name, \ + .parents =3D _parents, \ + .num_parents =3D ARRAY_SIZE(_parents), \ + .rate =3D _rate, \ + .reg =3D _reg, \ + .flags =3D _flags, \ + }, \ + } + +#define FIXED_DIV(_name, _parent, _div) \ + { \ + .type =3D ZX_CLOCK_FIXED_DIV, \ + .fixed_div =3D { \ + .name =3D _name, \ + .parent =3D _parent, \ + .div =3D _div, \ + }, \ + } + +#define MUX(_name, _parents, _reg, _shift, _size) \ + { \ + .type =3D ZX_CLOCK_MUX, \ + .mux =3D { \ + .name =3D _name, \ + .parents =3D _parents, \ + .num_parents =3D ARRAY_SIZE(_parents), \ + .reg =3D _reg, \ + .shift =3D _shift, \ + .size =3D _size, \ + }, \ + } + +#define DIV(_name, _parent, _reg, _shift, _size) \ + { \ + .type =3D ZX_CLOCK_DIV, \ + .div =3D { \ + .name =3D _name, \ + .parent =3D _parent, \ + .reg =3D _reg, \ + .shift =3D _shift, \ + .size =3D _size, \ + }, \ + } + +#define GATE(_name, _parent, _reg, _shift, _flags) \ + { \ + .type =3D ZX_CLOCK_GATE, \ + .gate =3D { \ + .name =3D _name, \ + .parent =3D _parent, \ + .reg =3D _reg, \ + .flags =3D _flags, \ + .shift =3D _shift, \ + }, \ + } + +static const struct zx_clock zx297520v3_top_clocks[] =3D { + /* + * Default setting: 0x48040c11. 624/312/156. Only a single possible paren= t. This is the + * PLL for pretty much everything, including CPU, RAM and USB. + * + * Changing this PLL makes it possible to overclock the CPU or do more fi= ne grained + * underclocking than the CPU's mux allows. It does run into two problems= though: The USB + * device uses this PLL's output directly and is *very* sensitive to diff= erences. DRAM + * is also fed by this clock and needs to be re-trained on larger changes= , which needs to + * be done by the stage 1 boot loader. + */ + [ZX_CLK_MPLL] =3D PLL("mpll", clk_main, 0, 0x8, 0), + + /* + * ZTE's code calls this PLL "upll". The only possible consumers I found = are clk-out1, + * which outputs this clock on GPIO 16 and HSIC. HSIC doesn't have anythi= ng connected to + * it on the devices I tested. The device that consumes clk-out1 seems to= be an SPI + * camera, which I haven't seen in any device so far. ZTE manipulates thi= s PLL directly out + * of the camera code, so it is unlikely to have another consumer. + * + * Long story short, shut it off. + */ + [ZX_CLK_UPLL] =3D PLL("upll", clk_main, 0, 0x10, 0), + + /* + * Default value 0x4834902d. Feeds dpll. 46.08 MHz. Bit 25 can be set, so= two parents are + * possible. It looks like both values select the 26 MHz oscillator thoug= h. + * + * Since dpll's prepare may depend on this clock generating a usable sign= al, it needs to be + * enabled when prepared. + * + * It isn't named anywhere in ZTE's code, but cpko.ko has the string "dpl= l2" somewhere in + * its clock tables. + */ + [ZX_CLK_DPLL2] =3D PLL("dpll2", clk_main, 0, 0x100, CLK_ZX_PL= L_PREPARE_IS_ENABLE), + [ZX_CLK_DPLL2_D2] =3D FIXED_DIV("dpll2-d2", PARENT_ID(ZX_CLK_DPL= L2), 2), + + /* + * The documentation says 491.52 MHz and measurement with the LSP TDM dev= ice supports this. + * The default value is 0x480c2011, but not all boot loaders set it up. T= o get to 491.52 + * with these settings it needs a 23.04 MHz reference clock, which matche= s dpll2-d2. If + * dpll2 is disabled, dpll loses its lock. We set the frequency on this P= LL if we find it is + * not prepared by the boot loader. + * + * The proprietary LTE driver and/or rproc prepare and unprepare it. TDM = and I2S can use it. + * + * It accepts parent values 0, 1, 2 and 3. Parent 0 is dpll2-d2. The othe= rs look like + * osc26m. With a parent !=3D 0 dpll never loses its lock even when all o= ther PLLs are off + * and the TDM counter register increases at a rate consistent with a 26.= 0/23.04 clock + * increase. + */ + [ZX_CLK_DPLL] =3D PLL("dpll", dpll_parents, 491520000, 0x18,= 0), + + /* + * "g" is either for "general" or "gigahertz". The VCO runs at 1 GHz. Out= put clocks are 200, + * 100, 50, 25, ... MHz. It is used optionally by SDIO and QSPI and can d= rive a GPIO clock + * output for RMII, so it doesn't seem very general. + */ + [ZX_CLK_GPLL] =3D PLL("gpll", clk_main, 0, 0x110, 0), + + /* osc26m division for clk_outX */ + [ZX_CLK_OSC26M_D2] =3D FIXED_DIV("osc26m-d2", clk_main[0], 2), + + /* Pre-0x140 distribution fixed divs */ + [ZX_CLK_TOP_MPLL_D2_PREGATE] =3D FIXED_DIV("mpll-d2", PARENT_ID(ZX_CLK_M= PLL), 2), + [ZX_CLK_TOP_MPLL_D5_PREGATE] =3D FIXED_DIV("mpll-d5", PARENT_ID(ZX_CLK_M= PLL), 5), + [ZX_CLK_TOP_MPLL_D6_PREGATE] =3D FIXED_DIV("mpll-d6", PARENT_ID(ZX_CLK_M= PLL), 6), + [ZX_CLK_TOP_MPLL_D8_PREGATE] =3D FIXED_DIV("mpll-d8", PARENT_ID(ZX_CLK_M= PLL), 8), + [ZX_CLK_TOP_UPLL_D12_PREGATE] =3D FIXED_DIV("upll-d12", PARENT_ID(ZX_CLK_= UPLL), 12), + [ZX_CLK_TOP_GPLL_D2_PREGATE] =3D FIXED_DIV("gpll-d2", PARENT_ID(ZX_CLK_G= PLL), 2), + [ZX_CLK_TOP_GPLL_D4_PREGATE] =3D FIXED_DIV("gpll-d4", PARENT_ID(ZX_CLK_G= PLL), 4), + + /* + * topcrm distribution gates. These are complicated, but shed a lot of li= ght on the board's + * clock distribution. + * + * Settable mask: 0x017333FF. Generally one nibble per PLL, except for MP= LL that has more. + * One for osc26m work clock. pclk and osc32k are not gated globally here= or anywhere else + * as far as I can see. + * + * If you want to test your understanding of this board, try to manually = configure it into a + * setup where bit 24 or bit 9 are off without crashing it. + */ + + /* Bit 0: No known consumer */ + /* Bit 1: M0's 78 MHz selection, but somehow also involved in USB too */ + [ZX_CLK_TOP_MPLL_D2] =3D GATE("top-mpll-d2", PARENT_ID(ZX_CLK_TOP_M= PLL_D2_PREGATE), + 0x140, 1, 0), + /* Bit 2: No known consumer, named "mpll_48m_clk" in ZTE's cpko.ko blob */ + [ZX_CLK_TOP_MPLL_D8] =3D GATE("top-mpll-d8", PARENT_ID(ZX_CLK_TOP_M= PLL_D8_PREGATE), + 0x140, 3, 0), + [ZX_CLK_TOP_MPLL_D6] =3D GATE("top-mpll-d6", PARENT_ID(ZX_CLK_TOP_M= PLL_D6_PREGATE), + 0x140, 4, 0), + /* Bit 5: No known consumer. "mpll_156m_clk" in cpko.ko */ + [ZX_CLK_TOMATRIX_MPLL_D5] =3D GATE("matrix-mpll-d5", PARENT_ID(ZX_CLK_TO= P_MPLL_D5_PREGATE), + 0x140, 6, ZX297520V3_AXI_CANDIDATE), + /* Bit 7: No known consumer */ + /* + * Bit 8: Has a consumer, LTE depends on it. But unknown what and how. Mo= st likely one of + * the gsm clocks in topcrm+0x64 listed in cpko.ko. + */ + /* + * Bit 9: Big MPLL provider for Matrix. It is an AXI voting candidate, bu= t it is protected + * in Matrix's 0x118 gates. + */ + [ZX_CLK_TOMATRIX_MPLL] =3D GATE("matrix-mpll", PARENT_ID(ZX_CLK_MPLL)= , 0x140, 9, 0), + /* Bit 10: Always 0 */ + /* Bit 11: Always 0 */ + + /* Bit 12: No known consumer. Existing patterns indicate a dpll consumer = in top itself */ + [ZX_CLK_TOMATRIX_DPLL] =3D GATE("matrix-dpll", PARENT_ID(ZX_CLK_DPLL)= , 0x140, 13, 0), + /* Bit 14: Always 0 */ + /* Bit 15: Always 0 */ + + [ZX_CLK_TOP_UPLL_D12] =3D GATE("top-upll-d12", PARENT_ID(ZX_CLK_TOP_= UPLL_D12_PREGATE), + 0x140, 16, 0), + [ZX_CLK_TOP_UPLL] =3D GATE("top-upll", PARENT_ID(ZX_CLK_UPLL), 0= x140, 17, 0), + /* Bit 18: Always 0 */ + /* Bit 19: Always 0 */ + + [ZX_CLK_TOP_GPLL_D4] =3D GATE("top-gpll-d4", PARENT_ID(ZX_CLK_TOP_G= PLL_D4_PREGATE), + 0x140, 20, 0), + [ZX_CLK_TOMATRIX_GPLL_D2] =3D GATE("matrix-gpll-d2", PARENT_ID(ZX_CLK_TO= P_GPLL_D2_PREGATE), + 0x140, 21, 0), + [ZX_CLK_TOMATRIX_GPLL] =3D GATE("matrix-gpll", PARENT_ID(ZX_CLK_GPLL)= , 0x140, 22, 0), + /* Bit 23: Always 0 */ + + /* + * Bit 24 covers all 26 MHz on matrix, but not pclks. Osc26m consumers on= topcrm do not + * use this, they get the ungated osc26m. It is an AXI voting candidate, = but does not + * need protection because it is the slowest speed. It will only be used = if every processor, + * including us, votes for it. + */ + [ZX_CLK_TOMATRIX_OSC26M] =3D GATE("matrix-osc26m", clk_main[0], 0x140, = 24, 0), + + /* + * Post-140 divisions. They enter through the same bit and can be selecte= d by different mux + * values of their consumers or get piped to multiple consumers with diff= erent documented + * rates - in particular, USB wclk (24 MHz according to ZTE) shares bit 1= with M0's 78 MHz. + */ + [ZX_CLK_TOP_MPLL_D2_D4] =3D FIXED_DIV("top-mpll-d2-d4", PARENT_ID(ZX_C= LK_TOP_MPLL_D2), 4), + [ZX_CLK_TOP_MPLL_D2_D13] =3D FIXED_DIV("top-mpll-d2-d13", PARENT_ID(ZX_= CLK_TOP_MPLL_D2), + 13), + [ZX_CLK_TOP_UPLL_D12_D2] =3D FIXED_DIV("top-upll-d12-d2", PARENT_ID(ZX_= CLK_TOP_UPLL_D12), + 2), + [ZX_CLK_TOP_GPLL_D4_D2] =3D FIXED_DIV("top-gpll-d4-d2", PARENT_ID(ZX_C= LK_TOP_GPLL_D4), 2), + + /* Device-specific Muxes */ + [ZX_CLK_M0_MUX] =3D MUX("m0-mux", m0_sel, 0x= 38, 0, 2), + [ZX_CLK_AHB_MUX] =3D MUX("ahb-mux", ahb_sel, 0x= 3c, 4, 2), + [ZX_CLK_TIMER_T08_MUX] =3D MUX("timer-t08-mux", timer_top_sel, 0x= 40, 1, 1), + [ZX_CLK_TIMER_T09_MUX] =3D MUX("timer-t09-mux", timer_top_sel, 0x= 40, 0, 1), + [ZX_CLK_TIMER_T12_MUX] =3D MUX("timer-t12-mux", timer_top_sel, 0x= 3c, 0, 1), + [ZX_CLK_TIMER_T13_MUX] =3D MUX("timer-t13-mux", timer_top_sel, 0x= 44, 0, 1), + [ZX_CLK_TIMER_T14_MUX] =3D MUX("timer-t14-mux", timer_top_sel, 0x= 44, 1, 1), + [ZX_CLK_TIMER_T15_MUX] =3D MUX("timer-t15-mux", timer_top_sel, 0x= 3c, 3, 1), + [ZX_CLK_TIMER_T16_MUX] =3D MUX("timer-t16-mux", timer_top_sel, 0x= 44, 2, 1), + [ZX_CLK_TIMER_T17_MUX] =3D MUX("timer-t17-mux", timer_top_sel, 0x1= 20, 0, 1), + [ZX_CLK_WDT_T18_MUX] =3D MUX("wdt-t18-mux", timer_top_sel, 0x= 3c, 6, 1), + [ZX_CLK_I2C0_MUX] =3D MUX("i2c0-mux", uart_top_sel, 0x= 3c, 1, 1), + [ZX_CLK_UART0_MUX] =3D MUX("uart0-mux", uart_top_sel, 0x= 40, 2, 1), + [ZX_CLK_OUT0_MUX] =3D MUX("out0-mux", out0_sel, 0x= 34, 5, 1), + [ZX_CLK_OUT1_MUX] =3D MUX("out1-mux", out1_sel, 0x= 34, 6, 2), + [ZX_CLK_OUT2_MUX] =3D MUX("out2-mux", out2_sel, 0x= 34, 8, 1), + [ZX_CLK_RMIIPHY_MUX] =3D MUX("rmiiphy-mux", rmii_sel, 0x1= 1c, 0, 2), + + /* Device-specific dividers */ + [ZX_CLK_TIMER_T08_DIV] =3D DIV("timer-t08-div", PARENT_ID(ZX_CLK_TIME= R_T08_MUX), + 0x4c, 8, 4), + [ZX_CLK_TIMER_T09_DIV] =3D DIV("timer-t09-div", PARENT_ID(ZX_CLK_TIME= R_T09_MUX), + 0x4c, 0, 4), + [ZX_CLK_TIMER_T12_DIV] =3D DIV("timer-t12-div", PARENT_ID(ZX_CLK_TIME= R_T12_MUX), + 0x48, 0, 4), + [ZX_CLK_TIMER_T13_DIV] =3D DIV("timer-t13-div", PARENT_ID(ZX_CLK_TIME= R_T13_MUX), + 0x50, 0, 4), + [ZX_CLK_TIMER_T14_DIV] =3D DIV("timer-t14-div", PARENT_ID(ZX_CLK_TIME= R_T14_MUX), + 0x50, 4, 4), + [ZX_CLK_TIMER_T15_DIV] =3D DIV("timer-t15-div", PARENT_ID(ZX_CLK_TIME= R_T15_MUX), + 0x48, 4, 4), + [ZX_CLK_TIMER_T16_DIV] =3D DIV("timer-t16-div", PARENT_ID(ZX_CLK_TIME= R_T16_MUX), + 0x50, 8, 4), + [ZX_CLK_TIMER_T17_DIV] =3D DIV("timer-t17-div", PARENT_ID(ZX_CLK_TIME= R_T17_MUX), + 0x124, 0, 4), + [ZX_CLK_WDT_T18_DIV] =3D DIV("wdt-t18-div", PARENT_ID(ZX_CLK_WDT_T1= 8_MUX), + 0x48, 8, 4), + [ZX_CLK_USIM1_DIV] =3D DIV("usim1-div", clk_unknown, + 0x48, 12, 1), + + /* Device specific gates */ + + /* + * AHB clock gates: Disabling these cuts off the A53 from register access= into 0x130000/ + * 0x140000, including the topcrm region, so it can't be re-enabled. Mark= them critical for + * that reason. + * + * Gating this off does not stop the M0 rproc, nor does it stop M0 from a= ccessing topcrm. It + * does however gate off M0 from the AXI interconnect, so it can't read R= AM, Matrix, etc. So + * these bits here merely gate the bus, not the actual devices. + */ + [ZX_CLK_AHB_PCLK] =3D GATE("ahb-pclk", PARENT_ID(ZX_CLK_AHB_MUX)= , 0x54, 12, + CLK_IS_CRITICAL), + [ZX_CLK_AHB_WCLK] =3D GATE("ahb-wclk", PARENT_ID(ZX_CLK_M0_MUX),= 0x54, 13, + CLK_IS_CRITICAL), + + /* SRAM1 and 2 clocks. Leave them on for now, as turning them off careles= sly hangs the M0 */ + [ZX_CLK_SRAM1_PCLK] =3D GATE("sram1-pclk", clk_main[0], 0x54, 18, = CLK_IS_CRITICAL), + [ZX_CLK_SRAM2_PCLK] =3D GATE("sram2-pclk", clk_main[0], 0x54, 16, = CLK_IS_CRITICAL), + + /* + * Pinmux (AON, TOP, IOCFG but not PDCFG). Critical as well until we have= a driver that + * consumes it. I don't think we'll realistically shut this off ever. + * + * Setting either bit 0 or 1 in register 0x58 makes the device work. + */ + [ZX_CLK_PMM_WCLK] =3D GATE("pmm-wclk", clk_main[0], 0x58, 0, CLK= _IS_CRITICAL), + [ZX_CLK_PMM_PCLK] =3D GATE("pmm-pclk", clk_main[0], 0x58, 1, CLK= _IS_CRITICAL), + + /* + * Timers. We don't use any of them, just shut them off. The timers are n= amed and sorted + * by the IO address of the main timer controls. Some of the controls are= documented in + * ZTE's kernel, the others I found by trial and error. Timers in registe= r 0x54 have the + * pclk first, the others have the wclk first. + * + * Timer T17 is used by the ZSP firmware. The rproc driver will enable it= as needed. + */ + [ZX_CLK_TIMER_T08_WCLK] =3D GATE("timer-t08-wclk", PARENT_ID(ZX_CLK_TI= MER_T08_DIV), + 0x5c, 8, 0), + [ZX_CLK_TIMER_T08_PCLK] =3D GATE("timer-t08-pclk", clk_main[0], 0x5c, = 9, 0), + [ZX_CLK_TIMER_T09_WCLK] =3D GATE("timer-t09-wclk", PARENT_ID(ZX_CLK_TI= MER_T09_DIV), + 0x5c, 4, 0), + [ZX_CLK_TIMER_T09_PCLK] =3D GATE("timer-t09-pclk", clk_main[0], 0x5c, = 5, 0), + [ZX_CLK_TIMER_T12_WCLK] =3D GATE("timer-t12-wclk", PARENT_ID(ZX_CLK_TI= MER_T12_DIV), + 0x54, 5, 0), + [ZX_CLK_TIMER_T12_PCLK] =3D GATE("timer-t12-pclk", clk_main[0], 0x54, = 4, 0), + [ZX_CLK_TIMER_T13_WCLK] =3D GATE("timer-t13-wclk", PARENT_ID(ZX_CLK_TI= MER_T13_DIV), + 0x60, 0, 0), + [ZX_CLK_TIMER_T13_PCLK] =3D GATE("timer-t13-pclk", clk_main[0], 0x60, = 1, 0), + [ZX_CLK_TIMER_T14_WCLK] =3D GATE("timer-t14-wclk", PARENT_ID(ZX_CLK_TI= MER_T14_DIV), + 0x60, 4, 0), + [ZX_CLK_TIMER_T14_PCLK] =3D GATE("timer-t14-pclk", clk_main[0], 0x60, = 5, 0), + [ZX_CLK_TIMER_T15_WCLK] =3D GATE("timer-t15-wclk", PARENT_ID(ZX_CLK_TI= MER_T15_DIV), + 0x54, 21, 0), + [ZX_CLK_TIMER_T15_PCLK] =3D GATE("timer-t15-pclk", clk_main[0], 0x54, = 20, 0), + [ZX_CLK_TIMER_T16_WCLK] =3D GATE("timer-t16-wclk", PARENT_ID(ZX_CLK_TI= MER_T16_DIV), + 0x60, 8, 0), + [ZX_CLK_TIMER_T16_PCLK] =3D GATE("timer-t16-pclk", clk_main[0], 0x60, = 9, 0), + [ZX_CLK_TIMER_T17_WCLK] =3D GATE("timer-t17-wclk", PARENT_ID(ZX_CLK_TI= MER_T17_DIV), + 0x128, 0, 0), + [ZX_CLK_TIMER_T17_PCLK] =3D GATE("timer-t17-pclk", clk_main[0], 0x128,= 1, 0), + + /* + * This watchdog is set up by ZTE's bootloader and in ZTE's OS the m0 fir= mware will feed the + * dog. The m0 firmware in turn wants to be fed in its own way. Since we = normally don't run + * any m0 firmware we shut it off by default and expose it to userspace v= ia the watchdog + * driver. + */ + [ZX_CLK_WDT_T18_WCLK] =3D GATE("wdt-t18-wclk", PARENT_ID(ZX_CLK_WDT_T= 18_DIV), + 0x54, 25, 0), + [ZX_CLK_WDT_T18_PCLK] =3D GATE("wdt-t18-pclk", clk_main[0], 0x54, 24,= 0), + + [ZX_CLK_I2C0_WCLK] =3D GATE("i2c0-wclk", PARENT_ID(ZX_CLK_I2C0_MUX= ), 0x54, 9, 0), + [ZX_CLK_I2C0_PCLK] =3D GATE("i2c0-pclk", clk_main[0], 0x54, 8, 0), + [ZX_CLK_UART0_WCLK] =3D GATE("uart0-wclk", PARENT_ID(ZX_CLK_UART0_M= UX), 0x5c, 12, 0), + [ZX_CLK_UART0_PCLK] =3D GATE("uart0-pclk", clk_main[0], 0x5c, 13, 0= ), + + /* + * ZTE says the USB input is a 24 MHz clock based on mpll. Testing shows = that upll is not + * involved. The USB register space can be accessed with ahb-pclk gated, = but not with + * ahb-wclk gated. ZTE also lists ahb-wclk as parent for the second clock. + * + * There doesn't seem to be a separate PHY clock. usb-wclk stops controll= er registers from + * updating, but doesn't cause the USB device to disconnect like assertin= g the PHY reset + * does. Bit 0 in this register can't be set, so no PHY clock is hiding t= here either. + */ + [ZX_CLK_USB_WCLK] =3D GATE("usb-wclk", PARENT_ID(ZX_CLK_TOP_MPLL_= D2_D13), 0x6c, 3, 0), + [ZX_CLK_USB_PCLK] =3D GATE("usb-pclk", PARENT_ID(ZX_CLK_AHB_WCLK)= , 0x6c, 4, 0), + /* + * The HSIC hardware is listed in ZTE's code with a physical address of 0= x01600000. Unlike + * the USB controller, it does consume upll. ZTE says 240 MHz, but 480 is= the usual one for + * HSIC. + */ + [ZX_CLK_HSIC_WCLK] =3D GATE("hsic-wclk", PARENT_ID(ZX_CLK_TOP_UPLL= ), 0x6c, 1, 0), + [ZX_CLK_HSIC_PCLK] =3D GATE("hsic-pclk", PARENT_ID(ZX_CLK_AHB_WCLK= ), 0x6c, 2, 0), + + /* + * How does this RTC work? I don't know, the ZTE kernel does not talk to = it. The actual RTC + * is on the I2C-connected PMIC. + */ + [ZX_CLK_RTC_WCLK] =3D GATE("rtc-wclk", clk_unknown, 0x54, 1, 0), + [ZX_CLK_RTC_PCLK] =3D GATE("rtc-pclk", clk_main[0], 0x54, 0, 0), + + [ZX_CLK_USIM1_WCLK] =3D GATE("usim1-wclk", PARENT_ID(ZX_CLK_USIM1_D= IV), 0x54, 29, 0), + [ZX_CLK_USIM1_PCLK] =3D GATE("usim1-pclk", clk_main[0], 0x54, 28, 0= ), + + /* + * LTE: gate only as far as I can see. I looked for resets and did not fi= nd any. There may + * be mux/div, but without understanding the behavior of this hardware it= is impossible to + * tell. They are sorted by physical MMIO address of the devices, which h= appens to be the + * inverse order of the bits. + * + * I don't know what "LPM", "TD" and "W" mean. I copied them from ZTE's n= ames. + * + * Like PMM in this register, either bit enables register access, whether= they control pclk + * or wclk cannot be distinguished. + */ + [ZX_CLK_LPM_GSM_WCLK] =3D GATE("lpm-gsm-wclk", clk_unknown, 0x58, 10,= 0), + [ZX_CLK_LPM_GSM_PCLK] =3D GATE("lpm-gsm-pclk", clk_main[0], 0x58, 11,= 0), + [ZX_CLK_LPM_LTE_WCLK] =3D GATE("lpm-lte-wclk", clk_unknown, 0x58, 8, = 0), + [ZX_CLK_LPM_LTE_PCLK] =3D GATE("lpm-lte-pclk", clk_main[0], 0x58, 9, = 0), + [ZX_CLK_LPM_TD_WCLK] =3D GATE("lpm-td-wclk", clk_unknown, 0x58, 6, 0= ), + [ZX_CLK_LPM_TD_PCLK] =3D GATE("lpm-td-pclk", clk_main[0], 0x58, 7, 0= ), + [ZX_CLK_LPM_W_WCLK] =3D GATE("lpm-w-wclk", clk_unknown, 0x58, 4, 0), + [ZX_CLK_LPM_W_PCLK] =3D GATE("lpm-w-pclk", clk_main[0], 0x58, 5, 0), + + [ZX_CLK_OUT0_WCLK] =3D GATE("out0-wclk", PARENT_ID(ZX_CLK_OUT0_MUX= ), 0x34, 0, 0), + [ZX_CLK_OUT1_WCLK] =3D GATE("out1-wclk", PARENT_ID(ZX_CLK_OUT1_MUX= ), 0x90, 2, 0), + [ZX_CLK_OUT2_WCLK] =3D GATE("out2-wclk", PARENT_ID(ZX_CLK_OUT2_MUX= ), 0x94, 2, 0), + [ZX_CLK_OUT32K_WCLK] =3D GATE("out32k-wclk", PARENT_FW("osc32k"), 0x= 34, 1, 0), + [ZX_CLK_RMIIPHY_WCLK] =3D GATE("rmiiphy-wclk", PARENT_ID(ZX_CLK_RMIIP= HY_MUX), + 0x11c, 2, 0), +}; + +static unsigned int zx297520v3_top_exports[] =3D { + [ZX297520V3_M0_WCLK] =3D ZX_CLK_M0_MUX, + [ZX297520V3_SRAM1_PCLK] =3D ZX_CLK_SRAM1_PCLK, + [ZX297520V3_SRAM2_PCLK] =3D ZX_CLK_SRAM2_PCLK, + [ZX297520V3_UART0_WCLK] =3D ZX_CLK_UART0_WCLK, + [ZX297520V3_UART0_PCLK] =3D ZX_CLK_UART0_PCLK, + [ZX297520V3_I2C0_WCLK] =3D ZX_CLK_I2C0_WCLK, + [ZX297520V3_I2C0_PCLK] =3D ZX_CLK_I2C0_PCLK, + [ZX297520V3_RTC_WCLK] =3D ZX_CLK_RTC_WCLK, + [ZX297520V3_RTC_PCLK] =3D ZX_CLK_RTC_PCLK, + [ZX297520V3_LPM_GSM_WCLK] =3D ZX_CLK_LPM_GSM_WCLK, + [ZX297520V3_LPM_GSM_PCLK] =3D ZX_CLK_LPM_GSM_PCLK, + [ZX297520V3_LPM_LTE_WCLK] =3D ZX_CLK_LPM_LTE_WCLK, + [ZX297520V3_LPM_LTE_PCLK] =3D ZX_CLK_LPM_LTE_PCLK, + [ZX297520V3_LPM_TD_WCLK] =3D ZX_CLK_LPM_TD_WCLK, + [ZX297520V3_LPM_TD_PCLK] =3D ZX_CLK_LPM_TD_PCLK, + [ZX297520V3_LPM_W_WCLK] =3D ZX_CLK_LPM_W_WCLK, + [ZX297520V3_LPM_W_PCLK] =3D ZX_CLK_LPM_W_PCLK, + [ZX297520V3_TIMER_T08_WCLK] =3D ZX_CLK_TIMER_T08_WCLK, + [ZX297520V3_TIMER_T08_PCLK] =3D ZX_CLK_TIMER_T08_PCLK, + [ZX297520V3_TIMER_T09_WCLK] =3D ZX_CLK_TIMER_T09_WCLK, + [ZX297520V3_TIMER_T09_PCLK] =3D ZX_CLK_TIMER_T09_PCLK, + [ZX297520V3_MPLL] =3D ZX_CLK_TOMATRIX_MPLL, + [ZX297520V3_MPLL_D5] =3D ZX_CLK_TOMATRIX_MPLL_D5, + [ZX297520V3_DPLL] =3D ZX_CLK_TOMATRIX_DPLL, + [ZX297520V3_GPLL] =3D ZX_CLK_TOMATRIX_GPLL, + [ZX297520V3_GPLL_D2] =3D ZX_CLK_TOMATRIX_GPLL_D2, + [ZX297520V3_GATED_OSC26M] =3D ZX_CLK_TOMATRIX_OSC26M, + [ZX297520V3_PMM_WCLK] =3D ZX_CLK_PMM_WCLK, + [ZX297520V3_PMM_PCLK] =3D ZX_CLK_PMM_PCLK, + [ZX297520V3_OUT0_WCLK] =3D ZX_CLK_OUT0_WCLK, + [ZX297520V3_OUT1_WCLK] =3D ZX_CLK_OUT1_WCLK, + [ZX297520V3_OUT2_WCLK] =3D ZX_CLK_OUT2_WCLK, + [ZX297520V3_OUT32K_WCLK] =3D ZX_CLK_OUT32K_WCLK, + [ZX297520V3_RMIIPHY_WCLK] =3D ZX_CLK_RMIIPHY_WCLK, + [ZX297520V3_TIMER_T12_WCLK] =3D ZX_CLK_TIMER_T12_WCLK, + [ZX297520V3_TIMER_T12_PCLK] =3D ZX_CLK_TIMER_T12_PCLK, + [ZX297520V3_TIMER_T13_WCLK] =3D ZX_CLK_TIMER_T13_WCLK, + [ZX297520V3_TIMER_T13_PCLK] =3D ZX_CLK_TIMER_T13_PCLK, + [ZX297520V3_TIMER_T14_WCLK] =3D ZX_CLK_TIMER_T14_WCLK, + [ZX297520V3_TIMER_T14_PCLK] =3D ZX_CLK_TIMER_T14_PCLK, + [ZX297520V3_TIMER_T15_WCLK] =3D ZX_CLK_TIMER_T15_WCLK, + [ZX297520V3_TIMER_T15_PCLK] =3D ZX_CLK_TIMER_T15_PCLK, + [ZX297520V3_TIMER_T16_WCLK] =3D ZX_CLK_TIMER_T16_WCLK, + [ZX297520V3_TIMER_T16_PCLK] =3D ZX_CLK_TIMER_T16_PCLK, + [ZX297520V3_TIMER_T17_WCLK] =3D ZX_CLK_TIMER_T17_WCLK, + [ZX297520V3_TIMER_T17_PCLK] =3D ZX_CLK_TIMER_T17_PCLK, + [ZX297520V3_WDT_T18_WCLK] =3D ZX_CLK_WDT_T18_WCLK, + [ZX297520V3_WDT_T18_PCLK] =3D ZX_CLK_WDT_T18_PCLK, + [ZX297520V3_USIM1_WCLK] =3D ZX_CLK_USIM1_WCLK, + [ZX297520V3_USIM1_PCLK] =3D ZX_CLK_USIM1_PCLK, + [ZX297520V3_AHB_WCLK] =3D ZX_CLK_AHB_WCLK, + [ZX297520V3_AHB_PCLK] =3D ZX_CLK_AHB_PCLK, + [ZX297520V3_USB_WCLK] =3D ZX_CLK_USB_WCLK, + [ZX297520V3_USB_PCLK] =3D ZX_CLK_USB_PCLK, + [ZX297520V3_HSIC_WCLK] =3D ZX_CLK_HSIC_WCLK, + [ZX297520V3_HSIC_PCLK] =3D ZX_CLK_HSIC_PCLK, +}; + +static const struct zx_clk_data zx297520v3_topclk_data =3D { + .clocks =3D zx297520v3_top_clocks, + .num_clocks =3D ARRAY_SIZE(zx297520v3_top_clocks), + .exports =3D zx297520v3_top_exports, + .num_exports =3D ARRAY_SIZE(zx297520v3_top_exports), +}; + +static int clk_zx297520v3_probe(struct platform_device *pdev) +{ + const struct platform_device_id *id =3D platform_get_device_id(pdev); + + if (!id) + return -ENODEV; + + return zx_clk_common_probe(&pdev->dev, pdev->dev.parent->of_node, + (const struct zx_clk_data *)id->driver_data); +} + +static const struct platform_device_id clk_zx297520v3_ids[] =3D { + { + .name =3D "zx297520v3-topclk", + .driver_data =3D (kernel_ulong_t)&zx297520v3_topclk_data, + }, + { } +}; +MODULE_DEVICE_TABLE(platform, clk_zx297520v3_ids); + +static struct platform_driver clk_zx297520v3 =3D { + .probe =3D clk_zx297520v3_probe, + .driver =3D { + .name =3D "clk-zx297520v3", + }, + .id_table =3D clk_zx297520v3_ids, +}; +module_platform_driver(clk_zx297520v3); + +MODULE_AUTHOR("Stefan D=C3=B6singer "); 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Sun, 02 Aug 2026 13:34:49 -0700 (PDT) From: =?utf-8?q?Stefan_D=C3=B6singer?= Date: Sun, 02 Aug 2026 23:33:41 +0300 Subject: [PATCH v9 09/12] clk: zte: Introduce a driver for zx297520v3 matrix clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260802-zx29clk-v9-9-d05530d85d28@gmail.com> References: <20260802-zx29clk-v9-0-d05530d85d28@gmail.com> In-Reply-To: <20260802-zx29clk-v9-0-d05530d85d28@gmail.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Brian Masney , Vinod Koul , Neil Armstrong , Russell King , Lee Jones Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, mfd@lists.linux.dev, =?utf-8?q?Stefan_D=C3=B6singer?= X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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a=openpgp; fpr=4F9C2C8728019633893EBBB98CB81F9A72BBA155 This clock controller controls high speed devices: CPU, DMA, RAM, SDIO, Ethernet. The only non-clock, non-reset registers I have spotted here are hardware spinlocks. Signed-off-by: Stefan D=C3=B6singer --- Version 9: Link internal parents by an (internal) clock ID rather than names. There are 3 intentional changes vs version 8 in the clock tree: "gmac-ahb" depends on the ahb clock imported from topcrm. This was already the case before, but it was missing from the bindings and the global name matching obscured it. When re-testing other devices for potential topcrm->ahb dependencies I noticed that the two SDIO devices take their pclk from topcrm->ahb as well. @Sashiko: Any possible other clock tree change compared to version 8 is unintentional and a likely bug. Version 8: Add another distribution gate register: 0x118 gates off matrix-generated divisions of mpll, dpll and gpll. It nicely fits the top->matrix forward picture. AXI 6.5 MHz is not an mpll child. I must have done something wrong when originally testing this Add explanations about additional ARM architected timer controls. Add gates for unknown LTE hardware at offset 0x60. They are not exported in the bindings because the actual name of the consumer isn't clear - but if dpll is unprepared and feeds a bypass 26 MHz signal, this device starts spamming IRQs (although the 0x118 and top+0x140 gates also prevent this usually) Double-check pclk and wclk of all devices. The SDIO and EDCP clocks were flipped in previous submissions. Version 7: Reduced the input clocks a lot. Most MPLL subdivisions are children of the same gate in top, so put the fixed factor clocks here. Added a few more clocks: DDR_CTRL, AXI bus, ARM architected timer. They are needed to tell CCF to keep the top gates enabled and marked critical because they aren't consumed by a DT node. The AXI bus is determined by a voting system. I've set up the driver to write to the ballot register ZTE's kernel uses and enable voting. This should make life easier with the LTE rproc blob later. Version 5: Make it an MFD child device, remove aux device Fix zx297529 -> zx297520 typos Fix AHB_wclk -> ahb_wclk. That was a leftover of my old composite structs Add SRAM0 and GSM_CFG clocks --- drivers/clk/zte/clk-zx297520v3.c | 483 +++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 483 insertions(+) diff --git a/drivers/clk/zte/clk-zx297520v3.c b/drivers/clk/zte/clk-zx29752= 0v3.c index f9915582f261..6c4a7a1c3a9b 100644 --- a/drivers/clk/zte/clk-zx297520v3.c +++ b/drivers/clk/zte/clk-zx297520v3.c @@ -769,6 +769,485 @@ static const struct zx_clk_data zx297520v3_topclk_dat= a =3D { .num_exports =3D ARRAY_SIZE(zx297520v3_top_exports), }; =20 +enum matrix_clock_ids { + ZX_CLK_MATRIX_OSC26M_D4, + ZX_CLK_MATRIX_MPLL_D2_PREGATE, + ZX_CLK_MATRIX_MPLL_D4_PREGATE, + ZX_CLK_MATRIX_MPLL_D6_PREGATE, + ZX_CLK_MATRIX_MPLL_D8_PREGATE, + ZX_CLK_MATRIX_MPLL_D12_PREGATE, + ZX_CLK_MATRIX_MPLL_D16_PREGATE, + ZX_CLK_MATRIX_GPLL_D2_D2_PREGATE, + ZX_CLK_MATRIX_GPLL_D2_D4_PREGATE, + ZX_CLK_MATRIX_DPLL_D6_PREGATE, + ZX_CLK_MATRIX_DPLL_D4_PREGATE, + + ZX_CLK_MATRIX_MPLL_D16, + ZX_CLK_MATRIX_MPLL_D12, + ZX_CLK_MATRIX_MPLL_D8, + ZX_CLK_MATRIX_MPLL_D6, + ZX_CLK_MATRIX_MPLL_D4, + ZX_CLK_MATRIX_MPLL_D2, + ZX_CLK_MATRIX_DPLL_D6, + ZX_CLK_MATRIX_DPLL_D4, + ZX_CLK_MATRIX_GPLL_D2_D4, + ZX_CLK_MATRIX_GPLL_D2_D2, + + ZX_CLK_CPU_MUX, + ZX_CLK_ZSP_MUX, + ZX_CLK_DDR_CTRL_MUX, + ZX_CLK_SD0_MUX, + ZX_CLK_SD1_MUX, + ZX_CLK_NAND_MUX, + ZX_CLK_EDCP_MUX, + ZX_CLK_TDM_MUX, + ZX_CLK_AXI_MUX, + + ZX_CLK_SYS_TIMER_WCLK, + ZX_CLK_CPU_WCLK, + ZX_CLK_CPU_PCLK, + ZX_CLK_DDR_CTRL_PCLK, + ZX_CLK_DDR_CTRL_WCLK, + ZX_CLK_ZSP_WCLK, + ZX_CLK_SD0_PCLK, + ZX_CLK_SD0_WCLK, + ZX_CLK_SD0_CDET, + ZX_CLK_SD1_PCLK, + ZX_CLK_SD1_WCLK, + ZX_CLK_SD1_CDET, + ZX_CLK_NAND_WCLK, + ZX_CLK_NAND_PCLK, + ZX_CLK_LTE_TPU_WCLK, + ZX_CLK_LTE_TPU_PCLK, + ZX_CLK_EDCP_PCLK, + ZX_CLK_EDCP_WCLK, + ZX_CLK_SSC_WCLK, + ZX_CLK_SSC_PCLK, + ZX_CLK_PDCFG_WCLK, + ZX_CLK_PDCFG_PCLK, + ZX_CLK_MBOX_PCLK, + ZX_CLK_SRAM0_PCLK, + ZX_CLK_GSM_CFG_PCLK, + ZX_CLK_GMAC_WCLK, + ZX_CLK_GMAC_PCLK, + ZX_CLK_GMAC_AHB, + ZX_CLK_AXI_WCLK, + ZX_CLK_DMA_PCLK, + ZX_CLK_VOU_WCLK, + ZX_CLK_VOU_PCLK, + ZX_CLK_TOLSP_MPLL_D5_WCLK, + ZX_CLK_TOLSP_MPLL_D4_WCLK, + ZX_CLK_TOLSP_MPLL_D6_WCLK, + ZX_CLK_TOLSP_MPLL_D8_WCLK, + ZX_CLK_TOLSP_MPLL_D12_WCLK, + ZX_CLK_TOLSP_OSC26M_WCLK, + ZX_CLK_TOLSP_OSC32K_WCLK, + ZX_CLK_TOLSP_PCLK, + ZX_CLK_TOLSP_TDM_WCLK, + ZX_CLK_TOLSP_DPLL_D4_WCLK, +}; + +/* + * For devices which have a working driver the work clock can be figured o= ut by gating off registers + * in topcrm+0x140. This is used for devices where I can't interpret the r= egister contents yet. + */ +static const struct zx_parent_desc matrix_unk =3D PARENT_FW("wclk-osc26m"); + +static const struct zx_parent_desc cpu_sel[] =3D { + PARENT_FW("wclk-osc26m"), + PARENT_FW("mpll"), /* 624 MHz */ + PARENT_ID(ZX_CLK_MATRIX_MPLL_D2), /* 312 MHz */ + PARENT_ID(ZX_CLK_MATRIX_MPLL_D4), /* 156 MHz */ +}; + +/* Low confidence on the actual value, but at least I know it is bit 13 in= top+0x140 */ +static const struct zx_parent_desc zsp_sel[] =3D { + PARENT_FW("wclk-osc26m"), + PARENT_FW("dpll"), /* 491.52 MHz */ +}; + +/* + * We can't realistically change DDR speed while running an OS out of DDR = (it reads garbage for a + * short while on transition), but we need to know if we have to keep gpll= alive. 32 MB devices use + * 200 MHz, while 64/128 MB ones use 156 MHz. + */ +static const struct zx_parent_desc ddr_ctrl_sel[] =3D { + PARENT_ID(ZX_CLK_MATRIX_MPLL_D4), /* 156 MHz */ + PARENT_FW("gpll"), /* 200 MHz */ + PARENT_ID(ZX_CLK_MATRIX_MPLL_D6), /* 104 MHz */ + PARENT_ID(ZX_CLK_MATRIX_MPLL_D8), /* 78 MHz */ +}; + +static const struct zx_parent_desc sd0_sel[] =3D { + PARENT_FW("wclk-osc26m"), + PARENT_ID(ZX_CLK_MATRIX_MPLL_D4), /* 156 MHz */ + PARENT_FW("gpll-d2"), /* 100 MHz */ + PARENT_ID(ZX_CLK_MATRIX_MPLL_D8), /* 78 MHz */ + PARENT_ID(ZX_CLK_MATRIX_GPLL_D2_D2), /* 50 MHz */ + PARENT_ID(ZX_CLK_MATRIX_GPLL_D2_D4), /* 25 MHz */ +}; + +static const struct zx_parent_desc sd1_sel[] =3D { + PARENT_FW("wclk-osc26m"), + PARENT_FW("gpll-d2"), /* 100 MHz */ + PARENT_ID(ZX_CLK_MATRIX_MPLL_D8), /* 78 MHz */ + PARENT_ID(ZX_CLK_MATRIX_GPLL_D2_D2), /* 50 MHz */ + PARENT_ID(ZX_CLK_MATRIX_MPLL_D16), /* 39 MHz */ + PARENT_ID(ZX_CLK_MATRIX_GPLL_D2_D4), /* 25 MHz */ +}; + +/* + * ZTE's kernel puts the high frequency first, but this is against the usu= al convention on this SoC. + * I don't have any device that has a raw NAND controller though. + */ +static const struct zx_parent_desc nand_sel[] =3D { + PARENT_FW("wclk-osc26m"), + PARENT_ID(ZX_CLK_MATRIX_MPLL_D4), /* 156 MHz */ +}; + +static const struct zx_parent_desc edcp_sel[] =3D { + PARENT_FW("wclk-osc26m"), + PARENT_ID(ZX_CLK_MATRIX_MPLL_D4), /* 156 MHz */ + PARENT_FW("mpll-d5"), /* 124.8 MHz */ + PARENT_ID(ZX_CLK_MATRIX_MPLL_D6), /* 104 MHz */ +}; + +static const struct zx_parent_desc tdm_sel[] =3D { + PARENT_FW("wclk-osc26m"), + PARENT_ID(ZX_CLK_MATRIX_DPLL_D4), /* 122.88 MHz */ + PARENT_ID(ZX_CLK_MATRIX_MPLL_D6), /* 104 MHz */ +}; + +/* + * ZTE's firmware uses 0x128 as the PHY's vote and names 0x120 as "PS" and= 0x124 as "AP" vote. + * However, their cpufreq driver ultimately uses the "PS" define and thus = writes to 0x120, which can + * be observed in the running system. + */ +#define ZX297520V3_AXI_AP_VOTE 0x120 +static const struct zx_parent_desc axi_sel[] =3D { + PARENT_FW("wclk-osc26m"), + PARENT_ID(ZX_CLK_MATRIX_MPLL_D4), /* 156 MHz */ + PARENT_FW("mpll-d5"), /* 124.8 MHz */ + PARENT_ID(ZX_CLK_MATRIX_MPLL_D6), /* 104 MHz */ + PARENT_ID(ZX_CLK_MATRIX_MPLL_D8), /* 78 MHz */ + PARENT_ID(ZX_CLK_MATRIX_MPLL_D12), /* 52 MHz */ + PARENT_ID(ZX_CLK_MATRIX_MPLL_D16), /* 39 MHz */ + PARENT_ID(ZX_CLK_MATRIX_OSC26M_D4), /* 6.5 MHz */ +}; + +static const struct zx_clock zx297520v3_matrix_clocks[] =3D { + [ZX_CLK_MATRIX_OSC26M_D4] =3D FIXED_DIV("matrix-osc26m-d4", PARENT_FW("wc= lk-osc26m"), 4), + [ZX_CLK_MATRIX_MPLL_D2_PREGATE] =3D FIXED_DIV("matrix-mpll-d2-pregate", P= ARENT_FW("mpll"), 2), + [ZX_CLK_MATRIX_MPLL_D4_PREGATE] =3D FIXED_DIV("matrix-mpll-d4-pregate", P= ARENT_FW("mpll"), 4), + /* div 5: provided as a separate line from topcrm */ + [ZX_CLK_MATRIX_MPLL_D6_PREGATE] =3D FIXED_DIV("matrix-mpll-d6-pregate", P= ARENT_FW("mpll"), 6), + [ZX_CLK_MATRIX_MPLL_D8_PREGATE] =3D FIXED_DIV("matrix-mpll-d8-pregate", P= ARENT_FW("mpll"), 8), + [ZX_CLK_MATRIX_MPLL_D12_PREGATE] =3D FIXED_DIV("matrix-mpll-d12-pregate",= PARENT_FW("mpll"), + 12), + [ZX_CLK_MATRIX_MPLL_D16_PREGATE] =3D FIXED_DIV("matrix-mpll-d16-pregate",= PARENT_FW("mpll"), + 16), + + [ZX_CLK_MATRIX_GPLL_D2_D2_PREGATE] =3D FIXED_DIV("matrix-gpll-d2-d2-prega= te", + PARENT_FW("gpll-d2"), 2), + [ZX_CLK_MATRIX_GPLL_D2_D4_PREGATE] =3D FIXED_DIV("matrix-gpll-d2-d4-prega= te", + PARENT_FW("gpll-d2"), 4), + + [ZX_CLK_MATRIX_DPLL_D6_PREGATE] =3D FIXED_DIV("matrix-dpll-d6-pregate", P= ARENT_FW("dpll"), 6), + [ZX_CLK_MATRIX_DPLL_D4_PREGATE] =3D FIXED_DIV("matrix-dpll-d4-pregate", P= ARENT_FW("dpll"), 4), + + /* + * Matrix distribution gates: Every matrix-generated subdivision of the i= nput PLLs + * has a gate in 0x118. The original inputs from topcrm (mpll 624, mpll 1= 24.8, gpll 200, + * gpll 100, dpll 491.52) do not. + * + * I do not know of any user of dpll-d6 and do not know the divisor. An 8= 1.92 MHz clock is + * listed as a root clock without a consumer in ZTE's code. Most likely i= t is a possible + * parent of the ZSP mux. + */ + [ZX_CLK_MATRIX_MPLL_D16] =3D GATE("matrix-mpll-d16", + PARENT_ID(ZX_CLK_MATRIX_MPLL_D16_PREGATE), 0x118, 0, + ZX297520V3_AXI_CANDIDATE), + [ZX_CLK_MATRIX_MPLL_D12] =3D GATE("matrix-mpll-d12", + PARENT_ID(ZX_CLK_MATRIX_MPLL_D12_PREGATE), 0x118, 1, + ZX297520V3_AXI_CANDIDATE), + [ZX_CLK_MATRIX_MPLL_D8] =3D GATE("matrix-mpll-d8", + PARENT_ID(ZX_CLK_MATRIX_MPLL_D8_PREGATE), 0x118, 2, + ZX297520V3_AXI_CANDIDATE), + [ZX_CLK_MATRIX_MPLL_D6] =3D GATE("matrix-mpll-d6", + PARENT_ID(ZX_CLK_MATRIX_MPLL_D6_PREGATE), 0x118, 3, + ZX297520V3_AXI_CANDIDATE), + [ZX_CLK_MATRIX_MPLL_D4] =3D GATE("matrix-mpll-d4", + PARENT_ID(ZX_CLK_MATRIX_MPLL_D4_PREGATE), 0x118, 4, + ZX297520V3_AXI_CANDIDATE), + [ZX_CLK_MATRIX_MPLL_D2] =3D GATE("matrix-mpll-d2", + PARENT_ID(ZX_CLK_MATRIX_MPLL_D2_PREGATE), 0x118, 5, 0), + + [ZX_CLK_MATRIX_DPLL_D6] =3D GATE("matrix-dpll-d6", + PARENT_ID(ZX_CLK_MATRIX_DPLL_D6_PREGATE), 0x118, 8, 0), + [ZX_CLK_MATRIX_DPLL_D4] =3D GATE("matrix-dpll-d4", + PARENT_ID(ZX_CLK_MATRIX_DPLL_D4_PREGATE), 0x118, 9, 0), + + [ZX_CLK_MATRIX_GPLL_D2_D4] =3D GATE("matrix-gpll-d2-d4", + PARENT_ID(ZX_CLK_MATRIX_GPLL_D2_D4_PREGATE), + 0x118, 12, 0), + [ZX_CLK_MATRIX_GPLL_D2_D2] =3D GATE("matrix-gpll-d2-d2", + PARENT_ID(ZX_CLK_MATRIX_GPLL_D2_D2_PREGATE), + 0x118, 13, 0), + + [ZX_CLK_CPU_MUX] =3D MUX("cpu-mux", cpu_sel, 0x20, 0, 2), + [ZX_CLK_ZSP_MUX] =3D MUX("zsp-mux", zsp_sel, 0x30, 0, 2), + [ZX_CLK_DDR_CTRL_MUX] =3D MUX("ddr-ctrl-mux", ddr_ctrl_sel, 0x50, 0, = 2), + [ZX_CLK_SD0_MUX] =3D MUX("sd0-mux", sd0_sel, 0x50, 4, 3), + [ZX_CLK_SD1_MUX] =3D MUX("sd1-mux", sd1_sel, 0x50, 8, 3), + [ZX_CLK_NAND_MUX] =3D MUX("nand-mux", nand_sel, 0x50, 12, 2), + [ZX_CLK_EDCP_MUX] =3D MUX("edcp-mux", edcp_sel, 0x50, 16, 2), + [ZX_CLK_TDM_MUX] =3D MUX("tdm-mux", tdm_sel, 0x50, 24, 2), + [ZX_CLK_AXI_MUX] =3D MUX("axi-mux", axi_sel, ZX297520V3_AXI_AP_V= OTE, 0, 3), + + /* + * This bit cuts off the clock signal to the ARM architected timer, which= the kernel uses + * as its main timer. It isn't critical per se - there are plenty of prop= rietary timers + * available that could be used - but the arm arch timer binding does not= accept a clock, so + * this CCF driver won't know if the timer is in use. + * + * This clock is fed by the osc26m gate in topcrm+0x140 - this critical c= lock here protects + * its parent. + * + * Registers 0x148, 0x14c, 0x150, 0x154 allow setting and clearing the ti= mer counter. To + * set the timer, load a value into 0x148 (high 32 bits) and 0x14c (low 3= 2 bits), then + * toggle 0x150 to 1. 0x150 will automatically reset to 0. 0x154 sets the= timer to some + * "clear" value, but this value isn't 0. + */ + [ZX_CLK_SYS_TIMER_WCLK] =3D GATE("sys-timer-wclk", PARENT_FW("wclk-osc2= 6m"), 0x144, 1, + CLK_IS_CRITICAL), + + /* + * Both 0x24 and 0x28 bits 1 and 2 stop the CPU. There is also a bit in t= opcrm+0x138, which + * ZTE's uboot calls "A53 reset", which also stops the CPU. I can't reall= y tell the + * difference between matrix+0x28 and top+0x138. The clock (matrix+0x24) = can be disabled + * and enabled from the Cortex M0 and it will nicely stop and restart the= A53, retaining + * all state. + */ + [ZX_CLK_CPU_WCLK] =3D GATE("cpu-wclk", PARENT_ID(ZX_CLK_CPU_MUX),= 0x24, 1, + CLK_IS_CRITICAL), + [ZX_CLK_CPU_PCLK] =3D GATE("cpu-pclk", clk_main[0], 0x24, 2, CLK_= IS_CRITICAL), + + /* + * There are a lot more controls in matrix+0x100. 13-16 appear to be 4 di= fferent AXI + * channels for different priorities. Bit 19 appears to be the DDR PHY wc= lk. + * + * The important task is to keep gpll enabled if the bootloader selected = a gpll-based rate + * for RAM. + */ + [ZX_CLK_DDR_CTRL_PCLK] =3D GATE("ddr-ctrl-pclk", clk_main[0], 0x100, 1= 7, CLK_IS_CRITICAL), + [ZX_CLK_DDR_CTRL_WCLK] =3D GATE("ddr-ctrl-wclk", PARENT_ID(ZX_CLK_DDR_= CTRL_MUX), 0x100, 18, + CLK_IS_CRITICAL), + + [ZX_CLK_ZSP_WCLK] =3D GATE("zsp-wclk", PARENT_ID(ZX_CLK_ZSP_MUX),= 0x3c, 0, 0), + + /* Both SDIO controllers depend on the ahb-pclk for register access. */ + [ZX_CLK_SD0_PCLK] =3D GATE("sd0-pclk", PARENT_FW("ahb"), 0x54, 12= , 0), + [ZX_CLK_SD0_WCLK] =3D GATE("sd0-wclk", PARENT_ID(ZX_CLK_SD0_MUX),= 0x54, 13, 0), + [ZX_CLK_SD0_CDET] =3D GATE("sd0-cdet", PARENT_FW("osc32k"), 0x54,= 14, 0), + [ZX_CLK_SD1_PCLK] =3D GATE("sd1-pclk", PARENT_FW("ahb"), 0x54, 4,= 0), + [ZX_CLK_SD1_WCLK] =3D GATE("sd1-wclk", PARENT_ID(ZX_CLK_SD1_MUX),= 0x54, 5, 0), + /* + * I don't know how the cdet clock works. Card detection in the way the d= wc,mmc driver uses + * it appears broken no matter this clock's setting. + */ + [ZX_CLK_SD1_CDET] =3D GATE("sd1-cdet", PARENT_FW("osc32k"), 0x54,= 6, 0), + + /* This is some "denali" NAND, not the qspi connected one */ + [ZX_CLK_NAND_WCLK] =3D GATE("nand-wclk", PARENT_ID(ZX_CLK_NAND_MUX= ), 0x54, 20, 0), + [ZX_CLK_NAND_PCLK] =3D GATE("nand-pclk", clk_main[0], 0x54, 21, 0), + + /* + * There is a set of gates for an unknown device at matrix+0x60. It is so= me LTE related + * device. If it is fed an incorrect clock, e.g. because dpll is not lock= ed and outputs + * 26 MHz, it will spam IRQs at SPI 68. This is likely a distress notific= ation that some + * internal PLL did not lock or similar + * + * ZTE's kernel has two defines for SPI 64: "LTE_TPU_INT_PS_INT" and "VOU= _OSD_INT". The + * latter is unlikely because VOU related clocks sit in matrix+0x168. + * + * Bit 9 in register 0x118 turns it off, providing a hint who the parent = is. + */ + [ZX_CLK_LTE_TPU_WCLK] =3D GATE("lte-tpu-wclk", PARENT_ID(ZX_CLK_MATRI= X_DPLL_D4), + 0x60, 0, 0), + [ZX_CLK_LTE_TPU_PCLK] =3D GATE("lte-tpu-pclk", clk_main[0], + 0x60, 2, 0), + + [ZX_CLK_EDCP_PCLK] =3D GATE("edcp-pclk", clk_main[0], 0x64, 1, 0), + [ZX_CLK_EDCP_WCLK] =3D GATE("edcp-wclk", PARENT_ID(ZX_CLK_EDCP_MUX= ), 0x64, 2, 0), + + /* + * This seems to be another SPI-Like device. ZTE's firmware operates it a= nd from testing + * it looks like the matrix-osc26m gate in top+0x140 stops this device. T= his would be + * consistent with the other SPI controllers too. + */ + [ZX_CLK_SSC_WCLK] =3D GATE("ssc-wclk", PARENT_FW("wclk-osc26m"), = 0x84, 1, 0), + [ZX_CLK_SSC_PCLK] =3D GATE("ssc-pclk", clk_main[0], 0x84, 2, 0), + + /* + * PDCFG. Like PMM, either clock bit will allow the device to function. P= robably there is + * no wclk line at all and the two bits are just an artifact of generally= having two bits + * per device. + */ + [ZX_CLK_PDCFG_WCLK] =3D GATE("pdcfg-wclk", matrix_unk, 0x88, 0, CLK= _IS_CRITICAL), + [ZX_CLK_PDCFG_PCLK] =3D GATE("pdcfg-pclk", clk_main[0], 0x88, 1, CL= K_IS_CRITICAL), + [ZX_CLK_MBOX_PCLK] =3D GATE("mbox-pclk", clk_main[0], 0x88, 2, 0), + [ZX_CLK_SRAM0_PCLK] =3D GATE("sram0-pclk", clk_main[0], 0x88, 4, 0), + [ZX_CLK_GSM_CFG_PCLK] =3D GATE("gsm-cfg-pclk", clk_main[0], 0x88, 8, = 0), + + /* + * ZTE's driver has a statement to the effect of *(top->base+0x11c) =3D 5= , with a comment + * suggesting that this sets a 50 MHz clock. The clock code itself lists = GMAC clocks in + * matrix+0x110 and lists the parents of these clocks as 50 MHz gpll outp= ut, but + * the downstream ZTE GMAC driver never enables the clocks. It turns out = ZTE's code is + * highly misleading. + * + * The GMAC's work clock is definitely not any gpll output because it kee= ps working fine + * with gpll disabled. Gating off matrix-osc26m breaks GMAC, so it must b= e its parent. + * + * The GMAC Gates are left enabled by the boot loader and are required fo= r the GMAC to work. + * + * As for the 50 MHz comment: See rmiiphy-wclk. + * + * The gmac-ahb clock is a child of topcrm's ahb-pclk and is required for= DMA transfers in + * and out of GMAC. Without it, GMAC still receives ethernet frames, but = can't drain them + * to memory and will eventually set the RX FIFO overflow flag. + */ + [ZX_CLK_GMAC_WCLK] =3D GATE("gmac-wclk", PARENT_FW("wclk-osc26m"),= 0x110, 0, 0), + [ZX_CLK_GMAC_PCLK] =3D GATE("gmac-pclk", clk_main[0], 0x110, 1, 0), + [ZX_CLK_GMAC_AHB] =3D GATE("gmac-ahb", PARENT_FW("ahb"), 0x110, 2= , 0), + + /* + * Is there an AXI bus gate? The symptom of cutting off the AXI mux selec= tion in top+0x140 + * is that matrixcrm becomes unreadable from m0 and A53 hangs. Inside mat= rix itself only 3 + * bits fit that bill: 0x8c bits 5, 6, 7. It seems a bit self-defeating t= o have a clock + * gate that shuts off access to itself though. I expect a clock gate for= the bus + * somewhere, and the mux exists, so exposing one AXI clock in the bindin= gs is the correct + * thing to do. It also serves to tell the kernel to keep the mux's paren= t enabled. + * + * Register 0x8c has 12 settable bits (0xfff). Ultimately it doesn't matt= er much which + * do-not-remove bit we don't remove. Other bits in this register behave = like gates (e.g + * bits 11:8 cut off USB temporarily), so I think we are looking in the r= ight place. + * + * If an explanation for the remaining bits surfaces and they are further= gates and/or + * resets, add them to the bindings. + */ + [ZX_CLK_AXI_WCLK] =3D GATE("axi-wclk", PARENT_ID(ZX_CLK_AXI_MUX),= 0x8c, 5, + CLK_IS_CRITICAL), + + [ZX_CLK_DMA_PCLK] =3D GATE("dma-pclk", clk_main[0], 0x94, 3, 0), + + /* + * There are a lot more VOU related controls in these registers, but turn= ing off the main + * clock seems to shut off the entire VOU MMIO range. + */ + [ZX_CLK_VOU_WCLK] =3D GATE("vou-wclk", matrix_unk, 0x168, 0, 0), + [ZX_CLK_VOU_PCLK] =3D GATE("vou-pclk", clk_main[0], 0x168, 1, 0), + + /* + * LSP uplink clocks. The pclk is fairly obvious (disabling it shuts off = the entire LSP + * register area). The wclk speeds were deduced by setting timers and qsp= i muxes to a + * specific speed and seeing which bit in matrix+0x7c needs to be enabled= for the device + * to work. + * + * Due to the timers I am certain about the 26 MHz and 32 kHz clocks. I c= annot directly + * observe the qspi mux frequency, so the clock rates depend on ZTE's qsp= i mux selection + * being correct. + * + * Two additional bits are specific to sound components - the mux for the= LSP's TDM IP is + * in matrixcrm and gets passed down. I2S has a mux in LSP, which can sel= ect the dpll-d4 + * clock. + */ + [ZX_CLK_TOLSP_MPLL_D5_WCLK] =3D GATE("lsp-mpll-d5", PARENT_FW("mpll-d5")= , 0x7c, 0, 0), + [ZX_CLK_TOLSP_MPLL_D4_WCLK] =3D GATE("lsp-mpll-d4", PARENT_ID(ZX_CLK_MAT= RIX_MPLL_D4), + 0x7c, 1, 0), + [ZX_CLK_TOLSP_MPLL_D6_WCLK] =3D GATE("lsp-mpll-d6", PARENT_ID(ZX_CLK_MAT= RIX_MPLL_D6), + 0x7c, 2, 0), + [ZX_CLK_TOLSP_MPLL_D8_WCLK] =3D GATE("lsp-mpll-d8", PARENT_ID(ZX_CLK_MAT= RIX_MPLL_D8), + 0x7c, 3, 0), + [ZX_CLK_TOLSP_MPLL_D12_WCLK] =3D GATE("lsp-mpll-d12", PARENT_ID(ZX_CLK_MA= TRIX_MPLL_D12), + 0x7c, 4, 0), + [ZX_CLK_TOLSP_OSC26M_WCLK] =3D GATE("lsp-osc26m", PARENT_FW("wclk-osc26= m"), 0x7c, 5, 0), + [ZX_CLK_TOLSP_OSC32K_WCLK] =3D GATE("lsp-osc32k", PARENT_FW("osc32k"), = 0x7c, 6, 0), + [ZX_CLK_TOLSP_PCLK] =3D GATE("lsp-pclk", clk_main[0], 0x7c, 7, 0= ), + [ZX_CLK_TOLSP_TDM_WCLK] =3D GATE("lsp-tdm-wclk", PARENT_ID(ZX_CLK_TD= M_MUX), 0x7c, 8, 0), + [ZX_CLK_TOLSP_DPLL_D4_WCLK] =3D GATE("lsp-dpll-d4", PARENT_ID(ZX_CLK_MAT= RIX_DPLL_D4), + 0x7c, 9, 0), +}; + +static int zx297520v3_matrix_init(struct regmap *map) +{ + u32 axi_val; + int res; + + /* Read the global AXI speed selection, insert it into our ballot and ena= ble voting */ + res =3D regmap_read(map, 0x0, &axi_val); + if (res) + return res; + + axi_val &=3D 0x7; + res =3D regmap_write(map, ZX297520V3_AXI_AP_VOTE, axi_val); + if (res) + return res; + + return regmap_write(map, 0x12c, 1); +} + +static unsigned int zx297520v3_matrix_exports[] =3D { + [ZX297520V3_SYS_TIMER_WCLK] =3D ZX_CLK_SYS_TIMER_WCLK, + [ZX297520V3_CPU_WCLK] =3D ZX_CLK_CPU_WCLK, + [ZX297520V3_CPU_PCLK] =3D ZX_CLK_CPU_PCLK, + [ZX297520V3_ZSP_WCLK] =3D ZX_CLK_ZSP_WCLK, + [ZX297520V3_DDR_CTRL_PCLK] =3D ZX_CLK_DDR_CTRL_PCLK, + [ZX297520V3_DDR_CTRL_WCLK] =3D ZX_CLK_DDR_CTRL_WCLK, + [ZX297520V3_EDCP_WCLK] =3D ZX_CLK_EDCP_WCLK, + [ZX297520V3_EDCP_PCLK] =3D ZX_CLK_EDCP_PCLK, + [ZX297520V3_SD0_WCLK] =3D ZX_CLK_SD0_WCLK, + [ZX297520V3_SD0_PCLK] =3D ZX_CLK_SD0_PCLK, + [ZX297520V3_SD0_CDET] =3D ZX_CLK_SD0_CDET, + [ZX297520V3_SD1_WCLK] =3D ZX_CLK_SD1_WCLK, + [ZX297520V3_SD1_PCLK] =3D ZX_CLK_SD1_PCLK, + [ZX297520V3_SD1_CDET] =3D ZX_CLK_SD1_CDET, + [ZX297520V3_NAND_WCLK] =3D ZX_CLK_NAND_WCLK, + [ZX297520V3_NAND_PCLK] =3D ZX_CLK_NAND_PCLK, + [ZX297520V3_DMA_PCLK] =3D ZX_CLK_DMA_PCLK, + [ZX297520V3_MBOX_PCLK] =3D ZX_CLK_MBOX_PCLK, + [ZX297520V3_PDCFG_WCLK] =3D ZX_CLK_PDCFG_WCLK, + [ZX297520V3_PDCFG_PCLK] =3D ZX_CLK_PDCFG_PCLK, + [ZX297520V3_SSC_WCLK] =3D ZX_CLK_SSC_WCLK, + [ZX297520V3_SSC_PCLK] =3D ZX_CLK_SSC_PCLK, + [ZX297520V3_AXI_WCLK] =3D ZX_CLK_AXI_WCLK, + [ZX297520V3_GMAC_WCLK] =3D ZX_CLK_GMAC_WCLK, + [ZX297520V3_GMAC_PCLK] =3D ZX_CLK_GMAC_PCLK, + [ZX297520V3_GMAC_AHB] =3D ZX_CLK_GMAC_AHB, + [ZX297520V3_VOU_WCLK] =3D ZX_CLK_VOU_WCLK, + [ZX297520V3_VOU_PCLK] =3D ZX_CLK_VOU_PCLK, + [ZX297520V3_LSP_MPLL_D5_WCLK] =3D ZX_CLK_TOLSP_MPLL_D5_WCLK, + [ZX297520V3_LSP_MPLL_D4_WCLK] =3D ZX_CLK_TOLSP_MPLL_D4_WCLK, + [ZX297520V3_LSP_MPLL_D6_WCLK] =3D ZX_CLK_TOLSP_MPLL_D6_WCLK, + [ZX297520V3_LSP_MPLL_D8_WCLK] =3D ZX_CLK_TOLSP_MPLL_D8_WCLK, + [ZX297520V3_LSP_MPLL_D12_WCLK] =3D ZX_CLK_TOLSP_MPLL_D12_WCLK, + [ZX297520V3_LSP_OSC26M_WCLK] =3D ZX_CLK_TOLSP_OSC26M_WCLK, + [ZX297520V3_LSP_OSC32K_WCLK] =3D ZX_CLK_TOLSP_OSC32K_WCLK, + [ZX297520V3_LSP_PCLK] =3D ZX_CLK_TOLSP_PCLK, + [ZX297520V3_LSP_TDM_WCLK] =3D ZX_CLK_TOLSP_TDM_WCLK, + [ZX297520V3_LSP_DPLL_D4_WCLK] =3D ZX_CLK_TOLSP_DPLL_D4_WCLK, + [ZX297520V3_SRAM0_PCLK] =3D ZX_CLK_SRAM0_PCLK, + [ZX297520V3_GSM_CFG_PCLK] =3D ZX_CLK_GSM_CFG_PCLK, +}; + +static const struct zx_clk_data zx297520v3_matrixclk_data =3D { + .init =3D zx297520v3_matrix_init, + .clocks =3D zx297520v3_matrix_clocks, + .num_clocks =3D ARRAY_SIZE(zx297520v3_matrix_clocks), + .exports =3D zx297520v3_matrix_exports, + .num_exports =3D ARRAY_SIZE(zx297520v3_matrix_exports), +}; + static int clk_zx297520v3_probe(struct platform_device *pdev) { const struct platform_device_id *id =3D platform_get_device_id(pdev); @@ -785,6 +1264,10 @@ static const struct platform_device_id clk_zx297520v3= _ids[] =3D { .name =3D "zx297520v3-topclk", .driver_data =3D (kernel_ulong_t)&zx297520v3_topclk_data, }, + { + .name =3D "zx297520v3-matrixclk", + .driver_data =3D (kernel_ulong_t)&zx297520v3_matrixclk_data, + }, { } }; MODULE_DEVICE_TABLE(platform, clk_zx297520v3_ids); --=20 2.54.0 From nobody Fri Oct 2 10:08:32 2026 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29FBF33CE9A for ; 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a=openpgp; fpr=4F9C2C8728019633893EBBB98CB81F9A72BBA155 "LSP" is ZTE's term for this part of the SoC, I suspect it stands for "low speed peripherals". The main UART is here, together with the flash controller and more surplus proprietary timers. It also has one more I2C controller that supposedly connects to a battery charger, SPI for displays and I2S for analog telephones. The boards I have don't have any of these components though. Signed-off-by: Stefan D=C3=B6singer --- Version 9: Link internal parents by an (internal) clock ID rather than names. One intentional clock tree change: The PWM device's parent is the 104 MHz mpll-d6 input. With some manual experimentation I managed to make the WiFi led blink with PWM, so I could confirm which matrixcrm bit gates off its parent. Update the comments to say that the device at lspcrm+0x4000 is indeed a Pulse Width Modulator. @Sashiko: If you find any other clock tree changes compared to version 8, they are unintentional and likely bugs. Version 8: Double-checked pclk and wclk. They were the wrong way around in previous submissions. Pclk is bit 0, wclk is bit 1. Version 7: Underscore in clock names to dashes Version 6: use MFD for LSP too Version 5: Removed unused tdm_lsp_sel. Fix zx297529 vs zx297520 typo. Adjusted .compatible to zte,zx297520v3-lspcrm --- drivers/clk/zte/clk-zx297520v3.c | 285 +++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 285 insertions(+) diff --git a/drivers/clk/zte/clk-zx297520v3.c b/drivers/clk/zte/clk-zx29752= 0v3.c index 6c4a7a1c3a9b..286eaedffce9 100644 --- a/drivers/clk/zte/clk-zx297520v3.c +++ b/drivers/clk/zte/clk-zx297520v3.c @@ -1248,6 +1248,287 @@ static const struct zx_clk_data zx297520v3_matrixcl= k_data =3D { .num_exports =3D ARRAY_SIZE(zx297520v3_matrix_exports), }; =20 +/* + * LSP clock entries have a common pattern: Bit 0 for pclk, Bit 1 for wclk= . Bit 4 (and sometimes + * more) for wclk mux. + * + * Bit 8 and 9 are resets handled by the reset-zte-zx297520v3 driver. + * + * Bits 15:12 can be a divisor, but not all clocks have it. Some clocks ha= ve a divisor in 19:16. + * + * The ID given in this table is the first register in the device's MMIO s= pace. ZTE's drivers + * usually call this a version register, but it looks more like a device i= dentifier. + * + * It looks like the registers map to devices like this: + * + * CRM Reg function div dev offset(lsp + xxxx) ID + * 0x0: Read-only, probably device identifier 0x00752100 + * 0x4: timer_l1 Y 0x1000 0x02020000 + * 0x8: watchdog_l2 Y 0x2000 0x02020000 + * 0xc: watchdog_l3 Y 0x3000 0x02020000 + * 0x10: pwm N 0x4000 0x01020000 + * 0x14: i2s0 Yh 0x5000 0x01030000 + * 0x18: always 0 - - - + * 0x1c: i2s1 Yh 0x6000 0x01030000 + * 0x20: always 0 - - - + * 0x24: qspi N 0x7000 0x01040000 + * 0x28: uart1 N 0x8000 0x01060000 + * 0x2c: i2c1 N 0x9000 0x01020000 + * 0x30: spi0 Y 0xa000 0x01040000 + * 0x34: timer_lb Y 0xb000 0x02020000 + * 0x38: timer_lc Y 0xc000 0x02020000 + * 0x3c: uart2 N 0xd000 0x01060000 + * 0x40: watchdog_le Y 0xe000 0x02020000 + * 0x44: timer_lf Y 0xf000 0x02020000 + * 0x48: spi1 Y 0x10000 0x01040000 + * 0x4c: timer_l11 Y 0x11000 0x02020000 + * 0x50: tdm Yh 0x12000 0x01040000 + * + * Registers 0x58, 0x5c, 0x60, 0x64, 0x68 seem to contain more controls fo= r i2s and tdm. + * + * The device at offset 0x4000 (clk reg 0x10) is a PWM device. The ID matc= hes that of i2c, it has a + * larger register set. ZTE's kernel does not operate it at all. The old u= pstream pwm-zx.c driver + * provided enough instructions to blink the Wifi led and isolate the pare= nt. + */ + +enum lsp_clock_ids { + ZX_CLK_TIMER_L1_MUX, + ZX_CLK_WDT_L2_MUX, + ZX_CLK_WDT_L3_MUX, + ZX_CLK_I2S0_MUX, + ZX_CLK_I2S1_MUX, + ZX_CLK_QSPI_MUX, + ZX_CLK_UART1_MUX, + ZX_CLK_I2C1_MUX, + ZX_CLK_SPI0_MUX, + ZX_CLK_TIMER_LB_MUX, + ZX_CLK_TIMER_LC_MUX, + ZX_CLK_UART2_MUX, + ZX_CLK_WDT_LE_MUX, + ZX_CLK_TIMER_LF_MUX, + ZX_CLK_SPI1_MUX, + ZX_CLK_TIMER_L11_MUX, + + ZX_CLK_TIMER_L1_DIV, + ZX_CLK_WDT_L2_DIV, + ZX_CLK_WDT_L3_DIV, + ZX_CLK_I2S0_DIV, + ZX_CLK_I2S1_DIV, + ZX_CLK_SPI0_DIV, + ZX_CLK_TIMER_LB_DIV, + ZX_CLK_TIMER_LC_DIV, + ZX_CLK_WDT_LE_DIV, + ZX_CLK_TIMER_LF_DIV, + ZX_CLK_SPI1_DIV, + ZX_CLK_TIMER_L11_DIV, + ZX_CLK_TDM_DIV, + + ZX_CLK_TIMER_L1_PCLK, + ZX_CLK_TIMER_L1_WCLK, + ZX_CLK_WDT_L2_PCLK, + ZX_CLK_WDT_L2_WCLK, + ZX_CLK_WDT_L3_PCLK, + ZX_CLK_WDT_L3_WCLK, + ZX_CLK_PWM_PCLK, + ZX_CLK_PWM_WCLK, + ZX_CLK_I2S0_PCLK, + ZX_CLK_I2S0_WCLK, + ZX_CLK_I2S1_PCLK, + ZX_CLK_I2S1_WCLK, + ZX_CLK_QSPI_PCLK, + ZX_CLK_QSPI_WCLK, + ZX_CLK_UART1_PCLK, + ZX_CLK_UART1_WCLK, + ZX_CLK_I2C1_PCLK, + ZX_CLK_I2C1_WCLK, + ZX_CLK_SPI0_PCLK, + ZX_CLK_SPI0_WCLK, + ZX_CLK_TIMER_LB_PCLK, + ZX_CLK_TIMER_LB_WCLK, + ZX_CLK_TIMER_LC_PCLK, + ZX_CLK_TIMER_LC_WCLK, + ZX_CLK_UART2_PCLK, + ZX_CLK_UART2_WCLK, + ZX_CLK_WDT_LE_PCLK, + ZX_CLK_WDT_LE_WCLK, + ZX_CLK_TIMER_LF_PCLK, + ZX_CLK_TIMER_LF_WCLK, + ZX_CLK_SPI1_PCLK, + ZX_CLK_SPI1_WCLK, + ZX_CLK_TIMER_L11_PCLK, + ZX_CLK_TIMER_L11_WCLK, + ZX_CLK_TDM_PCLK, + ZX_CLK_TDM_WCLK, +}; + +static const struct zx_parent_desc timer_lsp_sel[] =3D { + PARENT_FW("osc32k"), + PARENT_FW("osc26m"), +}; + +static const struct zx_parent_desc uart_lsp_sel[] =3D { + PARENT_FW("osc26m"), + PARENT_FW("mpll-d6"), +}; + +static const struct zx_parent_desc i2s_lsp_sel[] =3D { + PARENT_FW("osc26m"), + PARENT_FW("dpll-d4"), + PARENT_FW("mpll-d6"), + /* Unknown */ +}; + +static const struct zx_parent_desc spi_lsp_sel[] =3D { + PARENT_FW("osc26m"), + PARENT_FW("mpll-d4"), + PARENT_FW("mpll-d6"), + /* Unknown */ +}; + +static const struct zx_parent_desc qspi_lsp_sel[] =3D { + PARENT_FW("osc26m"), + PARENT_FW("mpll-d4"), + PARENT_FW("mpll-d5"), + PARENT_FW("mpll-d6"), + PARENT_FW("mpll-d8"), + PARENT_FW("mpll-d12"), + PARENT_FW("osc26m"), + PARENT_FW("osc26m"), +}; + +static const struct zx_clock zx297520v3_lsp_clocks[] =3D { + [ZX_CLK_TIMER_L1_MUX] =3D MUX("timer-l1-mux", timer_lsp_sel, 0x0= 4, 4, 1), + [ZX_CLK_WDT_L2_MUX] =3D MUX("wdt-l2-mux", timer_lsp_sel, 0x0= 8, 4, 1), + [ZX_CLK_WDT_L3_MUX] =3D MUX("wdt-l3-mux", timer_lsp_sel, 0x0= c, 4, 1), + /* PWM: No mux bit can be set */ + [ZX_CLK_I2S0_MUX] =3D MUX("i2s0-mux", i2s_lsp_sel, 0x1= 4, 4, 2), + /* 0x18: Always 0 */ + [ZX_CLK_I2S1_MUX] =3D MUX("i2s1-mux", i2s_lsp_sel, 0x1= c, 4, 2), + /* 0x20: Always 0 */ + [ZX_CLK_QSPI_MUX] =3D MUX("qspi-mux", qspi_lsp_sel, 0x2= 4, 4, 3), + [ZX_CLK_UART1_MUX] =3D MUX("uart1-mux", uart_lsp_sel, 0x2= 8, 4, 1), + [ZX_CLK_I2C1_MUX] =3D MUX("i2c1-mux", uart_lsp_sel, 0x2= c, 4, 1), + [ZX_CLK_SPI0_MUX] =3D MUX("spi0-mux", spi_lsp_sel, 0x3= 0, 4, 2), + [ZX_CLK_TIMER_LB_MUX] =3D MUX("timer-lb-mux", timer_lsp_sel, 0x3= 4, 4, 1), + [ZX_CLK_TIMER_LC_MUX] =3D MUX("timer-lc-mux", timer_lsp_sel, 0x3= 8, 4, 1), + [ZX_CLK_UART2_MUX] =3D MUX("uart2-mux", uart_lsp_sel, 0x3= c, 4, 1), + [ZX_CLK_WDT_LE_MUX] =3D MUX("wdt-le-mux", timer_lsp_sel, 0x4= 0, 4, 1), + [ZX_CLK_TIMER_LF_MUX] =3D MUX("timer-lf-mux", timer_lsp_sel, 0x4= 4, 4, 1), + [ZX_CLK_SPI1_MUX] =3D MUX("spi1-mux", spi_lsp_sel, 0x4= 8, 4, 2), + [ZX_CLK_TIMER_L11_MUX] =3D MUX("timer-l11-mux", timer_lsp_sel, 0x4= c, 4, 1), + /* TDM: No mux in LSP. Instead, it is in matrix with a separate clk line = to LSP */ + + [ZX_CLK_TIMER_L1_DIV] =3D DIV("timer-l1-div", PARENT_ID(ZX_CLK_TIMER_= L1_MUX), + 0x04, 12, 4), + [ZX_CLK_WDT_L2_DIV] =3D DIV("wdt-l2-div", PARENT_ID(ZX_CLK_WDT_L2_M= UX), 0x08, 12, 4), + [ZX_CLK_WDT_L3_DIV] =3D DIV("wdt-l3-div", PARENT_ID(ZX_CLK_WDT_L3_M= UX), 0x0c, 12, 4), + /* PWM: No div */ + [ZX_CLK_I2S0_DIV] =3D DIV("i2s0-div", PARENT_ID(ZX_CLK_I2S0_MUX),= 0x14, 16, 4), + /* 0x18: Always 0 */ + [ZX_CLK_I2S1_DIV] =3D DIV("i2s1-div", PARENT_ID(ZX_CLK_I2S1_MUX),= 0x1c, 16, 4), + /* 0x20: Always 0 */ + /* qspi, uart1, i2c1: No div */ + [ZX_CLK_SPI0_DIV] =3D DIV("spi0-div", PARENT_ID(ZX_CLK_SPI0_MUX),= 0x30, 12, 4), + [ZX_CLK_TIMER_LB_DIV] =3D DIV("timer-lb-div", PARENT_ID(ZX_CLK_TIMER_= LB_MUX), + 0x34, 12, 4), + [ZX_CLK_TIMER_LC_DIV] =3D DIV("timer-lc-div", PARENT_ID(ZX_CLK_TIMER_= LC_MUX), + 0x38, 12, 4), + /* uart2: No div */ + [ZX_CLK_WDT_LE_DIV] =3D DIV("wdt-le-div", PARENT_ID(ZX_CLK_WDT_LE_M= UX), 0x40, 12, 4), + [ZX_CLK_TIMER_LF_DIV] =3D DIV("timer-lf-div", PARENT_ID(ZX_CLK_TIMER_= LF_MUX), + 0x44, 12, 4), + [ZX_CLK_SPI1_DIV] =3D DIV("spi1-div", PARENT_ID(ZX_CLK_SPI1_MUX),= 0x48, 12, 4), + [ZX_CLK_TIMER_L11_DIV] =3D DIV("timer-l11-div", PARENT_ID(ZX_CLK_TIMER= _L11_MUX), + 0x4c, 12, 4), + [ZX_CLK_TDM_DIV] =3D DIV("tdm-div", PARENT_FW("tdm-wclk"), 0x50, 1= 6, 4), + + [ZX_CLK_TIMER_L1_PCLK] =3D GATE("timer-l1-pclk", PARENT_FW("pclk"), 0x04= , 0, 0), + [ZX_CLK_TIMER_L1_WCLK] =3D GATE("timer-l1-wclk", PARENT_ID(ZX_CLK_TIMER_= L1_DIV), 0x04, 1, 0), + [ZX_CLK_WDT_L2_PCLK] =3D GATE("wdt-l2-pclk", PARENT_FW("pclk"), 0x08, = 0, 0), + [ZX_CLK_WDT_L2_WCLK] =3D GATE("wdt-l2-wclk", PARENT_ID(ZX_CLK_WDT_L2_D= IV), 0x08, 1, 0), + [ZX_CLK_WDT_L3_PCLK] =3D GATE("wdt-l3-pclk", PARENT_FW("pclk"), 0x0c, = 0, 0), + [ZX_CLK_WDT_L3_WCLK] =3D GATE("wdt-l3-wclk", PARENT_ID(ZX_CLK_WDT_L3_D= IV), 0x0c, 1, 0), + [ZX_CLK_PWM_PCLK] =3D GATE("pwm-pclk", PARENT_FW("pclk"), 0x10, 0, = 0), + [ZX_CLK_PWM_WCLK] =3D GATE("pwm-wclk", PARENT_FW("mpll-d6"), 0x10, = 1, 0), + [ZX_CLK_I2S0_PCLK] =3D GATE("i2s0-pclk", PARENT_FW("pclk"), 0x14, 0,= 0), + [ZX_CLK_I2S0_WCLK] =3D GATE("i2s0-wclk", PARENT_ID(ZX_CLK_I2S0_DIV),= 0x14, 1, 0), + /* 0x18: Always 0 */ + [ZX_CLK_I2S1_PCLK] =3D GATE("i2s1-pclk", PARENT_FW("pclk"), 0x1c, 0,= 0), + [ZX_CLK_I2S1_WCLK] =3D GATE("i2s1-wclk", PARENT_ID(ZX_CLK_I2S1_DIV),= 0x1c, 1, 0), + /* 0x20: Always 0 */ + [ZX_CLK_QSPI_PCLK] =3D GATE("qspi-pclk", PARENT_FW("pclk"), 0x24, 0,= 0), + [ZX_CLK_QSPI_WCLK] =3D GATE("qspi-wclk", PARENT_ID(ZX_CLK_QSPI_MUX),= 0x24, 1, 0), + [ZX_CLK_UART1_PCLK] =3D GATE("uart1-pclk", PARENT_FW("pclk"), 0x28, 0= , 0), + [ZX_CLK_UART1_WCLK] =3D GATE("uart1-wclk", PARENT_ID(ZX_CLK_UART1_MUX= ), 0x28, 1, 0), + [ZX_CLK_I2C1_PCLK] =3D GATE("i2c1-pclk", PARENT_FW("pclk"), 0x2c, 0,= 0), + [ZX_CLK_I2C1_WCLK] =3D GATE("i2c1-wclk", PARENT_ID(ZX_CLK_I2C1_MUX),= 0x2c, 1, 0), + [ZX_CLK_SPI0_PCLK] =3D GATE("spi0-pclk", PARENT_FW("pclk"), 0x30, 0,= 0), + [ZX_CLK_SPI0_WCLK] =3D GATE("spi0-wclk", PARENT_ID(ZX_CLK_SPI0_DIV),= 0x30, 1, 0), + [ZX_CLK_TIMER_LB_PCLK] =3D GATE("timer-lb-pclk", PARENT_FW("pclk"), 0x34= , 0, 0), + [ZX_CLK_TIMER_LB_WCLK] =3D GATE("timer-lb-wclk", PARENT_ID(ZX_CLK_TIMER_= LB_DIV), 0x34, 1, 0), + [ZX_CLK_TIMER_LC_PCLK] =3D GATE("timer-lc-pclk", PARENT_FW("pclk"), 0x38= , 0, 0), + [ZX_CLK_TIMER_LC_WCLK] =3D GATE("timer-lc-wclk", PARENT_ID(ZX_CLK_TIMER_= LC_DIV), 0x38, 1, 0), + [ZX_CLK_UART2_PCLK] =3D GATE("uart2-pclk", PARENT_FW("pclk"), 0x3c, 0= , 0), + [ZX_CLK_UART2_WCLK] =3D GATE("uart2-wclk", PARENT_ID(ZX_CLK_UART2_MUX= ), 0x3c, 1, 0), + [ZX_CLK_WDT_LE_PCLK] =3D GATE("wdt-le-pclk", PARENT_FW("pclk"), 0x40, = 0, 0), + [ZX_CLK_WDT_LE_WCLK] =3D GATE("wdt-le-wclk", PARENT_ID(ZX_CLK_WDT_LE_D= IV), 0x40, 1, 0), + [ZX_CLK_TIMER_LF_PCLK] =3D GATE("timer-lf-pclk", PARENT_FW("pclk"), 0x44= , 0, 0), + [ZX_CLK_TIMER_LF_WCLK] =3D GATE("timer-lf-wclk", PARENT_ID(ZX_CLK_TIMER_= LF_DIV), 0x44, 1, 0), + [ZX_CLK_SPI1_PCLK] =3D GATE("spi1-pclk", PARENT_FW("pclk"), 0x48, 0,= 0), + [ZX_CLK_SPI1_WCLK] =3D GATE("spi1-wclk", PARENT_ID(ZX_CLK_SPI1_DIV),= 0x48, 1, 0), + [ZX_CLK_TIMER_L11_PCLK] =3D GATE("timer-l11-pclk", PARENT_FW("pclk"), 0x4= c, 0, 0), + [ZX_CLK_TIMER_L11_WCLK] =3D GATE("timer-l11-wclk", PARENT_ID(ZX_CLK_TIMER= _L11_DIV), + 0x4c, 1, 0), + [ZX_CLK_TDM_PCLK] =3D GATE("tdm-pclk", PARENT_FW("pclk"), 0x50, 0, = 0), + [ZX_CLK_TDM_WCLK] =3D GATE("tdm-wclk", PARENT_ID(ZX_CLK_TDM_DIV), 0= x50, 1, 0), +}; + +static unsigned int zx297520v3_lsp_exports[] =3D { + [ZX297520V3_TIMER_L1_WCLK] =3D ZX_CLK_TIMER_L1_WCLK, + [ZX297520V3_TIMER_L1_PCLK] =3D ZX_CLK_TIMER_L1_PCLK, + [ZX297520V3_WDT_L2_WCLK] =3D ZX_CLK_WDT_L2_WCLK, + [ZX297520V3_WDT_L2_PCLK] =3D ZX_CLK_WDT_L2_PCLK, + [ZX297520V3_WDT_L3_WCLK] =3D ZX_CLK_WDT_L3_WCLK, + [ZX297520V3_WDT_L3_PCLK] =3D ZX_CLK_WDT_L3_PCLK, + [ZX297520V3_PWM_WCLK] =3D ZX_CLK_PWM_WCLK, + [ZX297520V3_PWM_PCLK] =3D ZX_CLK_PWM_PCLK, + [ZX297520V3_I2S0_WCLK] =3D ZX_CLK_I2S0_WCLK, + [ZX297520V3_I2S0_PCLK] =3D ZX_CLK_I2S0_PCLK, + [ZX297520V3_I2S1_WCLK] =3D ZX_CLK_I2S1_WCLK, + [ZX297520V3_I2S1_PCLK] =3D ZX_CLK_I2S1_PCLK, + [ZX297520V3_QSPI_WCLK] =3D ZX_CLK_QSPI_WCLK, + [ZX297520V3_QSPI_PCLK] =3D ZX_CLK_QSPI_PCLK, + [ZX297520V3_UART1_WCLK] =3D ZX_CLK_UART1_WCLK, + [ZX297520V3_UART1_PCLK] =3D ZX_CLK_UART1_PCLK, + [ZX297520V3_I2C1_WCLK] =3D ZX_CLK_I2C1_WCLK, + [ZX297520V3_I2C1_PCLK] =3D ZX_CLK_I2C1_PCLK, + [ZX297520V3_SPI0_WCLK] =3D ZX_CLK_SPI0_WCLK, + [ZX297520V3_SPI0_PCLK] =3D ZX_CLK_SPI0_PCLK, + [ZX297520V3_TIMER_LB_WCLK] =3D ZX_CLK_TIMER_LB_WCLK, + [ZX297520V3_TIMER_LB_PCLK] =3D ZX_CLK_TIMER_LB_PCLK, + [ZX297520V3_TIMER_LC_WCLK] =3D ZX_CLK_TIMER_LC_WCLK, + [ZX297520V3_TIMER_LC_PCLK] =3D ZX_CLK_TIMER_LC_PCLK, + [ZX297520V3_UART2_WCLK] =3D ZX_CLK_UART2_WCLK, + [ZX297520V3_UART2_PCLK] =3D ZX_CLK_UART2_PCLK, + [ZX297520V3_WDT_LE_WCLK] =3D ZX_CLK_WDT_LE_WCLK, + [ZX297520V3_WDT_LE_PCLK] =3D ZX_CLK_WDT_LE_PCLK, + [ZX297520V3_TIMER_LF_WCLK] =3D ZX_CLK_TIMER_LF_WCLK, + [ZX297520V3_TIMER_LF_PCLK] =3D ZX_CLK_TIMER_LF_PCLK, + [ZX297520V3_SPI1_WCLK] =3D ZX_CLK_SPI1_WCLK, + [ZX297520V3_SPI1_PCLK] =3D ZX_CLK_SPI1_PCLK, + [ZX297520V3_TIMER_L11_WCLK] =3D ZX_CLK_TIMER_L11_WCLK, + [ZX297520V3_TIMER_L11_PCLK] =3D ZX_CLK_TIMER_L11_PCLK, + [ZX297520V3_TDM_WCLK] =3D ZX_CLK_TDM_WCLK, + [ZX297520V3_TDM_PCLK] =3D ZX_CLK_TDM_PCLK, +}; + +static const struct zx_clk_data zx297520v3_lspclk_data =3D { + .clocks =3D zx297520v3_lsp_clocks, + .num_clocks =3D ARRAY_SIZE(zx297520v3_lsp_clocks), + .exports =3D zx297520v3_lsp_exports, + .num_exports =3D ARRAY_SIZE(zx297520v3_lsp_exports), +}; + static int clk_zx297520v3_probe(struct platform_device *pdev) { const struct platform_device_id *id =3D platform_get_device_id(pdev); @@ -1268,6 +1549,10 @@ static const struct platform_device_id clk_zx297520v= 3_ids[] =3D { .name =3D "zx297520v3-matrixclk", .driver_data =3D (kernel_ulong_t)&zx297520v3_matrixclk_data, }, + { + .name =3D "zx297520v3-lspclk", + .driver_data =3D (kernel_ulong_t)&zx297520v3_lspclk_data, + }, { } }; MODULE_DEVICE_TABLE(platform, clk_zx297520v3_ids); --=20 2.54.0 From nobody Fri Oct 2 10:08:32 2026 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3358533F8B4 for ; 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Sun, 02 Aug 2026 13:35:00 -0700 (PDT) Received: from [192.168.0.2] ([197.250.226.155]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49807bb45ebsm118499905e9.4.2026.08.02.13.34.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Aug 2026 13:35:00 -0700 (PDT) From: =?utf-8?q?Stefan_D=C3=B6singer?= Date: Sun, 02 Aug 2026 23:33:43 +0300 Subject: [PATCH v9 11/12] reset: zte: Add a zx297520v3 reset driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260802-zx29clk-v9-11-d05530d85d28@gmail.com> References: <20260802-zx29clk-v9-0-d05530d85d28@gmail.com> In-Reply-To: <20260802-zx29clk-v9-0-d05530d85d28@gmail.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Brian Masney , Vinod Koul , Neil Armstrong , Russell King , Lee Jones Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, mfd@lists.linux.dev, =?utf-8?q?Stefan_D=C3=B6singer?= X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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a=openpgp; fpr=4F9C2C8728019633893EBBB98CB81F9A72BBA155 This drives the MFD child devices created by the zte-zx297520v3-crm driver. Reviewed-by: Philipp Zabel Signed-off-by: Stefan D=C3=B6singer --- v9: Remove HSIC and USB PHY resets, the phy driver will access them through the shared regmap directly Sort include files alphabetically Depend on HAS_IOMEM due to "select MFD_SYSCON" (Sashiko). This has some, but not consistent, precedent in the same file v8: Select MFD_SYSCON for COMPILE_TESTing this driver without the MFD parent driver. v7: Add MODULE_DEVICE_TABLE (Philipp) Add DDR control and LSP resets v6: Add a comment wrt checking all bits in .status() (Philipp) include cleanup (Philipp, Sashiko) v5: Make top and matrix MFD children instead of aux devices Split USB PHY reset into its own reset ID Remove USB reset wait code - this will be handled via syscon from a future minimal phy-zx29-usb driver --- MAINTAINERS | 1 + drivers/reset/Kconfig | 13 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-zte-zx297520v3.c | 236 +++++++++++++++++++++++++++++++= ++++ 4 files changed, 251 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 77fa86c671b8..eab0cdf8efac 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3917,6 +3917,7 @@ F: arch/arm/boot/dts/zte/ F: arch/arm/mach-zte/ F: drivers/clk/zte/ F: drivers/mfd/zte-zx297520v3-crm.c +F: drivers/reset/reset-zte-zx297520v3.c F: include/dt-bindings/clock/zte,zx297520v3-clk.h F: include/dt-bindings/phy/zte,zx297520v3-topcrm.h F: include/dt-bindings/reset/zte,zx297520v3-reset.h diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index d009eb0849a3..b92bd0c16517 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -404,6 +404,19 @@ config RESET_UNIPHIER_GLUE on UniPhier SoCs. Say Y if you want to control reset signals provided by the glue layer. =20 +config RESET_ZTE_ZX297520V3 + tristate "ZTE zx297520v3 Reset Driver" + depends on HAS_IOMEM + depends on MFD_ZTE_ZX297520V3_CRM || COMPILE_TEST + default SOC_ZX297520V3 + select MFD_SYSCON + help + This enables the reset controllers for ZTE zx297520v3 SoCs. The reset + controllers are required for booting this board and are part of the + clock and reset management controllers on this board, so you will also + need MFD_ZTE_ZX297520V3_CRM. Enable this if you are building a kernel + for a ZTE zx297520v3 based board. + config RESET_ZYNQ bool "ZYNQ Reset Driver" if COMPILE_TEST default ARCH_ZYNQ diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 3e52569bd276..9a8a48d44dc4 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -50,5 +50,6 @@ obj-$(CONFIG_RESET_TI_TPS380X) +=3D reset-tps380x.o obj-$(CONFIG_RESET_TN48M_CPLD) +=3D reset-tn48m.o obj-$(CONFIG_RESET_UNIPHIER) +=3D reset-uniphier.o obj-$(CONFIG_RESET_UNIPHIER_GLUE) +=3D reset-uniphier-glue.o +obj-$(CONFIG_RESET_ZTE_ZX297520V3) +=3D reset-zte-zx297520v3.o obj-$(CONFIG_RESET_ZYNQ) +=3D reset-zynq.o obj-$(CONFIG_RESET_ZYNQMP) +=3D reset-zynqmp.o diff --git a/drivers/reset/reset-zte-zx297520v3.c b/drivers/reset/reset-zte= -zx297520v3.c new file mode 100644 index 000000000000..bc2801d43d10 --- /dev/null +++ b/drivers/reset/reset-zte-zx297520v3.c @@ -0,0 +1,236 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026 Stefan D=C3=B6singer + */ +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Most devices on the zx297520v3 SoC have one reset bit per clock line. A= s a rule of thumb, the + * lower bit disconnects the device from the bus, similarly to turning off= PCLK - registers read 0 + * or hang indefinitely. Unlike PCLK, this reset may have a lingering effe= ct after deasserting. + * E.g. timers will be disabled, but retain their counter value. + * + * The other bit resets the actual device registers. + * + * For some devices, e.g. GMAC, both reset bits behave in the same way: Th= ey disconnect the device + * and registers will have their default state after deasserting. For devi= ces that have two reset + * bits, both need to be deasserted for the device to function. + */ +struct zte_reset_reg { + u32 mask; + u16 reg; +}; + +struct zte_reset_data { + const struct zte_reset_reg *resets; + unsigned int num; +}; + +struct zte_reset { + struct reset_controller_dev rcdev; + struct regmap *map; + const struct zte_reset_reg *resets; +}; + +static inline struct zte_reset *to_zte_reset(struct reset_controller_dev *= rcdev) +{ + return container_of(rcdev, struct zte_reset, rcdev); +} + +static int zx29_rst_assert(struct reset_controller_dev *rcdev, unsigned lo= ng id) +{ + struct zte_reset *rst =3D to_zte_reset(rcdev); + + return regmap_clear_bits(rst->map, rst->resets[id].reg, rst->resets[id].m= ask); +} + +static int zx29_rst_deassert(struct reset_controller_dev *rcdev, unsigned = long id) +{ + struct zte_reset *rst =3D to_zte_reset(rcdev); + + return regmap_set_bits(rst->map, rst->resets[id].reg, rst->resets[id].mas= k); +} + +static int zx29_rst_status(struct reset_controller_dev *rcdev, unsigned lo= ng id) +{ + struct zte_reset *rst =3D to_zte_reset(rcdev); + int res; + + /* Devices with two reset bits need both deasserted to work. So only repo= rt them as + * deasserted if both bits are set. + * + * assert()/deassert() will always clear/set both. The only reason a devi= ce might be in a + * hybrid state is an unexpected handover state from the bootloader. + */ + res =3D regmap_test_bits(rst->map, rst->resets[id].reg, rst->resets[id].m= ask); + if (res < 0) + return res; + + return !res; +} + +static const struct reset_control_ops zx29_rst_ops =3D { + .assert =3D zx29_rst_assert, + .deassert =3D zx29_rst_deassert, + .status =3D zx29_rst_status, +}; + +static const struct zte_reset_reg zx297520v3_top_resets[] =3D { + /* This bit is set by ZTE's cpko.ko blob, it looks like a reset bit for t= he LTE DSP + * coprocessor. Clocks for it are in matrixcrm. + */ + [ZX297520V3_ZSP_RESET] =3D { .reg =3D 0x13c, .mask =3D BIT(0) = }, + + [ZX297520V3_UART0_RESET] =3D { .reg =3D 0x78, .mask =3D BIT(6) | BI= T(7) }, + [ZX297520V3_I2C0_RESET] =3D { .reg =3D 0x74, .mask =3D BIT(8) | BI= T(9) }, + /* Only one reset. Bit 5 is settable but does not do anything observable = */ + [ZX297520V3_RTC_RESET] =3D { .reg =3D 0x74, .mask =3D BIT(4) = }, + [ZX297520V3_TIMER_T08_RESET] =3D { .reg =3D 0x78, .mask =3D BIT(4) | BI= T(5) }, + [ZX297520V3_TIMER_T09_RESET] =3D { .reg =3D 0x78, .mask =3D BIT(2) | BI= T(3) }, + /* Only one reset. Bit 0 is settable but does not do anything observable = */ + [ZX297520V3_PMM_RESET] =3D { .reg =3D 0x74, .mask =3D BIT(1) = }, + + /* I haven't found any clocks for GPIO. It probably wouldn't make much + * sense anyway. Only one reset bit per controller. + */ + [ZX297520V3_GPIO_RESET] =3D { .reg =3D 0x74, .mask =3D BIT(3) = }, + [ZX297520V3_GPIO8_RESET] =3D { .reg =3D 0x74, .mask =3D BIT(2) = }, + + [ZX297520V3_TIMER_T12_RESET] =3D { .reg =3D 0x74, .mask =3D BIT(6) | BI= T(7) }, + [ZX297520V3_TIMER_T13_RESET] =3D { .reg =3D 0x7c, .mask =3D BIT(0) | BI= T(1) }, + [ZX297520V3_TIMER_T14_RESET] =3D { .reg =3D 0x7c, .mask =3D BIT(2) | BI= T(3) }, + [ZX297520V3_TIMER_T15_RESET] =3D { .reg =3D 0x74, .mask =3D BIT(10) | BI= T(11) }, + [ZX297520V3_TIMER_T16_RESET] =3D { .reg =3D 0x7c, .mask =3D BIT(4) | BI= T(5) }, + [ZX297520V3_TIMER_T17_RESET] =3D { .reg =3D 0x12c, .mask =3D BIT(0) | BI= T(1) }, + [ZX297520V3_WDT_T18_RESET] =3D { .reg =3D 0x74, .mask =3D BIT(12) | BI= T(13) }, + [ZX297520V3_USIM1_RESET] =3D { .reg =3D 0x74, .mask =3D BIT(14) | BI= T(15) }, + [ZX297520V3_AHB_RESET] =3D { .reg =3D 0x70, .mask =3D BIT(0) | BI= T(1) }, + + /* USB reset. 0x84 returns the USB device status (0x1 for HSIC up, 0x2 fo= r USB up, but + * all 3 bits (PCLK, WCLK, PHY) need to be deasserted for the device to r= eport ready. + * Thus polling the status is the responsibility of the USB PHY driver. + */ + [ZX297520V3_USB_RESET] =3D { .reg =3D 0x80, .mask =3D BIT(4) | BIT= (5) }, + [ZX297520V3_HSIC_RESET] =3D { .reg =3D 0x80, .mask =3D BIT(1) | BIT= (2) }, +}; + +static const struct zte_reset_data zx297520v3_topreset_data =3D { + .resets =3D zx297520v3_top_resets, + .num =3D ARRAY_SIZE(zx297520v3_top_resets), +}; + +static const struct zte_reset_reg zx297520v3_matrix_resets[] =3D { + [ZX297520V3_CPU_RESET] =3D { .reg =3D 0x28, .mask =3D BIT(1) = }, + [ZX297520V3_DDR_CTRL_RESET] =3D { .reg =3D 0x100, .mask =3D BIT(10) | BI= T(11) }, + [ZX297520V3_EDCP_RESET] =3D { .reg =3D 0x68, .mask =3D BIT(0) = }, + [ZX297520V3_SD0_RESET] =3D { .reg =3D 0x58, .mask =3D BIT(1) = }, + [ZX297520V3_SD1_RESET] =3D { .reg =3D 0x58, .mask =3D BIT(0) = }, + [ZX297520V3_NAND_RESET] =3D { .reg =3D 0x58, .mask =3D BIT(4) = }, + [ZX297520V3_PDCFG_RESET] =3D { .reg =3D 0x94, .mask =3D BIT(20) = }, + [ZX297520V3_SSC_RESET] =3D { .reg =3D 0x94, .mask =3D BIT(24) = }, + [ZX297520V3_GMAC_RESET] =3D { .reg =3D 0x114, .mask =3D BIT(0) | BI= T(1) }, + [ZX297520V3_VOU_RESET] =3D { .reg =3D 0x16c, .mask =3D BIT(0) = }, + [ZX297520V3_LSP_RESET] =3D { .reg =3D 0x80, .mask =3D BIT(0) = }, +}; + +static const struct zte_reset_data zx297520v3_matrixreset_data =3D { + .resets =3D zx297520v3_matrix_resets, + .num =3D ARRAY_SIZE(zx297520v3_matrix_resets), +}; + +static const struct zte_reset_reg zx297520v3_lsp_resets[] =3D { + [ZX297520V3_TIMER_L1_RESET] =3D { .reg =3D 0x04, .mask =3D BIT(8) | BI= T(9) }, + [ZX297520V3_WDT_L2_RESET] =3D { .reg =3D 0x08, .mask =3D BIT(8) | BI= T(9) }, + [ZX297520V3_WDT_L3_RESET] =3D { .reg =3D 0x0c, .mask =3D BIT(8) | BI= T(9) }, + [ZX297520V3_PWM_RESET] =3D { .reg =3D 0x10, .mask =3D BIT(8) | BI= T(9) }, + [ZX297520V3_I2S0_RESET] =3D { .reg =3D 0x14, .mask =3D BIT(8) | BI= T(9) }, + /* 0x18: Not writeable */ + [ZX297520V3_I2S1_RESET] =3D { .reg =3D 0x1c, .mask =3D BIT(8) | BI= T(9) }, + /* 0x20: Not writeable */ + [ZX297520V3_QSPI_RESET] =3D { .reg =3D 0x24, .mask =3D BIT(8) | BI= T(9) }, + [ZX297520V3_UART1_RESET] =3D { .reg =3D 0x28, .mask =3D BIT(8) | BI= T(9) }, + [ZX297520V3_I2C1_RESET] =3D { .reg =3D 0x2c, .mask =3D BIT(8) | BI= T(9) }, + [ZX297520V3_SPI0_RESET] =3D { .reg =3D 0x30, .mask =3D BIT(8) | BI= T(9) }, + [ZX297520V3_TIMER_LB_RESET] =3D { .reg =3D 0x34, .mask =3D BIT(8) | BI= T(9) }, + [ZX297520V3_TIMER_LC_RESET] =3D { .reg =3D 0x38, .mask =3D BIT(8) | BI= T(9) }, + [ZX297520V3_UART2_RESET] =3D { .reg =3D 0x3c, .mask =3D BIT(8) | BI= T(9) }, + [ZX297520V3_WDT_LE_RESET] =3D { .reg =3D 0x40, .mask =3D BIT(8) | BI= T(9) }, + [ZX297520V3_TIMER_LF_RESET] =3D { .reg =3D 0x44, .mask =3D BIT(8) | BI= T(9) }, + [ZX297520V3_SPI1_RESET] =3D { .reg =3D 0x48, .mask =3D BIT(8) | BI= T(9) }, + [ZX297520V3_TIMER_L11_RESET] =3D { .reg =3D 0x4c, .mask =3D BIT(8) | BI= T(9) }, + [ZX297520V3_TDM_RESET] =3D { .reg =3D 0x50, .mask =3D BIT(8) | BI= T(9) }, +}; + +static const struct zte_reset_data zx297520v3_lspreset_data =3D { + .resets =3D zx297520v3_lsp_resets, + .num =3D ARRAY_SIZE(zx297520v3_lsp_resets), +}; + +static int reset_zx297520v3_probe(struct platform_device *pdev) +{ + const struct platform_device_id *id =3D platform_get_device_id(pdev); + struct device *dev =3D &pdev->dev; + struct device_node *of_node =3D dev->parent->of_node; + const struct zte_reset_data *data; + struct zte_reset *rst; + + if (!id) + return -ENODEV; + data =3D (const struct zte_reset_data *)id->driver_data; + + rst =3D devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL); + if (!rst) + return -ENOMEM; + + rst->resets =3D data->resets; + rst->rcdev.owner =3D THIS_MODULE; + rst->rcdev.nr_resets =3D data->num; + rst->rcdev.ops =3D &zx29_rst_ops; + rst->rcdev.of_node =3D of_node; + rst->rcdev.dev =3D dev; + + rst->map =3D device_node_to_regmap(of_node); + if (IS_ERR(rst->map)) + return dev_err_probe(dev, PTR_ERR(rst->map), "Cannot get parent syscon r= egmap\n"); + + return devm_reset_controller_register(dev, &rst->rcdev); +} + +static const struct platform_device_id reset_zx297520v3_ids[] =3D { + { + .name =3D "zx297520v3-topreset", + .driver_data =3D (kernel_ulong_t)&zx297520v3_topreset_data, + }, + { + .name =3D "zx297520v3-matrixreset", + .driver_data =3D (kernel_ulong_t)&zx297520v3_matrixreset_data, + }, + { + .name =3D "zx297520v3-lspreset", + .driver_data =3D (kernel_ulong_t)&zx297520v3_lspreset_data, + }, + { } +}; +MODULE_DEVICE_TABLE(platform, reset_zx297520v3_ids); + +static struct platform_driver reset_zx297520v3 =3D { + .probe =3D reset_zx297520v3_probe, + .driver =3D { + .name =3D "reset-zx297520v3", + }, + .id_table =3D reset_zx297520v3_ids, +}; +module_platform_driver(reset_zx297520v3); + +MODULE_AUTHOR("Stefan D=C3=B6singer "); +MODULE_DESCRIPTION("ZTE zx297520v3 reset driver"); +MODULE_LICENSE("GPL"); --=20 2.54.0 From nobody Fri Oct 2 10:08:32 2026 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 43CA133F585 for ; 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a=openpgp; fpr=4F9C2C8728019633893EBBB98CB81F9A72BBA155 This makes use of the driver added in the previous patches. It wires up the uart clocks and resets and allows getting rid of the placeholder uartclk node. Signed-off-by: Stefan D=C3=B6singer --- Version 9: Sort new nodes by mmio address rename syscon-reboot to "reboot" adjust to changes in bindings Version 7: Add phy nodes to topcrm Remove syscon from matrixclk again Adapt remove now-removed extra clk inputs from matrix Add reset to LSP osc26m -> clock-26m for the fixed rate clocks, likewise for 32k Version 6: Add syscon to matrixclk Version 5: Re-name from *clk to *crm Add the syscon-reboot node here because the binding requires it Re-add accidentally dropped uart2 IRQ --- arch/arm/boot/dts/zte/zx297520v3.dtsi | 81 +++++++++++++++++++++++++++++++= ---- 1 file changed, 73 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/zte/zx297520v3.dtsi b/arch/arm/boot/dts/zte/= zx297520v3.dtsi index a16c30a164bb..579ad45028f6 100644 --- a/arch/arm/boot/dts/zte/zx297520v3.dtsi +++ b/arch/arm/boot/dts/zte/zx297520v3.dtsi @@ -3,7 +3,9 @@ * Copyright (c) 2026 Stefan D=C3=B6singer */ =20 +#include #include +#include =20 / { #address-cells =3D <1>; @@ -20,13 +22,16 @@ cpu@0 { }; }; =20 - /* Base bus clock and default for the UART. It will be replaced once a cl= ock driver has - * been added. - */ - uartclk: uartclk-26000000 { - #clock-cells =3D <0>; + osc26m: clock-26m { compatible =3D "fixed-clock"; clock-frequency =3D <26000000>; + #clock-cells =3D <0>; + }; + + osc32k: clock-32k { + compatible =3D "fixed-clock"; + clock-frequency =3D <32768>; + #clock-cells =3D <0>; }; =20 timer { @@ -75,18 +80,77 @@ uart0: serial@131000 { arm,primecell-periphid =3D <0x0018c011>; reg =3D <0x00131000 0x1000>; interrupts =3D ; - clocks =3D <&uartclk>, <&uartclk>; + clocks =3D <&topcrm ZX297520V3_UART0_WCLK>, <&topcrm ZX297520V3_UART0_P= CLK>; clock-names =3D "uartclk", "apb_pclk"; + resets =3D <&topcrm ZX297520V3_UART0_RESET>; status =3D "disabled"; }; =20 + topcrm: clock-controller@13b000 { + compatible =3D "zte,zx297520v3-topcrm", "syscon"; + reg =3D <0x0013b000 0x400>; + clocks =3D <&osc26m>, <&osc32k>; + clock-names =3D "osc26m", "osc32k"; + interrupts =3D , + , + , + ; + interrupt-names =3D "usb-up", "usb-down", "hsic-up", "hsic-down"; + #clock-cells =3D <1>; + #phy-cells =3D <1>; + #reset-cells =3D <1>; + + reboot { + compatible =3D "syscon-reboot"; + offset =3D <0x0>; + value =3D <0x1>; + mask =3D <0x1>; + }; + }; + + matrixcrm: clock-controller@1306000 { + compatible =3D "zte,zx297520v3-matrixcrm"; + reg =3D <0x01306000 0x400>; + clocks =3D <&osc26m>, <&osc32k>, <&topcrm ZX297520V3_AHB_PCLK>, + <&topcrm ZX297520V3_MPLL>, <&topcrm ZX297520V3_MPLL_D5>, + <&topcrm ZX297520V3_DPLL>, <&topcrm ZX297520V3_GPLL>, + <&topcrm ZX297520V3_GPLL_D2>, <&topcrm ZX297520V3_GATED_OSC26M>; + clock-names =3D "osc26m", "osc32k", "ahb", "mpll", "mpll-d5", "dpll", + "gpll", "gpll-d2", "wclk-osc26m"; + #clock-cells =3D <1>; + #hwlock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + lspcrm: clock-controller@1400000 { + compatible =3D "zte,zx297520v3-lspcrm"; + reg =3D <0x01400000 0x100>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + + clocks =3D <&matrixcrm ZX297520V3_LSP_MPLL_D5_WCLK>, + <&matrixcrm ZX297520V3_LSP_MPLL_D4_WCLK>, + <&matrixcrm ZX297520V3_LSP_MPLL_D6_WCLK>, + <&matrixcrm ZX297520V3_LSP_MPLL_D8_WCLK>, + <&matrixcrm ZX297520V3_LSP_MPLL_D12_WCLK>, + <&matrixcrm ZX297520V3_LSP_OSC26M_WCLK>, + <&matrixcrm ZX297520V3_LSP_OSC32K_WCLK>, + <&matrixcrm ZX297520V3_LSP_PCLK>, + <&matrixcrm ZX297520V3_LSP_TDM_WCLK>, + <&matrixcrm ZX297520V3_LSP_DPLL_D4_WCLK>; + clock-names =3D "mpll-d5", "mpll-d4", "mpll-d6", "mpll-d8", "mpll-d12", + "osc26m", "osc32k", "pclk", "tdm-wclk", "dpll-d4"; + resets =3D <&matrixcrm ZX297520V3_LSP_RESET>; + }; + uart1: serial@1408000 { compatible =3D "arm,pl011", "arm,primecell"; arm,primecell-periphid =3D <0x0018c011>; reg =3D <0x01408000 0x1000>; interrupts =3D ; - clocks =3D <&uartclk>, <&uartclk>; + clocks =3D <&lspcrm ZX297520V3_UART1_WCLK>, <&lspcrm ZX297520V3_UART1_P= CLK>; clock-names =3D "uartclk", "apb_pclk"; + resets =3D <&lspcrm ZX297520V3_UART1_RESET>; status =3D "disabled"; }; =20 @@ -95,8 +159,9 @@ uart2: serial@140d000 { arm,primecell-periphid =3D <0x0018c011>; reg =3D <0x0140d000 0x1000>; interrupts =3D ; - clocks =3D <&uartclk>, <&uartclk>; + clocks =3D <&lspcrm ZX297520V3_UART2_WCLK>, <&lspcrm ZX297520V3_UART2_P= CLK>; clock-names =3D "uartclk", "apb_pclk"; + resets =3D <&lspcrm ZX297520V3_UART2_RESET>; status =3D "disabled"; }; }; --=20 2.54.0