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No functional change intended. Assisted-by: Claude:claude-sonnet-5 Signed-off-by: Maulik Shah Reviewed-by: Linus Walleij --- drivers/gpio/gpio-davinci.c | 8 ++++---- drivers/gpio/gpio-mt7621.c | 2 +- drivers/gpio/gpio-mvebu.c | 4 ++-- drivers/gpio/gpio-mxs.c | 4 ++-- drivers/gpio/gpio-omap.c | 9 ++++----- drivers/gpio/gpio-pl061.c | 5 ++--- drivers/gpio/gpio-pxa.c | 2 +- drivers/gpio/gpio-rda.c | 4 ++-- drivers/gpio/gpio-sa1100.c | 2 +- drivers/gpio/gpio-sodaville.c | 2 +- drivers/gpio/gpio-stmpe.c | 2 +- drivers/gpio/gpio-tegra.c | 4 ++-- drivers/gpio/gpio-timberdale.c | 2 +- 13 files changed, 24 insertions(+), 26 deletions(-) diff --git a/drivers/gpio/gpio-davinci.c b/drivers/gpio/gpio-davinci.c index 270cd7c88812..cccbaea1dec2 100644 --- a/drivers/gpio/gpio-davinci.c +++ b/drivers/gpio/gpio-davinci.c @@ -285,9 +285,9 @@ static void gpio_irq_unmask(struct irq_data *d) =20 gpiochip_enable_irq(&chips->chip, hwirq); =20 - status &=3D IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; + status &=3D IRQ_TYPE_EDGE_BOTH; if (!status) - status =3D IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; + status =3D IRQ_TYPE_EDGE_BOTH; =20 if (status & IRQ_TYPE_EDGE_FALLING) writel_relaxed(mask, &g->set_falling); @@ -297,7 +297,7 @@ static void gpio_irq_unmask(struct irq_data *d) =20 static int gpio_irq_type(struct irq_data *d, unsigned trigger) { - if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) + if (trigger & ~IRQ_TYPE_EDGE_BOTH) return -EINVAL; =20 return 0; @@ -400,7 +400,7 @@ static int gpio_irq_type_unbanked(struct irq_data *data= , unsigned trigger) =20 mask =3D __gpio_mask(i); =20 - if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) + if (trigger & ~IRQ_TYPE_EDGE_BOTH) return -EINVAL; =20 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING) diff --git a/drivers/gpio/gpio-mt7621.c b/drivers/gpio/gpio-mt7621.c index 87086c322f08..a86f6b1060fc 100644 --- a/drivers/gpio/gpio-mt7621.c +++ b/drivers/gpio/gpio-mt7621.c @@ -194,7 +194,7 @@ mt7621_gpio_irq_type(struct irq_data *d, unsigned int t= ype) rg->hlevel | rg->llevel) & mask) return 0; =20 - type =3D IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; + type =3D IRQ_TYPE_EDGE_BOTH; } =20 rg->rising &=3D ~mask; diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c index 8d3acadb0d68..93b8a08b04b9 100644 --- a/drivers/gpio/gpio-mvebu.c +++ b/drivers/gpio/gpio-mvebu.c @@ -1296,7 +1296,7 @@ static int mvebu_gpio_probe(struct platform_device *p= dev) gc =3D irq_get_domain_generic_chip(mvchip->domain, 0); gc->private =3D mvchip; ct =3D &gc->chip_types[0]; - ct->type =3D IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW; + ct->type =3D IRQ_TYPE_LEVEL_MASK; ct->chip.irq_mask =3D mvebu_gpio_level_irq_mask; ct->chip.irq_unmask =3D mvebu_gpio_level_irq_unmask; ct->chip.irq_set_type =3D mvebu_gpio_irq_set_type; @@ -1305,7 +1305,7 @@ static int mvebu_gpio_probe(struct platform_device *p= dev) ct->chip.name =3D mvchip->chip.label; =20 ct =3D &gc->chip_types[1]; - ct->type =3D IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; + ct->type =3D IRQ_TYPE_EDGE_BOTH; ct->chip.irq_ack =3D mvebu_gpio_irq_ack; ct->chip.irq_mask =3D mvebu_gpio_edge_irq_mask; ct->chip.irq_unmask =3D mvebu_gpio_edge_irq_unmask; diff --git a/drivers/gpio/gpio-mxs.c b/drivers/gpio/gpio-mxs.c index 5635694bf9f4..900315aba85a 100644 --- a/drivers/gpio/gpio-mxs.c +++ b/drivers/gpio/gpio-mxs.c @@ -198,7 +198,7 @@ static int mxs_gpio_init_gc(struct mxs_gpio_port *port,= int irq_base) gc->private =3D port; =20 ct =3D &gc->chip_types[0]; - ct->type =3D IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW; + ct->type =3D IRQ_TYPE_LEVEL_MASK; ct->chip.irq_ack =3D irq_gc_ack_set_bit; ct->chip.irq_mask =3D irq_gc_mask_disable_reg; ct->chip.irq_unmask =3D irq_gc_unmask_enable_reg; @@ -210,7 +210,7 @@ static int mxs_gpio_init_gc(struct mxs_gpio_port *port,= int irq_base) ct->regs.disable =3D PINCTRL_PIN2IRQ(port) + MXS_CLR; =20 ct =3D &gc->chip_types[1]; - ct->type =3D IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; + ct->type =3D IRQ_TYPE_EDGE_BOTH; ct->chip.irq_ack =3D irq_gc_ack_set_bit; ct->chip.irq_mask =3D irq_gc_mask_disable_reg; ct->chip.irq_unmask =3D irq_gc_unmask_enable_reg; diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c index e39723b5901b..005420baecf4 100644 --- a/drivers/gpio/gpio-omap.c +++ b/drivers/gpio/gpio-omap.c @@ -432,8 +432,7 @@ static int omap_gpio_irq_type(struct irq_data *d, unsig= ned type) if (type & ~IRQ_TYPE_SENSE_MASK) return -EINVAL; =20 - if (!bank->regs->leveldetect0 && - (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) + if (!bank->regs->leveldetect0 && (type & IRQ_TYPE_LEVEL_MASK)) return -EINVAL; =20 raw_spin_lock_irqsave(&bank->lock, flags); @@ -450,9 +449,9 @@ static int omap_gpio_irq_type(struct irq_data *d, unsig= ned type) } raw_spin_unlock_irqrestore(&bank->lock, flags); =20 - if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) + if (type & IRQ_TYPE_LEVEL_MASK) irq_set_handler_locked(d, handle_level_irq); - else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) + else if (type & IRQ_TYPE_EDGE_BOTH) /* * Edge IRQs are already cleared/acked in irq_handler and * not need to be masked, as result handle_edge_irq() @@ -702,7 +701,7 @@ static void omap_gpio_unmask_irq(struct irq_data *d) * after enabing the interrupt to clear the wakeup status. */ if (bank->regs->leveldetect0 && bank->regs->wkup_en && - trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) + trigger & IRQ_TYPE_LEVEL_MASK) omap_clear_gpio_irqstatus(bank, offset); =20 if (trigger) diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c index 919cf86fd590..fcd44e34f65e 100644 --- a/drivers/gpio/gpio-pl061.c +++ b/drivers/gpio/gpio-pl061.c @@ -132,8 +132,7 @@ static int pl061_irq_type(struct irq_data *d, unsigned = trigger) if (offset < 0 || offset >=3D PL061_GPIO_NR) return -EINVAL; =20 - if ((trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) && - (trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))) + if ((trigger & IRQ_TYPE_LEVEL_MASK) && (trigger & IRQ_TYPE_EDGE_BOTH)) { dev_err(gc->parent, "trying to configure line %d for both level and edge " @@ -149,7 +148,7 @@ static int pl061_irq_type(struct irq_data *d, unsigned = trigger) gpiois =3D readb(pl061->base + GPIOIS); gpioibe =3D readb(pl061->base + GPIOIBE); =20 - if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { + if (trigger & IRQ_TYPE_LEVEL_MASK) { bool polarity =3D trigger & IRQ_TYPE_LEVEL_HIGH; =20 /* Disable edge detection */ diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c index 5d61053e0596..2b5da973f51f 100644 --- a/drivers/gpio/gpio-pxa.c +++ b/drivers/gpio/gpio-pxa.c @@ -406,7 +406,7 @@ static int pxa_gpio_irq_type(struct irq_data *d, unsign= ed int type) if (__gpio_is_occupied(pchip, gpio)) return 0; =20 - type =3D IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; + type =3D IRQ_TYPE_EDGE_BOTH; } =20 gpdr =3D readl_relaxed(c->regbase + GPDR_OFFSET); diff --git a/drivers/gpio/gpio-rda.c b/drivers/gpio/gpio-rda.c index 7bbc6f0ce4c8..f6c05fdbe63f 100644 --- a/drivers/gpio/gpio-rda.c +++ b/drivers/gpio/gpio-rda.c @@ -169,9 +169,9 @@ static int rda_gpio_irq_set_type(struct irq_data *data,= unsigned int flow_type) if (ret) return ret; =20 - if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) + if (flow_type & IRQ_TYPE_LEVEL_MASK) irq_set_handler_locked(data, handle_level_irq); - else if (flow_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) + else if (flow_type & IRQ_TYPE_EDGE_BOTH) irq_set_handler_locked(data, handle_edge_irq); =20 return 0; diff --git a/drivers/gpio/gpio-sa1100.c b/drivers/gpio/gpio-sa1100.c index ffa73dd3b982..e4f3bf949b87 100644 --- a/drivers/gpio/gpio-sa1100.c +++ b/drivers/gpio/gpio-sa1100.c @@ -139,7 +139,7 @@ static int sa1100_gpio_type(struct irq_data *d, unsigne= d int type) if (type =3D=3D IRQ_TYPE_PROBE) { if ((sgc->irqrising | sgc->irqfalling) & mask) return 0; - type =3D IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; + type =3D IRQ_TYPE_EDGE_BOTH; } =20 if (type & IRQ_TYPE_EDGE_RISING) diff --git a/drivers/gpio/gpio-sodaville.c b/drivers/gpio/gpio-sodaville.c index 37c133837729..e2a784df275c 100644 --- a/drivers/gpio/gpio-sodaville.c +++ b/drivers/gpio/gpio-sodaville.c @@ -158,7 +158,7 @@ static int sdv_register_irqsupport(struct sdv_gpio_chip= _data *sd, =20 sd->gc->private =3D sd; ct =3D sd->gc->chip_types; - ct->type =3D IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW; + ct->type =3D IRQ_TYPE_LEVEL_MASK; ct->regs.eoi =3D GPSTR; ct->regs.mask =3D GPIO_INT; ct->chip.irq_mask =3D irq_gc_mask_clr_bit; diff --git a/drivers/gpio/gpio-stmpe.c b/drivers/gpio/gpio-stmpe.c index 6faf30347a36..ccdf13a741b7 100644 --- a/drivers/gpio/gpio-stmpe.c +++ b/drivers/gpio/gpio-stmpe.c @@ -149,7 +149,7 @@ static int stmpe_gpio_irq_set_type(struct irq_data *d, = unsigned int type) int regoffset =3D offset / 8; int mask =3D BIT(offset % 8); =20 - if (type & IRQ_TYPE_LEVEL_LOW || type & IRQ_TYPE_LEVEL_HIGH) + if (type & IRQ_TYPE_LEVEL_MASK) return -EINVAL; =20 /* STMPE801 and STMPE 1600 don't have RE and FE registers */ diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c index fa6c8ee92093..ccda3a56d599 100644 --- a/drivers/gpio/gpio-tegra.c +++ b/drivers/gpio/gpio-tegra.c @@ -342,9 +342,9 @@ static int tegra_gpio_irq_set_type(struct irq_data *d, = unsigned int type) return ret; } =20 - if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) + if (type & IRQ_TYPE_LEVEL_MASK) irq_set_handler_locked(d, handle_level_irq); - else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) + else if (type & IRQ_TYPE_EDGE_BOTH) irq_set_handler_locked(d, handle_edge_irq); =20 if (d->parent_data) diff --git a/drivers/gpio/gpio-timberdale.c b/drivers/gpio/gpio-timberdale.c index ec378a4220a7..727fa1b5ad3b 100644 --- a/drivers/gpio/gpio-timberdale.c +++ b/drivers/gpio/gpio-timberdale.c @@ -148,7 +148,7 @@ static int timbgpio_irq_type(struct irq_data *d, unsign= ed trigger) if (ver > 2) bflr =3D ioread32(tgpio->membase + TGPIO_BFLR); =20 - if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { + if (trigger & IRQ_TYPE_LEVEL_MASK) { bflr &=3D ~(1 << offset); flr &=3D ~(1 << offset); if (trigger & IRQ_TYPE_LEVEL_HIGH) --- base-commit: 415606a7be939835db9b0d6b711887586646346d change-id: 20260802-b4b4-irq-trigger-mask-gpio-1c3f66bcd26b Best regards, -- =20 Maulik Shah