From nobody Fri Oct 2 10:53:09 2026 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EFAE7175A86; Sat, 1 Aug 2026 14:31:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.75.144.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785594711; cv=none; b=ljU9UCaZ/+UhmyBh76ZRO4g7MOJ7VSwpXKOyZ45i2taMF9ToT/lTaVAb60x+RpV8g176g1MJDJkYrWTfzaCpyvYd6fnG6CALkDiPx5h67BpcWgOF5qUeyfMZZzt6nk6EagXK6Q/XF3cp8TiwzaJ8nGbaLvRvUn4dNI+h59iLJrE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785594711; c=relaxed/simple; bh=XJbxeE4P5CdrOG0V6r29IkFeA/RV47HiUzfl5xpQdwU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=N+MTrz+ltx1N2V+K9WqQpG3JBlgizR+Bsj5fyoFPshUfTuq9fiXhlsLWF7YofCxDJLPdiL39W9+bjxtFCiw6+NhIV2N2HyuT8N/Kj9xDhaSyWQoOmz+OpAUJbEXOjIjOzny7BtgIt5KmEj+OMvGQHDPJTD+HfVdefrULgzNQhsg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mainlining.org; spf=pass smtp.mailfrom=mainlining.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b=KMr9lFY4; dkim=permerror (0-bit key) header.d=mainlining.org header.i=@mainlining.org header.b=Oq29EeBo; arc=none smtp.client-ip=5.75.144.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mainlining.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mainlining.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b="KMr9lFY4"; dkim=permerror (0-bit key) header.d=mainlining.org header.i=@mainlining.org header.b="Oq29EeBo" DKIM-Signature: v=1; a=rsa-sha256; s=202507r; d=mainlining.org; c=relaxed/relaxed; h=Message-ID:Date:Subject:To:From; t=1785594694; bh=kT7FjJPCpQu6X2rYwUg3eaV cRYGLEPMtjJ7ctYM05ps=; b=KMr9lFY4UKyFYZQ2vuegh8OBSDBSfuMuxYDRfkNiD6G2zY/D1/ mswE8qzhTVIlubbTfWj3EUtQB0SI5HHrVy7N+XyKEisjC8XydPGG4nLoGmreFP/3Z7Ipb6Ye0VP OnS5h7BfF3oUFBgHlk05pWKEzsmQXGV91NrVRlqcQZ6W9Ep4EBA7NFDvrbGQJrX9VcYmQDnxt4Q yoW80yrSSLo7EmxXE6uaojWD2CkAQL1UR/iUmJD/VYPKn7YpDXUNtRR8UdZ2r4WQ16DCthkCfmr 1iQ0UkevETWCNjh2OSLuyFOu1u3vP4iNBBtKpzFRPUUP4hPHFhJV5k2oxub6Z0gL+ng==; DKIM-Signature: v=1; a=ed25519-sha256; s=202507e; d=mainlining.org; c=relaxed/relaxed; h=Message-ID:Date:Subject:To:From; t=1785594694; bh=kT7FjJPCpQu6X2rYwUg3eaV cRYGLEPMtjJ7ctYM05ps=; b=Oq29EeBoAhVwGI3q3UxC408N/goaZ5Zv4WJodBLHd+gnY3kR/9 /LQCkcGgAFTbQHwfOi5NioqSRENMnieGx5Dg==; From: Danila Tikhonov To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sakari Ailus , Vladimir Zapolskiy , Mauro Carvalho Chehab , Eugene Lepshy , Vasiliy Doylov , Achill Gilgenast , Luca Weiss Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Danila Tikhonov Subject: [PATCH 1/2] drivers: media: i2c: s5kjn1: Add support for 19.2MHz MCLK Date: Sat, 1 Aug 2026 17:31:24 +0300 Message-ID: <20260801143125.267054-2-danila@mainlining.org> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260801143125.267054-1-danila@mainlining.org> References: <20260801143125.267054-1-danila@mainlining.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The S5KJN1 sensor supports a range of external clock frequencies (MCLK), while the driver currently only supports a 24MHz MCLK. The 19.2MHz clock is used by the S5KJN1 camera sensor on the Nothing Phone (1) aka sm7325-nothing-spacewar. Add support for this frequency. While splitting the clock settings into separate register sequences, add definitions for the known clock-related registers and values instead of using raw register addresses and magic values. Signed-off-by: Danila Tikhonov Tested-by: Vasiliy Doylov --- drivers/media/i2c/s5kjn1.c | 183 ++++++++++++++++++++++++++++++------- 1 file changed, 151 insertions(+), 32 deletions(-) diff --git a/drivers/media/i2c/s5kjn1.c b/drivers/media/i2c/s5kjn1.c index a707cb740556..1036e629758f 100644 --- a/drivers/media/i2c/s5kjn1.c +++ b/drivers/media/i2c/s5kjn1.c @@ -15,6 +15,7 @@ #include =20 #define S5KJN1_LINK_FREQ_700MHZ (700ULL * HZ_PER_MHZ) +#define S5KJN1_MCLK_FREQ_19P2MHZ (19200 * HZ_PER_KHZ) #define S5KJN1_MCLK_FREQ_24MHZ (24 * HZ_PER_MHZ) #define S5KJN1_DATA_LANES 4 =20 @@ -25,6 +26,24 @@ #define S5KJN1_REG_CTRL_MODE CCI_REG8(0x0100) #define S5KJN1_MODE_STREAMING BIT(0) =20 +#define S5KJN1_REG_EXTCLK_INTEGER CCI_REG16(0x0136) +#define S5KJN1_REG_EXTCLK_FRACTION CCI_REG16(0x013e) +#define S5KJN1_REG_VT_PIX_CLK_DIV CCI_REG16(0x0300) +#define S5KJN1_REG_VT_SYS_CLK_DIV CCI_REG16(0x0302) +#define S5KJN1_REG_VT_PRE_PLL_CLK_DIV CCI_REG16(0x0304) +#define S5KJN1_REG_VT_PLL_MULTIPLIER CCI_REG16(0x0306) + +#define S5KJN1_EXTCLK_19P2MHZ_INTEGER 0x1300 +#define S5KJN1_EXTCLK_19P2MHZ_FRACTION 0x00c8 +#define S5KJN1_EXTCLK_24MHZ_INTEGER 0x1800 +#define S5KJN1_EXTCLK_24MHZ_FRACTION 0x0000 +#define S5KJN1_VT_PIX_CLK_DIV 0x0006 +#define S5KJN1_VT_SYS_CLK_DIV 0x0001 +#define S5KJN1_VT_PRE_PLL_DIV_19P2MHZ 0x0003 +#define S5KJN1_VT_PRE_PLL_DIV_24MHZ 0x0004 +#define S5KJN1_VT_PLL_MUL_19P2MHZ 0x0083 +#define S5KJN1_VT_PLL_MUL_24MHZ 0x008c + #define S5KJN1_REG_ORIENTATION CCI_REG8(0x0101) #define S5KJN1_VFLIP BIT(1) #define S5KJN1_HFLIP BIT(0) @@ -70,6 +89,17 @@ struct s5kjn1_reg_list { unsigned int num_regs; }; =20 +enum s5kjn1_mclk { + S5KJN1_MCLK_19P2MHZ, + S5KJN1_MCLK_24MHZ, + S5KJN1_NUM_MCLKS, +}; + +static const unsigned long s5kjn1_mclk_freqs[S5KJN1_NUM_MCLKS] =3D { + [S5KJN1_MCLK_19P2MHZ] =3D S5KJN1_MCLK_FREQ_19P2MHZ, + [S5KJN1_MCLK_24MHZ] =3D S5KJN1_MCLK_FREQ_24MHZ, +}; + struct s5kjn1_mode { u32 width; /* Frame width in pixels */ u32 height; /* Frame height in pixels */ @@ -78,7 +108,10 @@ struct s5kjn1_mode { u32 exposure; /* Default exposure value */ u32 exposure_margin; /* Exposure margin */ =20 - const struct s5kjn1_reg_list reg_list; /* Sensor register setting */ + /* Sensor register setting */ + const struct s5kjn1_reg_list mode_setup_reg_list; + const struct s5kjn1_reg_list clk_reg_list[S5KJN1_NUM_MCLKS]; + const struct s5kjn1_reg_list frame_timing_reg_list; }; =20 static const char * const s5kjn1_test_pattern_menu[] =3D { @@ -93,6 +126,7 @@ struct s5kjn1 { struct device *dev; struct regmap *regmap; struct clk *mclk; + unsigned int mclk_index; struct gpio_desc *reset_gpio; struct regulator *afvdd; /* Autofocus actuator power */ struct regulator *vdda; /* Analog power */ @@ -147,7 +181,7 @@ static const struct cci_reg_sequence init_array_setting= [] =3D { { CCI_REG16(0x011a), 0x0001 }, }; =20 -static const struct cci_reg_sequence s5kjn1_4080x3072_30fps_mode[] =3D { +static const struct cci_reg_sequence s5kjn1_4080x3072_30fps_mode_setup[] = =3D { { CCI_REG16(0x6028), 0x2400 }, { CCI_REG16(0x602a), 0x1a28 }, { CCI_REG16(0x6f12), 0x4c00 }, @@ -403,21 +437,39 @@ static const struct cci_reg_sequence s5kjn1_4080x3072= _30fps_mode[] =3D { { CCI_REG16(0x0110), 0x1002 }, { CCI_REG16(0x0114), 0x0301 }, { CCI_REG16(0x0116), 0x3000 }, +}; =20 - /* Clock settings */ - { CCI_REG16(0x0136), 0x1800 }, - { CCI_REG16(0x013e), 0x0000 }, - { CCI_REG16(0x0300), 0x0006 }, - { CCI_REG16(0x0302), 0x0001 }, - { CCI_REG16(0x0304), 0x0004 }, - { CCI_REG16(0x0306), 0x008c }, +static const struct cci_reg_sequence s5kjn1_4080x3072_30fps_19p2mhz_clk[] = =3D { + { S5KJN1_REG_EXTCLK_INTEGER, S5KJN1_EXTCLK_19P2MHZ_INTEGER }, + { S5KJN1_REG_EXTCLK_FRACTION, S5KJN1_EXTCLK_19P2MHZ_FRACTION }, + { S5KJN1_REG_VT_PIX_CLK_DIV, S5KJN1_VT_PIX_CLK_DIV }, + { S5KJN1_REG_VT_SYS_CLK_DIV, S5KJN1_VT_SYS_CLK_DIV }, + { S5KJN1_REG_VT_PRE_PLL_CLK_DIV, S5KJN1_VT_PRE_PLL_DIV_19P2MHZ }, + { S5KJN1_REG_VT_PLL_MULTIPLIER, S5KJN1_VT_PLL_MUL_19P2MHZ }, + { CCI_REG16(0x0308), 0x0008 }, + { CCI_REG16(0x030a), 0x0001 }, + { CCI_REG16(0x030c), 0x0000 }, + { CCI_REG16(0x030e), 0x0003 }, + { CCI_REG16(0x0310), 0x0089 }, + { CCI_REG16(0x0312), 0x0000 }, +}; + +static const struct cci_reg_sequence s5kjn1_4080x3072_30fps_24mhz_clk[] = =3D { + { S5KJN1_REG_EXTCLK_INTEGER, S5KJN1_EXTCLK_24MHZ_INTEGER }, + { S5KJN1_REG_EXTCLK_FRACTION, S5KJN1_EXTCLK_24MHZ_FRACTION }, + { S5KJN1_REG_VT_PIX_CLK_DIV, S5KJN1_VT_PIX_CLK_DIV }, + { S5KJN1_REG_VT_SYS_CLK_DIV, S5KJN1_VT_SYS_CLK_DIV }, + { S5KJN1_REG_VT_PRE_PLL_CLK_DIV, S5KJN1_VT_PRE_PLL_DIV_24MHZ }, + { S5KJN1_REG_VT_PLL_MULTIPLIER, S5KJN1_VT_PLL_MUL_24MHZ }, { CCI_REG16(0x0308), 0x0008 }, { CCI_REG16(0x030a), 0x0001 }, { CCI_REG16(0x030c), 0x0000 }, { CCI_REG16(0x030e), 0x0004 }, { CCI_REG16(0x0310), 0x0092 }, { CCI_REG16(0x0312), 0x0000 }, +}; =20 +static const struct cci_reg_sequence s5kjn1_4080x3072_30fps_frame_timing[]= =3D { { CCI_REG16(0x080e), 0x0000 }, { S5KJN1_REG_VTS, 0x10c0 }, { S5KJN1_REG_HTS, 0x1100 }, @@ -431,7 +483,7 @@ static const struct cci_reg_sequence s5kjn1_4080x3072_3= 0fps_mode[] =3D { { CCI_REG16(0x0816), 0x1c00 }, }; =20 -static const struct cci_reg_sequence s5kjn1_8160x6144_10fps_mode[] =3D { +static const struct cci_reg_sequence s5kjn1_8160x6144_10fps_mode_setup[] = =3D { { CCI_REG16(0x6028), 0x2400 }, { CCI_REG16(0x602a), 0x1a28 }, { CCI_REG16(0x6f12), 0x4c00 }, @@ -687,21 +739,39 @@ static const struct cci_reg_sequence s5kjn1_8160x6144= _10fps_mode[] =3D { { CCI_REG16(0x0110), 0x1002 }, { CCI_REG16(0x0114), 0x0300 }, { CCI_REG16(0x0116), 0x3000 }, +}; + +static const struct cci_reg_sequence s5kjn1_8160x6144_10fps_19p2mhz_clk[] = =3D { + { S5KJN1_REG_EXTCLK_INTEGER, S5KJN1_EXTCLK_19P2MHZ_INTEGER }, + { S5KJN1_REG_EXTCLK_FRACTION, S5KJN1_EXTCLK_19P2MHZ_FRACTION }, + { S5KJN1_REG_VT_PIX_CLK_DIV, S5KJN1_VT_PIX_CLK_DIV }, + { S5KJN1_REG_VT_SYS_CLK_DIV, S5KJN1_VT_SYS_CLK_DIV }, + { S5KJN1_REG_VT_PRE_PLL_CLK_DIV, S5KJN1_VT_PRE_PLL_DIV_19P2MHZ }, + { S5KJN1_REG_VT_PLL_MULTIPLIER, S5KJN1_VT_PLL_MUL_19P2MHZ }, + { CCI_REG16(0x0308), 0x0008 }, + { CCI_REG16(0x030a), 0x0001 }, + { CCI_REG16(0x030c), 0x0000 }, + { CCI_REG16(0x030e), 0x0003 }, + { CCI_REG16(0x0310), 0x006d }, + { CCI_REG16(0x0312), 0x0000 }, +}; =20 - /* Clock settings */ - { CCI_REG16(0x0136), 0x1800 }, - { CCI_REG16(0x013e), 0x0000 }, - { CCI_REG16(0x0300), 0x0006 }, - { CCI_REG16(0x0302), 0x0001 }, - { CCI_REG16(0x0304), 0x0004 }, - { CCI_REG16(0x0306), 0x008c }, +static const struct cci_reg_sequence s5kjn1_8160x6144_10fps_24mhz_clk[] = =3D { + { S5KJN1_REG_EXTCLK_INTEGER, S5KJN1_EXTCLK_24MHZ_INTEGER }, + { S5KJN1_REG_EXTCLK_FRACTION, S5KJN1_EXTCLK_24MHZ_FRACTION }, + { S5KJN1_REG_VT_PIX_CLK_DIV, S5KJN1_VT_PIX_CLK_DIV }, + { S5KJN1_REG_VT_SYS_CLK_DIV, S5KJN1_VT_SYS_CLK_DIV }, + { S5KJN1_REG_VT_PRE_PLL_CLK_DIV, S5KJN1_VT_PRE_PLL_DIV_24MHZ }, + { S5KJN1_REG_VT_PLL_MULTIPLIER, S5KJN1_VT_PLL_MUL_24MHZ }, { CCI_REG16(0x0308), 0x0008 }, { CCI_REG16(0x030a), 0x0001 }, { CCI_REG16(0x030c), 0x0000 }, { CCI_REG16(0x030e), 0x0004 }, { CCI_REG16(0x0310), 0x0074 }, { CCI_REG16(0x0312), 0x0000 }, +}; =20 +static const struct cci_reg_sequence s5kjn1_8160x6144_10fps_frame_timing[]= =3D { { CCI_REG16(0x080e), 0x0000 }, { S5KJN1_REG_VTS, 0x1900 }, { S5KJN1_REG_HTS, 0x21f0 }, @@ -722,9 +792,23 @@ static const struct s5kjn1_mode s5kjn1_supported_modes= [] =3D { .vts =3D 4288, .exposure =3D 3840, .exposure_margin =3D 22, - .reg_list =3D { - .regs =3D s5kjn1_4080x3072_30fps_mode, - .num_regs =3D ARRAY_SIZE(s5kjn1_4080x3072_30fps_mode), + .mode_setup_reg_list =3D { + .regs =3D s5kjn1_4080x3072_30fps_mode_setup, + .num_regs =3D ARRAY_SIZE(s5kjn1_4080x3072_30fps_mode_setup), + }, + .clk_reg_list =3D { + [S5KJN1_MCLK_19P2MHZ] =3D { + .regs =3D s5kjn1_4080x3072_30fps_19p2mhz_clk, + .num_regs =3D ARRAY_SIZE(s5kjn1_4080x3072_30fps_19p2mhz_clk), + }, + [S5KJN1_MCLK_24MHZ] =3D { + .regs =3D s5kjn1_4080x3072_30fps_24mhz_clk, + .num_regs =3D ARRAY_SIZE(s5kjn1_4080x3072_30fps_24mhz_clk), + }, + }, + .frame_timing_reg_list =3D { + .regs =3D s5kjn1_4080x3072_30fps_frame_timing, + .num_regs =3D ARRAY_SIZE(s5kjn1_4080x3072_30fps_frame_timing), }, }, { @@ -734,9 +818,23 @@ static const struct s5kjn1_mode s5kjn1_supported_modes= [] =3D { .vts =3D 6400, .exposure =3D 6144, .exposure_margin =3D 44, - .reg_list =3D { - .regs =3D s5kjn1_8160x6144_10fps_mode, - .num_regs =3D ARRAY_SIZE(s5kjn1_8160x6144_10fps_mode), + .mode_setup_reg_list =3D { + .regs =3D s5kjn1_8160x6144_10fps_mode_setup, + .num_regs =3D ARRAY_SIZE(s5kjn1_8160x6144_10fps_mode_setup), + }, + .clk_reg_list =3D { + [S5KJN1_MCLK_19P2MHZ] =3D { + .regs =3D s5kjn1_8160x6144_10fps_19p2mhz_clk, + .num_regs =3D ARRAY_SIZE(s5kjn1_8160x6144_10fps_19p2mhz_clk), + }, + [S5KJN1_MCLK_24MHZ] =3D { + .regs =3D s5kjn1_8160x6144_10fps_24mhz_clk, + .num_regs =3D ARRAY_SIZE(s5kjn1_8160x6144_10fps_24mhz_clk), + }, + }, + .frame_timing_reg_list =3D { + .regs =3D s5kjn1_8160x6144_10fps_frame_timing, + .num_regs =3D ARRAY_SIZE(s5kjn1_8160x6144_10fps_frame_timing), }, }, }; @@ -894,9 +992,12 @@ static int s5kjn1_enable_streams(struct v4l2_subdev *s= d, u64 streams_mask) { struct s5kjn1 *s5kjn1 =3D to_s5kjn1(sd); - const struct s5kjn1_reg_list *reg_list =3D &s5kjn1->mode->reg_list; + const struct s5kjn1_mode *mode =3D s5kjn1->mode; + const struct s5kjn1_reg_list *clk_reg_list; int ret; =20 + clk_reg_list =3D &mode->clk_reg_list[s5kjn1->mclk_index]; + ret =3D pm_runtime_resume_and_get(s5kjn1->dev); if (ret) return ret; @@ -924,8 +1025,12 @@ static int s5kjn1_enable_streams(struct v4l2_subdev *= sd, /* Sensor init settings */ cci_multi_reg_write(s5kjn1->regmap, init_array_setting, ARRAY_SIZE(init_array_setting), &ret); - cci_multi_reg_write(s5kjn1->regmap, reg_list->regs, - reg_list->num_regs, &ret); + cci_multi_reg_write(s5kjn1->regmap, mode->mode_setup_reg_list.regs, + mode->mode_setup_reg_list.num_regs, &ret); + cci_multi_reg_write(s5kjn1->regmap, clk_reg_list->regs, + clk_reg_list->num_regs, &ret); + cci_multi_reg_write(s5kjn1->regmap, mode->frame_timing_reg_list.regs, + mode->frame_timing_reg_list.num_regs, &ret); if (ret) goto error; =20 @@ -1199,6 +1304,23 @@ static int s5kjn1_check_hwcfg(struct s5kjn1 *s5kjn1) return ret; } =20 +static int s5kjn1_get_mclk_index(struct s5kjn1 *s5kjn1) +{ + unsigned long freq =3D clk_get_rate(s5kjn1->mclk); + unsigned int i; + + for (i =3D 0; i < ARRAY_SIZE(s5kjn1_mclk_freqs); i++) { + if (freq =3D=3D s5kjn1_mclk_freqs[i]) { + s5kjn1->mclk_index =3D i; + return 0; + } + } + + return dev_err_probe(s5kjn1->dev, -EINVAL, + "MCLK clock frequency %lu is not supported\n", + freq); +} + static int s5kjn1_power_on(struct device *dev) { struct v4l2_subdev *sd =3D dev_get_drvdata(dev); @@ -1290,7 +1412,6 @@ static int s5kjn1_power_off(struct device *dev) static int s5kjn1_probe(struct i2c_client *client) { struct s5kjn1 *s5kjn1; - unsigned long freq; int ret; =20 s5kjn1 =3D devm_kzalloc(&client->dev, sizeof(*s5kjn1), GFP_KERNEL); @@ -1310,11 +1431,9 @@ static int s5kjn1_probe(struct i2c_client *client) return dev_err_probe(s5kjn1->dev, PTR_ERR(s5kjn1->mclk), "failed to get MCLK clock\n"); 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From: Danila Tikhonov To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sakari Ailus , Vladimir Zapolskiy , Mauro Carvalho Chehab , Eugene Lepshy , Vasiliy Doylov , Achill Gilgenast , Luca Weiss Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Danila Tikhonov Subject: [PATCH 2/2] arm64: dts: qcom: sm7325-nothing-spacewar: Add ultra wide camera support Date: Sat, 1 Aug 2026 17:31:25 +0300 Message-ID: <20260801143125.267054-3-danila@mainlining.org> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260801143125.267054-1-danila@mainlining.org> References: <20260801143125.267054-1-danila@mainlining.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add and configure the necessary nodes to enable the ultra wide camera (Samsung S5KJN1), connected to CSIPHY 2. Signed-off-by: Danila Tikhonov Tested-by: Vasiliy Doylov --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 7 +++ .../boot/dts/qcom/sm7325-nothing-spacewar.dts | 47 ++++++++++++++++++- 2 files changed, 53 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qco= m/kodiak.dtsi index f74fa66f1a67..96bb354dad8f 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -5851,6 +5851,13 @@ tlmm: pinctrl@f100000 { gpio-ranges =3D <&tlmm 0 0 175>; wakeup-parent =3D <&pdc>; =20 + cam_mclk2_default: cam-mclk2-default-state { + pins =3D "gpio66"; + function =3D "cam_mclk"; + drive-strength =3D <2>; + bias-disable; + }; + cam_mclk3_default: cam-mclk3-default-state { pins =3D "gpio67"; function =3D "cam_mclk"; diff --git a/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts b/arch/ar= m64/boot/dts/qcom/sm7325-nothing-spacewar.dts index a6ba19cb60fd..c36e3274f783 100644 --- a/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts +++ b/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -831,6 +832,23 @@ vreg_bob: bob { }; }; =20 +&camss { + vdda-phy-supply =3D <&vreg_l10c_0p88>; + vdda-pll-supply =3D <&vreg_l6b_1p2>; + + status =3D "okay"; + + ports { + port@2 { + csiphy2_ep: endpoint { + data-lanes =3D <0 1 2 3>; + bus-type =3D ; + remote-endpoint =3D <&camera_s5kjn1_ep>; + }; + }; + }; +}; + &cci0 { /* * cci0_i2c1 bus is unused and GPIO 71&72 are repurposed. @@ -860,7 +878,34 @@ &cci1 { =20 &cci1_i2c0 { /* actuator (For Ultra Wide sensor) @ 0xc */ - /* D-PHY samsung,s5kjn1 (Ultra Wide) @ 0x2d */ + + camu_s5kjn1: camera@2d { + compatible =3D "samsung,s5kjn1"; + reg =3D <0x2d>; + + vdda-supply =3D <&vreg_camu_vana_2p8>; + vddd-supply =3D <&vreg_camu_vdig_1p1>; + vddio-supply =3D <&vreg_cam_vio_1p8>; + + clocks =3D <&camcc CAM_CC_MCLK2_CLK>; + assigned-clocks =3D <&camcc CAM_CC_MCLK2_CLK>; + assigned-clock-rates =3D <19200000>; + + reset-gpios =3D <&tlmm 77 GPIO_ACTIVE_LOW>; + pinctrl-0 =3D <&cam_mclk2_default>; + pinctrl-names =3D "default"; + + orientation =3D <1>; /* Rear facing */ + rotation =3D <90>; + + port { + camera_s5kjn1_ep: endpoint { + data-lanes =3D <1 2 3 4>; + link-frequencies =3D /bits/ 64 <700000000>; + remote-endpoint =3D <&csiphy2_ep>; + }; + }; + }; =20 camu_gt24p128e: eeprom@51 { compatible =3D "giantec,gt24p128e", --=20 2.55.0