From nobody Fri Oct 2 12:21:09 2026 Received: from canpmsgout07.his.huawei.com (canpmsgout07.his.huawei.com [113.46.200.222]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 099F137996C; Sat, 1 Aug 2026 09:24:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.222 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785576279; cv=none; b=rs4PWjK18moVn/lq6/qNpwSy0IcEVlpOyT6Be66nPydVvqmwS5EbkouwF0y2BofnGykv6lKVxRN9gRE541Jjf2EJ2MakheFF7NwPzn71Minj/kwe3N3JO09QuDb95TRdEsTTBPydKSQ+jOoLz3izGeFg2TMNuSZCs+aHSq47BaQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785576279; c=relaxed/simple; bh=zVNCJueQbKTwQGJWfcvsMr4+F9XrxARVLDEPzQp97IY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=lej5yVJyCTzZ6sC6YbFiL1g2Wib45KBCIgn5C88GhbLXTKj/24f4dGryeVaJC8NqiaVfTSCW+Db5z4p6p3aPhkhCOwyGllOJRjURBvWV7A5RZJiIY7UXhnsdsV4qEpygK6JPUk0NLtLbu87s7UNYYR1EeDA8aPqKu1qJIFbt2MI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b=KnR0cgim; arc=none smtp.client-ip=113.46.200.222 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b="KnR0cgim" dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=POLTv/dSyD6twt28Ah7GVbTOpw4mdCruwE8K2OjsAjk=; b=KnR0cgimq8mz/8eni2Ztl7+tofLt9gMAAssWaGhzrk+B9QRwGuwbaSdRaUEX0sKH5vAdPnJQN R4J7b3rgWthhheme1l/71yklrd3mY8Bsd70wKE7xISHjX5gtN4ZCvGgvxJLv10zTvJnFDJVPfcM xHszFCBFv4S3fWF0eJPr4JU= Received: from mail.maildlp.com (unknown [172.19.163.127]) by canpmsgout07.his.huawei.com (SkyGuard) with ESMTPS id 4hBy2G65mJzLlTg; Sat, 1 Aug 2026 17:15:02 +0800 (CST) Received: from kwepemo100012.china.huawei.com (unknown [7.202.195.139]) by mail.maildlp.com (Postfix) with ESMTPS id B003F402AB; Sat, 1 Aug 2026 17:24:31 +0800 (CST) Received: from huawei.com (10.50.163.32) by kwepemo100012.china.huawei.com (7.202.195.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.36; Sat, 1 Aug 2026 17:24:30 +0800 From: Yifan Wu To: , , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v4 1/3] selftests/resctrl: Introduce linked list management for IMC counters Date: Sat, 1 Aug 2026 17:24:27 +0800 Message-ID: <20260801092429.533956-2-wuyifan50@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20260801092429.533956-1-wuyifan50@huawei.com> References: <20260801092429.533956-1-wuyifan50@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To kwepemo100012.china.huawei.com (7.202.195.139) Content-Type: text/plain; charset="utf-8" The static array approach to managing IMC counters has fixed size constraints and limited compatibility and scalability. Introduce a linked list-based dynamic management infrastructure to address these limitations. Add the core data structure definitions and memory allocation and cleanup functions for dynamic counter configurations. Reviewed-by: Reinette Chatre Signed-off-by: Yifan Wu --- tools/testing/selftests/resctrl/mba_test.c | 1 + tools/testing/selftests/resctrl/mbm_test.c | 1 + tools/testing/selftests/resctrl/resctrl.h | 2 ++ tools/testing/selftests/resctrl/resctrl_val.c | 27 +++++++++++++++++-- 4 files changed, 29 insertions(+), 2 deletions(-) diff --git a/tools/testing/selftests/resctrl/mba_test.c b/tools/testing/sel= ftests/resctrl/mba_test.c index 39cee9898359..4bb1a82eb195 100644 --- a/tools/testing/selftests/resctrl/mba_test.c +++ b/tools/testing/selftests/resctrl/mba_test.c @@ -166,6 +166,7 @@ static int check_results(void) =20 static void mba_test_cleanup(void) { + cleanup_read_mem_bw_imc(); remove(RESULT_FILE_NAME); } =20 diff --git a/tools/testing/selftests/resctrl/mbm_test.c b/tools/testing/sel= ftests/resctrl/mbm_test.c index 6dbbc3b76003..68c89f50a34a 100644 --- a/tools/testing/selftests/resctrl/mbm_test.c +++ b/tools/testing/selftests/resctrl/mbm_test.c @@ -125,6 +125,7 @@ static int mbm_measure(const struct user_params *uparam= s, =20 static void mbm_test_cleanup(void) { + cleanup_read_mem_bw_imc(); remove(RESULT_FILE_NAME); } =20 diff --git a/tools/testing/selftests/resctrl/resctrl.h b/tools/testing/self= tests/resctrl/resctrl.h index 175101022bf3..a7556cdae0de 100644 --- a/tools/testing/selftests/resctrl/resctrl.h +++ b/tools/testing/selftests/resctrl/resctrl.h @@ -24,6 +24,7 @@ #include #include #include +#include #include "kselftest.h" =20 #define MB (1024 * 1024) @@ -183,6 +184,7 @@ void mem_flush(unsigned char *buf, size_t buf_size); void fill_cache_read(unsigned char *buf, size_t buf_size, bool once); ssize_t get_fill_buf_size(int cpu_no, const char *cache_type); int initialize_read_mem_bw_imc(void); +void cleanup_read_mem_bw_imc(void); int measure_read_mem_bw(const struct user_params *uparams, struct resctrl_val_param *param, pid_t bm_pid); void initialize_mem_bw_resctrl(const struct resctrl_val_param *param, diff --git a/tools/testing/selftests/resctrl/resctrl_val.c b/tools/testing/= selftests/resctrl/resctrl_val.c index f20d2194c35f..a72dc4ae61fe 100644 --- a/tools/testing/selftests/resctrl/resctrl_val.c +++ b/tools/testing/selftests/resctrl/resctrl_val.c @@ -28,6 +28,7 @@ struct membw_read_format { }; =20 struct imc_counter_config { + struct list_head entry; __u32 type; __u64 event; __u64 umask; @@ -38,6 +39,7 @@ struct imc_counter_config { static char mbm_total_path[1024]; static int imcs; static struct imc_counter_config imc_counters_config[MAX_IMCS]; +LIST_HEAD(imc_counters_list); static const struct resctrl_test *current_test; =20 static void read_mem_bw_initialize_perf_event_attr(int i) @@ -113,6 +115,7 @@ static int parse_imc_read_bw_events(char *imc_dir, unsi= gned int type, unsigned int *count) { char imc_events_dir[PATH_MAX], imc_counter_cfg[PATH_MAX]; + struct imc_counter_config *imc_counter; unsigned int orig_count =3D *count; char cas_count_cfg[1024]; struct dirent *ep; @@ -126,13 +129,13 @@ static int parse_imc_read_bw_events(char *imc_dir, un= signed int type, imc_dir); if (path_len >=3D sizeof(imc_events_dir)) { ksft_print_msg("Unable to create path to %sevents\n", imc_dir); - return -1; + goto out; } =20 dp =3D opendir(imc_events_dir); if (!dp) { ksft_perror("Unable to open PMU events directory"); - return -1; + goto out; } =20 while ((ep =3D readdir(dp))) { @@ -167,11 +170,17 @@ static int parse_imc_read_bw_events(char *imc_dir, un= signed int type, ksft_print_msg("Maximum iMC count exceeded\n"); goto out_close; } + imc_counter =3D calloc(1, sizeof(*imc_counter)); + if (!imc_counter) { + ksft_perror("Unable to allocate memory for iMC counters"); + goto out_close; + } =20 imc_counters_config[*count].type =3D type; get_read_event_and_umask(cas_count_cfg, *count); /* Do not fail after incrementing *count. */ *count +=3D 1; + list_add(&imc_counter->entry, &imc_counters_list); } if (*count =3D=3D orig_count) { ksft_print_msg("Unable to find events in %s\n", imc_events_dir); @@ -180,6 +189,10 @@ static int parse_imc_read_bw_events(char *imc_dir, uns= igned int type, ret =3D 0; out_close: closedir(dp); +out: + if (ret) + cleanup_read_mem_bw_imc(); + return ret; } =20 @@ -303,6 +316,16 @@ int initialize_read_mem_bw_imc(void) return 0; } =20 +void cleanup_read_mem_bw_imc(void) +{ + struct imc_counter_config *imc_counter, *tmp; + + list_for_each_entry_safe(imc_counter, tmp, &imc_counters_list, entry) { + list_del(&imc_counter->entry); + free(imc_counter); + } +} + static void perf_close_imc_read_mem_bw(void) { int mc; --=20 2.33.0 From nobody Fri Oct 2 12:21:09 2026 Received: from canpmsgout08.his.huawei.com (canpmsgout08.his.huawei.com [113.46.200.223]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4AB0737C926; Sat, 1 Aug 2026 09:24:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.223 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785576286; cv=none; b=P+zREAd7PeOzBZtHYGIrYAV5bXyYviATziHlKi0C/UcCmlW52VbKi2oWhDHl4TmWQWvrAIJIUtK1Z1gai8PrhLDkYbJCtHuPHSRXqZM1FNKHRi6lGrcqlJRzIwUbBhmjLxI7LufYJJNqqgKC6cc8uh7J7IqemxqdWdiBouB/v8U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785576286; c=relaxed/simple; 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h=From; bh=sabZ//AtpzLb7TMq3zY3IlaXl11sk1zDxBbZBnwOTU4=; b=TarxnRlK4WPRWM5o4U6EPdYYvDiAigoFHzQgzr41gmq4Xiz/jC43y8xCG4hegq86sTduPI61y chus0gFoLn5SgSLxGePwFr+xmWsFANcGK/9SgTYNwZwP1sWl37RoCR3vJzX7kNl8mdgZQ+EzWwX t254jpTZfGTKD0B/az9ig3c= Received: from mail.maildlp.com (unknown [172.19.162.92]) by canpmsgout08.his.huawei.com (SkyGuard) with ESMTPS id 4hBy2H2RJ0zmV8f; Sat, 1 Aug 2026 17:15:03 +0800 (CST) Received: from kwepemo100012.china.huawei.com (unknown [7.202.195.139]) by mail.maildlp.com (Postfix) with ESMTPS id 62C6440586; Sat, 1 Aug 2026 17:24:32 +0800 (CST) Received: from huawei.com (10.50.163.32) by kwepemo100012.china.huawei.com (7.202.195.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.36; Sat, 1 Aug 2026 17:24:31 +0800 From: Yifan Wu To: , , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v4 2/3] selftests/resctrl: Replace counter index references with pointers Date: Sat, 1 Aug 2026 17:24:28 +0800 Message-ID: <20260801092429.533956-3-wuyifan50@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20260801092429.533956-1-wuyifan50@huawei.com> References: <20260801092429.533956-1-wuyifan50@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To kwepemo100012.china.huawei.com (7.202.195.139) Content-Type: text/plain; charset="utf-8" Replace direct counter number references with pointers to remove the dependency on fixed array indexing and enable the use of different data structures for counter management. Reviewed-by: Reinette Chatre Signed-off-by: Yifan Wu --- tools/testing/selftests/resctrl/resctrl_val.c | 62 +++++++++---------- 1 file changed, 29 insertions(+), 33 deletions(-) diff --git a/tools/testing/selftests/resctrl/resctrl_val.c b/tools/testing/= selftests/resctrl/resctrl_val.c index a72dc4ae61fe..f4111da26fc2 100644 --- a/tools/testing/selftests/resctrl/resctrl_val.c +++ b/tools/testing/selftests/resctrl/resctrl_val.c @@ -42,40 +42,37 @@ static struct imc_counter_config imc_counters_config[MA= X_IMCS]; LIST_HEAD(imc_counters_list); static const struct resctrl_test *current_test; =20 -static void read_mem_bw_initialize_perf_event_attr(int i) +static void read_mem_bw_initialize_perf_event_attr(struct imc_counter_conf= ig *imc_counter) { - memset(&imc_counters_config[i].pe, 0, - sizeof(struct perf_event_attr)); - imc_counters_config[i].pe.type =3D imc_counters_config[i].type; - imc_counters_config[i].pe.size =3D sizeof(struct perf_event_attr); - imc_counters_config[i].pe.disabled =3D 1; - imc_counters_config[i].pe.inherit =3D 1; - imc_counters_config[i].pe.exclude_guest =3D 0; - imc_counters_config[i].pe.config =3D - imc_counters_config[i].umask << 8 | - imc_counters_config[i].event; - imc_counters_config[i].pe.sample_type =3D PERF_SAMPLE_IDENTIFIER; - imc_counters_config[i].pe.read_format =3D + memset(&imc_counter->pe, 0, sizeof(struct perf_event_attr)); + imc_counter->pe.type =3D imc_counter->type; + imc_counter->pe.size =3D sizeof(struct perf_event_attr); + imc_counter->pe.disabled =3D 1; + imc_counter->pe.inherit =3D 1; + imc_counter->pe.exclude_guest =3D 0; + imc_counter->pe.config =3D imc_counter->umask << 8 | imc_counter->event; + imc_counter->pe.sample_type =3D PERF_SAMPLE_IDENTIFIER; + imc_counter->pe.read_format =3D PERF_FORMAT_TOTAL_TIME_ENABLED | PERF_FORMAT_TOTAL_TIME_RUNNING; } =20 -static void read_mem_bw_ioctl_perf_event_ioc_reset_enable(int i) +static void read_mem_bw_ioctl_perf_event_ioc_reset_enable(struct imc_count= er_config *imc_counter) { - ioctl(imc_counters_config[i].fd, PERF_EVENT_IOC_RESET, 0); - ioctl(imc_counters_config[i].fd, PERF_EVENT_IOC_ENABLE, 0); + ioctl(imc_counter->fd, PERF_EVENT_IOC_RESET, 0); + ioctl(imc_counter->fd, PERF_EVENT_IOC_ENABLE, 0); } =20 -static void read_mem_bw_ioctl_perf_event_ioc_disable(int i) +static void read_mem_bw_ioctl_perf_event_ioc_disable(struct imc_counter_co= nfig *imc_counter) { - ioctl(imc_counters_config[i].fd, PERF_EVENT_IOC_DISABLE, 0); + ioctl(imc_counter->fd, PERF_EVENT_IOC_DISABLE, 0); } =20 /* * get_read_event_and_umask: Parse config into event and umask * @cas_count_cfg: Config - * @count: iMC number + * @imc_counter: iMC counter config */ -static void get_read_event_and_umask(char *cas_count_cfg, unsigned int cou= nt) +static void get_read_event_and_umask(char *cas_count_cfg, struct imc_count= er_config *imc_counter) { char *token[MAX_TOKENS]; int i =3D 0; @@ -89,21 +86,20 @@ static void get_read_event_and_umask(char *cas_count_cf= g, unsigned int count) if (!token[i]) break; if (strcmp(token[i], "event") =3D=3D 0) - imc_counters_config[count].event =3D strtol(token[i + 1], NULL, 16); + imc_counter->event =3D strtol(token[i + 1], NULL, 16); if (strcmp(token[i], "umask") =3D=3D 0) - imc_counters_config[count].umask =3D strtol(token[i + 1], NULL, 16); + imc_counter->umask =3D strtol(token[i + 1], NULL, 16); } } =20 -static int open_perf_read_event(int i, int cpu_no) +static int open_perf_read_event(int cpu_no, struct imc_counter_config *imc= _counter) { - imc_counters_config[i].fd =3D - perf_event_open(&imc_counters_config[i].pe, -1, cpu_no, -1, - PERF_FLAG_FD_CLOEXEC); + imc_counter->fd =3D perf_event_open(&imc_counter->pe, -1, cpu_no, -1, + PERF_FLAG_FD_CLOEXEC); =20 - if (imc_counters_config[i].fd =3D=3D -1) { + if (imc_counter->fd =3D=3D -1) { fprintf(stderr, "Error opening leader %llx\n", - imc_counters_config[i].pe.config); + imc_counter->pe.config); =20 return -1; } @@ -177,7 +173,7 @@ static int parse_imc_read_bw_events(char *imc_dir, unsi= gned int type, } =20 imc_counters_config[*count].type =3D type; - get_read_event_and_umask(cas_count_cfg, *count); + get_read_event_and_umask(cas_count_cfg, &imc_counters_config[*count]); /* Do not fail after incrementing *count. */ *count +=3D 1; list_add(&imc_counter->entry, &imc_counters_list); @@ -311,7 +307,7 @@ int initialize_read_mem_bw_imc(void) =20 /* Initialize perf_event_attr structures for all iMC's */ for (imc =3D 0; imc < imcs; imc++) - read_mem_bw_initialize_perf_event_attr(imc); + read_mem_bw_initialize_perf_event_attr(&imc_counters_config[imc]); =20 return 0; } @@ -350,7 +346,7 @@ static int perf_open_imc_read_mem_bw(int cpu_no) imc_counters_config[imc].fd =3D -1; =20 for (imc =3D 0; imc < imcs; imc++) { - ret =3D open_perf_read_event(imc, cpu_no); + ret =3D open_perf_read_event(cpu_no, &imc_counters_config[imc]); if (ret) goto close_fds; } @@ -373,13 +369,13 @@ static void do_imc_read_mem_bw_test(void) int imc; =20 for (imc =3D 0; imc < imcs; imc++) - read_mem_bw_ioctl_perf_event_ioc_reset_enable(imc); + read_mem_bw_ioctl_perf_event_ioc_reset_enable(&imc_counters_config[imc]); =20 sleep(1); =20 /* Stop counters after a second to get results. */ for (imc =3D 0; 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charset="utf-8" Remove the static array and the count and upper limit checks during initialization, allowing the system to dynamically use all available IMC counters detected by hardware. Reviewed-by: Reinette Chatre Signed-off-by: Yifan Wu --- tools/testing/selftests/resctrl/resctrl_val.c | 94 ++++++++----------- 1 file changed, 41 insertions(+), 53 deletions(-) diff --git a/tools/testing/selftests/resctrl/resctrl_val.c b/tools/testing/= selftests/resctrl/resctrl_val.c index f4111da26fc2..7e7d0f9cc249 100644 --- a/tools/testing/selftests/resctrl/resctrl_val.c +++ b/tools/testing/selftests/resctrl/resctrl_val.c @@ -14,7 +14,6 @@ #define READ_FILE_NAME "cas_count_read" #define DYN_PMU_PATH "/sys/bus/event_source/devices" #define SCALE 0.00006103515625 -#define MAX_IMCS 40 #define MAX_TOKENS 5 =20 #define CON_MBM_LOCAL_BYTES_PATH \ @@ -37,8 +36,6 @@ struct imc_counter_config { }; =20 static char mbm_total_path[1024]; -static int imcs; -static struct imc_counter_config imc_counters_config[MAX_IMCS]; LIST_HEAD(imc_counters_list); static const struct resctrl_test *current_test; =20 @@ -107,12 +104,11 @@ static int open_perf_read_event(int cpu_no, struct im= c_counter_config *imc_count return 0; } =20 -static int parse_imc_read_bw_events(char *imc_dir, unsigned int type, - unsigned int *count) +static int parse_imc_read_bw_events(char *imc_dir, unsigned int type) { char imc_events_dir[PATH_MAX], imc_counter_cfg[PATH_MAX]; struct imc_counter_config *imc_counter; - unsigned int orig_count =3D *count; + bool found_event =3D false; char cas_count_cfg[1024]; struct dirent *ep; int path_len; @@ -162,23 +158,18 @@ static int parse_imc_read_bw_events(char *imc_dir, un= signed int type, ksft_perror("Could not get iMC cas count read"); goto out_close; } - if (*count >=3D MAX_IMCS) { - ksft_print_msg("Maximum iMC count exceeded\n"); - goto out_close; - } imc_counter =3D calloc(1, sizeof(*imc_counter)); if (!imc_counter) { ksft_perror("Unable to allocate memory for iMC counters"); goto out_close; } =20 - imc_counters_config[*count].type =3D type; - get_read_event_and_umask(cas_count_cfg, &imc_counters_config[*count]); - /* Do not fail after incrementing *count. */ - *count +=3D 1; + imc_counter->type =3D type; + get_read_event_and_umask(cas_count_cfg, imc_counter); list_add(&imc_counter->entry, &imc_counters_list); + found_event =3D true; } - if (*count =3D=3D orig_count) { + if (!found_event) { ksft_print_msg("Unable to find events in %s\n", imc_events_dir); goto out_close; } @@ -193,7 +184,7 @@ static int parse_imc_read_bw_events(char *imc_dir, unsi= gned int type, } =20 /* Get type and config of an iMC counter's read event. */ -static int read_from_imc_dir(char *imc_dir, unsigned int *count) +static int read_from_imc_dir(char *imc_dir) { char imc_counter_type[PATH_MAX]; unsigned int type; @@ -221,7 +212,7 @@ static int read_from_imc_dir(char *imc_dir, unsigned in= t *count) ksft_perror("Could not get iMC type"); return -1; } - ret =3D parse_imc_read_bw_events(imc_dir, type, count); + ret =3D parse_imc_read_bw_events(imc_dir, type); if (ret) { ksft_print_msg("Unable to parse bandwidth event and umask\n"); return ret; @@ -231,21 +222,18 @@ static int read_from_imc_dir(char *imc_dir, unsigned = int *count) } =20 /* - * A system can have 'n' number of iMC (Integrated Memory Controller) - * counters, get that 'n'. Discover the properties of the available - * counters in support of needed performance measurement via perf. - * For each iMC counter get it's type and config. Also obtain each - * counter's event and umask for the memory read events that will be - * measured. + * Discover the properties of the available iMC (Integrated Memory Control= ler) + * counters in support of needed performance measurement via perf. For eac= h iMC + * counter get it's type and config. Also obtain each counter's event and = umask + * for the memory read events that will be measured. * - * Enumerate all these details into an array of structures. + * Enumerate all these details into a linked list of structures. * * Return: >=3D 0 on success. < 0 on failure. */ -static int num_of_imcs(void) +static int enumerate_imcs(void) { char imc_dir[512], *temp; - unsigned int count =3D 0; struct dirent *ep; int ret; DIR *dp; @@ -274,7 +262,7 @@ static int num_of_imcs(void) if (temp[0] >=3D '0' && temp[0] <=3D '9') { sprintf(imc_dir, "%s/%s/", DYN_PMU_PATH, ep->d_name); - ret =3D read_from_imc_dir(imc_dir, &count); + ret =3D read_from_imc_dir(imc_dir); if (ret) { closedir(dp); =20 @@ -283,7 +271,7 @@ static int num_of_imcs(void) } } closedir(dp); - if (count =3D=3D 0) { + if (list_empty(&imc_counters_list)) { ksft_print_msg("Unable to find iMC counters\n"); =20 return -1; @@ -294,20 +282,21 @@ static int num_of_imcs(void) return -1; } =20 - return count; + return 0; } =20 int initialize_read_mem_bw_imc(void) { - int imc; + struct imc_counter_config *imc_counter; + int ret; =20 - imcs =3D num_of_imcs(); - if (imcs <=3D 0) - return imcs; + ret =3D enumerate_imcs(); + if (ret < 0) + return ret; =20 /* Initialize perf_event_attr structures for all iMC's */ - for (imc =3D 0; imc < imcs; imc++) - read_mem_bw_initialize_perf_event_attr(&imc_counters_config[imc]); + list_for_each_entry(imc_counter, &imc_counters_list, entry) + read_mem_bw_initialize_perf_event_attr(imc_counter); =20 return 0; } @@ -324,11 +313,11 @@ void cleanup_read_mem_bw_imc(void) =20 static void perf_close_imc_read_mem_bw(void) { - int mc; + struct imc_counter_config *imc_counter; =20 - for (mc =3D 0; mc < imcs; mc++) { - if (imc_counters_config[mc].fd !=3D -1) - close(imc_counters_config[mc].fd); + list_for_each_entry(imc_counter, &imc_counters_list, entry) { + if (imc_counter->fd !=3D -1) + close(imc_counter->fd); } } =20 @@ -340,13 +329,14 @@ static void perf_close_imc_read_mem_bw(void) */ static int perf_open_imc_read_mem_bw(int cpu_no) { - int imc, ret; + struct imc_counter_config *imc_counter; + int ret; =20 - for (imc =3D 0; imc < imcs; imc++) - imc_counters_config[imc].fd =3D -1; + list_for_each_entry(imc_counter, &imc_counters_list, entry) + imc_counter->fd =3D -1; =20 - for (imc =3D 0; imc < imcs; imc++) { - ret =3D open_perf_read_event(cpu_no, &imc_counters_config[imc]); + list_for_each_entry(imc_counter, &imc_counters_list, entry) { + ret =3D open_perf_read_event(cpu_no, imc_counter); if (ret) goto close_fds; } @@ -366,16 +356,16 @@ static int perf_open_imc_read_mem_bw(int cpu_no) */ static void do_imc_read_mem_bw_test(void) { - int imc; + struct imc_counter_config *imc_counter; =20 - for (imc =3D 0; imc < imcs; imc++) - read_mem_bw_ioctl_perf_event_ioc_reset_enable(&imc_counters_config[imc]); + list_for_each_entry(imc_counter, &imc_counters_list, entry) + read_mem_bw_ioctl_perf_event_ioc_reset_enable(imc_counter); =20 sleep(1); =20 /* Stop counters after a second to get results. */ - for (imc =3D 0; imc < imcs; imc++) - read_mem_bw_ioctl_perf_event_ioc_disable(&imc_counters_config[imc]); + list_for_each_entry(imc_counter, &imc_counters_list, entry) + read_mem_bw_ioctl_perf_event_ioc_disable(imc_counter); } =20 /* @@ -390,17 +380,15 @@ static void do_imc_read_mem_bw_test(void) static int get_read_mem_bw_imc(float *bw_imc) { float reads =3D 0, of_mul_read =3D 1; - int imc; + struct imc_counter_config *r; =20 /* * Log read event values from all iMC counters into * struct imc_counter_config. * Take overflow into consideration before calculating total bandwidth. */ - for (imc =3D 0; imc < imcs; imc++) { + list_for_each_entry(r, &imc_counters_list, entry) { struct membw_read_format measurement; - struct imc_counter_config *r =3D - &imc_counters_config[imc]; =20 if (read(r->fd, &measurement, sizeof(measurement)) =3D=3D -1) { ksft_perror("Couldn't get read bandwidth through iMC"); --=20 2.33.0