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Hence add these clock resets. Fixes: 06498d59bb4e ("dt-bindings: clock: qcom: Add Nord Global Clock Contr= oller") Signed-off-by: Taniya Das Acked-by: Krzysztof Kozlowski --- include/dt-bindings/clock/qcom,nord-nwgcc.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/dt-bindings/clock/qcom,nord-nwgcc.h b/include/dt-bindi= ngs/clock/qcom,nord-nwgcc.h index b6253dd2aa85a3152f99447a60a6f8a3e85d8f3c..8beaa129aa814c82470deee4382= de5bdf8177892 100644 --- a/include/dt-bindings/clock/qcom,nord-nwgcc.h +++ b/include/dt-bindings/clock/qcom,nord-nwgcc.h @@ -65,5 +65,8 @@ #define NW_GCC_GPU_2_BCR 6 #define NW_GCC_GPU_BCR 7 #define NW_GCC_VIDEO_BCR 8 +#define NW_GCC_VIDEO_AXI0_CLK_ARES 9 +#define NW_GCC_VIDEO_AXI0C_CLK_ARES 10 +#define NW_GCC_VIDEO_AXI1_CLK_ARES 11 =20 #endif --=20 2.34.1 From nobody Fri Oct 2 11:44:01 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37C6F2F7EE8 for ; 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Hence add these clock resets. Fixes: a4f780cd5c7a ("clk: qcom: gcc: Add multiple global clock controller = driver for Nord SoC") Signed-off-by: Taniya Das Reviewed-by: Abel Vesa Reviewed-by: Dmitry Baryshkov --- drivers/clk/qcom/nwgcc-nord.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/qcom/nwgcc-nord.c b/drivers/clk/qcom/nwgcc-nord.c index e061c0623e9a468b87153f1b0ccf2e2c9e06ad19..280558f15748c95cfb373c09141= b3023d7fcec5c 100644 --- a/drivers/clk/qcom/nwgcc-nord.c +++ b/drivers/clk/qcom/nwgcc-nord.c @@ -623,6 +623,9 @@ static const struct qcom_reset_map nw_gcc_nord_resets[]= =3D { [NW_GCC_GPU_2_BCR] =3D { 0x24000 }, [NW_GCC_GPU_BCR] =3D { 0x23000 }, [NW_GCC_VIDEO_BCR] =3D { 0x1a000 }, + [NW_GCC_VIDEO_AXI0_CLK_ARES] =3D { 0x1a008, 2 }, + [NW_GCC_VIDEO_AXI0C_CLK_ARES] =3D { 0x1a01c, 2 }, + [NW_GCC_VIDEO_AXI1_CLK_ARES] =3D { 0x1a030, 2 }, }; =20 static const u32 nw_gcc_nord_critical_cbcrs[] =3D { --=20 2.34.1 From nobody Fri Oct 2 11:44:01 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B23E2931F3 for ; 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Signed-off-by: Taniya Das Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.ya= ml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml index 1e1fec1cd7ce96f103348baf85341e775fac690a..65620a656600ff61afdfc22b667= 5f5a46651bd26 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml @@ -18,6 +18,7 @@ description: | include/dt-bindings/clock/qcom,glymur-videocc.h include/dt-bindings/clock/qcom,hawi-videocc.h include/dt-bindings/clock/qcom,kaanapali-videocc.h + include/dt-bindings/clock/qcom,nord-videocc.h include/dt-bindings/clock/qcom,sm8450-videocc.h include/dt-bindings/clock/qcom,sm8650-videocc.h include/dt-bindings/clock/qcom,sm8750-videocc.h @@ -29,6 +30,7 @@ properties: - qcom,glymur-videocc - qcom,hawi-videocc - qcom,kaanapali-videocc + - qcom,nord-videocc - qcom,sm8450-videocc - qcom,sm8475-videocc - qcom,sm8550-videocc --=20 2.34.1 From nobody Fri Oct 2 11:44:01 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37416315D49 for ; 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Sat, 01 Aug 2026 07:14:24 -0700 (PDT) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-13fab4e506csm13570696c88.13.2026.08.01.07.14.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Aug 2026 07:14:24 -0700 (PDT) From: Taniya Das Date: Sat, 01 Aug 2026 19:43:55 +0530 Subject: [PATCH v2 4/6] dt-bindings: clock: qcom: Add support for Camera Clock Controller for Nord Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260801-nord_videocc_camcc-v2-4-674d7718e41f@oss.qualcomm.com> References: <20260801-nord_videocc_camcc-v2-0-674d7718e41f@oss.qualcomm.com> In-Reply-To: <20260801-nord_videocc_camcc-v2-0-674d7718e41f@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jagadeesh Kona , Vladimir Zapolskiy Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODAxMDExNCBTYWx0ZWRfXxNrmxmG8l9cm nZ8Tbq3u9mvw3NgTCQS+lBpH5GvqwyXoJIGNHb8omxlFegbySggC53qOp6eKibEHM6tWMNlNf9V 0OEx8ibvToEVgVWTGyKikDtOQhiaH5ZcRzUIosB9MeOElggIoUeVW03bA4Stt+SLraiLBPvHqBB cjXUGQyEZJLijQAMR+wosLygDz76VIyg3y+YnhhfcCpkhoajozsKTF4ynn4LTA77EUnJvWRHK97 f1HGYBXjeuUX4K7F8Q2o0LiRDKg5tMSGBiIlmu8keb7AWu05hmOnaKQt1uxIzb7F50N0LevLv2X twEc14I2UG7yXjgXTpNeA13gxh88ehgmlUOy524txLhcax/h0VcQ7XaCtIevCoEJ5IUosRa2okv Nd1IGIy8To1nrglSUWCjqR0Wu8FYTg8Kv0SpzwmOG1i+zivJM5g57PTJ03OiOoVY7kfpzbGwEnR RKCLdSAdMAYDRUhhuDw== X-Proofpoint-GUID: 6bGUM8U54rA_CU1Ijgrm075MQz-7NADL X-Authority-Analysis: v=2.4 cv=T9C8ifKQ c=1 sm=1 tr=0 ts=6a6dff42 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=npxppRvg8dUom-5OBigA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwODAxMDExNCBTYWx0ZWRfXzxzqR19F+8aO YEHuTV6XF0IQM6D/Suu40sU+UkAxqwOrR5LOwOcHn5ef2r++/OcpOp6sL1H1hpj0QsRKn2RIkmh iIRFZ+UmShqoT3lBmIaT5/TUg9b+35s= X-Proofpoint-ORIG-GUID: 6bGUM8U54rA_CU1Ijgrm075MQz-7NADL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-01_01,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 adultscore=0 suspectscore=0 spamscore=0 malwarescore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608010114 Update the compatible and the bindings for CAMCC support on Nord SoC. Signed-off-by: Taniya Das Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/qcom,sm8450-camcc.yaml | 2 + include/dt-bindings/clock/qcom,nord-camcc.h | 167 +++++++++++++++++= ++++ 2 files changed, 169 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml= b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml index b41247b257b193ce1a70e7100b2f88880f9d9bc5..f653807472201e731f9bea43e2c= 8ab781d817430 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml @@ -18,6 +18,7 @@ description: | See also: include/dt-bindings/clock/qcom,kaanapali-camcc.h include/dt-bindings/clock/qcom,kaanapali-cambistmclkcc.h + include/dt-bindings/clock/qcom,nord-camcc.h include/dt-bindings/clock/qcom,sm8450-camcc.h include/dt-bindings/clock/qcom,sm8550-camcc.h include/dt-bindings/clock/qcom,sm8650-camcc.h @@ -29,6 +30,7 @@ properties: enum: - qcom,kaanapali-cambistmclkcc - qcom,kaanapali-camcc + - qcom,nord-camcc - qcom,sm8450-camcc - qcom,sm8475-camcc - qcom,sm8550-camcc diff --git a/include/dt-bindings/clock/qcom,nord-camcc.h b/include/dt-bindi= ngs/clock/qcom,nord-camcc.h new file mode 100644 index 0000000000000000000000000000000000000000..655fef2084a580cdaabf8870a20= 9b32b604c8af0 --- /dev/null +++ b/include/dt-bindings/clock/qcom,nord-camcc.h @@ -0,0 +1,167 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_NORD_H +#define _DT_BINDINGS_CLK_QCOM_CAM_CC_NORD_H + +/* CAM_CC clocks */ +#define CAM_CC_CAMNOC_DCD_XO_CLK 0 +#define CAM_CC_CAMNOC_NRT_AXI_CLK 1 +#define CAM_CC_CAMNOC_RT_AXI_CLK 2 +#define CAM_CC_CAMNOC_RT_AXI_CLK_SRC 3 +#define CAM_CC_CAMNOC_XO_CLK 4 +#define CAM_CC_CCI_0_CLK 5 +#define CAM_CC_CCI_0_CLK_SRC 6 +#define CAM_CC_CCI_1_CLK 7 +#define CAM_CC_CCI_1_CLK_SRC 8 +#define CAM_CC_CCI_2_CLK 9 +#define CAM_CC_CCI_2_CLK_SRC 10 +#define CAM_CC_CCI_3_CLK 11 +#define CAM_CC_CCI_3_CLK_SRC 12 +#define CAM_CC_CCI_4_CLK 13 +#define CAM_CC_CCI_4_CLK_SRC 14 +#define CAM_CC_CCU_FAST_AHB_CLK 15 +#define CAM_CC_CORE_AHB_CLK 16 +#define CAM_CC_CPHY_RX_CLK_SRC 17 +#define CAM_CC_CSI0PHYTIMER_CLK 18 +#define CAM_CC_CSI0PHYTIMER_CLK_SRC 19 +#define CAM_CC_CSI1PHYTIMER_CLK 20 +#define CAM_CC_CSI1PHYTIMER_CLK_SRC 21 +#define CAM_CC_CSI2PHYTIMER_CLK 22 +#define CAM_CC_CSI2PHYTIMER_CLK_SRC 23 +#define CAM_CC_CSI3PHYTIMER_CLK 24 +#define CAM_CC_CSI3PHYTIMER_CLK_SRC 25 +#define CAM_CC_CSI4PHYTIMER_CLK 26 +#define CAM_CC_CSI4PHYTIMER_CLK_SRC 27 +#define CAM_CC_CSID_CLK 28 +#define CAM_CC_CSID_CLK_SRC 29 +#define CAM_CC_CSID_CSIPHY_RX_CLK 30 +#define CAM_CC_CSIPHY0_CLK 31 +#define CAM_CC_CSIPHY1_CLK 32 +#define CAM_CC_CSIPHY2_CLK 33 +#define CAM_CC_CSIPHY3_CLK 34 +#define CAM_CC_CSIPHY4_CLK 35 +#define CAM_CC_FAST_AHB_CLK_SRC 36 +#define CAM_CC_GDSC_CLK 37 +#define CAM_CC_ICP_0_AHB_CLK 38 +#define CAM_CC_ICP_0_CLK 39 +#define CAM_CC_ICP_0_CLK_SRC 40 +#define CAM_CC_ICP_1_AHB_CLK 41 +#define CAM_CC_ICP_1_CLK 42 +#define CAM_CC_ICP_1_CLK_SRC 43 +#define CAM_CC_IFE_0_MAIN_CLK 44 +#define CAM_CC_IFE_0_MAIN_CLK_SRC 45 +#define CAM_CC_IFE_0_MAIN_FAST_AHB_CLK 46 +#define CAM_CC_IFE_0_PCP_CLK 47 +#define CAM_CC_IFE_0_PCP_FAST_AHB_CLK 48 +#define CAM_CC_IFE_0_SCALAR_CLK 49 +#define CAM_CC_IFE_0_SCALAR_FAST_AHB_CLK 50 +#define CAM_CC_IFE_0_TMC_CLK 51 +#define CAM_CC_IFE_0_TMC_FAST_AHB_CLK 52 +#define CAM_CC_IFE_1_MAIN_CLK 53 +#define CAM_CC_IFE_1_MAIN_CLK_SRC 54 +#define CAM_CC_IFE_1_MAIN_FAST_AHB_CLK 55 +#define CAM_CC_IFE_1_PCP_CLK 56 +#define CAM_CC_IFE_1_PCP_FAST_AHB_CLK 57 +#define CAM_CC_IFE_1_SCALAR_CLK 58 +#define CAM_CC_IFE_1_SCALAR_FAST_AHB_CLK 59 +#define CAM_CC_IFE_1_TMC_CLK 60 +#define CAM_CC_IFE_1_TMC_FAST_AHB_CLK 61 +#define CAM_CC_IFE_2_MAIN_CLK 62 +#define CAM_CC_IFE_2_MAIN_CLK_SRC 63 +#define CAM_CC_IFE_2_MAIN_FAST_AHB_CLK 64 +#define CAM_CC_IFE_2_PCP_CLK 65 +#define CAM_CC_IFE_2_PCP_FAST_AHB_CLK 66 +#define CAM_CC_IFE_2_SCALAR_CLK 67 +#define CAM_CC_IFE_2_SCALAR_FAST_AHB_CLK 68 +#define CAM_CC_IFE_2_TMC_CLK 69 +#define CAM_CC_IFE_2_TMC_FAST_AHB_CLK 70 +#define CAM_CC_IFE_LITE_AHB_CLK 71 +#define CAM_CC_IFE_LITE_CLK 72 +#define CAM_CC_IFE_LITE_CLK_SRC 73 +#define CAM_CC_IFE_LITE_CPHY_RX_CLK 74 +#define CAM_CC_IFE_LITE_CSID_CLK 75 +#define CAM_CC_IFE_LITE_CSID_CLK_SRC 76 +#define CAM_CC_IPE_0_AHB_CLK 77 +#define CAM_CC_IPE_0_CLK 78 +#define CAM_CC_IPE_0_CLK_SRC 79 +#define CAM_CC_IPE_0_FAST_AHB_CLK 80 +#define CAM_CC_IPE_1_AHB_CLK 81 +#define CAM_CC_IPE_1_CLK 82 +#define CAM_CC_IPE_1_CLK_SRC 83 +#define CAM_CC_IPE_1_FAST_AHB_CLK 84 +#define CAM_CC_PLL0 85 +#define CAM_CC_PLL0_OUT_EVEN 86 +#define CAM_CC_PLL0_OUT_ODD 87 +#define CAM_CC_PLL2 88 +#define CAM_CC_PLL2_OUT_EVEN 89 +#define CAM_CC_PLL3 90 +#define CAM_CC_PLL3_OUT_EVEN 91 +#define CAM_CC_PLL4 92 +#define CAM_CC_PLL4_OUT_EVEN 93 +#define CAM_CC_PLL5 94 +#define CAM_CC_PLL5_OUT_EVEN 95 +#define CAM_CC_PLL6 96 +#define CAM_CC_PLL6_OUT_EVEN 97 +#define CAM_CC_QDSS_DEBUG_CLK 98 +#define CAM_CC_QDSS_DEBUG_CLK_SRC 99 +#define CAM_CC_QDSS_DEBUG_XO_CLK 100 +#define CAM_CC_QUP_AHBM_CLK 101 +#define CAM_CC_QUP_AHBM_CLK_SRC 102 +#define CAM_CC_QUP_CORE_2X_CLK 103 +#define CAM_CC_QUP_CORE_2X_CLK_SRC 104 +#define CAM_CC_QUP_CORE_2X_DIV_CLK_SRC 105 +#define CAM_CC_QUP_CORE_CLK 106 +#define CAM_CC_QUP_SE_CLK 107 +#define CAM_CC_QUP_SE_CLK_SRC 108 +#define CAM_CC_QUP_SLEEP_CLK 109 +#define CAM_CC_SFE_LITE_0_CLK 110 +#define CAM_CC_SFE_LITE_0_FAST_AHB_CLK 111 +#define CAM_CC_SFE_LITE_1_CLK 112 +#define CAM_CC_SFE_LITE_1_FAST_AHB_CLK 113 +#define CAM_CC_SFE_LITE_2_CLK 114 +#define CAM_CC_SFE_LITE_2_FAST_AHB_CLK 115 +#define CAM_CC_SLEEP_CLK 116 +#define CAM_CC_SLEEP_CLK_SRC 117 +#define CAM_CC_SLOW_AHB_CLK_SRC 118 +#define CAM_CC_SM_OBS_CLK 119 +#define CAM_CC_TOP_AHB_CLK 120 +#define CAM_CC_TOP_FAST_AHB_CLK 121 +#define CAM_CC_TOP_IFE_0_CLK 122 +#define CAM_CC_TOP_IFE_1_CLK 123 +#define CAM_CC_TOP_IFE_2_CLK 124 +#define CAM_CC_TOP_IFE_LITE_CLK 125 +#define CAM_CC_TOP_IPE_0_CLK 126 +#define CAM_CC_TOP_IPE_1_CLK 127 +#define CAM_CC_TOP_QUP_AHBM_CLK 128 +#define CAM_CC_TOP_SFE_LITE_0_CLK 129 +#define CAM_CC_TOP_SFE_LITE_1_CLK 130 +#define CAM_CC_TOP_SFE_LITE_2_CLK 131 +#define CAM_CC_TPG_CSIPHY_RX_CLK 132 +#define CAM_CC_XO_CLK_SRC 133 + +/* CAM_CC power domains */ +#define CAM_CC_IFE_0_GDSC 0 +#define CAM_CC_IFE_1_GDSC 1 +#define CAM_CC_IFE_2_GDSC 2 +#define CAM_CC_IPE_0_GDSC 3 +#define CAM_CC_IPE_1_GDSC 4 +#define CAM_CC_TITAN_TOP_GDSC 5 + +/* CAM_CC resets */ +#define CAM_CC_CCU_BCR 0 +#define CAM_CC_ICP_0_BCR 1 +#define CAM_CC_ICP_1_BCR 2 +#define CAM_CC_IFE_0_BCR 3 +#define CAM_CC_IFE_1_BCR 4 +#define CAM_CC_IFE_2_BCR 5 +#define CAM_CC_IPE_0_BCR 6 +#define CAM_CC_IPE_1_BCR 7 +#define CAM_CC_QDSS_DEBUG_BCR 8 +#define CAM_CC_SFE_LITE_0_BCR 9 +#define CAM_CC_SFE_LITE_1_BCR 10 +#define CAM_CC_SFE_LITE_2_BCR 11 + +#endif --=20 2.34.1 From nobody Fri Oct 2 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2026 19:43:56 +0530 Subject: [PATCH v2 5/6] clk: qcom: videocc-glymur: Add video clock controller support for Nord Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260801-nord_videocc_camcc-v2-5-674d7718e41f@oss.qualcomm.com> References: <20260801-nord_videocc_camcc-v2-0-674d7718e41f@oss.qualcomm.com> In-Reply-To: <20260801-nord_videocc_camcc-v2-0-674d7718e41f@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jagadeesh Kona , Vladimir Zapolskiy Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Taniya Das , Konrad Dybcio X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-ORIG-GUID: q7ojbeBfxHlpin4L3AwZf4YSVs6c920H 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AW1haW4tMjYwODAxMDExNCBTYWx0ZWRfX3UrZ3CSDI8kH b2FUUmK7HNHi4lMWZv4tTBuGGW8CS1WFGxbgeMRMi+7Lng2P4wW5jeByTdN28HfHnU5LSvgy26O p078BwEE2eijZVMIYZmpw85rspvt4vo= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-01_01,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 phishscore=0 spamscore=0 clxscore=1015 suspectscore=0 malwarescore=0 adultscore=0 bulkscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608010114 Nord shares the video clock controller topology with Glymur, differing only in the PLL0 hardware (Lucid-OLE vs Taycan-EKO-T) and the MVS0 frequency table. Extend the existing Glymur video clock controller driver to also probe on the qcom,nord-videocc compatible, switching to the Nord PLL configuration, VCO table, and MVS0 frequency table at probe time. Reviewed-by: Konrad Dybcio Signed-off-by: Taniya Das --- drivers/clk/qcom/Kconfig | 11 +++++++++++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/videocc-glymur.c | 38 +++++++++++++++++++++++++++++++++++= +++ 3 files changed, 50 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 63f271aff1771bea0885fb753dd28d02fd7d4ab6..a5c7faa4dcca1cf7c096ed5c3e1= 6bd1761c46506 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -192,6 +192,17 @@ config CLK_NORD_GCC SPI, I2C, USB, SD/UFS, PCIe etc. The clock controller is a combination of GCC, SE_GCC, NE_GCC and NW_GCC. =20 +config CLK_NORD_VIDEOCC + tristate "Nord VIDEO Clock Controller" + depends on ARM64 || COMPILE_TEST + select CLK_NORD_GCC + default m if ARCH_QCOM + help + Support for the video clock controller on Qualcomm Technologies, Inc. + Nord devices. + Say Y if you want to support video devices and functionality such as + video encode/decode. + config CLK_SHIKRA_GCC tristate "Shikra Global Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index fff069da16deb64311b7e9bdfab4248a706f6b0b..8dbca24fafd012cde3c25993a92= 5b756a9b83608 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -43,6 +43,7 @@ obj-$(CONFIG_CLK_KAANAPALI_TCSRCC) +=3D tcsrcc-kaanapali.o obj-$(CONFIG_CLK_KAANAPALI_VIDEOCC) +=3D videocc-kaanapali.o obj-$(CONFIG_CLK_NORD_GCC) +=3D gcc-nord.o negcc-nord.o nwgcc-nord.o segcc= -nord.o obj-$(CONFIG_CLK_NORD_TCSRCC) +=3D tcsrcc-nord.o +obj-$(CONFIG_CLK_NORD_VIDEOCC) +=3D videocc-glymur.o obj-$(CONFIG_CLK_SHIKRA_GCC) +=3D gcc-shikra.o obj-$(CONFIG_CLK_X1E80100_CAMCC) +=3D camcc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_DISPCC) +=3D dispcc-x1e80100.o diff --git a/drivers/clk/qcom/videocc-glymur.c b/drivers/clk/qcom/videocc-g= lymur.c index 18313a65e78d95426a436c94ddf2b26307d6fa80..2776140de3555d27b388d4235d0= 530523b8f8590 100644 --- a/drivers/clk/qcom/videocc-glymur.c +++ b/drivers/clk/qcom/videocc-glymur.c @@ -37,6 +37,10 @@ static const struct pll_vco taycan_eko_t_vco[] =3D { { 249600000, 2500000000, 0 }, }; =20 +static const struct pll_vco lucid_ole_vco[] =3D { + { 249600000, 2300000000, 0 }, +}; + /* 720.0 MHz Configuration */ static const struct alpha_pll_config video_cc_pll0_config =3D { .l =3D 0x25, @@ -48,6 +52,21 @@ static const struct alpha_pll_config video_cc_pll0_confi= g =3D { .user_ctl_hi_val =3D 0x00000002, }; =20 +/* 720.0 MHz Configuration */ +static const struct alpha_pll_config video_cc_pll0_config_nord =3D { + .l =3D 0x25, + .alpha =3D 0x8000, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x82aa299c, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x00000003, + .test_ctl_hi1_val =3D 0x00009000, + .test_ctl_hi2_val =3D 0x00000034, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00400005, +}; + static struct clk_alpha_pll video_cc_pll0 =3D { .offset =3D 0x0, .config =3D &video_cc_pll0_config, @@ -112,6 +131,15 @@ static struct clk_rcg2 video_cc_ahb_clk_src =3D { }, }; =20 +static const struct freq_tbl ftbl_video_cc_mvs0_clk_src_nord[] =3D { + F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1305000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1440000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1600000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1680000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + { } +}; 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Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Taniya Das --- drivers/clk/qcom/Kconfig | 11 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/camcc-nord.c | 2941 +++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 2953 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index a5c7faa4dcca1cf7c096ed5c3e16bd1761c46506..809a1300114fc6d75ee438abc38= 04a1d0d2b155c 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -181,6 +181,17 @@ config CLK_KAANAPALI_VIDEOCC Say Y if you want to support video devices and functionality such as video encode/decode. =20 +config CLK_NORD_CAMCC + tristate "Nord Camera Clock Controller" + depends on ARM64 || COMPILE_TEST + select CLK_NORD_GCC + default m if ARCH_QCOM + help + Support for the camera clock controller on Qualcomm Technologies, Inc + Nord devices. + Say Y if you want to support camera devices and functionality such as + capturing pictures. + config CLK_NORD_GCC tristate "Nord Global Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 8dbca24fafd012cde3c25993a925b756a9b83608..2fb687302ab77fe1f54d9c8e81f= acd6902ff756a 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -41,6 +41,7 @@ obj-$(CONFIG_CLK_KAANAPALI_GCC) +=3D gcc-kaanapali.o obj-$(CONFIG_CLK_KAANAPALI_GPUCC) +=3D gpucc-kaanapali.o gxclkctl-kaanapal= i.o obj-$(CONFIG_CLK_KAANAPALI_TCSRCC) +=3D tcsrcc-kaanapali.o obj-$(CONFIG_CLK_KAANAPALI_VIDEOCC) +=3D videocc-kaanapali.o +obj-$(CONFIG_CLK_NORD_CAMCC) +=3D camcc-nord.o obj-$(CONFIG_CLK_NORD_GCC) +=3D gcc-nord.o negcc-nord.o nwgcc-nord.o segcc= -nord.o obj-$(CONFIG_CLK_NORD_TCSRCC) +=3D tcsrcc-nord.o obj-$(CONFIG_CLK_NORD_VIDEOCC) +=3D videocc-glymur.o diff --git a/drivers/clk/qcom/camcc-nord.c b/drivers/clk/qcom/camcc-nord.c new file mode 100644 index 0000000000000000000000000000000000000000..9e3c40cb3ad5f06196bab87593a= fb7d1c7da411d --- /dev/null +++ b/drivers/clk/qcom/camcc-nord.c @@ -0,0 +1,2941 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_IFACE, + DT_BI_TCXO, + DT_BI_TCXO_AO, + DT_SLEEP_CLK +}; + +enum { + P_BI_TCXO, + P_CAM_CC_PLL0_OUT_EVEN, + P_CAM_CC_PLL0_OUT_MAIN, + P_CAM_CC_PLL0_OUT_ODD, + P_CAM_CC_PLL2_OUT_EVEN, + P_CAM_CC_PLL3_OUT_EVEN, + P_CAM_CC_PLL4_OUT_EVEN, + P_CAM_CC_PLL5_OUT_EVEN, + P_CAM_CC_PLL6_OUT_EVEN, + P_SLEEP_CLK, +}; + +static const struct pll_vco lucid_ole_vco[] =3D { + { 249600000, 2300000000, 0 }, +}; + +/* 1200.0 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll0_config =3D { + .l =3D 0x3e, + .alpha =3D 0x8000, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x82aa299c, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x00000003, + .test_ctl_hi1_val =3D 0x00009000, + .test_ctl_hi2_val =3D 0x00000034, + .user_ctl_val =3D 0x00008400, + .user_ctl_hi_val =3D 0x00400005, +}; + +static struct clk_alpha_pll cam_cc_pll0 =3D { + .offset =3D 0x0, + .config =3D &cam_cc_pll0_config, + .vco_table =3D lucid_ole_vco, + .num_vco =3D ARRAY_SIZE(lucid_ole_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO_AO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even =3D { + .offset =3D 0x0, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_cam_cc_pll0_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll0_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_pll0.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_lucid_evo_ops, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] =3D= { + { 0x2, 3 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd =3D { + .offset =3D 0x0, + .post_div_shift =3D 14, + .post_div_table =3D post_div_table_cam_cc_pll0_out_odd, + .num_post_div =3D ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll0_out_odd", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_pll0.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_lucid_evo_ops, + }, +}; + +/* 720.0 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll2_config =3D { + .l =3D 0x25, + .alpha =3D 0x8000, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x82aa299c, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x00000003, + .test_ctl_hi1_val =3D 0x00009000, + .test_ctl_hi2_val =3D 0x00000034, + .user_ctl_val =3D 0x00000400, + .user_ctl_hi_val =3D 0x00400005, +}; + +static struct clk_alpha_pll cam_cc_pll2 =3D { + .offset =3D 0x2000, + .config =3D &cam_cc_pll2_config, + .vco_table =3D lucid_ole_vco, + .num_vco =3D ARRAY_SIZE(lucid_ole_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll2", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll2_out_even[] = =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll2_out_even =3D { + .offset =3D 0x2000, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_cam_cc_pll2_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_cam_cc_pll2_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll2_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_pll2.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_lucid_evo_ops, + }, +}; + +/* 720.0 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll3_config =3D { + .l =3D 0x25, + .alpha =3D 0x8000, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x82aa299c, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x00000003, + .test_ctl_hi1_val =3D 0x00009000, + .test_ctl_hi2_val =3D 0x00000034, + .user_ctl_val =3D 0x00000400, + .user_ctl_hi_val =3D 0x00400005, +}; + +static struct clk_alpha_pll cam_cc_pll3 =3D { + .offset =3D 0x3000, + .config =3D &cam_cc_pll3_config, + .vco_table =3D lucid_ole_vco, + .num_vco =3D ARRAY_SIZE(lucid_ole_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll3", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even =3D { + .offset =3D 0x3000, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_cam_cc_pll3_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll3_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_pll3.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_lucid_evo_ops, + }, +}; + +/* 720.0 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll4_config =3D { + .l =3D 0x25, + .alpha =3D 0x8000, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x82aa299c, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x00000003, + .test_ctl_hi1_val =3D 0x00009000, + .test_ctl_hi2_val =3D 0x00000034, + .user_ctl_val =3D 0x00000400, + .user_ctl_hi_val =3D 0x00400005, +}; + +static struct clk_alpha_pll cam_cc_pll4 =3D { + .offset =3D 0x4000, + .config =3D &cam_cc_pll4_config, + .vco_table =3D lucid_ole_vco, + .num_vco =3D ARRAY_SIZE(lucid_ole_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll4", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even =3D { + .offset =3D 0x4000, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_cam_cc_pll4_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll4_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_pll4.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_lucid_evo_ops, + }, +}; + +/* 720.0 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll5_config =3D { + .l =3D 0x25, + .alpha =3D 0x8000, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x82aa299c, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x00000003, + .test_ctl_hi1_val =3D 0x00009000, + .test_ctl_hi2_val =3D 0x00000034, + .user_ctl_val =3D 0x00000400, + .user_ctl_hi_val =3D 0x00400005, +}; + +static struct clk_alpha_pll cam_cc_pll5 =3D { + .offset =3D 0x5000, + .config =3D &cam_cc_pll5_config, + .vco_table =3D lucid_ole_vco, + .num_vco =3D ARRAY_SIZE(lucid_ole_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll5", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even =3D { + .offset =3D 0x5000, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_cam_cc_pll5_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll5_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_pll5.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_lucid_evo_ops, + }, +}; + +/* 720.0 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll6_config =3D { + .l =3D 0x25, + .alpha =3D 0x8000, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x82aa299c, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x00000003, + .test_ctl_hi1_val =3D 0x00009000, + .test_ctl_hi2_val =3D 0x00000034, + .user_ctl_val =3D 0x00000400, + .user_ctl_hi_val =3D 0x00400005, +}; + +static struct clk_alpha_pll cam_cc_pll6 =3D { + .offset =3D 0x6000, + .config =3D &cam_cc_pll6_config, + .vco_table =3D lucid_ole_vco, + .num_vco =3D ARRAY_SIZE(lucid_ole_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll6", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even =3D { + .offset =3D 0x6000, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_cam_cc_pll6_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll6_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_pll6.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_lucid_evo_ops, + }, +}; + +static const struct parent_map cam_cc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL0_OUT_MAIN, 1 }, + { P_CAM_CC_PLL0_OUT_EVEN, 2 }, + { P_CAM_CC_PLL0_OUT_ODD, 3 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll0.clkr.hw }, + { .hw =3D &cam_cc_pll0_out_even.clkr.hw }, + { .hw =3D &cam_cc_pll0_out_odd.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL0_OUT_MAIN, 1 }, + { P_CAM_CC_PLL0_OUT_EVEN, 2 }, + { P_CAM_CC_PLL0_OUT_ODD, 3 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll0.clkr.hw }, + { .hw =3D &cam_cc_pll0_out_even.clkr.hw }, + { .hw =3D &cam_cc_pll0_out_odd.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_2[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL0_OUT_MAIN, 1 }, + { P_CAM_CC_PLL0_OUT_EVEN, 2 }, + { P_CAM_CC_PLL3_OUT_EVEN, 3 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_2[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll0.clkr.hw }, + { .hw =3D &cam_cc_pll0_out_even.clkr.hw }, + { .hw =3D &cam_cc_pll3_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_3[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL2_OUT_EVEN, 2 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_3[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll2_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_4[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL4_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_4[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll4_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_5[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL5_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_5[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll5_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_6[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL6_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_6[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll6_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_7[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL0_OUT_MAIN, 1 }, + { P_CAM_CC_PLL0_OUT_EVEN, 2 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_7[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll0.clkr.hw }, + { .hw =3D &cam_cc_pll0_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_8[] =3D { + { P_SLEEP_CLK, 0 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_8[] =3D { + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct parent_map cam_cc_parent_map_9[] =3D { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_9[] =3D { + { .index =3D DT_BI_TCXO }, +}; + +static const struct freq_tbl ftbl_cam_cc_camnoc_rt_axi_clk_src[] =3D { + F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_camnoc_rt_axi_clk_src =3D { + .cmd_rcgr =3D 0x13244, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_camnoc_rt_axi_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_rt_axi_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] =3D { + F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_cci_0_clk_src =3D { + .cmd_rcgr =3D 0x13110, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_cci_0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cci_0_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_cci_1_clk_src =3D { + .cmd_rcgr =3D 0x13130, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_cci_0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cci_1_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_cci_2_clk_src =3D { + .cmd_rcgr =3D 0x13150, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_cci_0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cci_2_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_cci_3_clk_src =3D { + .cmd_rcgr =3D 0x13170, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_cci_0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cci_3_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_cci_4_clk_src =3D { + .cmd_rcgr =3D 0x13190, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_cci_0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cci_4_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] =3D { + F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_cphy_rx_clk_src =3D { + .cmd_rcgr =3D 0x120ac, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_cphy_rx_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cphy_rx_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] =3D { + F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_csi0phytimer_clk_src =3D { + .cmd_rcgr =3D 0x10000, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_csi0phytimer_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi0phytimer_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi1phytimer_clk_src =3D { + .cmd_rcgr =3D 0x10028, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_csi0phytimer_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi1phytimer_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi2phytimer_clk_src =3D { + .cmd_rcgr =3D 0x1004c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_csi0phytimer_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi2phytimer_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi3phytimer_clk_src =3D { + .cmd_rcgr =3D 0x10070, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_csi0phytimer_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi3phytimer_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi4phytimer_clk_src =3D { + .cmd_rcgr =3D 0x10094, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_csi0phytimer_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi4phytimer_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_csid_clk_src[] =3D { + F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_csid_clk_src =3D { + .cmd_rcgr =3D 0x13214, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_csid_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csid_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] =3D { + F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), + F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_fast_ahb_clk_src =3D { + .cmd_rcgr =3D 0x131dc, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_fast_ahb_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_fast_ahb_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_icp_0_clk_src[] =3D { + F(360000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(480000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(600000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_icp_0_clk_src =3D { + .cmd_rcgr =3D 0x130a4, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_2, + .freq_tbl =3D ftbl_cam_cc_icp_0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_icp_0_clk_src", + .parent_data =3D cam_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_icp_1_clk_src =3D { + .cmd_rcgr =3D 0x130dc, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_2, + .freq_tbl =3D ftbl_cam_cc_icp_0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_icp_1_clk_src", + .parent_data =3D cam_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ife_0_main_clk_src[] =3D { + F(360000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + F(480000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + F(650000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ife_0_main_clk_src =3D { + .cmd_rcgr =3D 0x12018, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_4, + .freq_tbl =3D ftbl_cam_cc_ife_0_main_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_0_main_clk_src", + .parent_data =3D cam_cc_parent_data_4, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_4), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ife_1_main_clk_src[] =3D { + F(360000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + F(480000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + F(650000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ife_1_main_clk_src =3D { + .cmd_rcgr =3D 0x120dc, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_5, + .freq_tbl =3D ftbl_cam_cc_ife_1_main_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_1_main_clk_src", + .parent_data =3D cam_cc_parent_data_5, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_5), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ife_2_main_clk_src[] =3D { + F(360000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), + F(480000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), + F(650000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ife_2_main_clk_src =3D { + .cmd_rcgr =3D 0x12188, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_6, + .freq_tbl =3D ftbl_cam_cc_ife_2_main_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_2_main_clk_src", + .parent_data =3D cam_cc_parent_data_6, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_6), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_ife_lite_clk_src =3D { + .cmd_rcgr =3D 0x13000, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_csid_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_lite_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src =3D { + .cmd_rcgr =3D 0x13024, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_csid_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_lite_csid_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ipe_0_clk_src[] =3D { + F(360000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), + F(480000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), + F(650000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ipe_0_clk_src =3D { + .cmd_rcgr =3D 0x11018, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_3, + .freq_tbl =3D ftbl_cam_cc_ipe_0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ipe_0_clk_src", + .parent_data =3D cam_cc_parent_data_3, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_ipe_1_clk_src =3D { + .cmd_rcgr =3D 0x11074, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_3, + .freq_tbl =3D ftbl_cam_cc_ipe_0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ipe_1_clk_src", + .parent_data =3D cam_cc_parent_data_3, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_qdss_debug_clk_src[] =3D { + F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), + F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_qdss_debug_clk_src =3D { + .cmd_rcgr =3D 0x13330, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_qdss_debug_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_qdss_debug_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_qup_ahbm_clk_src[] =3D { + F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0), + F(240000000, P_CAM_CC_PLL0_OUT_MAIN, 5, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_qup_ahbm_clk_src =3D { + .cmd_rcgr =3D 0x132e8, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_qup_ahbm_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_qup_ahbm_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_qup_core_2x_clk_src[] =3D { + F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), + F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_qup_core_2x_clk_src =3D { + .cmd_rcgr =3D 0x132a0, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_qup_core_2x_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_qup_core_2x_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_qup_se_clk_src =3D { + .cmd_rcgr =3D 0x13308, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_7, + .freq_tbl =3D ftbl_cam_cc_cci_0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_qup_se_clk_src", + .parent_data =3D cam_cc_parent_data_7, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_7), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] =3D { + F(32000, P_SLEEP_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_sleep_clk_src =3D { + .cmd_rcgr =3D 0x13384, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_8, + .freq_tbl =3D ftbl_cam_cc_sleep_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_sleep_clk_src", + .parent_data =3D cam_cc_parent_data_8, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_8), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] =3D { + F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_slow_ahb_clk_src =3D { + .cmd_rcgr =3D 0x131f8, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_slow_ahb_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_slow_ahb_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_xo_clk_src =3D { + .cmd_rcgr =3D 0x13368, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_9, + .freq_tbl =3D ftbl_cam_cc_xo_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_xo_clk_src", + .parent_data =3D cam_cc_parent_data_9, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_9), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div cam_cc_qup_core_2x_div_clk_src =3D { + .reg =3D 0x132cc, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_qup_core_2x_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_qup_core_2x_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch cam_cc_camnoc_dcd_xo_clk =3D { + .halt_reg =3D 0x13290, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x13290, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_dcd_xo_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_nrt_axi_clk =3D { + .halt_reg =3D 0x13278, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x13278, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_nrt_axi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_camnoc_rt_axi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_rt_axi_clk =3D { + .halt_reg =3D 0x13260, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x13260, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_rt_axi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_camnoc_rt_axi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cci_0_clk =3D { + .halt_reg =3D 0x1312c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1312c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cci_0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cci_0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cci_1_clk =3D { + .halt_reg =3D 0x1314c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1314c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cci_1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cci_1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cci_2_clk =3D { + .halt_reg =3D 0x1316c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1316c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cci_2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cci_2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cci_3_clk =3D { + .halt_reg =3D 0x1318c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1318c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cci_3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cci_3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cci_4_clk =3D { + .halt_reg =3D 0x131ac, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x131ac, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cci_4_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cci_4_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ccu_fast_ahb_clk =3D { + .halt_reg =3D 0x1329c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1329c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ccu_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi0phytimer_clk =3D { + .halt_reg =3D 0x1001c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1001c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi0phytimer_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_csi0phytimer_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi1phytimer_clk =3D { + .halt_reg =3D 0x10044, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x10044, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi1phytimer_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_csi1phytimer_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi2phytimer_clk =3D { + .halt_reg =3D 0x10068, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x10068, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi2phytimer_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_csi2phytimer_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi3phytimer_clk =3D { + .halt_reg =3D 0x1008c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1008c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi3phytimer_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_csi3phytimer_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi4phytimer_clk =3D { + .halt_reg =3D 0x100b0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x100b0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi4phytimer_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_csi4phytimer_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csid_clk =3D { + .halt_reg =3D 0x13230, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x13230, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csid_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_csid_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csid_csiphy_rx_clk =3D { + .halt_reg =3D 0x10024, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x10024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csid_csiphy_rx_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy0_clk =3D { + .halt_reg =3D 0x10020, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x10020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csiphy0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy1_clk =3D { + .halt_reg =3D 0x10048, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x10048, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csiphy1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy2_clk =3D { + .halt_reg =3D 0x1006c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1006c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csiphy2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy3_clk =3D { + .halt_reg =3D 0x10090, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x10090, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csiphy3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy4_clk =3D { + .halt_reg =3D 0x100b4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x100b4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csiphy4_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_icp_0_ahb_clk =3D { + .halt_reg =3D 0x130d4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x130d4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_icp_0_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_icp_0_clk =3D { + .halt_reg =3D 0x130c0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x130c0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_icp_0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_icp_0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_icp_1_ahb_clk =3D { + .halt_reg =3D 0x1310c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1310c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_icp_1_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_icp_1_clk =3D { + .halt_reg =3D 0x130f8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x130f8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_icp_1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_icp_1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_main_clk =3D { + .halt_reg =3D 0x12034, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x12034, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_0_main_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_0_main_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_main_fast_ahb_clk =3D { + .halt_reg =3D 0x12054, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x12054, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_0_main_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_pcp_clk =3D { + .halt_reg =3D 0x12058, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x12058, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_0_pcp_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_0_main_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_pcp_fast_ahb_clk =3D { + .halt_reg =3D 0x12070, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x12070, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_0_pcp_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_scalar_clk =3D { + .halt_reg =3D 0x12074, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x12074, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_0_scalar_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_0_main_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_scalar_fast_ahb_clk =3D { + .halt_reg =3D 0x1208c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1208c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_0_scalar_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_tmc_clk =3D { + .halt_reg =3D 0x12090, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x12090, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_0_tmc_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_0_main_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_tmc_fast_ahb_clk =3D { + .halt_reg =3D 0x120a8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x120a8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_0_tmc_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_main_clk =3D { + .halt_reg =3D 0x120f8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x120f8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_1_main_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_1_main_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_main_fast_ahb_clk =3D { + .halt_reg =3D 0x12118, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x12118, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_1_main_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_pcp_clk =3D { + .halt_reg =3D 0x1211c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1211c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_1_pcp_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_1_main_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_pcp_fast_ahb_clk =3D { + .halt_reg =3D 0x12134, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x12134, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_1_pcp_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_scalar_clk =3D { + .halt_reg =3D 0x12138, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x12138, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_1_scalar_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_1_main_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_scalar_fast_ahb_clk =3D { + .halt_reg =3D 0x12150, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x12150, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_1_scalar_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_tmc_clk =3D { + .halt_reg =3D 0x12154, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x12154, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_1_tmc_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_1_main_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_tmc_fast_ahb_clk =3D { + .halt_reg =3D 0x1216c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1216c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_1_tmc_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_2_main_clk =3D { + .halt_reg =3D 0x121a4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x121a4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_2_main_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_2_main_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_2_main_fast_ahb_clk =3D { + .halt_reg =3D 0x121c4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x121c4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_2_main_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_2_pcp_clk =3D { + .halt_reg =3D 0x121c8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x121c8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_2_pcp_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_2_main_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_2_pcp_fast_ahb_clk =3D { + .halt_reg =3D 0x121e0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x121e0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_2_pcp_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_2_scalar_clk =3D { + .halt_reg =3D 0x121e4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x121e4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_2_scalar_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_2_main_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_2_scalar_fast_ahb_clk =3D { + .halt_reg =3D 0x121fc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x121fc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_2_scalar_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_2_tmc_clk =3D { + .halt_reg =3D 0x12200, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x12200, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_2_tmc_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_2_main_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_2_tmc_fast_ahb_clk =3D { + .halt_reg =3D 0x12218, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x12218, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_2_tmc_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_ahb_clk =3D { + .halt_reg =3D 0x13054, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x13054, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_lite_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_clk =3D { + .halt_reg =3D 0x1301c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1301c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_lite_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_lite_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_cphy_rx_clk =3D { + .halt_reg =3D 0x13050, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x13050, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_lite_cphy_rx_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_csid_clk =3D { + .halt_reg =3D 0x1303c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1303c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_lite_csid_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_lite_csid_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_0_ahb_clk =3D { + .halt_reg =3D 0x11054, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x11054, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ipe_0_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_0_clk =3D { + .halt_reg =3D 0x11034, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x11034, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ipe_0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ipe_0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_0_fast_ahb_clk =3D { + .halt_reg =3D 0x11058, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x11058, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ipe_0_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_1_ahb_clk =3D { + .halt_reg =3D 0x110b0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x110b0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ipe_1_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_1_clk =3D { + .halt_reg =3D 0x11090, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x11090, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ipe_1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ipe_1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_1_fast_ahb_clk =3D { + .halt_reg =3D 0x110b4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x110b4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ipe_1_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_qdss_debug_clk =3D { + .halt_reg =3D 0x13348, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x13348, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_qdss_debug_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_qdss_debug_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_qdss_debug_xo_clk =3D { + .halt_reg =3D 0x1334c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1334c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_qdss_debug_xo_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_qup_ahbm_clk =3D { + .halt_reg =3D 0x13300, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x13300, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_qup_ahbm_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_qup_ahbm_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_qup_core_2x_clk =3D { + .halt_reg =3D 0x132b8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x132b8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_qup_core_2x_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_qup_core_2x_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_qup_core_clk =3D { + .halt_reg =3D 0x132d0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x132d0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_qup_core_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_qup_core_2x_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_qup_se_clk =3D { + .halt_reg =3D 0x13320, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x13320, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_qup_se_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_qup_se_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_lite_0_clk =3D { + .halt_reg =3D 0x1305c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1305c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_sfe_lite_0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_0_main_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_lite_0_fast_ahb_clk =3D { + .halt_reg =3D 0x1306c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1306c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_sfe_lite_0_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_lite_1_clk =3D { + .halt_reg =3D 0x13074, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x13074, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_sfe_lite_1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_1_main_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_lite_1_fast_ahb_clk =3D { + .halt_reg =3D 0x13084, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x13084, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_sfe_lite_1_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_lite_2_clk =3D { + .halt_reg =3D 0x1308c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1308c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_sfe_lite_2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_2_main_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_lite_2_fast_ahb_clk =3D { + .halt_reg =3D 0x1309c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1309c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_sfe_lite_2_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sm_obs_clk =3D { + .halt_reg =3D 0x1401c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1401c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_sm_obs_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_top_ahb_clk =3D { + .halt_reg =3D 0x131b0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x131b0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_top_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_top_fast_ahb_clk =3D { + .halt_reg =3D 0x131c4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x131c4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_top_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_top_ife_0_clk =3D { + .halt_reg =3D 0x12048, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x12048, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_top_ife_0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_0_main_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_top_ife_1_clk =3D { + .halt_reg =3D 0x1210c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1210c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_top_ife_1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_1_main_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_top_ife_2_clk =3D { + .halt_reg =3D 0x121b8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x121b8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_top_ife_2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_2_main_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_top_ife_lite_clk =3D { + .halt_reg =3D 0x13020, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x13020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_top_ife_lite_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_lite_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_top_ipe_0_clk =3D { + .halt_reg =3D 0x11048, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x11048, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_top_ipe_0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ipe_0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_top_ipe_1_clk =3D { + .halt_reg =3D 0x110a4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x110a4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_top_ipe_1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ipe_1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_top_qup_ahbm_clk =3D { + .halt_reg =3D 0x13304, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x13304, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_top_qup_ahbm_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_qup_ahbm_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_top_sfe_lite_0_clk =3D { + .halt_reg =3D 0x13060, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x13060, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_top_sfe_lite_0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_0_main_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_top_sfe_lite_1_clk =3D { + .halt_reg =3D 0x13078, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x13078, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_top_sfe_lite_1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_1_main_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_top_sfe_lite_2_clk =3D { + .halt_reg =3D 0x13090, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x13090, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_top_sfe_lite_2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_2_main_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_tpg_csiphy_rx_clk =3D { + .halt_reg =3D 0x100b8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x100b8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_tpg_csiphy_rx_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc cam_cc_titan_top_gdsc =3D { + .gdscr =3D 0x13350, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "cam_cc_titan_top_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_ife_0_gdsc =3D { + .gdscr =3D 0x12004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "cam_cc_ife_0_gdsc", + }, + .parent =3D &cam_cc_titan_top_gdsc.pd, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_ife_1_gdsc =3D { + .gdscr =3D 0x120c8, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "cam_cc_ife_1_gdsc", + }, + .parent =3D &cam_cc_titan_top_gdsc.pd, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_ife_2_gdsc =3D { + .gdscr =3D 0x12174, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "cam_cc_ife_2_gdsc", + }, + .parent =3D &cam_cc_titan_top_gdsc.pd, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_ipe_0_gdsc =3D { + .gdscr =3D 0x11004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "cam_cc_ipe_0_gdsc", + }, + .parent =3D &cam_cc_titan_top_gdsc.pd, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_ipe_1_gdsc =3D { + .gdscr =3D 0x11060, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "cam_cc_ipe_1_gdsc", + }, + .parent =3D &cam_cc_titan_top_gdsc.pd, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct clk_regmap *cam_cc_nord_clocks[] =3D { + [CAM_CC_CAMNOC_DCD_XO_CLK] =3D &cam_cc_camnoc_dcd_xo_clk.clkr, + [CAM_CC_CAMNOC_NRT_AXI_CLK] =3D &cam_cc_camnoc_nrt_axi_clk.clkr, + [CAM_CC_CAMNOC_RT_AXI_CLK] =3D &cam_cc_camnoc_rt_axi_clk.clkr, + [CAM_CC_CAMNOC_RT_AXI_CLK_SRC] =3D &cam_cc_camnoc_rt_axi_clk_src.clkr, + [CAM_CC_CCI_0_CLK] =3D &cam_cc_cci_0_clk.clkr, + [CAM_CC_CCI_0_CLK_SRC] =3D &cam_cc_cci_0_clk_src.clkr, + [CAM_CC_CCI_1_CLK] =3D &cam_cc_cci_1_clk.clkr, + [CAM_CC_CCI_1_CLK_SRC] =3D &cam_cc_cci_1_clk_src.clkr, + [CAM_CC_CCI_2_CLK] =3D &cam_cc_cci_2_clk.clkr, + [CAM_CC_CCI_2_CLK_SRC] =3D &cam_cc_cci_2_clk_src.clkr, + [CAM_CC_CCI_3_CLK] =3D &cam_cc_cci_3_clk.clkr, + [CAM_CC_CCI_3_CLK_SRC] =3D &cam_cc_cci_3_clk_src.clkr, + [CAM_CC_CCI_4_CLK] =3D &cam_cc_cci_4_clk.clkr, + [CAM_CC_CCI_4_CLK_SRC] =3D &cam_cc_cci_4_clk_src.clkr, + [CAM_CC_CCU_FAST_AHB_CLK] =3D &cam_cc_ccu_fast_ahb_clk.clkr, + [CAM_CC_CPHY_RX_CLK_SRC] =3D &cam_cc_cphy_rx_clk_src.clkr, + [CAM_CC_CSI0PHYTIMER_CLK] =3D &cam_cc_csi0phytimer_clk.clkr, + [CAM_CC_CSI0PHYTIMER_CLK_SRC] =3D &cam_cc_csi0phytimer_clk_src.clkr, + [CAM_CC_CSI1PHYTIMER_CLK] =3D &cam_cc_csi1phytimer_clk.clkr, + [CAM_CC_CSI1PHYTIMER_CLK_SRC] =3D &cam_cc_csi1phytimer_clk_src.clkr, + [CAM_CC_CSI2PHYTIMER_CLK] =3D &cam_cc_csi2phytimer_clk.clkr, + [CAM_CC_CSI2PHYTIMER_CLK_SRC] =3D &cam_cc_csi2phytimer_clk_src.clkr, + [CAM_CC_CSI3PHYTIMER_CLK] =3D &cam_cc_csi3phytimer_clk.clkr, + [CAM_CC_CSI3PHYTIMER_CLK_SRC] =3D &cam_cc_csi3phytimer_clk_src.clkr, + [CAM_CC_CSI4PHYTIMER_CLK] =3D &cam_cc_csi4phytimer_clk.clkr, + [CAM_CC_CSI4PHYTIMER_CLK_SRC] =3D &cam_cc_csi4phytimer_clk_src.clkr, + [CAM_CC_CSID_CLK] =3D &cam_cc_csid_clk.clkr, + [CAM_CC_CSID_CLK_SRC] =3D &cam_cc_csid_clk_src.clkr, + [CAM_CC_CSID_CSIPHY_RX_CLK] =3D &cam_cc_csid_csiphy_rx_clk.clkr, + [CAM_CC_CSIPHY0_CLK] =3D &cam_cc_csiphy0_clk.clkr, + [CAM_CC_CSIPHY1_CLK] =3D &cam_cc_csiphy1_clk.clkr, + [CAM_CC_CSIPHY2_CLK] =3D &cam_cc_csiphy2_clk.clkr, + [CAM_CC_CSIPHY3_CLK] =3D &cam_cc_csiphy3_clk.clkr, + [CAM_CC_CSIPHY4_CLK] =3D &cam_cc_csiphy4_clk.clkr, + [CAM_CC_FAST_AHB_CLK_SRC] =3D &cam_cc_fast_ahb_clk_src.clkr, + [CAM_CC_ICP_0_AHB_CLK] =3D &cam_cc_icp_0_ahb_clk.clkr, + [CAM_CC_ICP_0_CLK] =3D &cam_cc_icp_0_clk.clkr, + [CAM_CC_ICP_0_CLK_SRC] =3D &cam_cc_icp_0_clk_src.clkr, + [CAM_CC_ICP_1_AHB_CLK] =3D &cam_cc_icp_1_ahb_clk.clkr, + [CAM_CC_ICP_1_CLK] =3D &cam_cc_icp_1_clk.clkr, + [CAM_CC_ICP_1_CLK_SRC] =3D &cam_cc_icp_1_clk_src.clkr, + [CAM_CC_IFE_0_MAIN_CLK] =3D &cam_cc_ife_0_main_clk.clkr, + [CAM_CC_IFE_0_MAIN_CLK_SRC] =3D &cam_cc_ife_0_main_clk_src.clkr, + [CAM_CC_IFE_0_MAIN_FAST_AHB_CLK] =3D &cam_cc_ife_0_main_fast_ahb_clk.clkr, + [CAM_CC_IFE_0_PCP_CLK] =3D &cam_cc_ife_0_pcp_clk.clkr, + [CAM_CC_IFE_0_PCP_FAST_AHB_CLK] =3D &cam_cc_ife_0_pcp_fast_ahb_clk.clkr, + [CAM_CC_IFE_0_SCALAR_CLK] =3D &cam_cc_ife_0_scalar_clk.clkr, + [CAM_CC_IFE_0_SCALAR_FAST_AHB_CLK] =3D &cam_cc_ife_0_scalar_fast_ahb_clk.= clkr, + [CAM_CC_IFE_0_TMC_CLK] =3D &cam_cc_ife_0_tmc_clk.clkr, + [CAM_CC_IFE_0_TMC_FAST_AHB_CLK] =3D &cam_cc_ife_0_tmc_fast_ahb_clk.clkr, + [CAM_CC_IFE_1_MAIN_CLK] =3D &cam_cc_ife_1_main_clk.clkr, + [CAM_CC_IFE_1_MAIN_CLK_SRC] =3D &cam_cc_ife_1_main_clk_src.clkr, + [CAM_CC_IFE_1_MAIN_FAST_AHB_CLK] =3D &cam_cc_ife_1_main_fast_ahb_clk.clkr, + [CAM_CC_IFE_1_PCP_CLK] =3D &cam_cc_ife_1_pcp_clk.clkr, + [CAM_CC_IFE_1_PCP_FAST_AHB_CLK] =3D &cam_cc_ife_1_pcp_fast_ahb_clk.clkr, + [CAM_CC_IFE_1_SCALAR_CLK] =3D &cam_cc_ife_1_scalar_clk.clkr, + [CAM_CC_IFE_1_SCALAR_FAST_AHB_CLK] =3D &cam_cc_ife_1_scalar_fast_ahb_clk.= clkr, + [CAM_CC_IFE_1_TMC_CLK] =3D &cam_cc_ife_1_tmc_clk.clkr, + [CAM_CC_IFE_1_TMC_FAST_AHB_CLK] =3D &cam_cc_ife_1_tmc_fast_ahb_clk.clkr, + [CAM_CC_IFE_2_MAIN_CLK] =3D &cam_cc_ife_2_main_clk.clkr, + [CAM_CC_IFE_2_MAIN_CLK_SRC] =3D &cam_cc_ife_2_main_clk_src.clkr, + [CAM_CC_IFE_2_MAIN_FAST_AHB_CLK] =3D &cam_cc_ife_2_main_fast_ahb_clk.clkr, + [CAM_CC_IFE_2_PCP_CLK] =3D &cam_cc_ife_2_pcp_clk.clkr, + [CAM_CC_IFE_2_PCP_FAST_AHB_CLK] =3D &cam_cc_ife_2_pcp_fast_ahb_clk.clkr, + [CAM_CC_IFE_2_SCALAR_CLK] =3D &cam_cc_ife_2_scalar_clk.clkr, + [CAM_CC_IFE_2_SCALAR_FAST_AHB_CLK] =3D &cam_cc_ife_2_scalar_fast_ahb_clk.= clkr, + [CAM_CC_IFE_2_TMC_CLK] =3D &cam_cc_ife_2_tmc_clk.clkr, + [CAM_CC_IFE_2_TMC_FAST_AHB_CLK] =3D &cam_cc_ife_2_tmc_fast_ahb_clk.clkr, + [CAM_CC_IFE_LITE_AHB_CLK] =3D &cam_cc_ife_lite_ahb_clk.clkr, + [CAM_CC_IFE_LITE_CLK] =3D &cam_cc_ife_lite_clk.clkr, + [CAM_CC_IFE_LITE_CLK_SRC] =3D &cam_cc_ife_lite_clk_src.clkr, + [CAM_CC_IFE_LITE_CPHY_RX_CLK] =3D &cam_cc_ife_lite_cphy_rx_clk.clkr, + [CAM_CC_IFE_LITE_CSID_CLK] =3D &cam_cc_ife_lite_csid_clk.clkr, + [CAM_CC_IFE_LITE_CSID_CLK_SRC] =3D &cam_cc_ife_lite_csid_clk_src.clkr, + [CAM_CC_IPE_0_AHB_CLK] =3D &cam_cc_ipe_0_ahb_clk.clkr, + [CAM_CC_IPE_0_CLK] =3D &cam_cc_ipe_0_clk.clkr, + [CAM_CC_IPE_0_CLK_SRC] =3D &cam_cc_ipe_0_clk_src.clkr, + [CAM_CC_IPE_0_FAST_AHB_CLK] =3D &cam_cc_ipe_0_fast_ahb_clk.clkr, + [CAM_CC_IPE_1_AHB_CLK] =3D &cam_cc_ipe_1_ahb_clk.clkr, + [CAM_CC_IPE_1_CLK] =3D &cam_cc_ipe_1_clk.clkr, + [CAM_CC_IPE_1_CLK_SRC] =3D &cam_cc_ipe_1_clk_src.clkr, + [CAM_CC_IPE_1_FAST_AHB_CLK] =3D &cam_cc_ipe_1_fast_ahb_clk.clkr, + [CAM_CC_PLL0] =3D &cam_cc_pll0.clkr, + [CAM_CC_PLL0_OUT_EVEN] =3D &cam_cc_pll0_out_even.clkr, + [CAM_CC_PLL0_OUT_ODD] =3D &cam_cc_pll0_out_odd.clkr, + [CAM_CC_PLL2] =3D &cam_cc_pll2.clkr, + [CAM_CC_PLL2_OUT_EVEN] =3D &cam_cc_pll2_out_even.clkr, + [CAM_CC_PLL3] =3D &cam_cc_pll3.clkr, + [CAM_CC_PLL3_OUT_EVEN] =3D &cam_cc_pll3_out_even.clkr, + [CAM_CC_PLL4] =3D &cam_cc_pll4.clkr, + [CAM_CC_PLL4_OUT_EVEN] =3D &cam_cc_pll4_out_even.clkr, + [CAM_CC_PLL5] =3D &cam_cc_pll5.clkr, + [CAM_CC_PLL5_OUT_EVEN] =3D &cam_cc_pll5_out_even.clkr, + [CAM_CC_PLL6] =3D &cam_cc_pll6.clkr, + [CAM_CC_PLL6_OUT_EVEN] =3D &cam_cc_pll6_out_even.clkr, + [CAM_CC_QDSS_DEBUG_CLK] =3D &cam_cc_qdss_debug_clk.clkr, + [CAM_CC_QDSS_DEBUG_CLK_SRC] =3D &cam_cc_qdss_debug_clk_src.clkr, + [CAM_CC_QDSS_DEBUG_XO_CLK] =3D &cam_cc_qdss_debug_xo_clk.clkr, + [CAM_CC_QUP_AHBM_CLK] =3D &cam_cc_qup_ahbm_clk.clkr, + [CAM_CC_QUP_AHBM_CLK_SRC] =3D &cam_cc_qup_ahbm_clk_src.clkr, + [CAM_CC_QUP_CORE_2X_CLK] =3D &cam_cc_qup_core_2x_clk.clkr, + [CAM_CC_QUP_CORE_2X_CLK_SRC] =3D &cam_cc_qup_core_2x_clk_src.clkr, + [CAM_CC_QUP_CORE_2X_DIV_CLK_SRC] =3D &cam_cc_qup_core_2x_div_clk_src.clkr, + [CAM_CC_QUP_CORE_CLK] =3D &cam_cc_qup_core_clk.clkr, + [CAM_CC_QUP_SE_CLK] =3D &cam_cc_qup_se_clk.clkr, + [CAM_CC_QUP_SE_CLK_SRC] =3D &cam_cc_qup_se_clk_src.clkr, + [CAM_CC_SFE_LITE_0_CLK] =3D &cam_cc_sfe_lite_0_clk.clkr, + [CAM_CC_SFE_LITE_0_FAST_AHB_CLK] =3D &cam_cc_sfe_lite_0_fast_ahb_clk.clkr, + [CAM_CC_SFE_LITE_1_CLK] =3D &cam_cc_sfe_lite_1_clk.clkr, + [CAM_CC_SFE_LITE_1_FAST_AHB_CLK] =3D &cam_cc_sfe_lite_1_fast_ahb_clk.clkr, + [CAM_CC_SFE_LITE_2_CLK] =3D &cam_cc_sfe_lite_2_clk.clkr, + [CAM_CC_SFE_LITE_2_FAST_AHB_CLK] =3D &cam_cc_sfe_lite_2_fast_ahb_clk.clkr, + [CAM_CC_SLEEP_CLK_SRC] =3D &cam_cc_sleep_clk_src.clkr, + [CAM_CC_SLOW_AHB_CLK_SRC] =3D &cam_cc_slow_ahb_clk_src.clkr, + [CAM_CC_SM_OBS_CLK] =3D &cam_cc_sm_obs_clk.clkr, + [CAM_CC_TOP_AHB_CLK] =3D &cam_cc_top_ahb_clk.clkr, + [CAM_CC_TOP_FAST_AHB_CLK] =3D &cam_cc_top_fast_ahb_clk.clkr, + [CAM_CC_TOP_IFE_0_CLK] =3D &cam_cc_top_ife_0_clk.clkr, + [CAM_CC_TOP_IFE_1_CLK] =3D &cam_cc_top_ife_1_clk.clkr, + [CAM_CC_TOP_IFE_2_CLK] =3D &cam_cc_top_ife_2_clk.clkr, + [CAM_CC_TOP_IFE_LITE_CLK] =3D &cam_cc_top_ife_lite_clk.clkr, + [CAM_CC_TOP_IPE_0_CLK] =3D &cam_cc_top_ipe_0_clk.clkr, + [CAM_CC_TOP_IPE_1_CLK] =3D &cam_cc_top_ipe_1_clk.clkr, + [CAM_CC_TOP_QUP_AHBM_CLK] =3D &cam_cc_top_qup_ahbm_clk.clkr, + [CAM_CC_TOP_SFE_LITE_0_CLK] =3D &cam_cc_top_sfe_lite_0_clk.clkr, + [CAM_CC_TOP_SFE_LITE_1_CLK] =3D &cam_cc_top_sfe_lite_1_clk.clkr, + [CAM_CC_TOP_SFE_LITE_2_CLK] =3D &cam_cc_top_sfe_lite_2_clk.clkr, + [CAM_CC_TPG_CSIPHY_RX_CLK] =3D &cam_cc_tpg_csiphy_rx_clk.clkr, + [CAM_CC_XO_CLK_SRC] =3D &cam_cc_xo_clk_src.clkr, +}; + +static struct gdsc *cam_cc_nord_gdscs[] =3D { + [CAM_CC_TITAN_TOP_GDSC] =3D &cam_cc_titan_top_gdsc, + [CAM_CC_IFE_0_GDSC] =3D &cam_cc_ife_0_gdsc, + [CAM_CC_IFE_1_GDSC] =3D &cam_cc_ife_1_gdsc, + [CAM_CC_IFE_2_GDSC] =3D &cam_cc_ife_2_gdsc, + [CAM_CC_IPE_0_GDSC] =3D &cam_cc_ipe_0_gdsc, + [CAM_CC_IPE_1_GDSC] =3D &cam_cc_ipe_1_gdsc, +}; + +static const struct qcom_reset_map cam_cc_nord_resets[] =3D { + [CAM_CC_CCU_BCR] =3D { 0x13298 }, + [CAM_CC_ICP_0_BCR] =3D { 0x130a0 }, + [CAM_CC_ICP_1_BCR] =3D { 0x130d8 }, + [CAM_CC_IFE_0_BCR] =3D { 0x12000 }, + [CAM_CC_IFE_1_BCR] =3D { 0x120c4 }, + [CAM_CC_IFE_2_BCR] =3D { 0x12170 }, + [CAM_CC_IPE_0_BCR] =3D { 0x11000 }, + [CAM_CC_IPE_1_BCR] =3D { 0x1105c }, + [CAM_CC_QDSS_DEBUG_BCR] =3D { 0x1332c }, + [CAM_CC_SFE_LITE_0_BCR] =3D { 0x13058 }, + [CAM_CC_SFE_LITE_1_BCR] =3D { 0x13070 }, + [CAM_CC_SFE_LITE_2_BCR] =3D { 0x13088 }, +}; + +static struct clk_alpha_pll *cam_cc_nord_plls[] =3D { + &cam_cc_pll0, + &cam_cc_pll2, + &cam_cc_pll3, + &cam_cc_pll4, + &cam_cc_pll5, + &cam_cc_pll6, +}; + +static const u32 cam_cc_nord_critical_cbcrs[] =3D { + 0x13294, /* CAM_CC_CAMNOC_XO_CLK */ + 0x13364, /* CAM_CC_CORE_AHB_CLK */ + 0x13380, /* CAM_CC_GDSC_CLK */ + 0x132e4, /* CAM_CC_QUP_SLEEP_CLK */ + 0x1339c, /* CAM_CC_SLEEP_CLK */ +}; + +static const struct regmap_config cam_cc_nord_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x17000, + .fast_io =3D true, +}; + +static const struct qcom_cc_driver_data cam_cc_nord_driver_data =3D { + .alpha_plls =3D cam_cc_nord_plls, + .num_alpha_plls =3D ARRAY_SIZE(cam_cc_nord_plls), + .clk_cbcrs =3D cam_cc_nord_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(cam_cc_nord_critical_cbcrs), +}; + +static const struct qcom_cc_desc cam_cc_nord_desc =3D { + .config =3D &cam_cc_nord_regmap_config, + .clks =3D cam_cc_nord_clocks, + .num_clks =3D ARRAY_SIZE(cam_cc_nord_clocks), + .resets =3D cam_cc_nord_resets, + .num_resets =3D ARRAY_SIZE(cam_cc_nord_resets), + .gdscs =3D cam_cc_nord_gdscs, + .num_gdscs =3D ARRAY_SIZE(cam_cc_nord_gdscs), + .use_rpm =3D true, + .driver_data =3D &cam_cc_nord_driver_data, +}; + +static const struct of_device_id cam_cc_nord_match_table[] =3D { + { .compatible =3D "qcom,nord-camcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, cam_cc_nord_match_table); + +static int cam_cc_nord_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &cam_cc_nord_desc); +} + +static struct platform_driver cam_cc_nord_driver =3D { + .probe =3D cam_cc_nord_probe, + .driver =3D { + .name =3D "camcc-nord", + .of_match_table =3D cam_cc_nord_match_table, + }, +}; + +module_platform_driver(cam_cc_nord_driver); + +MODULE_DESCRIPTION("QTI CAMCC Nord Driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1