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Maili gxclkctl is the same as Kaanapali gxclkctl and falls back to it. Add the compatibles for the graphics clock controllers on the Qualcomm Maili SoC. Signed-off-by: Jagadeesh Kona Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/clock/qcom,hawi-gpucc.yaml | 4 += ++- Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml | 1 + 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,hawi-gpucc.yaml b= /Documentation/devicetree/bindings/clock/qcom,hawi-gpucc.yaml index 3e40bc3c061d111620a988ac148861ffe9b18b05..b7179d53166f8c72bfe59a290d0= e5a406d3f08ea 100644 --- a/Documentation/devicetree/bindings/clock/qcom,hawi-gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,hawi-gpucc.yaml @@ -17,7 +17,9 @@ description: | =20 properties: compatible: - const: qcom,hawi-gpucc + enum: + - qcom,hawi-gpucc + - qcom,maili-gpucc =20 clocks: items: diff --git a/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkct= l.yaml b/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.ya= ml index 28b653f6b64d5ca748f8d77f01a250dc0a3101de..94f84d5294c6df8d8c7ac28c26a= 89a27ad1b8ebb 100644 --- a/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml @@ -28,6 +28,7 @@ properties: - items: - enum: - qcom,hawi-gxclkctl + - qcom,maili-gxclkctl - const: qcom,kaanapali-gxclkctl =20 power-domains: --=20 2.34.1 From nobody Fri Oct 2 12:21:54 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2881047ECED for ; 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Fri, 31 Jul 2026 12:13:13 -0700 (PDT) Received: from hu-jkona-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-13fab4d10bbsm4945869c88.11.2026.07.31.12.13.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Jul 2026 12:13:12 -0700 (PDT) From: Jagadeesh Kona Date: Sat, 01 Aug 2026 00:42:46 +0530 Subject: [PATCH 2/2] clk: qcom: Add Graphics clock controller support on Qualcomm Maili SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260801-maili_gpucc-v1-2-9d8c37bded69@oss.qualcomm.com> References: <20260801-maili_gpucc-v1-0-9d8c37bded69@oss.qualcomm.com> In-Reply-To: <20260801-maili_gpucc-v1-0-9d8c37bded69@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dongfang Zhao , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jagadeesh Kona X-Mailer: b4 0.14.2 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzMxMDE0NiBTYWx0ZWRfX6TW9yk9tUPrS LlNYwSnh+uscQ8N6fRg5WNmiGqiEigB/lj4iJkxD/MGEa6k7iLflG3/HCCuySDLwTup43J8gigH 1o6U919LfBL+Moun4LMDR1QrQ31sTos= X-Authority-Analysis: v=2.4 cv=TcamcxQh c=1 sm=1 tr=0 ts=6a6cf3ca cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=Hk_bfOifH1X1uJLPQC8A:9 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzMxMDE0NiBTYWx0ZWRfX8NnWAvboYUoR iI3fzZQh3E2COWtFb8pzUDyvvRq3knq6wslSPp2vqxWdtmEx4gRr9DTwk01ZCDeLiQczo3p8bCc jWA43/sdszThsSpcdReiv5CwZlcSR7r/yDjNhHvLwAPdA5tsRYNQhBzOH9EBkqqRdTckYqSU9Ga fcrakWLXfQCeguLwkXpD8Ww+jmZf5u8rFf/VbCPoywegDqyJECMrkvbw5HB6qPO3tNX+qXspbau WWypPAt6HCss1EUK4ISd3behcqqSY78eZnJV2uCPr+lTszOeWtrz2DAb6XvYVlVciioxrgS4HML VQSlRnd0GZJN+CC3uQ1aIcK+Ze7TFNBLzrzLiInSoQioSfWX7zE7ZJitCATDfdekrxOsnlFP1v9 uhCoMEvPS5w1bpbzCjlDTwYbukqLWXQajuuAHpK/sIKrE2sFwDsotGME2gWqMN9tBkjjL0z/OYx GtX6LW7kGLtPGIKU/Mg== X-Proofpoint-ORIG-GUID: MF2_1p0z6ROQKYABMXHNe9SngUYNQQpc X-Proofpoint-GUID: MF2_1p0z6ROQKYABMXHNe9SngUYNQQpc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-31_06,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 malwarescore=0 phishscore=0 priorityscore=1501 suspectscore=0 spamscore=0 adultscore=0 clxscore=1015 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607310146 Maili gpucc is a derivative of Hawi gpucc with pll0 configuration change. Hence, reuse the Hawi graphics clock controller and extend it for Qualcomm Maili SoC. Signed-off-by: Jagadeesh Kona Reviewed-by: Abel Vesa Reviewed-by: Taniya Das --- drivers/clk/qcom/gpucc-hawi.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/clk/qcom/gpucc-hawi.c b/drivers/clk/qcom/gpucc-hawi.c index 30b3ffb0638fb79e68dbcec66f60ad750768d042..3deb7edf7810ded20ffaa7f56cd= 8c2dbb516f3db 100644 --- a/drivers/clk/qcom/gpucc-hawi.c +++ b/drivers/clk/qcom/gpucc-hawi.c @@ -49,6 +49,18 @@ static const struct alpha_pll_config gpu_cc_pll0_config = =3D { .user_ctl_hi_val =3D 0x00000002, }; =20 +/* 788.0 MHz Configuration */ +static const struct alpha_pll_config gpu_cc_pll0_config_maili =3D { + .l =3D 0x29, + .cal_l =3D 0x42, + .alpha =3D 0xaaa, + .config_ctl_val =3D 0xa5c400e7, + .config_ctl_hi_val =3D 0x0a806160, + .config_ctl_hi1_val =3D 0xf51dea20, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00000002, +}; + static struct clk_alpha_pll gpu_cc_pll0 =3D { .offset =3D 0x0, .config =3D &gpu_cc_pll0_config, @@ -438,12 +450,16 @@ static const struct qcom_cc_desc gpu_cc_hawi_desc =3D= { =20 static const struct of_device_id gpu_cc_hawi_match_table[] =3D { { .compatible =3D "qcom,hawi-gpucc" }, + { .compatible =3D "qcom,maili-gpucc" }, { } }; MODULE_DEVICE_TABLE(of, gpu_cc_hawi_match_table); =20 static int gpu_cc_hawi_probe(struct platform_device *pdev) { + if (device_is_compatible(&pdev->dev, "qcom,maili-gpucc")) + gpu_cc_pll0.config =3D &gpu_cc_pll0_config_maili; + return qcom_cc_probe(pdev, &gpu_cc_hawi_desc); } =20 --=20 2.34.1