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Corruption was also observed in the captured output when the client dumped it to a file. On debugging, this was traced to the venus node not declaring dma-coherent. As a result, DMA buffers shared between the CPU and the venus video hardware/controller are not guaranteed to be I/O coherent: CPU writes to an input buffer can remain in CPU caches without being visible to the video hardware when it reads the same buffer, so the hardware receives input data that does not match what the CPU wrote. Likewise, on the capture path, data written by the video hardware to the output buffer may not be visible to the CPU, so the client reads stale or partial data, resulting in corruption. Add the dma-coherent property to the venus node so that DMA buffers shared between the CPU and the video hardware and controller remain coherent. Fixes: 37613aee2179 ("arm64: dts: qcom: sc7280: Add venus DT node") Cc: stable@vger.kernel.org Signed-off-by: Vishnu Reddy Reviewed-by: Bryan O'Donoghue --- Documentation/devicetree/bindings/media/qcom,sc7280-venus.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/media/qcom,sc7280-venus.yaml= b/Documentation/devicetree/bindings/media/qcom,sc7280-venus.yaml index 9725fcb761dc..cc31f3ba7e7e 100644 --- a/Documentation/devicetree/bindings/media/qcom,sc7280-venus.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sc7280-venus.yaml @@ -42,6 +42,8 @@ properties: - const: vcodec_core - const: vcodec_bus =20 + dma-coherent: true + iommus: maxItems: 1 =20 @@ -85,6 +87,7 @@ properties: =20 required: - compatible + - dma-coherent - power-domain-names - iommus =20 @@ -119,6 +122,8 @@ examples: <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0= >; interconnect-names =3D "cpu-cfg", "video-mem"; =20 + dma-coherent; + iommus =3D <&apps_smmu 0x2180 0x20>; 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Corruption was also observed in the captured output when the client dumped it to a file. On debugging, this was traced to the venus node not declaring dma-coherent. As a result, DMA buffers shared between the CPU and the venus video hardware/controller are not guaranteed to be I/O coherent: CPU writes to an input buffer can remain in CPU caches without being visible to the video hardware when it reads the same buffer, so the hardware receives input data that does not match what the CPU wrote. Likewise, on the capture path, data written by the video hardware to the output buffer may not be visible to the CPU, so the client reads stale or partial data, resulting in corruption. Add the dma-coherent property to the venus node so that DMA buffers shared between the CPU and the video hardware and controller remain coherent. Fixes: 37613aee2179 ("arm64: dts: qcom: sc7280: Add venus DT node") Cc: stable@vger.kernel.org Signed-off-by: Vishnu Reddy Reviewed-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qco= m/kodiak.dtsi index f74fa66f1a67..98184760b4bf 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -5024,6 +5024,8 @@ venus: video-codec@aa00000 { <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "cpu-cfg", "video-mem"; =20 + dma-coherent; + iommus =3D <&apps_smmu 0x2180 0x20>; memory-region =3D <&video_mem>; =20 --=20 2.34.1 From nobody Fri Oct 2 11:43:03 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A115C33F8C6 for ; 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This reverses the correct power-down sequence: with the power domain already removed, the subsequent clk_disable_unprepare() calls end up operating on clock-controller hardware that is no longer powered, which can hang or behave unpredictably. Reorder the calls so iris_disable_power_domains() runs after all three clocks are disabled, ensuring clocks are always turned off while their power domain is still active, and mirroring the reverse of the power-on sequence. Fixes: bb8a95aa038e ("media: iris: implement power management") Cc: stable@vger.kernel.org Signed-off-by: Vishnu Reddy Reviewed-by: Bryan O'Donoghue --- drivers/media/platform/qcom/iris/iris_vpu_common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.c index e4847c107709..3cd493b06d84 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -223,10 +223,10 @@ int iris_vpu_power_off_controller(struct iris_core *c= ore) void iris_vpu_power_off_hw(struct iris_core *core) { dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]= , false); - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWE= R_DOMAIN]); iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK); iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK); iris_disable_unprepare_clock(core, IRIS_HW_CLK); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWE= R_DOMAIN]); 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This caused client to enumerate only framerates of the form MAXIMUM_FPS/n (where n is a positive integer), restricting support to exact divisors of MAXIMUM_FPS (e.g., 480, 240, 160, 120, 96, 80, 60, 30, 24, 1). Framerates that are not exact divisors of MAXIMUM_FPS, such as 29 fps, 25 fps, were excluded from the enumerated list. There is no hardware restriction to framerates that are exact divisors of MAXIMUM_FPS. This caused GStreamer caps negotiation to fail with an "internal data stream error" when encoding content at such framerates. Fix this by using V4L2_FRMIVAL_TYPE_CONTINUOUS. With CONTINUOUS type, GStreamer creates a continuous framerate range [1, max_fps], allowing any integer framerate within the range to pass caps negotiation. The step field is set to 1/1 as required by the V4L2 specification for continuous frame intervals. Fixes: a6882431a138 ("media: iris: Add support for ENUM_FRAMESIZES/FRAMEINT= ERVALS for encoder") Cc: stable@vger.kernel.org Signed-off-by: Vishnu Reddy Reviewed-by: Bryan O'Donoghue --- drivers/media/platform/qcom/iris/iris_vidc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/p= latform/qcom/iris/iris_vidc.c index fcbc60016bee..8f20cb281a93 100644 --- a/drivers/media/platform/qcom/iris/iris_vidc.c +++ b/drivers/media/platform/qcom/iris/iris_vidc.c @@ -438,14 +438,14 @@ static int iris_enum_frameintervals(struct file *filp= , void *fh, mbpf =3D NUM_MBS_PER_FRAME(fival->height, fival->width); fps =3D DIV_ROUND_UP(core->iris_platform_data->max_core_mbps, mbpf); =20 - fival->type =3D V4L2_FRMIVAL_TYPE_STEPWISE; + fival->type =3D V4L2_FRMIVAL_TYPE_CONTINUOUS; fival->stepwise.min.numerator =3D 1; fival->stepwise.min.denominator =3D min_t(u32, fps, MAXIMUM_FPS); fival->stepwise.max.numerator =3D 1; fival->stepwise.max.denominator =3D 1; fival->stepwise.step.numerator =3D 1; - fival->stepwise.step.denominator =3D MAXIMUM_FPS; + fival->stepwise.step.denominator =3D 1; =20 return 0; } --=20 2.34.1