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Fri, 31 Jul 2026 12:45:41 -0700 (PDT) Received: from hu-jkona-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3153ddda5d9sm11489915eec.13.2026.07.31.12.45.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Jul 2026 12:45:40 -0700 (PDT) From: Jagadeesh Kona Date: Sat, 01 Aug 2026 01:15:07 +0530 Subject: [PATCH] clk: qcom: Fix camera rivian PLL configuration settings Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260801-cam-rivian-pll-config-fix-v1-1-6918d58cd823@oss.qualcomm.com> X-B4-Tracking: v=1; b=H4sIAEL7bGoC/x2MWwqAIBAArxL73YKJPa8SfZittlAmChGEd0/6n IGZFxJFpgRT9UKkmxNfvkBTV2B27R0hb4VBCtmJXo5o9ImRb9Yew3Ggubxlh5YfpFavalBqFd0 GpQ+Riv7f85LzBwOGvbtrAAAA X-Change-ID: 20260729-cam-rivian-pll-config-fix-e5ab4844b06d To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Maxime Coquelin , Alexandre Torgue , Konrad Dybcio , Taniya Das , Vladimir Zapolskiy , Dmitry Baryshkov , Bryan O'Donoghue , Jingyi Wang Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jagadeesh Kona X-Mailer: b4 0.14.2 X-Proofpoint-ORIG-GUID: tsbwaE2IlqJTcwyoj-CxZjMl32B1ZnjD X-Proofpoint-GUID: tsbwaE2IlqJTcwyoj-CxZjMl32B1ZnjD X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzMxMDE1MCBTYWx0ZWRfXwa7EVLNeFreB JlHqSR8X6tUBESuWcOR4pDRIhKpJCymQYUj0YOxPiipdkI2G6lT86xw9V4IMXrhFRF12lDF1Izd oEcL7L+j2Gx1KEdZyWj5ouT5Pb0JKUL6WqWZQ0TeyRMgn10WtMECZbJkj3ryWRmQoJYggPRnMaR 82EWN8zLR+OCOZo0OSWnqAmokWZpvZA2MpATEInWC+sgGkWHVZ3aXPbI+tvt6MJNmjdqev1qUt/ OASQnObHMeYOfS5ZRdIqi3NTmbvUJ0dDtsalv65WJ7SgRrqHQF4tPSmh0n1ewLx8iHpTcGnrEWy 7s16pJI/k8QpV697JE8VE96ikeKLjUlBAE/EJNw5wCyqmsXVcbabUHITQqmIk0vJrvN0jnnb5ZK TjOuq8wzFo7236QxXvSh4zU2cyc8yolXRcK5CZXldUwAnL7Grf9lyf+4BYxx1/Y9p61ANUVmvYy TH6MiHPYaQ9cVrBXgvA== X-Authority-Analysis: v=2.4 cv=SKZykuvH c=1 sm=1 tr=0 ts=6a6cfb66 cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=orJqCwW2HSwFgp0icTcA:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzMxMDE1MCBTYWx0ZWRfXyfhouQWhJtTG t1UU0/lvNCAbWABt+Wa3yrr2mdw+4qw3cwdujaL+AEmM9lC/wixRSa5MFG02LDFA3s70fv1YbCr b/o/AQJzo6a6qg0yzXh41cBLHteX+LU= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-31_06,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 bulkscore=0 malwarescore=0 adultscore=0 impostorscore=0 spamscore=0 suspectscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607310150 clk_alpha_pll_write_config() in the PLL configure function skips writes to PLL registers when the configured value is 0. However, hardware requires USER_CTL_U and CONFIG_CTL_U2 to be explicitly programmed to 0 for a few rivian PLLs. Add a clk_regs_configure() callback to ensure these rivian PLL registers are correctly initialized on Glymur, SM8750, and Kaanapali platforms. Fixes: 97255eedd690 ("clk: qcom: camcc-glymur: Add camera clock controller = driver") Fixes: f9580bafd39c ("clk: qcom: camcc: Add camera clock controller driver = for SM8750 SoC") Fixes: 92aae35f667c ("clk: qcom: camcc: Add support for camera clock contro= ller for Kaanapali") Signed-off-by: Jagadeesh Kona Reviewed-by: Taniya Das --- drivers/clk/qcom/cambistmclkcc-kaanapali.c | 7 +++++++ drivers/clk/qcom/cambistmclkcc-sm8750.c | 7 +++++++ drivers/clk/qcom/camcc-glymur.c | 7 +++++++ 3 files changed, 21 insertions(+) diff --git a/drivers/clk/qcom/cambistmclkcc-kaanapali.c b/drivers/clk/qcom/= cambistmclkcc-kaanapali.c index c96e9196d908e5d20f24ecaf94393633f63b6ab6..b5bafc1e7d428567cfec1eaf3c0= 44bfe90059151 100644 --- a/drivers/clk/qcom/cambistmclkcc-kaanapali.c +++ b/drivers/clk/qcom/cambistmclkcc-kaanapali.c @@ -394,11 +394,18 @@ static const struct regmap_config cam_bist_mclk_cc_ka= anapali_regmap_config =3D { .fast_io =3D true, }; =20 +static void cam_bist_mclk_cc_kaanapali_regs_configure(struct device *dev, = struct regmap *regmap) +{ + regmap_write(regmap, 0x18, 0); /* CAM_BIST_MCLK_CC_PLL0_USER_CTL_U */ + regmap_write(regmap, 0x28, 0); /* CAM_BIST_MCLK_CC_PLL0_CONFIG_CTL_U2 */ +} + static const struct qcom_cc_driver_data cam_bist_mclk_cc_kaanapali_driver_= data =3D { .alpha_plls =3D cam_bist_mclk_cc_kaanapali_plls, .num_alpha_plls =3D ARRAY_SIZE(cam_bist_mclk_cc_kaanapali_plls), .clk_cbcrs =3D cam_bist_mclk_cc_kaanapali_critical_cbcrs, .num_clk_cbcrs =3D ARRAY_SIZE(cam_bist_mclk_cc_kaanapali_critical_cbcrs), + .clk_regs_configure =3D cam_bist_mclk_cc_kaanapali_regs_configure, }; =20 static const struct qcom_cc_desc cam_bist_mclk_cc_kaanapali_desc =3D { diff --git a/drivers/clk/qcom/cambistmclkcc-sm8750.c b/drivers/clk/qcom/cam= bistmclkcc-sm8750.c index 69abb756c04f2afba45db2dd371ee12f7b4366e4..45788ddb9dcc62a7c5d8efe086a= 235a337a18a05 100644 --- a/drivers/clk/qcom/cambistmclkcc-sm8750.c +++ b/drivers/clk/qcom/cambistmclkcc-sm8750.c @@ -413,11 +413,18 @@ static const struct regmap_config cam_bist_mclk_cc_sm= 8750_regmap_config =3D { .fast_io =3D true, }; =20 +static void cam_bist_mclk_cc_sm8750_regs_configure(struct device *dev, str= uct regmap *regmap) +{ + regmap_write(regmap, 0x18, 0); /* CAM_BIST_MCLK_CC_PLL0_USER_CTL_U */ + regmap_write(regmap, 0x28, 0); /* CAM_BIST_MCLK_CC_PLL0_CONFIG_CTL_U2 */ +} + static const struct qcom_cc_driver_data cam_bist_mclk_cc_sm8750_driver_dat= a =3D { .alpha_plls =3D cam_bist_mclk_cc_sm8750_plls, .num_alpha_plls =3D ARRAY_SIZE(cam_bist_mclk_cc_sm8750_plls), .clk_cbcrs =3D cam_bist_mclk_cc_sm8750_critical_cbcrs, .num_clk_cbcrs =3D ARRAY_SIZE(cam_bist_mclk_cc_sm8750_critical_cbcrs), + .clk_regs_configure =3D cam_bist_mclk_cc_sm8750_regs_configure, }; =20 static const struct qcom_cc_desc cam_bist_mclk_cc_sm8750_desc =3D { diff --git a/drivers/clk/qcom/camcc-glymur.c b/drivers/clk/qcom/camcc-glymu= r.c index 81c1e102b110e5baca82db42bb0479d8db28db1c..6d022bbd2ce2ef5a7040abc2d5e= fe806ea45f0d9 100644 --- a/drivers/clk/qcom/camcc-glymur.c +++ b/drivers/clk/qcom/camcc-glymur.c @@ -2235,11 +2235,18 @@ static const struct regmap_config cam_cc_glymur_reg= map_config =3D { .fast_io =3D true, }; =20 +static void cam_cc_glymur_regs_configure(struct device *dev, struct regmap= *regmap) +{ + regmap_write(regmap, 0x2018, 0); /* CAM_CC_PLL2_PLL_USER_CTL_U */ + regmap_write(regmap, 0x2028, 0); /* CAM_CC_PLL2_PLL_CONFIG_CTL_U2 */ +} + static const struct qcom_cc_driver_data cam_cc_glymur_driver_data =3D { .alpha_plls =3D cam_cc_glymur_plls, .num_alpha_plls =3D ARRAY_SIZE(cam_cc_glymur_plls), .clk_cbcrs =3D cam_cc_glymur_critical_cbcrs, .num_clk_cbcrs =3D ARRAY_SIZE(cam_cc_glymur_critical_cbcrs), + .clk_regs_configure =3D cam_cc_glymur_regs_configure, }; =20 static const struct qcom_cc_desc cam_cc_glymur_desc =3D { --- base-commit: 415606a7be939835db9b0d6b711887586646346d change-id: 20260729-cam-rivian-pll-config-fix-e5ab4844b06d Best regards, --=20 Jagadeesh Kona