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charset="utf-8" Enable the HSMP driver on the Family 1Ah client platforms, Models 80h-8Fh and E0h-E3h. These parts speak the Ryzen Master SMC (RMSMC) message set rather than the server message IDs, and they reach their mailbox over SMN rather than through the MMIO window the server ACPI path uses: their ACPI device carries no _CRS describing a window and no _DSD naming the registers, so the client addresses are fixed in hsmp.h instead of being discovered. Only the ACPI driver probes these models; the platform driver keeps to the server parts it already supported. Add the client message set and its descriptor table to the UAPI header. With two descriptor tables, every lookup has to pick the one matching the running platform. Describe the platform once rather than test it at each lookup: struct hsmp_plat_desc holds the mailbox addresses, the descriptor table and its size, and the IDs of the messages the driver issues itself. hsmp_common_init() resolves it once, before the drivers that depend on this module can probe, and the message plumbing reads the bound and the message IDs from there. The server descriptor is also the static initialiser, so that plumbing cannot reach a NULL descriptor. static_assert() ties each table's length to its message-ID enum so the two cannot drift apart. Documentation/arch/x86/amd_hsmp.rst gains the client models. The character device and ioctl interface are unchanged there; only the accepted message IDs differ. Signed-off-by: Muralidhara M K --- Documentation/arch/x86/amd_hsmp.rst | 10 +- arch/x86/include/uapi/asm/amd_hsmp.h | 289 +++++++++++++++++++++++++++ drivers/platform/x86/amd/hsmp/hsmp.c | 153 +++++++++++--- drivers/platform/x86/amd/hsmp/hsmp.h | 71 +++++++ drivers/platform/x86/amd/hsmp/plat.c | 19 +- 5 files changed, 496 insertions(+), 46 deletions(-) diff --git a/Documentation/arch/x86/amd_hsmp.rst b/Documentation/arch/x86/a= md_hsmp.rst index fa1fc240e212..b95f09945193 100644 --- a/Documentation/arch/x86/amd_hsmp.rst +++ b/Documentation/arch/x86/amd_hsmp.rst @@ -8,6 +8,13 @@ Newer Fam19h(model 0x00-0x1f, 0x30-0x3f, 0x90-0x9f, 0xa0-0= xaf), Fam1Ah(model 0x00-0x1f) EPYC server line of processors from AMD support system management functionality via HSMP (Host System Management Port). =20 +The Fam1Ah(model 0x80-0x8f, 0xe0-0xe3) client line of processors is +supported as well. Those models share one mailbox and speak the Ryzen +Master SMC message set instead of the server HSMP message set, so the +message IDs accepted on them are the HSMP_CLIENT_* ones listed in +arch/x86/include/uapi/asm/amd_hsmp.h. The character device and ioctl +interface described below are the same. + The Host System Management Port (HSMP) is an interface to provide OS-level software with access to system management functions via a set of mailbox registers. @@ -17,7 +24,8 @@ More details on the interface can be found in chapter Eg: https://docs.amd.com/v/u/en-US/55898_B1_pub_0_50 =20 =20 -HSMP interface is supported on EPYC line of server CPUs and MI300A (APU). +HSMP interface is supported on EPYC line of server CPUs, MI300A (APU) and +the Fam1Ah client models listed above. =20 =20 HSMP device diff --git a/arch/x86/include/uapi/asm/amd_hsmp.h b/arch/x86/include/uapi/a= sm/amd_hsmp.h index eda336bfd3e9..44c2b33434b0 100644 --- a/arch/x86/include/uapi/asm/amd_hsmp.h +++ b/arch/x86/include/uapi/asm/amd_hsmp.h @@ -664,4 +664,293 @@ struct hsmp_telemetry_data { #define HSMP_IOCTL_GET_TELEMETRY_DATA \ _IOW(HSMP_BASE_IOCTL_NR, 1, struct hsmp_telemetry_data) =20 +/* + * Client HSMP messages supported on the Family 1Ah client platforms, + * Models 80h-8Fh and E0h-E3h. + * These map to Ryzen Master SMC (RMSMC) message IDs. + */ +enum hsmp_client_message_ids { + HSMP_CLIENT_TEST =3D 1, /* 01h Test message */ + HSMP_CLIENT_GET_SMU_VER, /* 02h Get MP1 firmware version */ + HSMP_CLIENT_GET_INTERFACE_VER, /* 03h Get interface version */ + HSMP_CLIENT_GET_METRICS_TABLE_VER, /* 04h Get metrics table version */ + HSMP_CLIENT_GET_METRICS_TABLE, /* 05h Get metrics table */ + HSMP_CLIENT_GET_METRICS_TABLE_DRAM_ADDR,/* 06h Get metrics table dram add= ress */ + HSMP_CLIENT_SET_CORE_PSM_MARGIN, /* 07h Set core voltage margin */ + HSMP_CLIENT_SET_ALL_CORE_PSM_MARGIN, /* 08h Set voltage margin for all co= res */ + HSMP_CLIENT_SET_FAST_PPT_LIMIT, /* 09h Set APU fast PPT limit */ + HSMP_CLIENT_SET_VRM_VDD_CURRENT_LIMIT, /* 0Ah Set VDDCR_VDD TDC */ + HSMP_CLIENT_SET_VRM_VDD_MAX_CURRENT_LIMIT,/* 0Bh Set VDDCR_VDD EDC */ + HSMP_CLIENT_SET_TJ_MAX, /* 0Ch Set maximum junction temperature */ + HSMP_CLIENT_SET_FIT_LIMIT_SCALAR, /* 0Dh Set failures in time limit scala= r */ + HSMP_CLIENT_ENABLE_OVERCLOCKING, /* 0Eh Enable overclocking */ + HSMP_CLIENT_DISABLE_OVERCLOCKING, /* 0Fh Disable overclocking */ + HSMP_CLIENT_SET_OVERCLOCK_FREQ_ALL_CORES,/* 10h Set all core overclock fr= equency */ + HSMP_CLIENT_SET_OVERCLOCK_FREQ_PER_CORE,/* 11h Set per core overclock fre= quency */ + HSMP_CLIENT_SET_OVERCLOCK_VID, /* 12h Set overclock VID */ + HSMP_CLIENT_SET_FCLK_OVERCLOCK_ON_THE_FLY,/* 13h Set FCLK overclock on th= e fly */ + HSMP_CLIENT_GET_CORE_PERF_ORDER, /* 14h Get core performance order */ + HSMP_CLIENT_SET_SUSTAINED_POWER_LIMIT, /* 15h Set SOC sustained power lim= it */ + HSMP_CLIENT_SET_SLOW_PPT_LIMIT, /* 16h Set APU slow PPT limit */ + HSMP_CLIENT_SET_VRM_GFX_MAX_CURRENT_LIMIT,/* 17h Set VDDCR_GFX EDC */ + HSMP_CLIENT_SET_VRM_SOC_CURRENT_LIMIT, /* 18h Set VDDCR_SOC TDC */ + HSMP_CLIENT_SET_FAST_SPM_LIMIT, /* 19h Set fast SPM limit */ + HSMP_CLIENT_SET_SLOW_SPM_LIMIT, /* 1Ah Set slow SPM limit */ + HSMP_CLIENT_GET_CORE_PSM_MARGIN, /* 1Bh Get core voltage margin */ + HSMP_CLIENT_GET_GFX_PSM_MARGIN, /* 1Ch Get graphics voltage margin */ + HSMP_CLIENT_SPARE_0X1D, /* 1Dh Reserved */ + HSMP_CLIENT_SPARE_0X1E, /* 1Eh Reserved */ + HSMP_CLIENT_SPARE_0X1F, /* 1Fh Reserved */ + HSMP_CLIENT_SPARE_0X20, /* 20h Reserved */ + HSMP_CLIENT_SET_GFXCLK_OVERDRIVE_BY_FREQ_VID,/* 21h Set GfxClk overdrive = by freq/VID */ + HSMP_CLIENT_DISABLE_GFXCLK_OVERDRIVE, /* 22h Disable GfxClk overdrive */ + HSMP_CLIENT_SET_GFX_PSM_MARGIN, /* 23h Set graphics voltage margin */ + HSMP_CLIENT_SET_CCLK_FMAX_OFFSET, /* 24h Set CCLK Fmax offset */ + HSMP_CLIENT_SET_CORE_POWER_LIMIT_OFFSET,/* 25h Set core power limit offse= t */ + HSMP_CLIENT_ADD_EXTRA_PSM_GUARDBAND, /* 26h Add extra core PSM guardband = */ + HSMP_CLIENT_ADD_EXTRA_PSM_GUARDBAND_GFX,/* 27h Add extra graphics PSM gua= rdband */ + HSMP_CLIENT_SET_GFXCLK_FMAX, /* 28h Set GfxClk Fmax */ + HSMP_CLIENT_MSG_ID_MAX, +}; + +/* + * Client message descriptor table (Family 1Ah Models 80h-8Fh, E0h-E3h). + * + * User may use these comments as reference, please find the supported list + * of messages and message definition in the HSMP chapter of respective + * family/model PPR. + * + * Not supported messages would return -ENOMSG. + */ +static const struct hsmp_msg_desc hsmp_client_msg_desc_table[] + __attribute__((unused)) =3D { + /* RESERVED */ + {0, 0, HSMP_RSVD}, + + /* + * HSMP_CLIENT_TEST, num_args =3D 1, response_sz =3D 1 + * input: args[0] =3D xx + * output: args[0] =3D xx + 1 + */ + {1, 1, HSMP_GET}, + + /* + * HSMP_CLIENT_GET_SMU_VER, num_args =3D 0, response_sz =3D 1 + * output: args[0] =3D MP1 fw ver + */ + {0, 1, HSMP_GET}, + + /* + * HSMP_CLIENT_GET_INTERFACE_VER, num_args =3D 0, response_sz =3D 1 + * output: args[0] =3D interface version + */ + {0, 1, HSMP_GET}, + + /* + * HSMP_CLIENT_GET_METRICS_TABLE_VER, num_args =3D 0, response_sz =3D 1 + * output: args[0] =3D metrics table version + */ + {0, 1, HSMP_GET}, + + /* + * HSMP_CLIENT_GET_METRICS_TABLE, num_args =3D 0, response_sz =3D 0 + * Success means firmware has written the metrics table to the DRAM + * address reported by HSMP_CLIENT_GET_METRICS_TABLE_DRAM_ADDR. + */ + {0, 0, HSMP_GET}, + + /* + * HSMP_CLIENT_GET_METRICS_TABLE_DRAM_ADDR, num_args =3D 0, response_sz = =3D 3 + * output: args[0] =3D metrics table dram address[31:0] + * args[1] =3D metrics table dram address[63:32] + * args[2] =3D metrics table size in bytes + */ + {0, 3, HSMP_GET}, + + /* + * HSMP_CLIENT_SET_CORE_PSM_MARGIN, num_args =3D 1, response_sz =3D 0 + * input: args[0] =3D ApicId[31:16] + voltage margin in mV[15:0] + */ + {1, 0, HSMP_SET}, + + /* + * HSMP_CLIENT_SET_ALL_CORE_PSM_MARGIN, num_args =3D 1, response_sz =3D 0 + * input: args[0] =3D voltage margin in mV[15:0] + */ + {1, 0, HSMP_SET}, + + /* + * HSMP_CLIENT_SET_FAST_PPT_LIMIT, num_args =3D 1, response_sz =3D 0 + * input: args[0] =3D fast PPT limit in mW + */ + {1, 0, HSMP_SET}, + + /* + * HSMP_CLIENT_SET_VRM_VDD_CURRENT_LIMIT, num_args =3D 1, response_sz =3D= 0 + * input: args[0] =3D VDDCR_VDD TDC in mA + */ + {1, 0, HSMP_SET}, + + /* + * HSMP_CLIENT_SET_VRM_VDD_MAX_CURRENT_LIMIT, num_args =3D 1, response_sz= =3D 0 + * input: args[0] =3D VDDCR_VDD EDC in mA + */ + {1, 0, HSMP_SET}, + + /* + * HSMP_CLIENT_SET_TJ_MAX, num_args =3D 1, response_sz =3D 0 + * input: args[0] =3D maximum junction temperature in degrees C + */ + {1, 0, HSMP_SET}, + + /* + * HSMP_CLIENT_SET_FIT_LIMIT_SCALAR, num_args =3D 1, response_sz =3D 0 + * input: args[0] =3D failures in time limit scalar (0 to 100) + */ + {1, 0, HSMP_SET}, + + /* HSMP_CLIENT_ENABLE_OVERCLOCKING, num_args =3D 0, response_sz =3D 0 */ + {0, 0, HSMP_SET}, + + /* HSMP_CLIENT_DISABLE_OVERCLOCKING, num_args =3D 0, response_sz =3D 0 */ + {0, 0, HSMP_SET}, + + /* + * HSMP_CLIENT_SET_OVERCLOCK_FREQ_ALL_CORES, num_args =3D 1, response_sz = =3D 0 + * input: args[0] =3D frequency in MHz[15:0] + */ + {1, 0, HSMP_SET}, + + /* + * HSMP_CLIENT_SET_OVERCLOCK_FREQ_PER_CORE, num_args =3D 1, response_sz = =3D 0 + * input: args[0] =3D ApicId[31:16] + frequency in MHz[15:0] + */ + {1, 0, HSMP_SET}, + + /* + * HSMP_CLIENT_SET_OVERCLOCK_VID, num_args =3D 1, response_sz =3D 0 + * input: args[0] =3D voltage in mV[15:0] + */ + {1, 0, HSMP_SET}, + + /* + * HSMP_CLIENT_SET_FCLK_OVERCLOCK_ON_THE_FLY, num_args =3D 1, response_sz= =3D 0 + * input: args[0] =3D FCLK in MHz[15:0] + */ + {1, 0, HSMP_SET}, + + /* + * HSMP_CLIENT_GET_CORE_PERF_ORDER, num_args =3D 1, response_sz =3D 1 + * input: args[0] =3D ApicId[15:0] + * output: args[0] =3D frequency in MHz[15:0] + */ + {1, 1, HSMP_GET}, + + /* + * HSMP_CLIENT_SET_SUSTAINED_POWER_LIMIT, num_args =3D 1, response_sz =3D= 0 + * input: args[0] =3D sustained power limit in mW + */ + {1, 0, HSMP_SET}, + + /* + * HSMP_CLIENT_SET_SLOW_PPT_LIMIT, num_args =3D 1, response_sz =3D 0 + * input: args[0] =3D slow PPT limit in mW + */ + {1, 0, HSMP_SET}, + + /* + * HSMP_CLIENT_SET_VRM_GFX_MAX_CURRENT_LIMIT, num_args =3D 1, response_sz= =3D 0 + * input: args[0] =3D VDDCR_GFX EDC in mA + */ + {1, 0, HSMP_SET}, + + /* + * HSMP_CLIENT_SET_VRM_SOC_CURRENT_LIMIT, num_args =3D 1, response_sz =3D= 0 + * input: args[0] =3D VDDCR_SOC TDC in mA + */ + {1, 0, HSMP_SET}, + + /* + * HSMP_CLIENT_SET_FAST_SPM_LIMIT, num_args =3D 1, response_sz =3D 0 + * input: args[0] =3D fast SPM limit in mW + */ + {1, 0, HSMP_SET}, + + /* + * HSMP_CLIENT_SET_SLOW_SPM_LIMIT, num_args =3D 1, response_sz =3D 0 + * input: args[0] =3D slow SPM limit in mW + */ + {1, 0, HSMP_SET}, + + /* + * HSMP_CLIENT_GET_CORE_PSM_MARGIN, num_args =3D 1, response_sz =3D 1 + * input: args[0] =3D ApicId[15:0] + * output: args[0] =3D voltage margin in mV[15:0] + */ + {1, 1, HSMP_GET}, + + /* + * HSMP_CLIENT_GET_GFX_PSM_MARGIN, num_args =3D 0, response_sz =3D 1 + * output: args[0] =3D voltage margin in mV[15:0] + */ + {0, 1, HSMP_GET}, + + /* HSMP_CLIENT_SPARE_0X1D */ + {0, 0, HSMP_RSVD}, + + /* HSMP_CLIENT_SPARE_0X1E */ + {0, 0, HSMP_RSVD}, + + /* HSMP_CLIENT_SPARE_0X1F */ + {0, 0, HSMP_RSVD}, + + /* HSMP_CLIENT_SPARE_0X20 */ + {0, 0, HSMP_RSVD}, + + /* + * HSMP_CLIENT_SET_GFXCLK_OVERDRIVE_BY_FREQ_VID, num_args =3D 1, response= _sz =3D 0 + * input: args[0] =3D frequency in MHz[31:16] + voltage in mV[15:0] + */ + {1, 0, HSMP_SET}, + + /* HSMP_CLIENT_DISABLE_GFXCLK_OVERDRIVE, num_args =3D 0, response_sz =3D = 0 */ + {0, 0, HSMP_SET}, + + /* + * HSMP_CLIENT_SET_GFX_PSM_MARGIN, num_args =3D 1, response_sz =3D 0 + * input: args[0] =3D voltage margin in mV[15:0] + */ + {1, 0, HSMP_SET}, + + /* + * HSMP_CLIENT_SET_CCLK_FMAX_OFFSET, num_args =3D 1, response_sz =3D 0 + * input: args[0] =3D maximum frequency in MHz[15:0] + */ + {1, 0, HSMP_SET}, + + /* + * HSMP_CLIENT_SET_CORE_POWER_LIMIT_OFFSET, num_args =3D 1, response_sz = =3D 0 + * input: args[0] =3D core power limit in mW + */ + {1, 0, HSMP_SET}, + + /* + * HSMP_CLIENT_ADD_EXTRA_PSM_GUARDBAND, num_args =3D 1, response_sz =3D 0 + * input: args[0] =3D voltage in mV[15:0] + */ + {1, 0, HSMP_SET}, + + /* + * HSMP_CLIENT_ADD_EXTRA_PSM_GUARDBAND_GFX, num_args =3D 1, response_sz = =3D 0 + * input: args[0] =3D voltage in mV[15:0] + */ + {1, 0, HSMP_SET}, + + /* + * HSMP_CLIENT_SET_GFXCLK_FMAX, num_args =3D 1, response_sz =3D 0 + * input: args[0] =3D maximum frequency in MHz[15:0] + */ + {1, 0, HSMP_SET}, +}; + #endif /*_ASM_X86_AMD_HSMP_H_*/ diff --git a/drivers/platform/x86/amd/hsmp/hsmp.c b/drivers/platform/x86/am= d/hsmp/hsmp.c index 5e123a4ecea9..5cb2c4399043 100644 --- a/drivers/platform/x86/amd/hsmp/hsmp.c +++ b/drivers/platform/x86/amd/hsmp/hsmp.c @@ -10,6 +10,8 @@ #include =20 #include +#include +#include #include #include #include @@ -45,7 +47,76 @@ */ #define CHECK_GET_BIT BIT(31) =20 -static struct hsmp_plat_device hsmp_pdev; +static const struct hsmp_mbaddr_info hsmp_mbinfo_server =3D { + .base_addr =3D SMN_HSMP_BASE, + .msg_id_off =3D SMN_HSMP_MSG_ID, + .msg_resp_off =3D SMN_HSMP_MSG_RESP, + .msg_arg_off =3D SMN_HSMP_MSG_DATA, +}; + +/* RM: Ryzen Master, the SMC interface these client addresses belong to */ +static const struct hsmp_mbaddr_info hsmp_mbinfo_client =3D { + .base_addr =3D SMN_HSMP_BASE_RM, + .msg_id_off =3D SMN_HSMP_MSG_ID_RM, + .msg_resp_off =3D SMN_HSMP_MSG_RESP_RM, + .msg_arg_off =3D SMN_HSMP_MSG_DATA_RM, +}; + +/* + * Each table is indexed by message ID and must therefore have one entry p= er + * ID its enum defines, including the reserved ID 0. Tie the two together= so + * that a message added to one without the other fails the build here rath= er + * than reading past the table at runtime. + */ +static_assert(ARRAY_SIZE(hsmp_msg_desc_table) =3D=3D HSMP_MSG_ID_MAX); +static_assert(ARRAY_SIZE(hsmp_client_msg_desc_table) =3D=3D HSMP_CLIENT_MS= G_ID_MAX); + +/* + * The descriptors carry only the message IDs the driver issues itself, wh= ich + * are also the only ones the two message sets have in common. Messages n= amed + * by userspace in an ioctl need no entry here, as that path already resol= ves + * the ID against the running platform's table. + */ +static const struct hsmp_plat_desc hsmp_desc_server =3D { + .mbinfo =3D &hsmp_mbinfo_server, + .msg_desc =3D hsmp_msg_desc_table, + .num_msgs =3D HSMP_MSG_ID_MAX, + .test_msg =3D HSMP_TEST, + .proto_ver_msg =3D HSMP_GET_PROTO_VER, +}; + +/* The client drives a different mailbox with the Ryzen Master SMC message= set */ +static const struct hsmp_plat_desc hsmp_desc_client =3D { + .mbinfo =3D &hsmp_mbinfo_client, + .msg_desc =3D hsmp_client_msg_desc_table, + .num_msgs =3D HSMP_CLIENT_MSG_ID_MAX, + .test_msg =3D HSMP_CLIENT_TEST, + .proto_ver_msg =3D HSMP_CLIENT_GET_INTERFACE_VER, +}; + +static struct hsmp_plat_device hsmp_pdev =3D { + /* Overridden for the client in hsmp_common_init() */ + .desc =3D &hsmp_desc_server, +}; + +/* + * Look up a message in the running platform's table. Returns NULL for an= ID + * the table does not describe, either because it is out of range or becau= se + * the entry is reserved. Both are reachable from the ioctl, so the caller + * decides whether a miss is a userspace error or a driver bug. + */ +static inline const struct hsmp_msg_desc *get_msg_desc(u32 msg_id) +{ + const struct hsmp_plat_desc *desc =3D hsmp_pdev.desc; + + if (msg_id >=3D desc->num_msgs) + return NULL; + + if (desc->msg_desc[msg_id].type =3D=3D HSMP_RSVD) + return NULL; + + return &desc->msg_desc[msg_id]; +} =20 /* * Gates the AMD HSMP data plane against socket bring-up and teardown. @@ -184,30 +255,29 @@ static int __hsmp_send_message(struct hsmp_socket *so= ck, struct hsmp_message *ms =20 static int validate_message(struct hsmp_message *msg) { - /* msg_id against valid range of message IDs */ - if (msg->msg_id < HSMP_TEST || msg->msg_id >=3D HSMP_MSG_ID_MAX) - return -ENOMSG; + const struct hsmp_msg_desc *desc; =20 - /* msg_id is a reserved message ID */ - if (hsmp_msg_desc_table[msg->msg_id].type =3D=3D HSMP_RSVD) + /* Unknown or reserved message ID for this platform */ + desc =3D get_msg_desc(msg->msg_id); + if (!desc) return -ENOMSG; =20 /* * num_args passed by user should match the num_args specified in * message description table. */ - if (msg->num_args !=3D hsmp_msg_desc_table[msg->msg_id].num_args) + if (msg->num_args !=3D desc->num_args) return -EINVAL; =20 /* * As the HSMP protocol evolves, newer platforms may define more * response arguments for existing messages. Use an upper-bound * check so that older userspace callers requesting fewer response - * words than what the current hsmp_msg_desc_table[] defines are - * still accepted, while rejecting requests that exceed the - * hardware capability. + * words than what the current descriptor table defines are still + * accepted, while rejecting requests that exceed the hardware + * capability. */ - if (msg->response_sz > hsmp_msg_desc_table[msg->msg_id].response_sz) + if (msg->response_sz > desc->response_sz) return -EINVAL; =20 return 0; @@ -316,7 +386,7 @@ int hsmp_test(u16 sock_ind, u32 value) * Test the hsmp port by performing TEST command. The test message * takes one argument and returns the value of that argument + 1. */ - msg.msg_id =3D HSMP_TEST; + msg.msg_id =3D hsmp_pdev.desc->test_msg; msg.num_args =3D 1; msg.response_sz =3D 1; msg.args[0] =3D value; @@ -338,12 +408,12 @@ int hsmp_test(u16 sock_ind, u32 value) } EXPORT_SYMBOL_NS_GPL(hsmp_test, "AMD_HSMP"); =20 -static bool is_get_msg(struct hsmp_message *msg) +static bool is_get_msg(const struct hsmp_msg_desc *desc, struct hsmp_messa= ge *msg) { - if (hsmp_msg_desc_table[msg->msg_id].type =3D=3D HSMP_GET) + if (desc->type =3D=3D HSMP_GET) return true; =20 - if (hsmp_msg_desc_table[msg->msg_id].type =3D=3D HSMP_SET_GET && + if (desc->type =3D=3D HSMP_SET_GET && (msg->args[0] & CHECK_GET_BIT)) return true; =20 @@ -354,6 +424,7 @@ static long hsmp_ioctl_msg(struct file *fp, unsigned lo= ng arg) { int __user *arguser =3D (int __user *)arg; struct hsmp_message msg =3D { 0 }; + const struct hsmp_msg_desc *desc; int ret; =20 if (copy_struct_from_user(&msg, sizeof(msg), arguser, sizeof(struct hsmp_= message))) @@ -361,23 +432,26 @@ static long hsmp_ioctl_msg(struct file *fp, unsigned = long arg) =20 /* * Check msg_id is within the range of supported msg ids - * i.e within the array bounds of hsmp_msg_desc_table + * i.e within the array bounds of the platform's descriptor table */ - if (msg.msg_id < HSMP_TEST || msg.msg_id >=3D HSMP_MSG_ID_MAX) + if (msg.msg_id < hsmp_pdev.desc->test_msg || + msg.msg_id >=3D hsmp_pdev.desc->num_msgs) return -ENOMSG; =20 /* * Sanitize the user-controlled msg_id against speculative * execution. The bounds check above retires the out-of-range * case with -ENOMSG, but a mispredicted branch can still let the - * CPU speculatively use msg_id as an index into - * hsmp_msg_desc_table[] (here and in validate_message() / - * is_get_msg() called downstream via hsmp_send_message()), and - * pull arbitrary kernel memory into the cache (Spectre v1, - * CVE-2017-5753). Clamp once into msg.msg_id so every downstream - * dereference sees the sanitized value. + * CPU speculatively use msg_id as an index into the message + * descriptor table, here and again in validate_message() called + * downstream via hsmp_send_message(). */ - msg.msg_id =3D array_index_nospec(msg.msg_id, HSMP_MSG_ID_MAX); + msg.msg_id =3D array_index_nospec(msg.msg_id, hsmp_pdev.desc->num_msgs); + + /* Rejects the reserved IDs the table describes as such */ + desc =3D get_msg_desc(msg.msg_id); + if (!desc) + return -ENOMSG; =20 switch (fp->f_mode & (FMODE_WRITE | FMODE_READ)) { case FMODE_WRITE: @@ -385,7 +459,7 @@ static long hsmp_ioctl_msg(struct file *fp, unsigned lo= ng arg) * Device is opened in O_WRONLY mode * Execute only set/configure commands */ - if (is_get_msg(&msg)) + if (is_get_msg(desc, &msg)) return -EPERM; break; case FMODE_READ: @@ -393,7 +467,7 @@ static long hsmp_ioctl_msg(struct file *fp, unsigned lo= ng arg) * Device is opened in O_RDONLY mode * Execute only get/monitor commands */ - if (!is_get_msg(&msg)) + if (!is_get_msg(desc, &msg)) return -EPERM; break; case FMODE_READ | FMODE_WRITE: @@ -410,7 +484,7 @@ static long hsmp_ioctl_msg(struct file *fp, unsigned lo= ng arg) if (ret) return ret; =20 - if (hsmp_msg_desc_table[msg.msg_id].response_sz > 0) { + if (desc->response_sz > 0) { /* Copy results back to user for get/monitor commands */ if (copy_to_user(arguser, &msg, sizeof(struct hsmp_message))) return -EFAULT; @@ -685,11 +759,16 @@ EXPORT_SYMBOL_NS_GPL(hsmp_get_tbl_dram_base, "AMD_HSM= P"); int hsmp_cache_proto_ver(u16 sock_ind) { struct hsmp_message msg =3D { 0 }; + const struct hsmp_msg_desc *desc; int ret; =20 - msg.msg_id =3D HSMP_GET_PROTO_VER; + desc =3D get_msg_desc(hsmp_pdev.desc->proto_ver_msg); + if (WARN_ON(!desc)) + return -ENOMSG; + + msg.msg_id =3D hsmp_pdev.desc->proto_ver_msg; msg.sock_ind =3D sock_ind; - msg.response_sz =3D hsmp_msg_desc_table[HSMP_GET_PROTO_VER].response_sz; + msg.response_sz =3D desc->response_sz; =20 ret =3D hsmp_send_message_locked(&msg); if (!ret) @@ -739,6 +818,22 @@ struct hsmp_plat_device *get_hsmp_pdev(void) } EXPORT_SYMBOL_NS_GPL(get_hsmp_pdev, "AMD_HSMP"); =20 +static int __init hsmp_common_init(void) +{ + /* + * The CPU this selects on is fixed long before anything can call in + * here, and this module initializes before the platform and ACPI + * drivers that depend on it, so resolving the description once is + * enough to have it in place for every mailbox access, including the + * ones the probe paths make themselves. + */ + if (is_client_platform()) + hsmp_pdev.desc =3D &hsmp_desc_client; + + return 0; +} +module_init(hsmp_common_init); + MODULE_DESCRIPTION("AMD HSMP Common driver"); MODULE_VERSION(DRIVER_VERSION); MODULE_LICENSE("GPL"); diff --git a/drivers/platform/x86/amd/hsmp/hsmp.h b/drivers/platform/x86/am= d/hsmp/hsmp.h index 8dbff16a87b1..3e7814f26635 100644 --- a/drivers/platform/x86/amd/hsmp/hsmp.h +++ b/drivers/platform/x86/amd/hsmp/hsmp.h @@ -10,6 +10,8 @@ #ifndef HSMP_H #define HSMP_H =20 +#include + #include #include #include @@ -17,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -32,6 +35,49 @@ =20 #define DRIVER_VERSION "2.6" =20 +/* + * To access a specific HSMP mailbox register, s/w writes the SMN address = of the + * HSMP mailbox register into the SMN_INDEX register, and reads/writes the + * SMN_DATA reg. Below are the SMN addresses of the HSMP mailbox register= s in + * SMU address space, as consumed by the fixed mailbox descriptors in hsmp= .c. + * + * The server set is used by the non-ACPI path only; the ACPI path discove= rs the + * equivalent values from _CRS/_DSD. The _RM set is the client one, named= for + * the Ryzen Master SMC (RMSMC) interface whose mailbox it addresses, and = is + * used by the ACPI path alone: client parts probe through ACPI only, and = their + * ACPI device exposes no _CRS/_DSD to discover the values from. The two = sets + * share a base and differ only in the register offsets behind it, but are= kept + * separate so each stays tied to the platform it was documented for. + */ +#define SMN_HSMP_BASE 0x03B00000 +#define SMN_HSMP_MSG_ID 0x00010534 +#define SMN_HSMP_MSG_ID_F1A_M0H 0x00010934 +#define SMN_HSMP_MSG_RESP 0x00010980 +#define SMN_HSMP_MSG_DATA 0x000109E0 + +/* _RM: Ryzen Master SMC, the client mailbox */ +#define SMN_HSMP_BASE_RM 0x03B00000 +#define SMN_HSMP_MSG_ID_RM 0x00010A8C +#define SMN_HSMP_MSG_RESP_RM 0x00010A90 +#define SMN_HSMP_MSG_DATA_RM 0x00010A94 + +static inline bool is_client_platform(void) +{ + if (boot_cpu_data.x86_vendor !=3D X86_VENDOR_AMD) + return false; + + if (boot_cpu_data.x86 !=3D 0x1A) + return false; + + switch (boot_cpu_data.x86_model) { + case 0x80 ... 0x8F: + case 0xE0 ... 0xE3: + return true; + default: + return false; + } +} + struct hsmp_mbaddr_info { u32 base_addr; u32 msg_id_off; @@ -40,6 +86,30 @@ struct hsmp_mbaddr_info { u32 size; }; =20 +/** + * struct hsmp_plat_desc - Per-platform mailbox and message set description + * @mbinfo: fixed SMN mailbox addresses. The ACPI path uses these + * only where firmware exposes no _CRS/_DSD to read them + * from, i.e. on the client. + * @msg_desc: message descriptor table, indexed by message ID. + * @num_msgs: number of entries in @msg_desc, and so the exclusive + * upper bound on a valid message ID. + * @test_msg: no-op message used to probe the mailbox. Also the + * lowest valid message ID, as ID 0 is reserved. + * @proto_ver_msg: returns the interface version. + * + * Resolved once from the running CPU and reached through hsmp_pdev->desc,= so + * neither the message plumbing nor the probe paths have to re-derive which + * platform they are on. + */ +struct hsmp_plat_desc { + const struct hsmp_mbaddr_info *mbinfo; + const struct hsmp_msg_desc *msg_desc; + u32 num_msgs; + u32 test_msg; + u32 proto_ver_msg; +}; + struct hsmp_socket { struct bin_attribute hsmp_attr; struct hsmp_mbaddr_info mbinfo; @@ -59,6 +129,7 @@ struct hsmp_socket { struct hsmp_plat_device { struct miscdevice mdev; struct hsmp_socket *sock; + const struct hsmp_plat_desc *desc; u32 proto_ver; u16 num_sockets; }; diff --git a/drivers/platform/x86/amd/hsmp/plat.c b/drivers/platform/x86/am= d/hsmp/plat.c index e9b2b809c0f5..957deee86d74 100644 --- a/drivers/platform/x86/amd/hsmp/plat.c +++ b/drivers/platform/x86/amd/hsmp/plat.c @@ -29,17 +29,6 @@ =20 #define DRIVER_NAME "amd_hsmp" =20 -/* - * To access specific HSMP mailbox register, s/w writes the SMN address of= HSMP mailbox - * register into the SMN_INDEX register, and reads/writes the SMN_DATA reg. - * Below are required SMN address for HSMP Mailbox register offsets in SMU= address space - */ -#define SMN_HSMP_BASE 0x3B00000 -#define SMN_HSMP_MSG_ID 0x0010534 -#define SMN_HSMP_MSG_ID_F1A_M0H 0x0010934 -#define SMN_HSMP_MSG_RESP 0x0010980 -#define SMN_HSMP_MSG_DATA 0x00109E0 - static struct hsmp_plat_device *hsmp_pdev; =20 static int amd_hsmp_pci_rdwr(struct hsmp_socket *sock, u32 offset, @@ -157,20 +146,18 @@ static int init_platform_device(struct device *dev) sock =3D &hsmp_pdev->sock[i]; sock->sock_ind =3D i; sock->dev =3D dev; - sock->mbinfo.base_addr =3D SMN_HSMP_BASE; sock->amd_hsmp_rdwr =3D amd_hsmp_pci_rdwr; + sock->mbinfo =3D *hsmp_pdev->desc->mbinfo; =20 /* * This is a transitional change from non-ACPI to ACPI, only * family 0x1A, model 0x00 platform is supported for both ACPI and non-A= CPI. + * It is the one part whose message-id register sits at a + * different offset on this path than the descriptor gives. */ if (is_f1a_m0h()) sock->mbinfo.msg_id_off =3D SMN_HSMP_MSG_ID_F1A_M0H; - else - sock->mbinfo.msg_id_off =3D SMN_HSMP_MSG_ID; =20 - sock->mbinfo.msg_resp_off =3D SMN_HSMP_MSG_RESP; - sock->mbinfo.msg_arg_off =3D SMN_HSMP_MSG_DATA; sema_init(&sock->hsmp_sem, 1); =20 /* Test the hsmp interface on each socket */ --=20 2.34.1 From nobody Fri Oct 2 12:20:45 2026 Received: from PH8PR06CU001.outbound.protection.outlook.com (mail-westus3azon11012004.outbound.protection.outlook.com [40.107.209.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3AC3E44B690; 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charset="utf-8" Wire the client metric table and metrics DRAM address messages into the metric table read path for the Family 1Ah client platforms (Models 80h-8Fh and E0h-E3h). The client reaches its metric table through the Ryzen Master SMC message set, so add the two message IDs to struct hsmp_plat_desc and have hsmp_metric_tbl_read_locked() and hsmp_get_tbl_dram_base() take them from there. Unlike the test and version queries, these two are not numbered alike in the two sets - 24h/25h on the server against 05h/06h on the client - which is why they have to come from the descriptor rather than a shared constant. Signed-off-by: Muralidhara M K --- drivers/platform/x86/amd/hsmp/hsmp.c | 16 ++++++++++++---- drivers/platform/x86/amd/hsmp/hsmp.h | 4 ++++ 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/drivers/platform/x86/amd/hsmp/hsmp.c b/drivers/platform/x86/am= d/hsmp/hsmp.c index 5cb2c4399043..345cc2db7f22 100644 --- a/drivers/platform/x86/amd/hsmp/hsmp.c +++ b/drivers/platform/x86/amd/hsmp/hsmp.c @@ -76,6 +76,10 @@ static_assert(ARRAY_SIZE(hsmp_client_msg_desc_table) =3D= =3D HSMP_CLIENT_MSG_ID_MAX); * are also the only ones the two message sets have in common. Messages n= amed * by userspace in an ioctl need no entry here, as that path already resol= ves * the ID against the running platform's table. + * + * Being common does not mean being numbered alike. The test and version + * queries are 01h and 03h in both sets, but the two metric table messages= are + * 24h/25h on the server against 05h/06h on the client. */ static const struct hsmp_plat_desc hsmp_desc_server =3D { .mbinfo =3D &hsmp_mbinfo_server, @@ -83,6 +87,8 @@ static const struct hsmp_plat_desc hsmp_desc_server =3D { .num_msgs =3D HSMP_MSG_ID_MAX, .test_msg =3D HSMP_TEST, .proto_ver_msg =3D HSMP_GET_PROTO_VER, + .metric_tbl_msg =3D HSMP_GET_METRIC_TABLE, + .metric_dram_msg =3D HSMP_GET_METRIC_TABLE_DRAM_ADDR, }; =20 /* The client drives a different mailbox with the Ryzen Master SMC message= set */ @@ -92,6 +98,8 @@ static const struct hsmp_plat_desc hsmp_desc_client =3D { .num_msgs =3D HSMP_CLIENT_MSG_ID_MAX, .test_msg =3D HSMP_CLIENT_TEST, .proto_ver_msg =3D HSMP_CLIENT_GET_INTERFACE_VER, + .metric_tbl_msg =3D HSMP_CLIENT_GET_METRICS_TABLE, + .metric_dram_msg =3D HSMP_CLIENT_GET_METRICS_TABLE_DRAM_ADDR, }; =20 static struct hsmp_plat_device hsmp_pdev =3D { @@ -639,11 +647,11 @@ static ssize_t hsmp_metric_tbl_read_locked(struct hsm= p_socket *sock, char *buf, return -EINVAL; } =20 - msg.msg_id =3D HSMP_GET_METRIC_TABLE; + msg.msg_id =3D hsmp_pdev.desc->metric_tbl_msg; msg.sock_ind =3D sock->sock_ind; =20 /* - * HSMP_GET_METRIC_TABLE makes firmware refill this socket's shared + * The metric table message makes firmware refill this socket's shared * metric DRAM region, which is then copied out below. Hold the * per-socket lock across the fill-and-copy so concurrent readers of the * same socket cannot return a torn snapshot. @@ -709,8 +717,8 @@ int hsmp_get_tbl_dram_base(u16 sock_ind) int ret; =20 msg.sock_ind =3D sock_ind; - msg.response_sz =3D hsmp_msg_desc_table[HSMP_GET_METRIC_TABLE_DRAM_ADDR].= response_sz; - msg.msg_id =3D HSMP_GET_METRIC_TABLE_DRAM_ADDR; + msg.msg_id =3D hsmp_pdev.desc->metric_dram_msg; + msg.response_sz =3D get_msg_desc(msg.msg_id)->response_sz; =20 ret =3D hsmp_send_message_locked(&msg); if (ret) diff --git a/drivers/platform/x86/amd/hsmp/hsmp.h b/drivers/platform/x86/am= d/hsmp/hsmp.h index 3e7814f26635..815804f8054f 100644 --- a/drivers/platform/x86/amd/hsmp/hsmp.h +++ b/drivers/platform/x86/amd/hsmp/hsmp.h @@ -97,6 +97,8 @@ struct hsmp_mbaddr_info { * @test_msg: no-op message used to probe the mailbox. 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charset="utf-8" On the Family 1Ah client platforms (Models 80h-8Fh and E0h-E3h) the ACPI HSMP device (HID AMDI0097) is present but exposes neither a _CRS memory window nor a _DSD mailbox-offset package, and names its socket differently. The missing _CRS decides how the mailbox is reached. On the server it is an MMIO window that firmware describes in _CRS and the driver maps. The client supports no such window; its mailbox sits in SMN register space at the fixed addresses the platform descriptor carries, so reach it with amd_smn_hsmp_rdwr() for both the reads and the writes the handshake needs. Handle the client explicitly: - hsmp_get_uid(): strip the "ID" prefix only when present, so both forms are accepted; kstrtou16() still rejects anything else. - hsmp_parse_acpi_table(): for is_client_platform(), skip _CRS/_DSD and take the fixed client mailbox addresses from the platform descriptor. - init_acpi(): treat the interface-version query as non-fatal on the client and fetch the metric table whatever version was reported. The client branch publishes sock->dev last with smp_store_release(), as the server path does: it is the readiness gate the data plane tests with smp_load_acquire(), so it must not become visible before the accessor and mailbox offsets it depends on. Server behaviour is unchanged. Signed-off-by: Muralidhara M K --- drivers/platform/x86/amd/hsmp/acpi.c | 77 ++++++++++++++++++++++++---- 1 file changed, 68 insertions(+), 9 deletions(-) diff --git a/drivers/platform/x86/amd/hsmp/acpi.c b/drivers/platform/x86/am= d/hsmp/acpi.c index 8257cd1da48e..80a6ede0f0e0 100644 --- a/drivers/platform/x86/amd/hsmp/acpi.c +++ b/drivers/platform/x86/amd/hsmp/acpi.c @@ -10,6 +10,7 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt =20 #include +#include =20 #include #include @@ -71,6 +72,26 @@ static int amd_hsmp_acpi_rdwr(struct hsmp_socket *sock, = u32 offset, return 0; } =20 +/* + * Family 1Ah client platforms (Models 80h-8Fh and E0h-E3h) expose the HSMP + * ACPI device (HID AMDI0097, ACPI path \_SB_.TELD) but, unlike server + * platforms, the device provides neither a _CRS memory window nor a _DSD + * mailbox-offset package. + * + * That difference is what decides how the mailbox is reached. On the ser= ver + * the mailbox is an MMIO window: firmware describes it in _CRS, the driver + * maps it, and every access lands inside a region firmware has vouched fo= r. + * The client has no such window to map, so the mailbox is reached in SMN + * register space instead. + */ + +static int amd_hsmp_acpi_smn_rdwr(struct hsmp_socket *sock, u32 offset, + u32 *value, bool write) +{ + return amd_smn_hsmp_rdwr(sock->sock_ind, sock->mbinfo.base_addr + offset, + value, write); +} + /* This is the UUID used for HSMP */ static const guid_t acpi_hsmp_uuid =3D GUID_INIT(0xb74d619d, 0x5707, 0x48b= d, 0xa6, 0x9f, 0x4e, 0xa2, @@ -89,15 +110,19 @@ static inline int hsmp_get_uid(struct device *dev, u16= *sock_ind) char *uid; =20 /* - * UID (ID00, ID01..IDXX) is used for differentiating sockets, - * read it and strip the "ID" part of it and convert the remaining - * bytes to integer. + * Server firmware differentiates the sockets with "ID00", "ID01".. + * "IDXX", so strip the "ID" before converting the rest. The client + * device carries a bare socket number with no prefix to strip, so + * only skip one when it is actually there. */ uid =3D acpi_device_uid(ACPI_COMPANION(dev)); - if (!uid || strlen(uid) < 3) + if (!uid) return -EINVAL; =20 - return kstrtou16(uid + 2, 10, sock_ind); + if (!strncmp(uid, "ID", 2)) + uid +=3D 2; + + return kstrtou16(uid, 10, sock_ind); } =20 static acpi_status hsmp_resource(struct acpi_resource *res, void *data) @@ -240,12 +265,34 @@ static int hsmp_parse_acpi_table(struct device *dev, = u16 sock_ind) int ret; =20 sock->sock_ind =3D sock_ind; - sock->amd_hsmp_rdwr =3D amd_hsmp_acpi_rdwr; =20 sema_init(&sock->hsmp_sem, 1); =20 dev_set_drvdata(dev, sock); =20 + /* + * On the client platforms the bound ACPI device has no _CRS window to + * map, so take the fixed client SMN mailbox addresses from the + * platform descriptor and reach them over SMN. + */ + if (is_client_platform()) { + sock->amd_hsmp_rdwr =3D amd_hsmp_acpi_smn_rdwr; + sock->mbinfo =3D *hsmp_pdev->desc->mbinfo; + dev_dbg(dev, "Client SMN mailbox at 0x%08x\n", + sock->mbinfo.base_addr); + /* + * Publish sock->dev last, for the same reason as the server + * path below: it is the readiness gate for the data plane, so + * it must not become visible before the accessor and the + * mailbox offsets this socket needs. + */ + smp_store_release(&sock->dev, dev); + + return 0; + } + + sock->amd_hsmp_rdwr =3D amd_hsmp_acpi_rdwr; + /* Read MP1 base address from CRS method */ ret =3D hsmp_read_acpi_crs(dev, sock); if (ret) @@ -553,11 +600,23 @@ static int init_acpi(struct device *dev) =20 ret =3D hsmp_cache_proto_ver(sock_ind); if (ret) { - dev_err(dev, "Failed to read HSMP protocol version\n"); - return ret; + /* + * Some client SMU builds reject the interface-version query + * with "invalid message" even though the mailbox is functional + * (the preceding test message succeeds). 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charset="utf-8" The client models return the Ryzen Master SMC telemetry table, and the driver copies it out without interpreting it. Document the Telemetry Table RM layout, which HSMP_CLIENT_GET_METRICS_TABLE_VER reports as version 5, so that a tool can decode a snapshot from this file. Carry the RM layout as the structure declarations themselves - the array size defines, the per-IOD counters, the per-CCX core counters and the top-level table - rather than as a paraphrase of them, so the file states the byte layout a decoder has to follow. The Public PPR for the model in use stays the reference for the units and encodings, which are firmware defined. Signed-off-by: Muralidhara M K --- Documentation/arch/x86/amd_hsmp.rst | 277 ++++++++++++++++++++++++++++ 1 file changed, 277 insertions(+) diff --git a/Documentation/arch/x86/amd_hsmp.rst b/Documentation/arch/x86/a= md_hsmp.rst index b95f09945193..cf6faba6aa44 100644 --- a/Documentation/arch/x86/amd_hsmp.rst +++ b/Documentation/arch/x86/amd_hsmp.rst @@ -221,9 +221,286 @@ The following IOCTLs are defined: ``sizeof(struct hsmp_metric_table)``. Later version metrics table layout is documented in the Public PPR. =20 + The Family 1Ah client models carry their own telemetry table instead, + described in `Family 1Ah client telemetry table`_ below. + The ioctl would return a non-zero on failure; you can read errno to see what happened. The transaction returns 0 on success. =20 +Family 1Ah client telemetry table +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D +On the Family 1Ah client models the table returned by +``HSMP_CLIENT_GET_METRICS_TABLE`` (05h) uses the Ryzen Master SMC +telemetry layout. Table version 5, as reported by +``HSMP_CLIENT_GET_METRICS_TABLE_VER`` (04h), is the Telemetry Table RM +layout below. ``HSMP_CLIENT_GET_METRICS_TABLE_DRAM_ADDR`` (06h) returns +the DRAM address the SMU writes the table to, and 05h asks it to refill +that region. The driver issues both and copies the table out without +interpreting it. + +Use the telemetry table chapter of the AMD Public PPR for the model in +use as the authoritative reference. + +Telemetry Table RM layout:: + + /* + * Telemetry Table RM (Ryzen Master SMC, F1A Models 80h-8Fh and + * E0h-E3h client) + * + * Layout returned by HSMP_CLIENT_GET_METRICS_TABLE: the SMU writes the + * table into DRAM at the address reported by + * HSMP_CLIENT_GET_METRICS_TABLE_DRAM_ADDR and the driver returns it + * through the HSMP_IOCTL_GET_TELEMETRY_DATA ioctl. The structure + * mirrors the RM spec published with the AMD HSMP telemetry sample + * application. + * Field grouping (SET VOLTAGES, TELEMETRY VOLTAGES, ... ) matches the + * SMU spec; accumulator (*_acc) fields are monotonic counters from + * which consumers derive deltas across two snapshots. Units are + * firmware-defined (typically mW for power, milli-degC for temperatur= e, + * MHz for frequency); see the AMD HSMP/Ryzen Master SMC spec for exact + * unit definitions. + * + * The composition is: + * struct hsmp_telemetry_table_rm + * +-- struct hsmp_telemetry_table_rm_iod iod; + * +-- struct hsmp_telemetry_table_rm_ccx ccx[HSMP_TELEMETRY_RM_= MAX_CCX]; + * + * Spare fields are explicit firmware padding and must be preserved to + * maintain the on-the-wire byte layout. + */ + #define HSMP_TELEMETRY_RM_MAX_CCX 4 + #define HSMP_TELEMETRY_RM_CORES_PER_CCX 12 + #define HSMP_TELEMETRY_RM_FREQ_TABLE_SIZE 8 + #define HSMP_TELEMETRY_RM_NPU_BUSY_DOMAINS 3 + #define HSMP_TELEMETRY_RM_OC_DOMAINS 5 + #define HSMP_TELEMETRY_RM_OC_SUBDOMAINS 5 + #define HSMP_TELEMETRY_RM_OC_GUARDBANDS 3 + + /** + * struct hsmp_telemetry_table_rm_iod - I/O die counters for RM teleme= try. + * + * Populated once per SMU telemetry sample. Accumulator (*_acc) fields + * are monotonic; consumers compute deltas across two snapshots and + * normalise by accumulation_counter. Per-rail limit fields report the + * currently active limit in firmware-defined units. + */ + struct hsmp_telemetry_table_rm_iod { + __u32 accumulation_counter; + + /* SET VOLTAGES */ + __u64 vddcr_set_voltage; + __u64 vddcr_soc_set_voltage; + __u64 vddcr_npu_set_voltage; + __u64 vddcr_lp_set_voltage; + __u64 vddcr_gfx_set_voltage; + __u64 vdd_misc_set_voltage; + + /* TELEMETRY VOLTAGES */ + __u64 vddcr_telemetry_voltage; + __u64 vddcr_soc_telemetry_voltage; + __u64 vddcr_npu_telemetry_voltage; + __u64 vddcr_lp_telemetry_voltage; + __u64 vddcr_gfx_telemetry_voltage; + __u64 vdd_misc_telemetry_voltage; + + /* TELEMETRY POWERS */ + __u64 vddcr_telemetry_power; + __u64 vddcr_soc_telemetry_power; + __u64 vddcr_npu_telemetry_power; + __u64 vddcr_lp_telemetry_power; + __u64 vddcr_gfx_telemetry_power; + __u64 vdd_misc_telemetry_power; + + /* THROTTLERS - FAST PPT */ + __u32 fppt_fused_limit; + __u32 fppt_max_irm_limit; + __u32 fppt_max_pbo_limit; + __u32 fppt_limit; + __u64 fppt_value_acc; + __u32 fppt_residency_acc; + + /* THROTTLERS - SLOW PPT */ + __u32 sppt_fused_limit; + __u32 sppt_max_irm_limit; + __u32 sppt_max_pbo_limit; + __u32 sppt_limit; + __u64 sppt_value_acc; + __u32 sppt_residency_acc; + + /* THROTTLERS - SPL */ + __u32 spl_fused_limit; + __u32 spl_max_irm_limit; + __u32 spl_max_pbo_limit; + __u32 spl_limit; + __u64 spl_value_acc; + __u32 spl_residency_acc; + + /* THROTTLERS - TDC VDDCR */ + __u32 tdc_vddcr_fused_limit; + __u32 tdc_vddcr_max_irm_limit; + __u32 tdc_vddcr_max_pbo_limit; + __u32 tdc_vddcr_limit; + __u64 tdc_vddcr_value_acc; + __u32 tdc_vddcr_residency_acc; + + /* THROTTLERS - TDC VDDCR SOC */ + __u32 tdc_vddcr_soc_fused_limit; + __u32 tdc_vddcr_soc_max_irm_limit; + __u32 tdc_vddcr_soc_max_pbo_limit; + __u32 tdc_vddcr_soc_limit; + __u64 tdc_vddcr_soc_value_acc; + __u32 tdc_vddcr_soc_residency_acc; + + /* THROTTLERS - TDC VDDCR NPU */ + __u32 tdc_vddcr_npu_fused_limit; + __u32 tdc_vddcr_npu_max_irm_limit; + __u32 tdc_vddcr_npu_max_pbo_limit; + __u32 tdc_vddcr_npu_limit; + __u64 tdc_vddcr_npu_value_acc; + __u32 tdc_vddcr_npu_residency_acc; + + /* THROTTLERS - TDC VDDCR LP */ + __u32 tdc_vddcr_lp_fused_limit; + __u32 tdc_vddcr_lp_max_irm_limit; + __u32 tdc_vddcr_lp_max_pbo_limit; + __u32 tdc_vddcr_lp_limit; + __u64 tdc_vddcr_lp_value_acc; + __u32 tdc_vddcr_lp_residency_acc; + + /* THROTTLERS - TDC VDDCR GFX */ + __u32 tdc_vddcr_gfx_fused_limit; + __u32 tdc_vddcr_gfx_max_irm_limit; + __u32 tdc_vddcr_gfx_max_pbo_limit; + __u32 tdc_vddcr_gfx_limit; + __u64 tdc_vddcr_gfx_value_acc; + __u32 tdc_vddcr_gfx_residency_acc; + + /* THROTTLERS - EDC VDDCR */ + __u32 edc_vddcr_fused_limit; + __u32 edc_vddcr_max_irm_limit; + __u32 edc_vddcr_max_pbo_limit; + __u32 edc_vddcr_limit; + + /* THROTTLERS - THERMAL */ + __u32 thm_fused_limit; + __u32 thm_limit; + __u64 thm_value_acc; + __u32 thm_residency_acc; + __u32 prochot_residency_acc; + __u64 gfx_temp_acc; + __u64 soc_temp_acc; + __u32 p3t_fused_limit; + __u64 p3t_value_acc; + + /* POWER */ + __u64 system_power_acc; + __u64 apu_power_acc; + __u64 dgpu_power_acc; + __u64 npu_power_acc; + + /* FREQUENCIES */ + __u64 fclk_freq_eff_acc; + __u64 memclk_freq_eff_acc; + __u64 lclk_freq_eff_acc; + __u64 gfxclk_freq_eff_acc; + __u64 socclk_freq_eff_acc; + __u64 vclk_freq_eff_acc; + __u64 vpeclk_freq_eff_acc; + __u64 aieclk_freq_eff_acc; + __u64 npuhclk_freq_eff_acc; + + /* BANDWIDTH */ + __u64 dram_read_bandwidth; + __u64 dram_write_bandwidth; + + /* ACTIVITY MONITORS */ + __u64 gfx_busy_acc; + __u64 vcn_busy_acc; + __u64 npu_busy_acc[HSMP_TELEMETRY_RM_NPU_BUSY_DOMAINS]; + + /* STT (Skin Temperature Tracking) */ + __u32 stt_min_limit; + __u64 stt_apu_hot_spot_temp_acc; + __u64 stt_hs2_hot_spot_temp_acc; + __u32 stt_apu_temp_limit; + __u64 stt_apu_skin_temp_acc; + + /* RESIDENCIES - per-CCX CPU off */ + __u64 cpu_off_residency[HSMP_TELEMETRY_RM_MAX_CCX]; + + /* DF P-STATES */ + __u32 fclk_freq_table[HSMP_TELEMETRY_RM_FREQ_TABLE_SIZE]; + __u32 uclk_freq_table[HSMP_TELEMETRY_RM_FREQ_TABLE_SIZE]; + __u32 ddr_rate_table[HSMP_TELEMETRY_RM_FREQ_TABLE_SIZE]; + __u8 df_pstate_source[HSMP_TELEMETRY_RM_FREQ_TABLE_SIZE]; + + /* SYSTEM */ + __u8 gfx_disabled; + __u8 spare2[3]; + __u32 gfxclk_fmax; + __u8 cclk_core_fuse_enable[HSMP_TELEMETRY_RM_MAX_CCX][HSMP_TE= LEMETRY_RM_CORES_PER_CCX]; + __u8 cclk_core_enabled[HSMP_TELEMETRY_RM_MAX_CCX][HSMP_TELEME= TRY_RM_CORES_PER_CCX]; + __u32 cclk_fmax[HSMP_TELEMETRY_RM_MAX_CCX][HSMP_TELEMETRY_RM_C= ORES_PER_CCX]; + + /* OVERCLOCK CAPABLE */ + __u8 cpu_precise_and_direct_oc_capable; + __u8 gfx_precise_and_direct_oc_capable; + __u8 pbo_basic_oc_capable; + __u8 pbo_advanced_oc_capable; + __u8 pbo_nitro_oc_capable; + __u8 memory_and_fabric_oc_capable; + __u8 misc_oc_capable; + __u8 extreme_cold_oc_capable; + __u8 down_config_control_capable; + __u8 spare0[3]; + + /* OVERCLOCK STATUS */ + __u32 fit_limit_scalar; + __u8 ln2_enabled; + __u8 cpu_precise_and_direct_oc_enabled; + __u8 gfx_precise_and_direct_oc_enabled; + __u8 spare1[2]; + __s8 psm_guardband[HSMP_TELEMETRY_RM_OC_DOMAINS] + [HSMP_TELEMETRY_RM_OC_SUBDOMAINS] + [HSMP_TELEMETRY_RM_OC_GUARDBANDS]; + __s32 core_power_limit_offset; + __u32 max_freq_offset[HSMP_TELEMETRY_RM_OC_DOMAINS]; + }; + + /** + * struct hsmp_telemetry_table_rm_ccx - Per-CCX core counters for RM t= elemetry. + * + * Each CCX exposes per-core monotonic counters for residency, frequen= cy, + * temperature and power. Arrays are sized for the maximum cores per + * CCX; entries past the actual enabled-core count are zero-padded by + * the SMU. Use the cclk_core_enabled[] mask in struct + * hsmp_telemetry_table_rm_iod to determine which lanes are valid. + */ + struct hsmp_telemetry_table_rm_ccx { + __u64 core_c0[HSMP_TELEMETRY_RM_CORES_PER_CCX]; + __u64 core_cc6[HSMP_TELEMETRY_RM_CORES_PER_CCX]; + __u64 core_freq[HSMP_TELEMETRY_RM_CORES_PER_CCX]; + __u64 core_freq_eff[HSMP_TELEMETRY_RM_CORES_PER_CCX]; + __u64 core_temp[HSMP_TELEMETRY_RM_CORES_PER_CCX]; + __u64 core_power[HSMP_TELEMETRY_RM_CORES_PER_CCX]; + }; + + /** + * struct hsmp_telemetry_table_rm - Top-level RM telemetry table. + * @iod: I/O die counters and per-rail/per-throttler/SYSTEM telem= etry. + * @ccx: Per-CCX core counters, one entry per CCX. + * + * Returned by the SMU at the DRAM address obtained from + * HSMP_CLIENT_GET_METRICS_TABLE_DRAM_ADDR after a successful + * HSMP_CLIENT_GET_METRICS_TABLE request. The on-wire layout is fixed + * at the RM spec; future revisions will be exposed via a different + * table version and a sibling struct. + */ + struct hsmp_telemetry_table_rm { + struct hsmp_telemetry_table_rm_iod iod; + struct hsmp_telemetry_table_rm_ccx ccx[HSMP_TELEMETRY_RM_MAX_C= CX]; + }; + More details on the interface and message definitions can be found in chap= ter "7 Host System Management Port (HSMP)" of the respective family/model PPR eg: https://docs.amd.com/v/u/en-US/55898_B1_pub_0_50 --=20 2.34.1