From nobody Fri Oct 2 13:14:00 2026 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A5260429039; Fri, 31 Jul 2026 12:03:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.135.140.105 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785499390; cv=none; b=fjltKvp43x4HEwt/z7ikYNlps49j1bVqDrrEi0+ZOmsG+N26hS97EvzGupZOuSKwO0+Wzafxnkx/yOewD8ILkgAAKB/ardCVSYRviyuAQAwl2PAAoRf0zG3vpIqcrKhqe9vEzpRkzHP6pAgYxnaNc7B1PWtDvzoi/YIuiBIiSZ4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785499390; c=relaxed/simple; bh=9cxKqRSzDI1k9DZMBIppT7I1D0ocQhPQ6p2OsQkLhW4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=mIFaWER0sNOovMRM5pNOIL2t4bi3tan9u7sk4GkKfhvpIkbx4sGp1S9kt5kog2geVwnMfMY0cEtCf35byGKnmIO7g1yGUXTYcw99x+EWwH9r1ikvevjYARE7Ww+RBfpAYtGgS7E+nhcmkjNK4acBDBI/FhNACUxHmG0QQrVZanE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr; spf=none smtp.mailfrom=cjdns.fr; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b=K6nnlHDC; arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="K6nnlHDC" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 5B97A11D0F3; Fri, 31 Jul 2026 14:02:57 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1785499380; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=Q6cAAX9tCyXcIpCsb2E2vZSxmNLsA1iEdhH9bQm/us8=; b=K6nnlHDCXa8kdLBW5LU6xyPfIM5j/dPEZErOxvSA0/Wek3ajlXSCXVp5yllsslpY5eOpTQ HxbHrQHzLgCnuWaHQkSMRJ4o9tDXoH9+7Yc60OCAOYrDxtBoyaiAYEfoAVcbCOAl0+Rnbi DRp+leW5vRmHAuHENmABVvgUXxa1vKGnuHByFJR1vo2aPENZN7rrMxaZnCcjSCvwyPe/6z bQPEf0u/paxGR2huRYlP0Li7tW30QxC+mT4rVV2iCNedwQIqggHh/0GF5YpJUNv/TRjndU zHxtZsTrKUfyjD4ZOjeDHNqmz8c6S035w3WpnPLruVP/h/8v4XhyeAjtWA7bdw== From: Caleb James DeLisle To: linux-mips@vger.kernel.org Cc: conor+dt@kernel.org, daniel.lezcano@kernel.org, devicetree@vger.kernel.org, krzk+dt@kernel.org, linux-kernel@vger.kernel.org, naseefkm@gmail.com, robh@kernel.org, tglx@kernel.org, grandmaster@al2klimov.de, Caleb James DeLisle Subject: [PATCH v7 1/5] clocksource/timer-econet-en751221: fix refcount leak Date: Fri, 31 Jul 2026 12:02:42 +0000 Message-Id: <20260731120246.1296955-2-cjd@cjdns.fr> In-Reply-To: <20260731120246.1296955-1-cjd@cjdns.fr> References: <20260731120246.1296955-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" From: "Alexander A. Klimov" Every value returned from of_clk_get() is supposed to be cleaned up via clk_put() once not needed anymore. Fixes: 3b4c33ac87d0 ("clocksource/drivers: Add EcoNet Timer HPT driver") Signed-off-by: Alexander A. Klimov Signed-off-by: Caleb James DeLisle --- drivers/clocksource/timer-econet-en751221.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clocksource/timer-econet-en751221.c b/drivers/clocksou= rce/timer-econet-en751221.c index 4008076b1a21..1859335345b5 100644 --- a/drivers/clocksource/timer-econet-en751221.c +++ b/drivers/clocksource/timer-econet-en751221.c @@ -181,6 +181,7 @@ static int __init timer_init(struct device_node *np) } =20 econet_timer.freq_hz =3D clk_get_rate(clk); + clk_put(clk); =20 for (int i =3D 0; i < num_blocks; i++) { econet_timer.membase[i] =3D of_iomap(np, i); --=20 2.39.5 From nobody Fri Oct 2 13:14:00 2026 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E909423E98; Fri, 31 Jul 2026 12:03:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.135.140.105 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785499388; cv=none; b=ABWMO9TceG8RKqCKL7mWrGxYOcWbHGFB3oEWylThvEiD8ZFXLEbeO1Nce9LYwhrvhnnUJQWaYdQOaHzTY/p8sdPvtULUtJEX2VjVjVByn+TNN4KFZ/tFesdljN04hwkbDQtOgJ0OJGvhzMOvwZtg1ffY0HQUqyw3mpSn/cQqsBA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785499388; c=relaxed/simple; bh=Ze4Nv8y680E6FSf/un9hYJUthpJ2COzdxd+LB34Yb2I=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Z3JxEYO+NZwjfXY/Igo0qDQKU88bx0pf3TNU30du84BZVPhm0eJjTS/DiSfssty7/I4zxNC1EjKZq9GU1xenRHnqR2hBUv0a2gliA2CX+38I2v8dXWASPVP8ikJiHDxEGt5fpY0uRqxCSLxmMxkvMXMjGnMeKqrHJZN0yp0OxJU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr; spf=pass smtp.mailfrom=cjdns.fr; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b=HLVhojJ2; arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="HLVhojJ2" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id A320611D969; Fri, 31 Jul 2026 14:03:00 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1785499383; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=X5WYmjC+W1XLRGqsI2xwQZ9HsjRo/iUHSgzYnXKRgcw=; b=HLVhojJ2RRdAQYHV6upLlCPKbKwyLzLZH8wcYrSl01Q7v1G2XqLqxHUCFkcbXmO4xGkV+A sOoKKh8rufcU+uQq5FWa3ZblR25Z5vCl7LRtEquaSZ8T/rViCNNzZIIJaJk2+1BimWr2RP zu+l4MbrYfpM9Yq7F7L3fozuNYBVCmMWYjEo048oF4Ggedq5Cbi0VXeOtLb/IlvBz/N+K+ +OInMHOMS62v6fQRJn1BDWMc1lJRRb8YWnqP95mpc6FyQLLeJ30pZrT9axcrMcl5ODQNeD b7HSt6F2ToZTQku7BJNbq2m6bJ7ADBHzcTxMC9qTTUWCLa/+EExYVUNMPQMjuQ== From: Caleb James DeLisle To: linux-mips@vger.kernel.org Cc: conor+dt@kernel.org, daniel.lezcano@kernel.org, devicetree@vger.kernel.org, krzk+dt@kernel.org, linux-kernel@vger.kernel.org, naseefkm@gmail.com, robh@kernel.org, tglx@kernel.org, grandmaster@al2klimov.de, Caleb James DeLisle , Conor Dooley Subject: [PATCH v7 2/5] dt-bindings: timer: econet: Update EN751627 for multi-IRQ Date: Fri, 31 Jul 2026 12:02:43 +0000 Message-Id: <20260731120246.1296955-3-cjd@cjdns.fr> In-Reply-To: <20260731120246.1296955-1-cjd@cjdns.fr> References: <20260731120246.1296955-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" This hardware is found in the EN751221 SoC family as well as the EN751627. The former uses a percpu IRQ for all timers while the latter uses an individual IRQ number per timer. Signed-off-by: Caleb James DeLisle Acked-by: Conor Dooley --- .../bindings/timer/econet,en751221-timer.yaml | 31 ++++++++++++------- 1 file changed, 20 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/timer/econet,en751221-timer.= yaml b/Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml index c1e7c2b6afde..ac25785ecfdf 100644 --- a/Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml +++ b/Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml @@ -12,24 +12,23 @@ maintainers: description: The EcoNet High Precision Timer (HPT) is a timer peripheral found in var= ious EcoNet SoCs, including the EN751221 and EN751627 families. It provides p= er-VPE - count/compare registers and a per-CPU control register, with a single in= terrupt - line using a percpu-devid interrupt mechanism. + count/compare registers and a per-CPU control register. On EN751221 it u= ses a + single interrupt line using a percpu-devid interrupt mechanism, and on + EN751627 it uses an interrupt per VPE. =20 properties: compatible: - oneOf: - - const: econet,en751221-timer - - items: - - const: econet,en751627-timer - - const: econet,en751221-timer + enum: + - econet,en751221-timer + - econet,en751627-timer =20 reg: minItems: 1 maxItems: 2 =20 interrupts: - maxItems: 1 - description: A percpu-devid timer interrupt shared across CPUs. + minItems: 1 + maxItems: 4 =20 clocks: maxItems: 1 @@ -52,21 +51,31 @@ allOf: items: - description: VPE timers 0 and 1 - description: VPE timers 2 and 3 + interrupts: + description: An interrupt for each timer (one per VPE) + minItems: 4 else: properties: reg: items: - description: VPE timers 0 and 1 + interrupts: + description: A percpu-devid timer interrupt shared across timers + maxItems: 1 =20 additionalProperties: false =20 examples: - | + #include timer@1fbf0400 { - compatible =3D "econet,en751627-timer", "econet,en751221-timer"; + compatible =3D "econet,en751627-timer"; reg =3D <0x1fbf0400 0x100>, <0x1fbe0000 0x100>; interrupt-parent =3D <&intc>; - interrupts =3D <30>; + interrupts =3D , + , + , + ; clocks =3D <&hpt_clock>; }; - | --=20 2.39.5 From nobody Fri Oct 2 13:14:00 2026 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B12D942A150; Fri, 31 Jul 2026 12:03:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.135.140.105 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785499392; cv=none; b=Gg6gMwu47Tc03agD286v6eeBbVRWfxCj1drJZJH80bspN8OCfk42VRVibN3lFnqIiClgXbyDu4tgA8/KSWKZ1DirvmJAnQ7HXQ3RE+MwOsP0Y/b7bLF8LuKOCHQf5KA77IEM49TXK3qreKXWtbfGE1KewNDbQw524Si7Y8ln0Qk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785499392; c=relaxed/simple; bh=xkU7FTh2Qx1l444kXVxCZ72X6BDvMmnbijkDMtD0tYY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=gIFXx85ZRFc7Alc1VkKxCB8GKeqz3MnXajqo/OdQXIwp2ZLPw67iiL37/gvyPon/qR4iK8a+etRrJsMLN/k5XneSOJiCHGrhDiwuDgsGxDJZ4XebO7Bx5algI/MRy0lL/oaknfPhDpu1lWMh57fZzynVfDpzzkqb5wJcNY4g+6E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr; spf=pass smtp.mailfrom=cjdns.fr; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b=CXUhqPoO; arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="CXUhqPoO" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 8787E11F905; Fri, 31 Jul 2026 14:03:03 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1785499386; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=B1OV7lBJrmDaac8ePy8dHk2DEYoP6HJXQm0PFK+z8S0=; b=CXUhqPoOErQ6cyW5eKI0EYXSiWzZXL40Q5Gh9IE5zCYGgpiJg8cSMdK9J+bRqNSPHTssXn zFJoEfqJ6D30589tR5vvN9qNERH3AmcAFnSuce2KH5U6xEd2eg3E4PuOaQvffUf/mPR9fo OdyDt5j+FYtHLSkjEdcHSNh7NLE0KNek21iKPAjPSVhqQv6HXhSbfUpNh6AzXmt/XLlp0d xdo3+8p3xydkV97Nlr7yjbmdPxwekWWt0tH8joEtneHAelpdD8rBB9mK6lJ4FDsaDqbdzL IjPvHXzsbr2+cbU5+wU9235KYCQo2Ykx8vx6tyJOYv+SqaD7PN56zlFmkaXCNg== From: Caleb James DeLisle To: linux-mips@vger.kernel.org Cc: conor+dt@kernel.org, daniel.lezcano@kernel.org, devicetree@vger.kernel.org, krzk+dt@kernel.org, linux-kernel@vger.kernel.org, naseefkm@gmail.com, robh@kernel.org, tglx@kernel.org, grandmaster@al2klimov.de, Caleb James DeLisle Subject: [PATCH v7 3/5] clocksource/timer-econet-en751221: Init teardown on error if possible Date: Fri, 31 Jul 2026 12:02:44 +0000 Message-Id: <20260731120246.1296955-4-cjd@cjdns.fr> In-Reply-To: <20260731120246.1296955-1-cjd@cjdns.fr> References: <20260731120246.1296955-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" As a clocksource, much of the initialization process is irreversible and the impact of a failure to initialize is a failure to boot. That said, good practice is to attempt a clean exit if probing fails, and supporting this pattern will reduce the likelihood that future contributions introduce a bug by trying to teardown after it is no longer possible to do so. Convert the init process into two clearly delineated phases, one which is reverted in case of error, and the other which can't be. Move all IRQ and address resource mapping before that point, and add teardown logic in case of error before the point of no return. Signed-off-by: Caleb James DeLisle --- drivers/clocksource/timer-econet-en751221.c | 84 ++++++++++++--------- 1 file changed, 50 insertions(+), 34 deletions(-) diff --git a/drivers/clocksource/timer-econet-en751221.c b/drivers/clocksou= rce/timer-econet-en751221.c index 1859335345b5..714702b9ef12 100644 --- a/drivers/clocksource/timer-econet-en751221.c +++ b/drivers/clocksource/timer-econet-en751221.c @@ -24,6 +24,7 @@ =20 static struct { void __iomem *membase[ECONET_NUM_BLOCKS]; + int irq; u32 freq_hz; } econet_timer __ro_after_init; =20 @@ -126,22 +127,9 @@ static void __init cevt_dev_init(uint cpu) iowrite32(U32_MAX, reg_compare(cpu)); } =20 -static int __init cevt_init(struct device_node *np) +static void __init cevt_init(struct device_node *np) { - int i, irq, ret; - - irq =3D irq_of_parse_and_map(np, 0); - if (irq <=3D 0) { - pr_err("%pOFn: irq_of_parse_and_map failed", np); - return -EINVAL; - } - - ret =3D request_percpu_irq(irq, cevt_interrupt, np->name, &econet_timer_p= cpu); - - if (ret < 0) { - pr_err("%pOFn: IRQ %d setup failed (%d)\n", np, irq, ret); - goto err_unmap_irq; - } + int i; =20 for_each_possible_cpu(i) { struct clock_event_device *cd =3D &per_cpu(econet_timer_pcpu, i); @@ -151,21 +139,12 @@ static int __init cevt_init(struct device_node *np) CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_PERCPU; cd->set_next_event =3D cevt_set_next_event; - cd->irq =3D irq; + cd->irq =3D econet_timer.irq; cd->cpumask =3D cpumask_of(i); cd->name =3D np->name; =20 cevt_dev_init(i); } - - cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, - "clockevents/econet/timer:starting", - cevt_init_cpu, NULL); - return 0; - -err_unmap_irq: - irq_dispose_mapping(irq); - return ret; } =20 static int __init timer_init(struct device_node *np) @@ -187,22 +166,45 @@ static int __init timer_init(struct device_node *np) econet_timer.membase[i] =3D of_iomap(np, i); if (!econet_timer.membase[i]) { pr_err("%pOFn: failed to map register [%d]\n", np, i); - return -ENXIO; + ret =3D -ENXIO; + goto out_membase; } } =20 + econet_timer.irq =3D irq_of_parse_and_map(np, 0); + if (econet_timer.irq <=3D 0) { + pr_err("%pOFn: irq_of_parse_and_map failed\n", np); + ret =3D -EINVAL; + goto out_membase; + } + + ret =3D request_percpu_irq(econet_timer.irq, cevt_interrupt, np->name, + &econet_timer_pcpu); + + if (ret < 0) { + pr_err("%pOFn: IRQ %d setup failed (%d)\n", np, + econet_timer.irq, ret); + goto out_irq_mapping; + } + + cevt_init(np); + + ret =3D cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, + "clockevents/econet/timer:starting", + cevt_init_cpu, NULL); + if (ret < 0) { + pr_err("%pOFn: cpuhp setup failed (%d)\n", np, ret); + goto out_irq_free; + } + + /* Point of no return, do not attempt to tear down after this. */ + /* For clocksource purposes always read clock zero, whatever the CPU */ ret =3D clocksource_mmio_init(reg_count(0), np->name, econet_timer.freq_hz, 301, ECONET_BITS, clocksource_mmio_readl_up); - if (ret) { - pr_err("%pOFn: clocksource_mmio_init failed: %d", np, ret); - return ret; - } - - ret =3D cevt_init(np); - if (ret < 0) - return ret; + if (ret) + pr_err("%pOFn: clocksource_mmio_init failed: %d\n", np, ret); =20 sched_clock_register(sched_clock_read, ECONET_BITS, econet_timer.freq_hz); @@ -212,6 +214,20 @@ static int __init timer_init(struct device_node *np) (econet_timer.freq_hz / 1000) % 1000); =20 return 0; + +out_irq_free: + free_percpu_irq(econet_timer.irq, &econet_timer_pcpu); +out_irq_mapping: + irq_dispose_mapping(econet_timer.irq); +out_membase: + for (int i =3D 0; i < ARRAY_SIZE(econet_timer.membase); i++) { + if (econet_timer.membase[i]) { + iounmap(econet_timer.membase[i]); + econet_timer.membase[i] =3D NULL; + } + } + + return ret; } =20 TIMER_OF_DECLARE(econet_timer_hpt, "econet,en751221-timer", timer_init); --=20 2.39.5 From nobody Fri Oct 2 13:14:00 2026 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F33A42BE86; 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arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="ASphqsCb" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 11DD511F2CF; Fri, 31 Jul 2026 14:03:07 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1785499389; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=lRhqM7LAgl/X+6g5+JRRCWTiassQyFmX1v5QtTJrszQ=; b=ASphqsCbo6HVTXzDsSX8H/bSmr1yQ8ckUmPoJVIXZ4G0OYNUfQWy3hrXIpB6kMn4Zxo81/ nq55T3W0p2s0+BFEMf55EH3zhI/mQofQ82F68cB5ufduteiwHGadBigYof+ddkwMOFKsNO sku1/s4/05L7dRK4g+WbDFO6FFS/eAGgLReNgJXchdkPMefKOlWKrpKW2B2wPnuYVvbbsH tbs/d0CMmRtnQQJcimKT+7ZUzGKC+OGMD+EMA3GTZksJpNmzOKGuPnL+PTzYANSwZz9U1T DWKfCDRi3PnOHOxkvDHFMkA4cVX5eX76CB3qLdFs8BhEvoiRWSPASBcZu1+8sg== From: Caleb James DeLisle To: linux-mips@vger.kernel.org Cc: conor+dt@kernel.org, daniel.lezcano@kernel.org, devicetree@vger.kernel.org, krzk+dt@kernel.org, linux-kernel@vger.kernel.org, naseefkm@gmail.com, robh@kernel.org, tglx@kernel.org, grandmaster@al2klimov.de, Caleb James DeLisle Subject: [PATCH v7 4/5] clocksource/timer-econet-en751221: Disable IRQ until cevt registered Date: Fri, 31 Jul 2026 12:02:45 +0000 Message-Id: <20260731120246.1296955-5-cjd@cjdns.fr> In-Reply-To: <20260731120246.1296955-1-cjd@cjdns.fr> References: <20260731120246.1296955-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Eliminate a race condition where cevt_interrupt may trigger before clockevents_config_and_register has been called, and dev->event_handler is at that point NULL. Additionally, NULL check dev->event_handler in interrupt callback just in case clockevents_config_and_register failed. Signed-off-by: Caleb James DeLisle --- drivers/clocksource/timer-econet-en751221.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/clocksource/timer-econet-en751221.c b/drivers/clocksou= rce/timer-econet-en751221.c index 714702b9ef12..f2c4c1ee0a56 100644 --- a/drivers/clocksource/timer-econet-en751221.c +++ b/drivers/clocksource/timer-econet-en751221.c @@ -75,7 +75,10 @@ static irqreturn_t cevt_interrupt(int irq, void *dev_id) return IRQ_NONE; =20 iowrite32(ioread32(reg_count(cpu)), reg_compare(cpu)); - dev->event_handler(dev); + + if (dev->event_handler) + dev->event_handler(dev); + return IRQ_HANDLED; } =20 @@ -104,12 +107,11 @@ static int cevt_init_cpu(uint cpu) reg =3D ioread32(reg_ctl(cpu)) | ctl_bit_enabled(cpu); iowrite32(reg, reg_ctl(cpu)); =20 - enable_percpu_irq(cd->irq, IRQ_TYPE_NONE); - - /* Do this last because it synchronously configures the timer */ clockevents_config_and_register(cd, econet_timer.freq_hz, ECONET_MIN_DELTA, ECONET_MAX_DELTA); =20 + enable_percpu_irq(cd->irq, IRQ_TYPE_NONE); + return 0; } =20 @@ -178,6 +180,8 @@ static int __init timer_init(struct device_node *np) goto out_membase; } =20 + irq_set_status_flags(econet_timer.irq, IRQ_NOAUTOEN); + ret =3D request_percpu_irq(econet_timer.irq, cevt_interrupt, np->name, &econet_timer_pcpu); =20 --=20 2.39.5 From nobody Fri Oct 2 13:14:00 2026 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7EDC042C51B; Fri, 31 Jul 2026 12:03:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.135.140.105 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785499399; cv=none; b=HRqzzbgIH2lcwcaQCh17wHJOqMMY0y/4BuCiLRpDbDSkC1E6h8XyigHpgR3SLZzob+QJ/16RzrPwjwbh5jCCEE9zdy87vaUpQrkXma1HkwVbnKg+bXoF6zVK2zbEutVFG7dXDhFMKDoHt+HRIvkOvR5/ym8GCEwhKWp+qLVFKTM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785499399; c=relaxed/simple; bh=DU59HSNaB9phG8rCZl4dDJTjeDMq0KTL47w2Dyh4SlU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Z2cBtkwAgbwNh4d7SNKREeiiqZF1TwUrr7ffmLIcvpCvEUZeIjDkt6NxjcsnTxNoEVu0brr8mlw2iJ3CzEU9JOpHQkGNT9dNvAju+QO2q44JAsT4efvPICQXarsrNP6HDFJ8P8NIn6ObWsg+QmjfJOikbqTTzX7lBWEY75vkVJU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr; spf=none smtp.mailfrom=cjdns.fr; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b=g6OFSZ3I; arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="g6OFSZ3I" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 8014911F554; Fri, 31 Jul 2026 14:03:09 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1785499391; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=4og5/uHZUOe1X8csZf1Cd0lBdViJnSG21+7PRelLts0=; b=g6OFSZ3IH/0+IKx6mhJxmX1vFc50LLGQoo4O0pIW0z+HclaXuV/vG1obF7trhcQwoXZi32 0rSyZ5JD3s9jkt7G1HAFqB8l/OHz1S5UbXhHBl7DziX0yZ8wDkrRWD1z3kkQkS5jJBKSQ0 FrUtZRke8Fnnt1PcgjimI0NHnatMD//60pPFtJQ9Xut49m8rXCpK97dcXtlr40VYK3rAzI n0QXyDM0iWp9l+FkYpZPPFC1xOeaG+sWdsNRRhBk8o2yqt0ewJLNJn0fpZBaxawwio97hK oPTIHZb8shIPiOVO0tWGlrqiJiyyJiF8qj2Z+dNgrbRkGGMY609Enx8CvKU4RQ== From: Caleb James DeLisle To: linux-mips@vger.kernel.org Cc: conor+dt@kernel.org, daniel.lezcano@kernel.org, devicetree@vger.kernel.org, krzk+dt@kernel.org, linux-kernel@vger.kernel.org, naseefkm@gmail.com, robh@kernel.org, tglx@kernel.org, grandmaster@al2klimov.de, Caleb James DeLisle Subject: [PATCH v7 5/5] clocksource/timer-econet-en751221: Support EN751627 without percpu IRQ Date: Fri, 31 Jul 2026 12:02:46 +0000 Message-Id: <20260731120246.1296955-6-cjd@cjdns.fr> In-Reply-To: <20260731120246.1296955-1-cjd@cjdns.fr> References: <20260731120246.1296955-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" EN751627 is based on the 1004Kc which uses a different interrupt number for each CPU timer. Support both this and the EN751221 which uses a single percpu interrupt. Signed-off-by: Caleb James DeLisle --- drivers/clocksource/timer-econet-en751221.c | 122 ++++++++++++++++---- 1 file changed, 99 insertions(+), 23 deletions(-) diff --git a/drivers/clocksource/timer-econet-en751221.c b/drivers/clocksou= rce/timer-econet-en751221.c index f2c4c1ee0a56..040386ded132 100644 --- a/drivers/clocksource/timer-econet-en751221.c +++ b/drivers/clocksource/timer-econet-en751221.c @@ -21,10 +21,12 @@ #define ECONET_MAX_DELTA GENMASK(ECONET_BITS - 2, 0) /* 34Kc hardware has 1 block and 1004Kc has 2. */ #define ECONET_NUM_BLOCKS DIV_ROUND_UP(NR_CPUS, 2) +#define ECONET_NUM_IRQS NR_CPUS =20 static struct { void __iomem *membase[ECONET_NUM_BLOCKS]; - int irq; + int irqs[ECONET_NUM_IRQS]; + bool is_percpu; u32 freq_hz; } econet_timer __ro_after_init; =20 @@ -102,6 +104,25 @@ static int cevt_init_cpu(uint cpu) struct clock_event_device *cd =3D &per_cpu(econet_timer_pcpu, cpu); u32 reg; =20 + if (!reg_ctl(cpu)) { + pr_err("%s: missing address resource for CPU %d\n", cd->name, + cpu); + return -EINVAL; + } + if (cd->irq <=3D 0) { + pr_err("%s: missing IRQ for CPU %d\n", cd->name, cpu); + return -EINVAL; + } + if (!econet_timer.is_percpu) { + int ret =3D irq_force_affinity(cd->irq, cpumask_of(cpu)); + + if (ret) { + pr_err("%s: failed to set IRQ affinity to CPU %d: %pe\n", + cd->name, cpu, ERR_PTR(ret)); + return ret; + } + } + pr_debug("%s: Setting up clockevent for CPU %d\n", cd->name, cpu); =20 reg =3D ioread32(reg_ctl(cpu)) | ctl_bit_enabled(cpu); @@ -110,7 +131,10 @@ static int cevt_init_cpu(uint cpu) clockevents_config_and_register(cd, econet_timer.freq_hz, ECONET_MIN_DELTA, ECONET_MAX_DELTA); =20 - enable_percpu_irq(cd->irq, IRQ_TYPE_NONE); + if (econet_timer.is_percpu) + enable_percpu_irq(cd->irq, IRQ_TYPE_NONE); + else + enable_irq(cd->irq); =20 return 0; } @@ -141,19 +165,52 @@ static void __init cevt_init(struct device_node *np) CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_PERCPU; cd->set_next_event =3D cevt_set_next_event; - cd->irq =3D econet_timer.irq; + + if (econet_timer.is_percpu) + cd->irq =3D econet_timer.irqs[0]; + else + cd->irq =3D econet_timer.irqs[i]; + cd->cpumask =3D cpumask_of(i); cd->name =3D np->name; =20 - cevt_dev_init(i); + /* + * Tolerate CPUs that could exist but don't. + * Fail in cevt_init_cpu when they try to start. + */ + if (reg_ctl(i)) + cevt_dev_init(i); } } =20 static int __init timer_init(struct device_node *np) { - int num_blocks =3D DIV_ROUND_UP(num_possible_cpus(), 2); + int num_blocks =3D of_address_count(np); + int num_irqs =3D of_irq_count(np); struct clk *clk; - int ret; + int ret, i; + + econet_timer.is_percpu =3D of_device_is_compatible(np, "econet,en751221-t= imer"); + + if (econet_timer.is_percpu && num_irqs !=3D 1) { + pr_err("%pOFn: EN751221 clock must have 1 IRQ not %d\n", np, + num_irqs); + return -EINVAL; + } + if (num_irqs > ARRAY_SIZE(econet_timer.irqs)) { + pr_err("%pOFn: Too many IRQs max %d got %d\n", np, + ARRAY_SIZE(econet_timer.irqs), num_irqs); + return -EINVAL; + } + if (num_blocks > ARRAY_SIZE(econet_timer.membase)) { + pr_err("%pOFn: Too many regs: max %d got %d\n", np, + ARRAY_SIZE(econet_timer.membase), num_blocks); + return -EINVAL; + } + if (num_blocks =3D=3D 0) { + pr_err("%pOFn: At least one reg block must be provided\n", np); + return -EINVAL; + } =20 clk =3D of_clk_get(np, 0); if (IS_ERR(clk)) { @@ -164,7 +221,7 @@ static int __init timer_init(struct device_node *np) econet_timer.freq_hz =3D clk_get_rate(clk); clk_put(clk); =20 - for (int i =3D 0; i < num_blocks; i++) { + for (i =3D 0; i < num_blocks; i++) { econet_timer.membase[i] =3D of_iomap(np, i); if (!econet_timer.membase[i]) { pr_err("%pOFn: failed to map register [%d]\n", np, i); @@ -173,22 +230,32 @@ static int __init timer_init(struct device_node *np) } } =20 - econet_timer.irq =3D irq_of_parse_and_map(np, 0); - if (econet_timer.irq <=3D 0) { - pr_err("%pOFn: irq_of_parse_and_map failed\n", np); - ret =3D -EINVAL; - goto out_membase; + for (i =3D 0; i < num_irqs; i++) { + econet_timer.irqs[i] =3D irq_of_parse_and_map(np, i); + if (econet_timer.irqs[i] <=3D 0) { + pr_err("%pOFn: failed mapping irq %d\n", np, i); + ret =3D -EINVAL; + goto out_irq_mapping; + } } =20 - irq_set_status_flags(econet_timer.irq, IRQ_NOAUTOEN); - - ret =3D request_percpu_irq(econet_timer.irq, cevt_interrupt, np->name, - &econet_timer_pcpu); - - if (ret < 0) { - pr_err("%pOFn: IRQ %d setup failed (%d)\n", np, - econet_timer.irq, ret); - goto out_irq_mapping; + for (i =3D 0; i < num_irqs; i++) { + irq_set_status_flags(econet_timer.irqs[i], IRQ_NOAUTOEN); + + if (econet_timer.is_percpu) + ret =3D request_percpu_irq(econet_timer.irqs[i], + cevt_interrupt, np->name, + &econet_timer_pcpu); + else + ret =3D request_irq(econet_timer.irqs[i], cevt_interrupt, + IRQF_TIMER | IRQF_NOBALANCING, + np->name, NULL); + + if (ret < 0) { + pr_err("%pOFn: IRQ %d setup failed: %pe\n", np, + i, ERR_PTR(ret)); + goto out_irq_free; + } } =20 cevt_init(np); @@ -220,9 +287,17 @@ static int __init timer_init(struct device_node *np) return 0; =20 out_irq_free: - free_percpu_irq(econet_timer.irq, &econet_timer_pcpu); + while (--i >=3D 0) { + if (econet_timer.is_percpu) + free_percpu_irq(econet_timer.irqs[i], &econet_timer_pcpu); + else + free_irq(econet_timer.irqs[i], NULL); + } out_irq_mapping: - irq_dispose_mapping(econet_timer.irq); + for (i =3D 0; i < num_irqs; i++) { + if (econet_timer.irqs[i] > 0) + irq_dispose_mapping(econet_timer.irqs[i]); + } out_membase: for (int i =3D 0; i < ARRAY_SIZE(econet_timer.membase); i++) { if (econet_timer.membase[i]) { @@ -235,3 +310,4 @@ static int __init timer_init(struct device_node *np) } =20 TIMER_OF_DECLARE(econet_timer_hpt, "econet,en751221-timer", timer_init); +TIMER_OF_DECLARE(econet_timer_en751627, "econet,en751627-timer", timer_ini= t); --=20 2.39.5