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Fri, 31 Jul 2026 04:41:19 -0700 (PDT) From: Svyatoslav Ryhel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Mikko Perttunen , Svyatoslav Ryhel Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 01/10] ARM: tegra: tf701t: Configure CPU DFLL clock node Date: Fri, 31 Jul 2026 14:40:57 +0300 Message-ID: <20260731114106.169398-2-clamor95@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260731114106.169398-1-clamor95@gmail.com> References: <20260731114106.169398-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable DFLL for ASUS TF701T since it is now supported by Tegra114. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen --- arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts b/arch/arm/b= oot/dts/nvidia/tegra114-asus-tf701t.dts index f02e2cf65fe82..5358cdb6efc10 100644 --- a/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts +++ b/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts @@ -1621,6 +1621,14 @@ i2s@70080600 { }; }; =20 + /* CPU DFLL clock */ + clock@70110000 { + status =3D "okay"; + nvidia,sample-rate =3D <11500>; + nvidia,i2c-fs-rate =3D <400000>; + vdd-cpu-supply =3D <&vdd_cpu>; + }; + brcm_wifi_pwrseq: pwrseq-wifi { compatible =3D "mmc-pwrseq-simple"; =20 --=20 2.53.0 From nobody Fri Oct 2 13:10:15 2026 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8FB3E3FD960 for ; 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charset="utf-8" Add required core supply to Tegra PMC node. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen --- arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts b/arch/arm/b= oot/dts/nvidia/tegra114-asus-tf701t.dts index 5358cdb6efc10..55e9256e80f33 100644 --- a/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts +++ b/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts @@ -1599,6 +1599,7 @@ pmc@7000e400 { nvidia,core-pwr-off-time =3D <2000>; nvidia,core-power-req-active-high; nvidia,sys-clock-req-active-high; + core-supply =3D <&vdd_core>; =20 /* Clear DEV_ON bit in DEV_CTRL register of TPS65913 PMIC */ i2c-thermtrip { --=20 2.53.0 From nobody Fri Oct 2 13:10:15 2026 Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF5E73F8238 for ; Fri, 31 Jul 2026 11:41:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 31 Jul 2026 04:41:25 -0700 (PDT) Received: from xeon ([188.163.112.51]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47fd41d0064sm3769336f8f.5.2026.07.31.04.41.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Jul 2026 04:41:24 -0700 (PDT) From: Svyatoslav Ryhel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Mikko Perttunen , Svyatoslav Ryhel Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 03/10] ARM: tegra: tf701t: Add MC and EMC timing nodes Date: Fri, 31 Jul 2026 14:40:59 +0300 Message-ID: <20260731114106.169398-4-clamor95@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260731114106.169398-1-clamor95@gmail.com> References: <20260731114106.169398-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Configure Memory Controllers of ASUS TF701T. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen --- .../boot/dts/nvidia/tegra114-asus-tf701t.dts | 713 ++++++++++++++++++ 1 file changed, 713 insertions(+) diff --git a/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts b/arch/arm/b= oot/dts/nvidia/tegra114-asus-tf701t.dts index 55e9256e80f33..00eeedf3ef7a5 100644 --- a/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts +++ b/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts @@ -101,6 +101,89 @@ panel_secondary: panel@0 { }; }; =20 + clock@60006000 { + emc-timings-0 { + nvidia,ram-code =3D <0>; + + timing-12750000 { + clock-frequency =3D <12750000>; + nvidia,parent-clock-frequency =3D <408000000>; + clocks =3D <&tegra_car TEGRA114_CLK_PLL_P>; + clock-names =3D "emc-parent"; + }; + + timing-20400000 { + clock-frequency =3D <20400000>; + nvidia,parent-clock-frequency =3D <408000000>; + clocks =3D <&tegra_car TEGRA114_CLK_PLL_P>; + clock-names =3D "emc-parent"; + }; + + timing-40800000 { + clock-frequency =3D <40800000>; + nvidia,parent-clock-frequency =3D <408000000>; + clocks =3D <&tegra_car TEGRA114_CLK_PLL_P>; + clock-names =3D "emc-parent"; + }; + + timing-68000000 { + clock-frequency =3D <68000000>; + nvidia,parent-clock-frequency =3D <408000000>; + clocks =3D <&tegra_car TEGRA114_CLK_PLL_P>; + clock-names =3D "emc-parent"; + }; + + timing-102000000 { + clock-frequency =3D <102000000>; + nvidia,parent-clock-frequency =3D <408000000>; + clocks =3D <&tegra_car TEGRA114_CLK_PLL_P>; + clock-names =3D "emc-parent"; + }; + + timing-204000000 { + clock-frequency =3D <204000000>; + nvidia,parent-clock-frequency =3D <408000000>; + clocks =3D <&tegra_car TEGRA114_CLK_PLL_P>; + clock-names =3D "emc-parent"; + }; + + timing-312000000 { + clock-frequency =3D <312000000>; + nvidia,parent-clock-frequency =3D <624000000>; + clocks =3D <&tegra_car TEGRA114_CLK_PLL_C>; + clock-names =3D "emc-parent"; + }; + + timing-408000000 { + clock-frequency =3D <408000000>; + nvidia,parent-clock-frequency =3D <408000000>; + clocks =3D <&tegra_car TEGRA114_CLK_PLL_P>; + clock-names =3D "emc-parent"; + }; + + timing-528000000 { + clock-frequency =3D <528000000>; + nvidia,parent-clock-frequency =3D <792000000>; + clocks =3D <&tegra_car TEGRA114_CLK_PLL_M>; + clock-names =3D "emc-parent"; + }; + + timing-624000000 { + clock-frequency =3D <624000000>; + nvidia,parent-clock-frequency =3D <624000000>; + clocks =3D <&tegra_car TEGRA114_CLK_PLL_C>; + clock-names =3D "emc-parent"; + }; + + timing-792000000 { + clock-frequency =3D <792000000>; + nvidia,parent-clock-frequency =3D <792000000>; + clocks =3D <&tegra_car TEGRA114_CLK_PLL_M>; + clock-names =3D "emc-parent"; + }; + }; + }; + vde@6001a000 { assigned-clocks =3D <&tegra_car TEGRA114_CLK_VDE>; assigned-clock-parents =3D <&tegra_car TEGRA114_CLK_PLL_P>; @@ -1610,6 +1693,636 @@ i2c-thermtrip { }; }; =20 + memory-controller@70019000 { + emc-timings-0 { + /* Mozart Rev B Hynix DDR3 792MHz */ + nvidia,ram-code =3D <0>; + + timing-12750000 { + clock-frequency =3D <12750000>; + + nvidia,emem-configuration =3D < 0x40040001 0x8000003f + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000002 0x00000008 + 0x00000002 0x00000001 0x00000003 0x00000006 + 0x06030102 0x000a0402 0x77e30303 0x001f0000 >; + }; + + timing-20400000 { + clock-frequency =3D <20400000>; + + nvidia,emem-configuration =3D < 0x40020001 0x80000046 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000002 0x00000008 + 0x00000002 0x00000001 0x00000003 0x00000006 + 0x06030102 0x000a0402 0x76230303 0x001f0000 >; + }; + + timing-40800000 { + clock-frequency =3D <40800000>; + + nvidia,emem-configuration =3D < 0xa0000001 0x8000005b + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000002 0x00000008 + 0x00000002 0x00000001 0x00000003 0x00000006 + 0x06030102 0x000a0402 0x74a30303 0x001f0000 >; + }; + + timing-68000000 { + clock-frequency =3D <68000000>; + + nvidia,emem-configuration =3D < 0x00000001 0x80000076 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000002 0x00000008 + 0x00000002 0x00000001 0x00000003 0x00000006 + 0x06030102 0x000a0402 0x74230403 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency =3D <102000000>; + + nvidia,emem-configuration =3D < 0x08000001 0x80000098 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000002 0x00000001 0x00000002 0x00000008 + 0x00000002 0x00000001 0x00000003 0x00000006 + 0x06030102 0x000a0403 0x73c30504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency =3D <204000000>; + + nvidia,emem-configuration =3D < 0x01000003 0x800000fe + 0x00000001 0x00000001 0x00000005 0x00000002 + 0x00000004 0x00000001 0x00000002 0x00000008 + 0x00000002 0x00000001 0x00000003 0x00000006 + 0x06030102 0x000a0405 0x73840a06 0x001f0000 >; + }; + + timing-312000000 { + clock-frequency =3D <312000000>; + + nvidia,emem-configuration =3D < 0x0b000004 0x8000016a + 0x00000001 0x00000002 0x00000007 0x00000004 + 0x00000006 0x00000001 0x00000002 0x00000007 + 0x00000002 0x00000002 0x00000004 0x00000006 + 0x06040202 0x000b0607 0x76e50f08 0x001f0000 >; + }; + + timing-408000000 { + clock-frequency =3D <408000000>; + + nvidia,emem-configuration =3D < 0x02000006 0x80000190 + 0x00000001 0x00000002 0x0000000a 0x00000006 + 0x00000008 0x00000001 0x00000002 0x00000009 + 0x00000002 0x00000002 0x00000004 0x00000006 + 0x06040202 0x000e070a 0x7547130b 0x001f0000 >; + }; + + timing-528000000 { + clock-frequency =3D <528000000>; + + nvidia,emem-configuration =3D < 0x0f000007 0x80000190 + 0x00000002 0x00000003 0x0000000d 0x00000008 + 0x0000000a 0x00000001 0x00000002 0x00000009 + 0x00000002 0x00000002 0x00000005 0x00000006 + 0x06050202 0x0010090d 0x7428180e 0x001f0000 >; + }; + + timing-624000000 { + clock-frequency =3D <624000000>; + + nvidia,emem-configuration =3D < 0x06000009 0x80000190 + 0x00000003 0x00000004 0x0000000f 0x00000009 + 0x0000000c 0x00000001 0x00000003 0x0000000b + 0x00000002 0x00000002 0x00000005 0x00000007 + 0x07050202 0x00130b0f 0x736a1d10 0x001f0000 >; + }; + + timing-792000000 { + clock-frequency =3D <792000000>; + + nvidia,emem-configuration =3D < 0x0e00000b 0x80000190 + 0x00000004 0x00000005 0x00000013 0x0000000c + 0x0000000f 0x00000002 0x00000003 0x0000000c + 0x00000002 0x00000002 0x00000006 0x00000008 + 0x08060202 0x00160d13 0x734c2414 0x001f0000 >; + }; + }; + }; + + external-memory-controller@7001b000 { + emc-timings-0 { + /* Mozart Rev B Hynix DDR3 792MHz */ + nvidia,ram-code =3D <0>; + + timing-12750000 { + clock-frequency =3D <12750000>; + + nvidia,emc-zcal-cnt-long =3D <0x00000042>; + nvidia,emc-auto-cal-interval =3D <0x001fffff>; + nvidia,emc-cfg =3D <0x7324000e>; + nvidia,emc-mode-1 =3D <0x80100003>; + nvidia,emc-mode-2 =3D <0x80200008>; + nvidia,emc-mode-4 =3D <0x00000000>; + nvidia,emc-mode-reset =3D <0x80001221>; + nvidia,emc-auto-cal-config =3D <0xa0f10f0f>; + nvidia,emc-auto-cal-config2 =3D <0x00000000>; + nvidia,emc-auto-cal-config3 =3D <0x00000000>; + nvidia,emc-ctt-term-ctrl =3D <0x00000802>; + nvidia,emc-mrs-wait-cnt =3D <0x000c000c>; + nvidia,emc-sel-dpd-ctrl =3D <0x00040320>; + nvidia,emc-xm2dqspadctrl2 =3D <0x0000a11c>; + nvidia,emc-zcal-interval =3D <0x00000000>; + + nvidia,emc-configuration =3D < 0x00000000 + 0x00000003 0x00000000 0x00000000 0x00000004 + 0x0000000a 0x00000003 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x0000000f 0x00000006 0x00000006 + 0x00000004 0x00000004 0x00010000 0x00000000 + 0x00000000 0x00000004 0x00000009 0x0000000d + 0x0000000f 0x00000060 0x00000000 0x00000018 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000005 0x00000005 + 0x00000004 0x00000004 0x00000004 0x00000004 + 0x00000000 0x00000004 0x00000005 0x00000064 + 0x00000005 0x00000006 0x00000020 0x00000000 + 0x0000aa88 0x002c00a0 0x00008000 0x00064000 + 0x00064000 0x00064000 0x00064000 0x00064000 + 0x00064000 0x00064000 0x00064000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x0007c000 + 0x0007c000 0x0007c000 0x0007c000 0x001112a0 + 0x00000000 0x00000000 0x77ffc085 0x81f1f108 + 0x03037504 0x0000003f 0x20820800 0x00249249 + 0x0000003f 0x00000007 0x02000000 0x00000042 + 0x000c000c 0x00000000 0x00000000 0x800001c5 >; + }; + + timing-20400000 { + clock-frequency =3D <20400000>; + + nvidia,emc-zcal-cnt-long =3D <0x00000042>; + nvidia,emc-auto-cal-interval =3D <0x001fffff>; + nvidia,emc-cfg =3D <0x7324000e>; + nvidia,emc-mode-1 =3D <0x80100003>; + nvidia,emc-mode-2 =3D <0x80200008>; + nvidia,emc-mode-4 =3D <0x00000000>; + nvidia,emc-mode-reset =3D <0x80001221>; + nvidia,emc-auto-cal-config =3D <0xa0f10f0f>; + nvidia,emc-auto-cal-config2 =3D <0x00000000>; + nvidia,emc-auto-cal-config3 =3D <0x00000000>; + nvidia,emc-ctt-term-ctrl =3D <0x00000802>; + nvidia,emc-mrs-wait-cnt =3D <0x000c000c>; + nvidia,emc-sel-dpd-ctrl =3D <0x00040320>; + nvidia,emc-xm2dqspadctrl2 =3D <0x0000a11c>; + nvidia,emc-zcal-interval =3D <0x00000000>; + + nvidia,emc-configuration =3D < 0x00000000 + 0x00000005 0x00000000 0x00000000 0x00000004 + 0x0000000a 0x00000003 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x0000000f 0x00000006 0x00000006 + 0x00000004 0x00000004 0x00010000 0x00000000 + 0x00000000 0x00000004 0x00000009 0x0000000d + 0x0000000f 0x0000009a 0x00000000 0x00000026 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000006 0x00000006 + 0x00000004 0x00000004 0x00000004 0x00000004 + 0x00000000 0x00000004 0x00000005 0x000000a0 + 0x00000005 0x00000006 0x00000020 0x00000000 + 0x0000aa88 0x002c00a0 0x00008000 0x00064000 + 0x00064000 0x00064000 0x00064000 0x00064000 + 0x00064000 0x00064000 0x00064000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x0007c000 + 0x0007c000 0x0007c000 0x0007c000 0x001112a0 + 0x00000000 0x00000000 0x77ffc085 0x81f1f108 + 0x03037504 0x0000003f 0x20820800 0x00249249 + 0x0000003f 0x0000000b 0x02000000 0x00000042 + 0x000c000c 0x00000000 0x00000000 0x8000023a >; + }; + + timing-40800000 { + clock-frequency =3D <40800000>; + + nvidia,emc-zcal-cnt-long =3D <0x00000042>; + nvidia,emc-auto-cal-interval =3D <0x001fffff>; + nvidia,emc-cfg =3D <0x7324000e>; + nvidia,emc-mode-1 =3D <0x80100003>; + nvidia,emc-mode-2 =3D <0x80200008>; + nvidia,emc-mode-4 =3D <0x00000000>; + nvidia,emc-mode-reset =3D <0x80001221>; + nvidia,emc-auto-cal-config =3D <0xa0f10f0f>; + nvidia,emc-auto-cal-config2 =3D <0x00000000>; + nvidia,emc-auto-cal-config3 =3D <0x00000000>; + nvidia,emc-ctt-term-ctrl =3D <0x00000802>; + nvidia,emc-mrs-wait-cnt =3D <0x000c000c>; + nvidia,emc-sel-dpd-ctrl =3D <0x00040320>; + nvidia,emc-xm2dqspadctrl2 =3D <0x0000a11c>; + nvidia,emc-zcal-interval =3D <0x00000000>; + + nvidia,emc-configuration =3D < 0x00000001 + 0x0000000a 0x00000001 0x00000000 0x00000004 + 0x0000000a 0x00000003 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x0000000f 0x00000006 0x00000006 + 0x00000004 0x00000004 0x00010000 0x00000000 + 0x00000000 0x00000004 0x00000009 0x0000000d + 0x0000000f 0x00000134 0x00000000 0x0000004d + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000008 0x0000000f 0x0000000c 0x0000000c + 0x00000004 0x00000004 0x00000004 0x00000004 + 0x00000000 0x00000004 0x00000005 0x0000013f + 0x00000005 0x00000006 0x00000020 0x00000000 + 0x0000aa88 0x002c00a0 0x00008000 0x00064000 + 0x00064000 0x00064000 0x00064000 0x00064000 + 0x00064000 0x00064000 0x00064000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x0007c000 + 0x0007c000 0x0007c000 0x0007c000 0x001112a0 + 0x00000000 0x00000000 0x77ffc085 0x81f1f108 + 0x03037504 0x0000003f 0x20820800 0x00249249 + 0x0000003f 0x00000015 0x02000000 0x00000042 + 0x000c000c 0x00000000 0x00000000 0x80000370 >; + }; + + timing-68000000 { + clock-frequency =3D <68000000>; + + nvidia,emc-zcal-cnt-long =3D <0x00000042>; + nvidia,emc-auto-cal-interval =3D <0x001fffff>; + nvidia,emc-cfg =3D <0x7324000e>; + nvidia,emc-mode-1 =3D <0x80100003>; + nvidia,emc-mode-2 =3D <0x80200008>; + nvidia,emc-mode-4 =3D <0x00000000>; + nvidia,emc-mode-reset =3D <0x80001221>; + nvidia,emc-auto-cal-config =3D <0xa0f10f0f>; + nvidia,emc-auto-cal-config2 =3D <0x00000000>; + nvidia,emc-auto-cal-config3 =3D <0x00000000>; + nvidia,emc-ctt-term-ctrl =3D <0x00000802>; + nvidia,emc-mrs-wait-cnt =3D <0x000c000c>; + nvidia,emc-sel-dpd-ctrl =3D <0x00040320>; + nvidia,emc-xm2dqspadctrl2 =3D <0x0000a11c>; + nvidia,emc-zcal-interval =3D <0x00000000>; + + nvidia,emc-configuration =3D < 0x00000003 + 0x00000011 0x00000002 0x00000000 0x00000004 + 0x0000000a 0x00000003 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x0000000f 0x00000006 0x00000006 + 0x00000004 0x00000004 0x00010000 0x00000000 + 0x00000000 0x00000004 0x00000009 0x0000000d + 0x0000000f 0x00000202 0x00000000 0x00000080 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x0000000f 0x0000000f 0x00000013 0x00000013 + 0x00000004 0x00000004 0x00000004 0x00000004 + 0x00000000 0x00000004 0x00000005 0x00000213 + 0x00000005 0x00000006 0x00000020 0x00000000 + 0x0000aa88 0x002c00a0 0x00008000 0x00064000 + 0x00064000 0x00064000 0x00064000 0x00064000 + 0x00064000 0x00064000 0x00064000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x0007c000 + 0x0007c000 0x0007c000 0x0007c000 0x001112a0 + 0x00000000 0x00000000 0x77ffc085 0x81f1f108 + 0x03037504 0x0000003f 0x20820800 0x00249249 + 0x0000003f 0x00000022 0x02000000 0x00000042 + 0x000c000c 0x00000000 0x00000000 0x8000050e >; + }; + + timing-102000000 { + clock-frequency =3D <102000000>; + + nvidia,emc-zcal-cnt-long =3D <0x00000042>; + nvidia,emc-auto-cal-interval =3D <0x001fffff>; + nvidia,emc-cfg =3D <0x7324000e>; + nvidia,emc-mode-1 =3D <0x80100003>; + nvidia,emc-mode-2 =3D <0x80200008>; + nvidia,emc-mode-4 =3D <0x00000000>; + nvidia,emc-mode-reset =3D <0x80001221>; + nvidia,emc-auto-cal-config =3D <0xa0f10f0f>; + nvidia,emc-auto-cal-config2 =3D <0x00000000>; + nvidia,emc-auto-cal-config3 =3D <0x00000000>; + nvidia,emc-ctt-term-ctrl =3D <0x00000802>; + nvidia,emc-mrs-wait-cnt =3D <0x000c000c>; + nvidia,emc-sel-dpd-ctrl =3D <0x00040320>; + nvidia,emc-xm2dqspadctrl2 =3D <0x0000a11c>; + nvidia,emc-zcal-interval =3D <0x00000000>; + + nvidia,emc-configuration =3D < 0x00000004 + 0x0000001a 0x00000003 0x00000001 0x00000004 + 0x0000000a 0x00000003 0x0000000b 0x00000001 + 0x00000001 0x00000003 0x00000001 0x00000000 + 0x00000005 0x0000000f 0x00000006 0x00000006 + 0x00000004 0x00000004 0x00010000 0x00000000 + 0x00000000 0x00000004 0x00000009 0x0000000d + 0x0000000f 0x00000303 0x00000000 0x000000c0 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000018 0x0000000f 0x0000001c 0x0000001c + 0x00000004 0x00000004 0x00000004 0x00000005 + 0x00000000 0x00000004 0x00000005 0x0000031c + 0x00000005 0x00000006 0x00000020 0x00000000 + 0x0000aa88 0x002c00a0 0x00008000 0x00064000 + 0x00064000 0x00064000 0x00064000 0x00064000 + 0x00064000 0x00064000 0x00064000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x0007c000 + 0x0007c000 0x0007c000 0x0007c000 0x001112a0 + 0x00000000 0x00000000 0x77ffc085 0x81f1f108 + 0x03037504 0x0000003f 0x20820800 0x00249249 + 0x0000003f 0x00000033 0x02000000 0x00000042 + 0x000c000c 0x00000000 0x00000000 0x80000713 >; + }; + + timing-204000000 { + clock-frequency =3D <204000000>; + + nvidia,emc-zcal-cnt-long =3D <0x00000042>; + nvidia,emc-auto-cal-interval =3D <0x001fffff>; + nvidia,emc-cfg =3D <0x7320000e>; + nvidia,emc-mode-1 =3D <0x80100003>; + nvidia,emc-mode-2 =3D <0x80200008>; + nvidia,emc-mode-4 =3D <0x00000000>; + nvidia,emc-mode-reset =3D <0x80001221>; + nvidia,emc-auto-cal-config =3D <0xa0f10f0f>; + nvidia,emc-auto-cal-config2 =3D <0x00000000>; + nvidia,emc-auto-cal-config3 =3D <0x00000000>; + nvidia,emc-ctt-term-ctrl =3D <0x00000802>; + nvidia,emc-mrs-wait-cnt =3D <0x000c000c>; + nvidia,emc-sel-dpd-ctrl =3D <0x00040320>; + nvidia,emc-xm2dqspadctrl2 =3D <0x0000a11c>; + nvidia,emc-zcal-interval =3D <0x00020000>; + + nvidia,emc-configuration =3D < 0x00000009 + 0x00000035 0x00000007 0x00000002 0x00000004 + 0x0000000a 0x00000003 0x0000000b 0x00000002 + 0x00000002 0x00000003 0x00000001 0x00000000 + 0x00000005 0x0000000f 0x00000007 0x00000006 + 0x00000004 0x00000004 0x00010000 0x00000000 + 0x00000000 0x00000004 0x00000009 0x0000000d + 0x0000000f 0x00000607 0x00000000 0x00000181 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000032 0x0000000f 0x00000038 0x00000038 + 0x00000004 0x00000004 0x00000004 0x00000009 + 0x00000000 0x00000004 0x00000005 0x00000638 + 0x00000006 0x00000004 0x00000020 0x00000000 + 0x0000aa88 0x002c00a0 0x00008000 0x00064000 + 0x00064000 0x00064000 0x00064000 0x00064000 + 0x00064000 0x00064000 0x00064000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x0007c000 + 0x0007c000 0x0007c000 0x0007c000 0x001112a0 + 0x00000000 0x00000000 0x77ffc085 0x81f1f108 + 0x03037504 0x0000003f 0x20820800 0x00249249 + 0x0000003f 0x00000000 0x02000000 0x00000100 + 0x000c000c 0x00000000 0x00000000 0x80000d22 >; + }; + + timing-312000000 { + clock-frequency =3D <312000000>; + + nvidia,emc-zcal-cnt-long =3D <0x00000042>; + nvidia,emc-auto-cal-interval =3D <0x001fffff>; + nvidia,emc-cfg =3D <0x5300000e>; + nvidia,emc-mode-1 =3D <0x80100002>; + nvidia,emc-mode-2 =3D <0x80200000>; + nvidia,emc-mode-4 =3D <0x00000000>; + nvidia,emc-mode-reset =3D <0x80000321>; + nvidia,emc-auto-cal-config =3D <0xa0f10f0f>; + nvidia,emc-auto-cal-config2 =3D <0x00000000>; + nvidia,emc-auto-cal-config3 =3D <0x00000000>; + nvidia,emc-ctt-term-ctrl =3D <0x00000802>; + nvidia,emc-mrs-wait-cnt =3D <0x0171000c>; + nvidia,emc-sel-dpd-ctrl =3D <0x00040320>; + nvidia,emc-xm2dqspadctrl2 =3D <0x0001013d>; + nvidia,emc-zcal-interval =3D <0x00020000>; + + nvidia,emc-configuration =3D < 0x0000000e + 0x00000050 0x00000009 0x00000003 0x00000004 + 0x00000008 0x00000002 0x00000009 0x00000003 + 0x00000003 0x00000002 0x00000001 0x00000000 + 0x00000004 0x0000000f 0x00000006 0x00000006 + 0x00000005 0x00000004 0x00010000 0x00000000 + 0x00000000 0x00000004 0x0000000b 0x0000000d + 0x0000000f 0x00000941 0x00000000 0x00000250 + 0x00000001 0x00000008 0x00000001 0x00000000 + 0x0000004d 0x0000000e 0x00000055 0x00000200 + 0x00000004 0x00000004 0x00000004 0x0000000d + 0x00000000 0x00000004 0x00000005 0x00000982 + 0x00000000 0x00000004 0x00000020 0x00000000 + 0x00005088 0x002c00a0 0x00008000 0x00030000 + 0x00030000 0x00030000 0x00030000 0x00030000 + 0x00030000 0x00030000 0x00030000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x0003c000 + 0x0003c000 0x0003c000 0x0003c000 0x001112a0 + 0x00000000 0x00000000 0x77ffc085 0x81f1f108 + 0x03037504 0x00000000 0x20820800 0x00249249 + 0x0000003f 0x00000000 0x02000000 0x00000100 + 0x0171000c 0x00000000 0x00000000 0x8000138d >; + }; + + timing-408000000 { + clock-frequency =3D <408000000>; + + nvidia,emc-zcal-cnt-long =3D <0x00000042>; + nvidia,emc-auto-cal-interval =3D <0x001fffff>; + nvidia,emc-cfg =3D <0x53000006>; + nvidia,emc-mode-1 =3D <0x80100002>; + nvidia,emc-mode-2 =3D <0x80200008>; + nvidia,emc-mode-4 =3D <0x00000000>; + nvidia,emc-mode-reset =3D <0x80000731>; + nvidia,emc-auto-cal-config =3D <0xa0f10f0f>; + nvidia,emc-auto-cal-config2 =3D <0x00000000>; + nvidia,emc-auto-cal-config3 =3D <0x00000000>; + nvidia,emc-ctt-term-ctrl =3D <0x00000802>; + nvidia,emc-mrs-wait-cnt =3D <0x0158000c>; + nvidia,emc-sel-dpd-ctrl =3D <0x00040320>; + nvidia,emc-xm2dqspadctrl2 =3D <0x0001013d>; + nvidia,emc-zcal-interval =3D <0x00020000>; + + nvidia,emc-configuration =3D < 0x00000012 + 0x00000069 0x0000000d 0x00000004 0x00000005 + 0x00000009 0x00000002 0x0000000c 0x00000004 + 0x00000004 0x00000002 0x00000001 0x00000000 + 0x00000004 0x0000000f 0x00000006 0x00000006 + 0x00000005 0x00000004 0x00010000 0x00000000 + 0x00000000 0x00000004 0x0000000c 0x0000000e + 0x00000010 0x00000c2e 0x00000000 0x0000030b + 0x00000001 0x00000008 0x00000001 0x00000000 + 0x00000066 0x00000011 0x0000006f 0x00000200 + 0x00000004 0x00000004 0x00000004 0x00000011 + 0x00000000 0x00000004 0x00000005 0x00000c6f + 0x00000000 0x00000004 0x00000020 0x00000000 + 0x00005088 0x002c0080 0x00008000 0x00030000 + 0x00030000 0x00030000 0x00030000 0x00030000 + 0x00030000 0x00030000 0x00030000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x0003c000 + 0x0003c000 0x0003c000 0x0003c000 0x001112a0 + 0x00000000 0x00000000 0x77ffc085 0x81f1f108 + 0x03037504 0x00000000 0x20820800 0x00249249 + 0x0000003f 0x00000000 0x02000000 0x00000100 + 0x0158000c 0x00000000 0x00000000 0x80001941 >; + }; + + timing-528000000 { + clock-frequency =3D <528000000>; + + nvidia,emc-zcal-cnt-long =3D <0x00000042>; + nvidia,emc-auto-cal-interval =3D <0x001fffff>; + nvidia,emc-cfg =3D <0x53000004>; + nvidia,emc-mode-1 =3D <0x80100002>; + nvidia,emc-mode-2 =3D <0x80200008>; + nvidia,emc-mode-4 =3D <0x00000000>; + nvidia,emc-mode-reset =3D <0x80000941>; + nvidia,emc-auto-cal-config =3D <0xa0f10f0f>; + nvidia,emc-auto-cal-config2 =3D <0x00000000>; + nvidia,emc-auto-cal-config3 =3D <0x00000000>; + nvidia,emc-ctt-term-ctrl =3D <0x00000802>; + nvidia,emc-mrs-wait-cnt =3D <0x013a000c>; + nvidia,emc-sel-dpd-ctrl =3D <0x00040320>; + nvidia,emc-xm2dqspadctrl2 =3D <0x0000013d>; + nvidia,emc-zcal-interval =3D <0x00020000>; + + nvidia,emc-configuration =3D < 0x00000018 + 0x00000088 0x00000011 0x00000006 0x00000006 + 0x00000009 0x00000002 0x0000000d 0x00000006 + 0x00000006 0x00000002 0x00000001 0x00000000 + 0x00000005 0x0000000f 0x00000008 0x00000009 + 0x00000007 0x00000004 0x00010000 0x00000000 + 0x00000000 0x00000006 0x0000000c 0x00000010 + 0x00000012 0x00000fd6 0x00000000 0x000003f5 + 0x00000002 0x0000000b 0x00000001 0x00000000 + 0x00000084 0x00000012 0x0000008f 0x00000200 + 0x00000004 0x00000004 0x00000004 0x00000016 + 0x00000000 0x00000005 0x00000006 0x00001017 + 0x00000000 0x00000006 0x00000020 0x00000000 + 0x00005088 0xf0120091 0x00008000 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x0000000c + 0x0000000b 0x0000000c 0x0000000c 0x001112a0 + 0x00000000 0x00000000 0x77ffc085 0x81f1f108 + 0x07077504 0x00000000 0x20820800 0x00249249 + 0x0000003f 0x00000000 0x02000000 0x00000100 + 0x013a000c 0x00000000 0x00000000 0x80002062 >; + }; + + timing-624000000 { + clock-frequency =3D <624000000>; + + nvidia,emc-zcal-cnt-long =3D <0x00000042>; + nvidia,emc-auto-cal-interval =3D <0x001fffff>; + nvidia,emc-cfg =3D <0x53200000>; + nvidia,emc-mode-1 =3D <0x80100002>; + nvidia,emc-mode-2 =3D <0x80200410>; + nvidia,emc-mode-4 =3D <0x00000000>; + nvidia,emc-mode-reset =3D <0x80000b61>; + nvidia,emc-auto-cal-config =3D <0xa0f10f0f>; + nvidia,emc-auto-cal-config2 =3D <0x00000000>; + nvidia,emc-auto-cal-config3 =3D <0x00000000>; + nvidia,emc-ctt-term-ctrl =3D <0x00000802>; + nvidia,emc-mrs-wait-cnt =3D <0x0122000c>; + nvidia,emc-sel-dpd-ctrl =3D <0x00040320>; + nvidia,emc-xm2dqspadctrl2 =3D <0x0000013d>; + nvidia,emc-zcal-interval =3D <0x00020000>; + + nvidia,emc-configuration =3D < 0x0000001d + 0x000000a1 0x00000014 0x00000007 0x00000007 + 0x0000000b 0x00000003 0x00000010 0x00000007 + 0x00000007 0x00000002 0x00000001 0x00000000 + 0x00000005 0x0000000f 0x00000009 0x0000000a + 0x00000008 0x00000004 0x00010000 0x00000000 + 0x00000000 0x00000007 0x0000000c 0x00000012 + 0x00000014 0x000012c3 0x00000000 0x000004b0 + 0x00000002 0x0000000d 0x00000001 0x00000000 + 0x0000009c 0x00000015 0x000000a9 0x00000200 + 0x00000005 0x00000005 0x00000005 0x00000019 + 0x00000000 0x00000006 0x00000007 0x00001304 + 0x00000009 0x00000006 0x80000000 0x00000000 + 0x0000ba88 0xf00d0191 0x00008000 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x0000000b + 0x0000000b 0x0000000b 0x0000000b 0x001112a0 + 0x00000000 0x00000000 0x77ffc085 0x81f1f108 + 0x07077504 0x00000000 0x20820800 0x0028a28a + 0x0000003f 0x00000000 0x02000000 0x00000100 + 0x0122000c 0x00000000 0x00000000 0x80002617 >; + }; + + timing-792000000 { + clock-frequency =3D <792000000>; + + nvidia,emc-zcal-cnt-long =3D <0x00000042>; + nvidia,emc-auto-cal-interval =3D <0x001fffff>; + nvidia,emc-cfg =3D <0x53000000>; + nvidia,emc-mode-1 =3D <0x80100002>; + nvidia,emc-mode-2 =3D <0x80200418>; + nvidia,emc-mode-4 =3D <0x00000000>; + nvidia,emc-mode-reset =3D <0x80000d71>; + nvidia,emc-auto-cal-config =3D <0xa0f10f0f>; + nvidia,emc-auto-cal-config2 =3D <0x00000000>; + nvidia,emc-auto-cal-config3 =3D <0x00000000>; + nvidia,emc-ctt-term-ctrl =3D <0x00000802>; + nvidia,emc-mrs-wait-cnt =3D <0x00f8000c>; + nvidia,emc-sel-dpd-ctrl =3D <0x00040000>; + nvidia,emc-xm2dqspadctrl2 =3D <0x0000013d>; + nvidia,emc-zcal-interval =3D <0x00020000>; + + nvidia,emc-configuration =3D < 0x00000025 + 0x000000cc 0x0000001a 0x00000009 0x00000008 + 0x0000000d 0x00000004 0x00000013 0x00000009 + 0x00000009 0x00000003 0x00000001 0x00000000 + 0x00000006 0x0000000f 0x0000000a 0x0000000b + 0x00000008 0x00000006 0x00010000 0x00000000 + 0x00000000 0x00000008 0x0000000d 0x00000014 + 0x00000016 0x000017e1 0x00000000 0x000005f8 + 0x00000003 0x00000011 0x00000001 0x00000000 + 0x000000c6 0x00000018 0x000000d6 0x00000200 + 0x00000005 0x00000005 0x00000005 0x00000020 + 0x00000000 0x00000007 0x00000008 0x00001822 + 0x00000000 0x00000006 0x80000000 0x00000000 + 0x00005088 0xf0070191 0x00008000 0x00000009 + 0x00000009 0x00000009 0x00000009 0x00000009 + 0x00000009 0x00000009 0x00000009 0x00018000 + 0x00018000 0x00018000 0x00018000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x0000000b + 0x0000000b 0x0000000b 0x0000000b 0x001112a0 + 0x00000000 0x00000000 0x77ffc085 0x81f1f108 + 0x07077504 0x00000000 0x1c71c700 0x0028a28a + 0x0000003f 0x00000000 0x02000000 0x00000100 + 0x00f8000c 0x00000000 0x00000000 0x80003012 >; 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Fri, 31 Jul 2026 04:41:25 -0700 (PDT) From: Svyatoslav Ryhel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Mikko Perttunen , Svyatoslav Ryhel Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 04/10] ARM: tegra: tf701t: Remove pin_ prefix from PMIC pinmux Date: Fri, 31 Jul 2026 14:41:00 +0300 Message-ID: <20260731114106.169398-5-clamor95@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260731114106.169398-1-clamor95@gmail.com> References: <20260731114106.169398-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Schema discourages using "_" in node names. Since pin names in palmas pinmux is not an ABI, remove all "pin_" prefixes from names. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen --- .../boot/dts/nvidia/tegra114-asus-tf701t.dts | 20 +++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts b/arch/arm/b= oot/dts/nvidia/tegra114-asus-tf701t.dts index 00eeedf3ef7a5..a27d3c4f2c63c 100644 --- a/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts +++ b/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts @@ -1462,52 +1462,52 @@ pinmux { pinctrl-0 =3D <&palmas_default>; =20 palmas_default: pinmux { - pin_gpio0 { + gpio0 { pins =3D "gpio0"; function =3D "gpio"; }; =20 - pin_gpio1 { + gpio1 { pins =3D "gpio1"; function =3D "gpio"; }; =20 - pin_gpio2 { + gpio2 { pins =3D "gpio2"; function =3D "gpio"; }; =20 - pin_gpio3 { + gpio3 { pins =3D "gpio3"; function =3D "gpio"; }; =20 - pin_gpio4 { + gpio4 { pins =3D "gpio4"; function =3D "gpio"; }; =20 - pin_gpio5 { + gpio5 { pins =3D "gpio5"; function =3D "gpio"; }; =20 - pin_gpio6 { + gpio6 { pins =3D "gpio6"; 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charset="utf-8" ASUS TF701T has an additional thermal sensor for more accurate readings. Add thermal zones for this sensor. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen --- .../boot/dts/nvidia/tegra114-asus-tf701t.dts | 83 +++++++++++++++++++ 1 file changed, 83 insertions(+) diff --git a/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts b/arch/arm/b= oot/dts/nvidia/tegra114-asus-tf701t.dts index a27d3c4f2c63c..83f8dd84d28a2 100644 --- a/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts +++ b/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts @@ -4,6 +4,7 @@ =20 #include #include +#include =20 #include "tegra114.dtsi" =20 @@ -2682,4 +2683,86 @@ vdd_1v8_touch: regulator-touch-vio { enable-active-high; vin-supply =3D <&vdd_3v3_sys>; }; + + thermal-zones { + /* + * NCT72 has two sensors: + * + * 0: internal that monitors ambient/skin temperature + * 1: external that is connected to the CPU's diode + * + * Ideally we should use userspace thermal governor, + * but it's a much more complex solution. The "skin" + * zone exists as a simpler solution which prevents + * Transformer from getting too hot from a user's + * tactile perspective. The CPU zone is intended to + * protect silicon from damage. + */ + + nct72-skin-thermal { + polling-delay-passive =3D <1000>; /* milliseconds */ + polling-delay =3D <5000>; /* milliseconds */ + + thermal-sensors =3D <&temp_sensor 0>; + + trips { + skin_alert_trip: skin-alert { + /* throttle at 57C until temperature drops to 56.5C */ + temperature =3D <57000>; + hysteresis =3D <500>; + type =3D "passive"; + }; + + skin-crit { + /* shut down at 65C */ + temperature =3D <65000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + + cooling-maps { + map-skin { + trip =3D <&skin_alert_trip>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + nct72-cpu-thermal { + polling-delay-passive =3D <1000>; /* milliseconds */ + polling-delay =3D <5000>; /* milliseconds */ + + thermal-sensors =3D <&temp_sensor 1>; + + trips { + cpu_alert_trip: cpu-alert { + /* throttle at 75C until temperature drops to 74.5C */ + temperature =3D <75000>; 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charset="utf-8" Add SDR104 mode to WiFi SDIO and uSD device nodes, remove mmc-ddr-1_8v which is eMMC specific and improve their power sequences. The uSD card refuses to work reliably with fixed regulator and 1.8V IO supply. Adjust configuration to mimic setup proposed by the vendor in the downstream kernel. Add HS200 mode support to the eMMC sdmmc device node. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen --- .../boot/dts/nvidia/tegra114-asus-tf701t.dts | 35 +++++++------------ 1 file changed, 13 insertions(+), 22 deletions(-) diff --git a/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts b/arch/arm/b= oot/dts/nvidia/tegra114-asus-tf701t.dts index 83f8dd84d28a2..3de5c84d5f009 100644 --- a/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts +++ b/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts @@ -1645,9 +1645,9 @@ ldo8 { =20 vddio_usd: ldo9 { regulator-name =3D "vddio_usd"; - /* min voltage of 1.8v is not stable */ - regulator-min-microvolt =3D <2900000>; + regulator-min-microvolt =3D <1800000>; regulator-max-microvolt =3D <2900000>; + regulator-boot-on; }; =20 avdd_hdmi: ldoln { @@ -2350,9 +2350,9 @@ brcm_wifi_pwrseq: pwrseq-wifi { clocks =3D <&tegra_pmc TEGRA_PMC_CLK_BLINK>; clock-names =3D "ext_clock"; =20 - reset-gpios =3D <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; - post-power-on-delay-ms =3D <300>; - power-off-delay-us =3D <300>; + reset-gpios =3D <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_LOW>; + post-power-on-delay-ms =3D <100>; + power-off-delay-us =3D <100>; }; =20 /* WiFi */ @@ -2372,9 +2372,7 @@ mmc@78000000 { non-removable; =20 sd-uhs-ddr50; - mmc-ddr-1_8v; - - power-gpios =3D <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>; + sd-uhs-sdr104; =20 nvidia,default-tap =3D <0x2>; nvidia,default-trim =3D <0x2>; @@ -2396,14 +2394,18 @@ wifi@1 { /* MicroSD card */ mmc@78000400 { status =3D "okay"; - bus-width =3D <4>; + cd-gpios =3D <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + power-gpios =3D <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; + + sd-uhs-ddr50; + sd-uhs-sdr104; =20 nvidia,default-tap =3D <0x3>; nvidia,default-trim =3D <0x3>; =20 - vmmc-supply =3D <&vdd_2v9_usd>; + vmmc-supply =3D <&vcore_emmc>; vqmmc-supply =3D <&vddio_usd>; }; =20 @@ -2414,6 +2416,7 @@ mmc@78000600 { =20 non-removable; mmc-ddr-1_8v; + mmc-hs200-1_8v; =20 vmmc-supply =3D <&vcore_emmc>; vqmmc-supply =3D <&vdd_1v8_vio>; @@ -2608,17 +2611,6 @@ hdmi_5v0_sys: regulator-hdmi { vin-supply =3D <&vdd_smps10_out2>; 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Fri, 31 Jul 2026 04:41:32 -0700 (PDT) Received: from xeon ([188.163.112.51]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47fd41d0064sm3769336f8f.5.2026.07.31.04.41.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Jul 2026 04:41:31 -0700 (PDT) From: Svyatoslav Ryhel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Mikko Perttunen , Svyatoslav Ryhel Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 07/10] ARM: tegra: tf701t: Fix BCM43341 WiFi/BT chip configuration Date: Fri, 31 Jul 2026 14:41:03 +0300 Message-ID: <20260731114106.169398-8-clamor95@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260731114106.169398-1-clamor95@gmail.com> References: <20260731114106.169398-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The BCM4334 chip's Bluetooth part does not support reset-gpio. This was confirmed by testing on the TF701T, so drop reset-gpio from the Bluetooth node to comply with the existing schema. Additionally, the BCM4334 supports an LPO clock, which is required for proper and stable operation of WiFi and Bluetooth, so add it to both nodes. Lastly, the BCM4334 chip's WiFi part has a dedicated compatible in the schema, so set 'brcm,bcm43340-fmac' as the primary compatible while 'brcm,bcm4329-fmac' remains as a fallback. Signed-off-by: Svyatoslav Ryhel --- arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts b/arch/arm/b= oot/dts/nvidia/tegra114-asus-tf701t.dts index 3de5c84d5f009..b71a02b3fd86f 100644 --- a/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts +++ b/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts @@ -1300,8 +1300,9 @@ bluetooth { compatible =3D "brcm,bcm4334-bt"; max-speed =3D <4000000>; =20 - clocks =3D <&tegra_pmc TEGRA_PMC_CLK_BLINK>; - clock-names =3D "txco"; + clocks =3D <&tegra_pmc TEGRA_PMC_CLK_BLINK>, + <&palmas_clk32k>; + clock-names =3D "txco", "lpo"; =20 interrupt-parent =3D <&gpio>; interrupts =3D ; @@ -1309,7 +1310,6 @@ bluetooth { =20 device-wakeup-gpios =3D <&gpio TEGRA_GPIO(EE, 1) GPIO_ACTIVE_HIGH>; shutdown-gpios =3D <&gpio TEGRA_GPIO(Q, 7) GPIO_ACTIVE_HIGH>; - reset-gpios =3D <&gpio TEGRA_GPIO(Q, 6) GPIO_ACTIVE_LOW>; =20 vbat-supply =3D <&vdd_3v3_com>; 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charset="utf-8" Add missing vs-supply and io-channel-cells. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen --- arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts b/arch/arm/b= oot/dts/nvidia/tegra114-asus-tf701t.dts index b71a02b3fd86f..32d55c18c7446 100644 --- a/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts +++ b/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts @@ -1391,6 +1391,9 @@ power-sensor@44 { reg =3D <0x44>; =20 shunt-resistor =3D <5000>; + + vs-supply =3D <&vdd_3v3_sys>; + #io-channel-cells =3D <1>; }; }; =20 --=20 2.53.0 From nobody Fri Oct 2 13:10:15 2026 Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 781183FBEB0 for ; Fri, 31 Jul 2026 11:41:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.54 ARC-Seal: i=1; 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charset="utf-8" Set UART-B line to use hsuart since it has GPS device linked to it. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen --- arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts b/arch/arm/b= oot/dts/nvidia/tegra114-asus-tf701t.dts index 32d55c18c7446..0d182fa5c1af2 100644 --- a/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts +++ b/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts @@ -1283,6 +1283,11 @@ drive-gma { }; =20 serial@70006040 { + compatible =3D "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart"; + reset-names =3D "serial"; + /delete-property/ reg-shift; + status =3D "okay"; + /* GPS */ }; =20 --=20 2.53.0 From nobody Fri Oct 2 13:10:15 2026 Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D01D042A168 for ; Fri, 31 Jul 2026 11:41:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 31 Jul 2026 04:41:40 -0700 (PDT) Received: from xeon ([188.163.112.51]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47fd41d0064sm3769336f8f.5.2026.07.31.04.41.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Jul 2026 04:41:40 -0700 (PDT) From: Svyatoslav Ryhel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Mikko Perttunen , Svyatoslav Ryhel Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 10/10] ARM: tegra: tf701t: Add chosen node Date: Fri, 31 Jul 2026 14:41:06 +0300 Message-ID: <20260731114106.169398-11-clamor95@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260731114106.169398-1-clamor95@gmail.com> References: <20260731114106.169398-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add chosen node since some bootloaders may require it and add stdout link to UART-D to simplify getting kernel log via console. Signed-off-by: Svyatoslav Ryhel --- arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts b/arch/arm/b= oot/dts/nvidia/tegra114-asus-tf701t.dts index 0d182fa5c1af2..1b9839a855610 100644 --- a/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts +++ b/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts @@ -26,6 +26,10 @@ aliases { serial2 =3D &uartb; /* GPS */ }; =20 + chosen { + stdout-path =3D "serial0:115200n8"; + }; + firmware { trusted-foundations { compatible =3D "tlm,trusted-foundations"; --=20 2.53.0