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charset="utf-8" Static-config MMCM/PLL ratios are fixed at IP build time, so the kernel cannot read per-output multiply/divide from registers and needs DT pairs to register fixed-factor clocks. Also add the tuples by pair in example. In static-config mode the IP exposes only fixed-factor clock outputs and has no runtime-programmable registers, so reg is not required. Make reg optional for static-config In static-config mode the AXI bus interface is unused, so s_axi_aclk is not required. Allow clocks/clock-names to have only one entry (clk_in1) when xlnx,static-config is present and enforce two entries otherwise. Update the static-config example accordingly. Reviewed-by: Rob Herring (Arm) Signed-off-by: Shubhrajyoti Datta --- Changes in v3: Added reviewed tag Changes in v2: Merged the similar patches Allow check for current dt even if it is unused. .../bindings/clock/xlnx,clocking-wizard.yaml | 53 +++++++++++++++++-- 1 file changed, 48 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.y= aml b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml index b497c28e8094..865927b9f1be 100644 --- a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml +++ b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml @@ -29,11 +29,13 @@ properties: const: 1 =20 clocks: + minItems: 1 items: - description: clock input - description: axi clock =20 clock-names: + minItems: 1 items: - const: clk_in1 - const: s_axi_aclk @@ -57,27 +59,68 @@ properties: description: Number of outputs. =20 + xlnx,clk-mul-div: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: + Fixed MMCM/PLL multiply/divide ratios, one (multiplier, divisor) + pair per clock output relative to clk_in1. The number of entries + must equal xlnx,nr-outputs. + minItems: 1 + maxItems: 8 + items: + items: + - description: multiplier + minimum: 1 + - description: divisor + minimum: 1 + required: - compatible - - reg - "#clock-cells" - clocks - clock-names - xlnx,speed-grade - xlnx,nr-outputs =20 +allOf: + - if: + required: + - xlnx,static-config + then: + required: + - xlnx,clk-mul-div + else: + required: + - reg + properties: + clocks: + minItems: 2 + clock-names: + minItems: 2 + additionalProperties: false =20 examples: - | - clock-controller@b0000000 { + clock-controller@b0000000 { compatible =3D "xlnx,clocking-wizard"; reg =3D <0xb0000000 0x10000>; #clock-cells =3D <1>; - xlnx,static-config; + clocks =3D <&clkc 15>, <&clkc 18>; + clock-names =3D "clk_in1", "s_axi_aclk"; + xlnx,nr-outputs =3D <6>; xlnx,speed-grade =3D <1>; + }; + + - | + clock-controller { + compatible =3D "xlnx,clocking-wizard"; + #clock-cells =3D <1>; + clocks =3D <&clkc 15>; + clock-names =3D "clk_in1"; xlnx,nr-outputs =3D <6>; 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charset="utf-8" With xlnx,static-config the MMCM/PLL topology is fixed at synthesis time and no register programming is performed; only the dynamic path needs the AXI register block. Move devm_platform_ioremap_resource() under the non-static-config branch. Signed-off-by: Shubhrajyoti Datta --- (no changes since v1) drivers/clk/xilinx/clk-xlnx-clock-wizard.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c b/drivers/clk/xilin= x/clk-xlnx-clock-wizard.c index 4a0136349f71..e082051221be 100644 --- a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c +++ b/drivers/clk/xilinx/clk-xlnx-clock-wizard.c @@ -1168,10 +1168,6 @@ static int clk_wzrd_probe(struct platform_device *pd= ev) return -ENOMEM; platform_set_drvdata(pdev, clk_wzrd); =20 - clk_wzrd->base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(clk_wzrd->base)) - return PTR_ERR(clk_wzrd->base); - clk_wzrd->axi_clk =3D devm_clk_get_enabled(&pdev->dev, "s_axi_aclk"); if (IS_ERR(clk_wzrd->axi_clk)) return dev_err_probe(&pdev->dev, PTR_ERR(clk_wzrd->axi_clk), @@ -1183,6 +1179,10 @@ static int clk_wzrd_probe(struct platform_device *pd= ev) } =20 if (!of_property_present(np, "xlnx,static-config")) { + clk_wzrd->base =3D devm_platform_ioremap_resource(pdev, 0); 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charset="utf-8" The clk_in1 is the input clock for both the dynamic reconfig and the static-config paths. Acquire clk_in1 for static-config as well. Output clocks are registered as fixed-factor children of clk_in1. Signed-off-by: Shubhrajyoti Datta --- (no changes since v1) drivers/clk/xilinx/clk-xlnx-clock-wizard.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c b/drivers/clk/xilin= x/clk-xlnx-clock-wizard.c index e082051221be..ffc78c90bee6 100644 --- a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c +++ b/drivers/clk/xilinx/clk-xlnx-clock-wizard.c @@ -1178,6 +1178,11 @@ static int clk_wzrd_probe(struct platform_device *pd= ev) return -EINVAL; } =20 + clk_wzrd->clk_in1 =3D devm_clk_get(&pdev->dev, "clk_in1"); + if (IS_ERR(clk_wzrd->clk_in1)) + return dev_err_probe(&pdev->dev, PTR_ERR(clk_wzrd->clk_in1), + "failed to get clk_in1\n"); + if (!of_property_present(np, "xlnx,static-config")) { clk_wzrd->base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(clk_wzrd->base)) @@ -1192,11 +1197,6 @@ static int clk_wzrd_probe(struct platform_device *pd= ev) } } =20 - clk_wzrd->clk_in1 =3D devm_clk_get(&pdev->dev, "clk_in1"); - if (IS_ERR(clk_wzrd->clk_in1)) - return dev_err_probe(&pdev->dev, PTR_ERR(clk_wzrd->clk_in1), - "clk_in1 not found\n"); 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charset="utf-8" When xlnx,static-config is present the divider/multiplier path is synthesized inside the Wizard without exposing runtime MMIO reconfiguration, so omit the AXI register mapping and advertise each routed output clock as a clk_fixed_factor child of clk_in1 using the synthesized ratios exported through xlnx,clk-mul-div. However the parent clock of clk_in1 can still be gated, disabled, or (re-)enabled after FPGA programming (typical FPGA Manager flows, CCF-managed parents, PLL fabric power sequencing). Add a 10 us delay in each output clock's .enable() hook so consumers wait for reference settling before first access. Signed-off-by: Shubhrajyoti Datta --- Changes in v3: the number of outputs duplication removed drivers/clk/xilinx/clk-xlnx-clock-wizard.c | 137 ++++++++++++++++++++- 1 file changed, 135 insertions(+), 2 deletions(-) diff --git a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c b/drivers/clk/xilin= x/clk-xlnx-clock-wizard.c index ffc78c90bee6..1332abc8a950 100644 --- a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c +++ b/drivers/clk/xilinx/clk-xlnx-clock-wizard.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -107,6 +108,7 @@ #define VER_WZRD_O_MAX 511 #define WZRD_MIN_ERR 20000 #define WZRD_FRAC_POINTS 1000 +#define WZRD_ENABLE_DELAY_US 10 =20 /* Get the mask from width */ #define div_mask(width) ((1 << (width)) - 1) @@ -697,6 +699,13 @@ static int clk_wzrd_ver_determine_rate_all(struct clk_= hw *hw, return 0; } =20 +static int clk_wzrd_enable(struct clk_hw *hw) +{ + /* Allow the output clock to settle after enable */ + udelay(WZRD_ENABLE_DELAY_US); + return 0; +} + static const struct clk_ops clk_wzrd_ver_divider_ops =3D { .determine_rate =3D clk_wzrd_determine_rate, .set_rate =3D clk_wzrd_ver_dynamic_reconfig, @@ -790,6 +799,85 @@ static const struct clk_ops clk_wzrd_clk_divider_ops_f= =3D { .recalc_rate =3D clk_wzrd_recalc_ratef, }; =20 +static unsigned long +clk_wzrd_static_factor_recalc_rate(struct clk_hw *hw, unsigned long parent= _rate) +{ + struct clk_fixed_factor *fix =3D to_clk_fixed_factor(hw); + unsigned long long rate; + + rate =3D (unsigned long long)parent_rate * fix->mult; + do_div(rate, fix->div); + return (unsigned long)rate; +} + +static int clk_wzrd_static_factor_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_fixed_factor *fix =3D to_clk_fixed_factor(hw); + + if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { + unsigned long best_parent; + + best_parent =3D (req->rate / fix->mult) * fix->div; + req->best_parent_rate =3D + clk_hw_round_rate(clk_hw_get_parent(hw), best_parent); + } + + req->rate =3D (req->best_parent_rate / fix->div) * fix->mult; + + return 0; +} + +static int clk_wzrd_static_factor_set_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate) +{ + return 0; +} + +static const struct clk_ops clk_wzrd_static_fixed_factor_ops =3D { + .enable =3D clk_wzrd_enable, + .determine_rate =3D clk_wzrd_static_factor_determine_rate, + .set_rate =3D clk_wzrd_static_factor_set_rate, + .recalc_rate =3D clk_wzrd_static_factor_recalc_rate, +}; + +static struct clk_hw * +clk_wzrd_devm_register_static_fixed_factor(struct device *dev, + const char *name, + const struct clk_parent_data *parent_data, + unsigned long flags, + unsigned int mult, + unsigned int div) +{ + struct clk_init_data init =3D {}; + struct clk_fixed_factor *fix; + struct clk_hw *hw; + int ret; + + fix =3D devm_kzalloc(dev, sizeof(*fix), GFP_KERNEL); + if (!fix) + return ERR_PTR(-ENOMEM); + + fix->mult =3D mult; + fix->div =3D div; + + init.name =3D name; + init.ops =3D &clk_wzrd_static_fixed_factor_ops; + init.flags =3D flags; + init.parent_data =3D parent_data; + init.num_parents =3D 1; + + fix->hw.init =3D &init; + + hw =3D &fix->hw; + ret =3D devm_clk_hw_register(dev, hw); + if (ret) + return ERR_PTR(ret); + + return hw; +} + static struct clk_hw *clk_wzrd_register_divf(struct device *dev, const char *name, const char *parent_name, @@ -1154,9 +1242,11 @@ static int clk_wzrd_probe(struct platform_device *pd= ev) { struct device_node *np =3D pdev->dev.of_node; struct clk_wzrd *clk_wzrd; + const char *clk_name; unsigned long rate; + struct clk_hw *hw; int nr_outputs; - int ret; + int ret, i; =20 ret =3D of_property_read_u32(np, "xlnx,nr-outputs", &nr_outputs); if (ret || nr_outputs > WZRD_NUM_OUTPUTS) @@ -1166,6 +1256,7 @@ static int clk_wzrd_probe(struct platform_device *pde= v) GFP_KERNEL); if (!clk_wzrd) return -ENOMEM; + clk_wzrd->clk_data.num =3D nr_outputs; platform_set_drvdata(pdev, clk_wzrd); =20 clk_wzrd->axi_clk =3D devm_clk_get_enabled(&pdev->dev, "s_axi_aclk"); @@ -1201,7 +1292,6 @@ static int clk_wzrd_probe(struct platform_device *pde= v) if (ret) return ret; =20 - clk_wzrd->clk_data.num =3D nr_outputs; ret =3D devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get, &clk_wzrd->clk_data); if (ret) { @@ -1224,6 +1314,49 @@ static int clk_wzrd_probe(struct platform_device *pd= ev) dev_warn(&pdev->dev, "unable to register clock notifier\n"); } + } else { + u32 mul_div[WZRD_NUM_OUTPUTS * 2]; + const struct clk_parent_data parent_data =3D { .fw_name =3D "clk_in1" }; + int num_elems =3D nr_outputs * 2; + + /* + * xlnx,clk-mul-div is a uint32-matrix of pairs; + * FDT encodes it as a flat u32 array so we can read it directly. + */ + ret =3D of_property_read_u32_array(np, "xlnx,clk-mul-div", + mul_div, num_elems); + if (ret) { + dev_err(&pdev->dev, "xlnx,clk-mul-div missing or invalid\n"); + return ret; + } + + for (i =3D 0; i < nr_outputs; i++) { + u32 mul =3D mul_div[2 * i]; + u32 div =3D mul_div[2 * i + 1]; + + if (!mul || !div) + return dev_err_probe(&pdev->dev, -EINVAL, + "invalid mul/div for clkout%d\n", i); + + clk_name =3D devm_kasprintf(&pdev->dev, GFP_KERNEL, + "%s_out%d", dev_name(&pdev->dev), i); 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charset="utf-8" For static-config mode the AXI bus interface is not used, so there is no need to get and enable s_axi_aclk. Move the axi_clk setup inside the non-static-config branch. Signed-off-by: Shubhrajyoti Datta --- (no changes since v1) drivers/clk/xilinx/clk-xlnx-clock-wizard.c | 23 +++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c b/drivers/clk/xilin= x/clk-xlnx-clock-wizard.c index 1332abc8a950..c79733f58082 100644 --- a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c +++ b/drivers/clk/xilinx/clk-xlnx-clock-wizard.c @@ -1243,7 +1243,6 @@ static int clk_wzrd_probe(struct platform_device *pde= v) struct device_node *np =3D pdev->dev.of_node; struct clk_wzrd *clk_wzrd; const char *clk_name; - unsigned long rate; struct clk_hw *hw; int nr_outputs; int ret, i; @@ -1259,22 +1258,24 @@ static int clk_wzrd_probe(struct platform_device *p= dev) clk_wzrd->clk_data.num =3D nr_outputs; platform_set_drvdata(pdev, clk_wzrd); =20 - clk_wzrd->axi_clk =3D devm_clk_get_enabled(&pdev->dev, "s_axi_aclk"); - if (IS_ERR(clk_wzrd->axi_clk)) - return dev_err_probe(&pdev->dev, PTR_ERR(clk_wzrd->axi_clk), - "s_axi_aclk not found\n"); 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charset="utf-8" Align the devm_platform_ioremap_resource() error path with clk_in1 and s_axi_aclk handling for consistent logging and deferred-probe behavior. Signed-off-by: Shubhrajyoti Datta --- (no changes since v1) drivers/clk/xilinx/clk-xlnx-clock-wizard.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c b/drivers/clk/xilin= x/clk-xlnx-clock-wizard.c index c79733f58082..4ddcb4135306 100644 --- a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c +++ b/drivers/clk/xilinx/clk-xlnx-clock-wizard.c @@ -1278,7 +1278,8 @@ static int clk_wzrd_probe(struct platform_device *pde= v) =20 clk_wzrd->base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(clk_wzrd->base)) - return PTR_ERR(clk_wzrd->base); + return dev_err_probe(&pdev->dev, PTR_ERR(clk_wzrd->base), + "failed to map registers\n"); =20 ret =3D of_property_read_u32(np, "xlnx,speed-grade", &clk_wzrd->speed_gr= ade); if (!ret) { --=20 2.34.1 From nobody Fri Oct 2 13:07:30 2026 Received: from PH0PR06CU001.outbound.protection.outlook.com (mail-westus3azon11011000.outbound.protection.outlook.com [40.107.208.0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 325A63AA1BC; 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charset="utf-8" 1. clk_wzrd_determine_rate(): DIV_ROUND_CLOSEST() can return 0 when the requested rate greatly exceeds the parent rate, causing a division by zero on the subsequent parent_rate / div. Clamp div to a minimum of 1. 2. clk_wzrd_dynamic_reconfig(): min_t() result was not assigned back to value, so the cap to WZRD_DR_MAX_INT_DIV_VALUE was never applied before the register write. 3. clk_wzrd_get_divisors() and clk_wzrd_get_divisors_ver(): If rate is 0, DIV_ROUND_CLOSEST_ULL divides by zero. Return -EINVAL early. Signed-off-by: Shubhrajyoti Datta --- (no changes since v2) Changes in v2: Patch added drivers/clk/xilinx/clk-xlnx-clock-wizard.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c b/drivers/clk/xilin= x/clk-xlnx-clock-wizard.c index 4ddcb4135306..b16656a11f4b 100644 --- a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c +++ b/drivers/clk/xilinx/clk-xlnx-clock-wizard.c @@ -296,7 +296,7 @@ static int clk_wzrd_dynamic_reconfig(struct clk_hw *hw,= unsigned long rate, value =3D DIV_ROUND_CLOSEST(parent_rate, rate); =20 /* Cap the value to max */ - min_t(u32, value, WZRD_DR_MAX_INT_DIV_VALUE); + value =3D min_t(u32, value, WZRD_DR_MAX_INT_DIV_VALUE); =20 /* Set divisor and clear phase offset */ writel(value, div_addr); @@ -334,6 +334,8 @@ static int clk_wzrd_determine_rate(struct clk_hw *hw, * achievable */ div =3D DIV_ROUND_CLOSEST(req->best_parent_rate, req->rate); + if (!div) + div =3D 1; =20 req->rate =3D req->best_parent_rate / div; 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charset="utf-8" A struct notifier_block has a single 'next' pointer, so registering the same instance to two different notification chains corrupts the linked lists. Use a dedicated nb_axi for the s_axi_aclk notifier chain. Signed-off-by: Shubhrajyoti Datta --- Changes in v3: Split notifier into per-clock callbacks drivers/clk/xilinx/clk-xlnx-clock-wizard.c | 42 +++++++++++++++++----- 1 file changed, 33 insertions(+), 9 deletions(-) diff --git a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c b/drivers/clk/xilin= x/clk-xlnx-clock-wizard.c index b16656a11f4b..cfad11593b2b 100644 --- a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c +++ b/drivers/clk/xilinx/clk-xlnx-clock-wizard.c @@ -126,7 +126,8 @@ enum clk_wzrd_int_clks { /** * struct clk_wzrd - Clock wizard private data structure * - * @nb: Notifier block + * @nb: Notifier block for clk_in1 + * @nb_axi: Notifier block for s_axi_aclk * @base: Memory base * @clk_in1: Handle to input clock 'clk_in1' * @axi_clk: Handle to input clock 's_axi_aclk' @@ -137,6 +138,7 @@ enum clk_wzrd_int_clks { */ struct clk_wzrd { struct notifier_block nb; + struct notifier_block nb_axi; void __iomem *base; struct clk *clk_in1; struct clk *axi_clk; @@ -184,6 +186,7 @@ struct versal_clk_data { }; =20 #define to_clk_wzrd(_nb) container_of(_nb, struct clk_wzrd, nb) +#define to_clk_wzrd_axi(_nb) container_of(_nb, struct clk_wzrd, nb_axi) =20 /* maximum frequencies for input/output clocks per speed grade */ static const unsigned long clk_wzrd_max_freq[] =3D { @@ -1024,6 +1027,30 @@ static struct clk_hw *clk_wzrd_register_divider(stru= ct device *dev, =20 static int clk_wzrd_clk_notifier(struct notifier_block *nb, unsigned long = event, void *data) +{ + unsigned long max; + struct clk_notifier_data *ndata =3D data; + struct clk_wzrd *clk_wzrd =3D to_clk_wzrd_axi(nb); + + if (clk_wzrd->suspended) + return NOTIFY_OK; + + max =3D WZRD_ACLK_MAX_FREQ; + + switch (event) { + case PRE_RATE_CHANGE: + if (ndata->new_rate > max) + return NOTIFY_BAD; + return NOTIFY_OK; + case POST_RATE_CHANGE: + case ABORT_RATE_CHANGE: + default: + return NOTIFY_DONE; + } +} + +static int clk_wzrd_clk_notifier_in1(struct notifier_block *nb, unsigned l= ong event, + void *data) { unsigned long max; struct clk_notifier_data *ndata =3D data; @@ -1032,12 +1059,7 @@ static int clk_wzrd_clk_notifier(struct notifier_blo= ck *nb, unsigned long event, if (clk_wzrd->suspended) return NOTIFY_OK; =20 - if (ndata->clk =3D=3D clk_wzrd->clk_in1) - max =3D clk_wzrd_max_freq[clk_wzrd->speed_grade - 1]; - else if (ndata->clk =3D=3D clk_wzrd->axi_clk) - max =3D WZRD_ACLK_MAX_FREQ; - else - return NOTIFY_DONE; /* should never happen */ + max =3D clk_wzrd_max_freq[clk_wzrd->speed_grade - 1]; =20 switch (event) { case PRE_RATE_CHANGE: @@ -1310,7 +1332,7 @@ static int clk_wzrd_probe(struct platform_device *pde= v) } =20 if (clk_wzrd->speed_grade) { - clk_wzrd->nb.notifier_call =3D clk_wzrd_clk_notifier; + clk_wzrd->nb.notifier_call =3D clk_wzrd_clk_notifier_in1; =20 ret =3D devm_clk_notifier_register(&pdev->dev, clk_wzrd->clk_in1, &clk_wzrd->nb); @@ -1318,8 +1340,10 @@ static int clk_wzrd_probe(struct platform_device *pd= ev) dev_warn(&pdev->dev, "unable to register clock notifier\n"); =20 + clk_wzrd->nb_axi.notifier_call =3D clk_wzrd_clk_notifier; + ret =3D devm_clk_notifier_register(&pdev->dev, clk_wzrd->axi_clk, - &clk_wzrd->nb); + &clk_wzrd->nb_axi); if (ret) dev_warn(&pdev->dev, "unable to register clock notifier\n"); --=20 2.34.1