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Thu, 30 Jul 2026 18:21:33 -0700 (PDT) Received: from ryzen.lan ([2601:644:8000:7a86::e35]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38facf50124sm198867a91.3.2026.07.30.18.21.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jul 2026 18:21:33 -0700 (PDT) From: Rosen Penev To: linux-edac@vger.kernel.org Cc: Frank Li , Borislav Petkov , Tony Luck , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt , York Sun , imx@lists.linux.dev (open list:EDAC-FSL_DDR), linux-kernel@vger.kernel.org (open list), llvm@lists.linux.dev (open list:CLANG/LLVM BUILD SUPPORT:Keyword:\b(?i:clang|llvm)\b) Subject: [PATCHv2 1/3] EDAC/fsl_ddr: use devm_platform_ioremap_resource() Date: Thu, 30 Jul 2026 18:21:28 -0700 Message-ID: <20260731012130.1212640-2-rosenp@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260731012130.1212640-1-rosenp@gmail.com> References: <20260731012130.1212640-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Replace the open-coded of_address_to_resource() plus devm_request_mem_regio= n() and devm_ioremap() sequence with devm_platform_ioremap_resource(), which fo= lds the resource lookup, region reservation and mapping into one step and retur= ns an ERR_PTR checked with IS_ERR()/PTR_ERR(). Behaviorally equivalent with respect to region reservation: the driver already reserved the region, so the non-overlapping reg requirement was already satisfied. Drop the now-unused linux/of_address.h include. Remove devres stuff. Not needed. devm is already used. Fix a mistaken return code of -ENOMEM when PTR_ERR should be used. Assisted-by: opencode:hy3-free Signed-off-by: Rosen Penev --- drivers/edac/fsl_ddr_edac.c | 39 +++++++------------------------------ 1 file changed, 7 insertions(+), 32 deletions(-) diff --git a/drivers/edac/fsl_ddr_edac.c b/drivers/edac/fsl_ddr_edac.c index 2a545e5812e7..3745eec67335 100644 --- a/drivers/edac/fsl_ddr_edac.c +++ b/drivers/edac/fsl_ddr_edac.c @@ -22,7 +22,6 @@ #include =20 #include -#include #include "edac_module.h" #include "fsl_ddr_edac.h" =20 @@ -495,13 +494,14 @@ int fsl_mc_err_probe(struct platform_device *op) struct mem_ctl_info *mci; struct edac_mc_layer layers[2]; struct fsl_mc_pdata *pdata; - struct resource r; + void __iomem *mc_vbase; u32 ecc_en_mask; u32 sdram_ctl; int res; =20 - if (!devres_open_group(&op->dev, fsl_mc_err_probe, GFP_KERNEL)) - return -ENOMEM; + mc_vbase =3D devm_platform_ioremap_resource(op, 0); + if (IS_ERR(mc_vbase)) + return PTR_ERR(mc_vbase); =20 layers[0].type =3D EDAC_MC_LAYER_CHIP_SELECT; layers[0].size =3D 4; @@ -511,10 +511,8 @@ int fsl_mc_err_probe(struct platform_device *op) layers[1].is_virt_csrow =3D false; mci =3D edac_mc_alloc(edac_mc_idx, ARRAY_SIZE(layers), layers, sizeof(*pdata)); - if (!mci) { - devres_release_group(&op->dev, fsl_mc_err_probe); + if (!mci) return -ENOMEM; - } =20 pdata =3D mci->pvt_info; pdata->name =3D "fsl_mc_err"; @@ -531,33 +529,12 @@ int fsl_mc_err_probe(struct platform_device *op) * Default is big endian. */ pdata->little_endian =3D of_property_read_bool(op->dev.of_node, "little-e= ndian"); - - res =3D of_address_to_resource(op->dev.of_node, 0, &r); - if (res) { - pr_err("%s: Unable to get resource for MC err regs\n", - __func__); - goto err; - } - - if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r), - pdata->name)) { - pr_err("%s: Error while requesting mem region\n", - __func__); - res =3D -EBUSY; - goto err; - } - - pdata->mc_vbase =3D devm_ioremap(&op->dev, r.start, resource_size(&r)); - if (!pdata->mc_vbase) { - pr_err("%s: Unable to setup MC err regs\n", __func__); - res =3D -ENOMEM; - goto err; - } + pdata->mc_vbase =3D mc_vbase; =20 if (pdata->flag =3D=3D TYPE_IMX9) { pdata->inject_vbase =3D devm_platform_ioremap_resource_byname(op, "injec= t"); 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Thu, 30 Jul 2026 18:21:35 -0700 (PDT) Received: from ryzen.lan ([2601:644:8000:7a86::e35]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38facf50124sm198867a91.3.2026.07.30.18.21.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jul 2026 18:21:34 -0700 (PDT) From: Rosen Penev To: linux-edac@vger.kernel.org Cc: Frank Li , Borislav Petkov , Tony Luck , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt , York Sun , imx@lists.linux.dev (open list:EDAC-FSL_DDR), linux-kernel@vger.kernel.org (open list), llvm@lists.linux.dev (open list:CLANG/LLVM BUILD SUPPORT:Keyword:\b(?i:clang|llvm)\b) Subject: [PATCHv2 2/3] EDAC/fsl_ddr: use non devm for request_irq() Date: Thu, 30 Jul 2026 18:21:29 -0700 Message-ID: <20260731012130.1212640-3-rosenp@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260731012130.1212640-1-rosenp@gmail.com> References: <20260731012130.1212640-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" We need to tear down the irq before edac_mc_free() to avoid a use after free on teardown as request_irq uses mci as dev_id. Signed-off-by: Rosen Penev --- drivers/edac/fsl_ddr_edac.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/edac/fsl_ddr_edac.c b/drivers/edac/fsl_ddr_edac.c index 3745eec67335..c505fb268474 100644 --- a/drivers/edac/fsl_ddr_edac.c +++ b/drivers/edac/fsl_ddr_edac.c @@ -599,7 +599,7 @@ int fsl_mc_err_probe(struct platform_device *op) =20 /* register interrupts */ pdata->irq =3D platform_get_irq(op, 0); - res =3D devm_request_irq(&op->dev, pdata->irq, + res =3D request_irq(pdata->irq, fsl_mc_isr, IRQF_SHARED, "[EDAC] MC err", mci); @@ -635,6 +635,7 @@ void fsl_mc_err_remove(struct platform_device *op) =20 if (edac_op_state =3D=3D EDAC_OPSTATE_INT) { ddr_out32(pdata, FSL_MC_ERR_INT_EN, 0); + free_irq(pdata->irq, mci); } =20 ddr_out32(pdata, FSL_MC_ERR_DISABLE, --=20 2.55.0 From nobody Fri Oct 2 14:02:41 2026 Received: from mail-pj1-f49.google.com (mail-pj1-f49.google.com [209.85.216.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AADCD2D29C8 for ; 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Thu, 30 Jul 2026 18:21:37 -0700 (PDT) Received: from ryzen.lan ([2601:644:8000:7a86::e35]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38facf50124sm198867a91.3.2026.07.30.18.21.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jul 2026 18:21:36 -0700 (PDT) From: Rosen Penev To: linux-edac@vger.kernel.org Cc: Frank Li , Borislav Petkov , Tony Luck , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt , York Sun , imx@lists.linux.dev (open list:EDAC-FSL_DDR), linux-kernel@vger.kernel.org (open list), llvm@lists.linux.dev (open list:CLANG/LLVM BUILD SUPPORT:Keyword:\b(?i:clang|llvm)\b) Subject: [PATCHv2 3/3] EDAC/fsl_ddr: restore MC error registers on probe failure Date: Thu, 30 Jul 2026 18:21:30 -0700 Message-ID: <20260731012130.1212640-4-rosenp@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260731012130.1212640-1-rosenp@gmail.com> References: <20260731012130.1212640-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" fsl_mc_err_probe() clears FSL_MC_ERR_DISABLE and, in EDAC_OPSTATE_INT mode, sets FSL_MC_ERR_INT_EN to enable error reporting. If a later initialization step fails and jumps to the err/err2 labels, the cleanup only frees driver memory and does not restore these hardware registers. This leaves the memory controller configured to generate interrupts while no handler is successfully registered, which can cause an unhandled interrupt storm on the shared IRQ line. Restore FSL_MC_ERR_DISABLE, FSL_MC_ERR_INT_EN and the SBE threshold in both error paths. Do not pre-initialize orig_ddr_err_disable/orig_ddr_err_sbe to 0; the err path must only restore registers that were actually modified. Split the error labels so early failures (before the first hardware write at line ~~580) jump to err_free, which does cleanup without touching hardware registers. Save orig_ddr_err_sbe alongside orig_ddr_err_disable so the err label correctly restores both registers, avoiding stale bootloader state clobbers. Built for arm64 (defconfig + CONFIG_EDAC_FSL_DDR) with LLVM=3D1; drivers/edac/fsl_ddr_edac.o compiles cleanly. Fixes: ea2eb9a8b620 ("EDAC, fsl-ddr: Separate FSL DDR driver from MPC85xx") Assisted-by: opencode:hy3-free Signed-off-by: Rosen Penev --- drivers/edac/fsl_ddr_edac.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/edac/fsl_ddr_edac.c b/drivers/edac/fsl_ddr_edac.c index c505fb268474..139277c4e2f0 100644 --- a/drivers/edac/fsl_ddr_edac.c +++ b/drivers/edac/fsl_ddr_edac.c @@ -577,23 +577,22 @@ int fsl_mc_err_probe(struct platform_device *op) pdata->orig_ddr_err_disable =3D ddr_in32(pdata, FSL_MC_ERR_DISABLE); ddr_out32(pdata, FSL_MC_ERR_DISABLE, 0); =20 + /* store the original SBE threshold */ + pdata->orig_ddr_err_sbe =3D ddr_in32(pdata, FSL_MC_ERR_SBE) & 0xff0000; + /* clear all error bits */ ddr_out32(pdata, FSL_MC_ERR_DETECT, ~0); =20 res =3D edac_mc_add_mc_with_groups(mci, fsl_ddr_dev_groups); if (res) { edac_dbg(3, "failed edac_mc_add_mc()\n"); - goto err; + goto err1; } =20 if (edac_op_state =3D=3D EDAC_OPSTATE_INT) { ddr_out32(pdata, FSL_MC_ERR_INT_EN, DDR_EIE_MBEE | DDR_EIE_SBEE); =20 - /* store the original error management threshold */ - pdata->orig_ddr_err_sbe =3D ddr_in32(pdata, - FSL_MC_ERR_SBE) & 0xff0000; - /* set threshold to 1 error per interrupt */ ddr_out32(pdata, FSL_MC_ERR_SBE, 0x10000); =20 @@ -621,6 +620,11 @@ int fsl_mc_err_probe(struct platform_device *op) =20 err2: edac_mc_del_mc(&op->dev); + ddr_out32(pdata, FSL_MC_ERR_INT_EN, 0); +err1: + ddr_out32(pdata, FSL_MC_ERR_DISABLE, + pdata->orig_ddr_err_disable); + ddr_out32(pdata, FSL_MC_ERR_SBE, pdata->orig_ddr_err_sbe); err: edac_mc_free(mci); return res; --=20 2.55.0