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Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Bjorn Andersson , Konrad Dybcio Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, Kamal Wadhwa , Anjelique Melendez , Manaf Meethalavalappu Pallikunhi , Priyansh Jain , Jishnu Prakash X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1785521244; l=2813; i=jishnu.prakash@oss.qualcomm.com; s=20251014; h=from:subject:message-id; bh=XDRR7aZZVES2zWWZ6WdrsJXHYCx5Eg0S2b6tcAaOtrU=; b=eyEx5PpgmqO03+r4NcBGbSrqUUz2tWRd2RabPxljUE5wf0O/ucPGiqhU0/TqisFht5IMNobpu BnPfRAMk4HRD/BnZj4cvcs658iKls0sYlZTl9kidnhCrlh565pdfitE X-Developer-Key: i=jishnu.prakash@oss.qualcomm.com; a=ed25519; pk=g89pXdLVwRjdTeQ+uX1QzvBO346E3hQAc1N7fcTXgmk= X-Proofpoint-Spam-Info: AW1haW4tMjYwNzMxMDEzOSBTYWx0ZWRfX4BE/bD96OKkS 8etHzvPCd9HYonXxBaUcFaskXygtwcCoTAVQxBbq4UJFQcGWckZbyvCBUt2hB4C2tLmxv5QMZMQ FWxxyaCz66DUOPg30uvIkHF4ph8+Yxo= X-Authority-Analysis: v=2.4 cv=GpByPE1C c=1 sm=1 tr=0 ts=6a6ce46c cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=6RJ8VYccIssSBGSfHBcA:9 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzMxMDEzOSBTYWx0ZWRfX1OM1XKIZPY3q ETxdOFChf9183DAU+eHvs3xGelpawGSAbs4mAejh11LMLEdsQYlbUUVOjQe0tSTzuUyZenhlGdn yUa+GSmEFaSpAZnRoKtjTfxv01ZnEMMA9/JgvVeYX8Y0LTR3RB42I3yuTCWk4DCqKnqkKQikqjH XSuiymL0TbyUMbVhOoJPO13LqjfUHCLujgfC6g1tlL55jliFkDIKVFeHHFX+Mbj0A5Mhx76Tex8 Gg9uP/6msuOPTUvhpz2nCmKdcL8Daw2cx8V+X4qtQKIMdPocJsivv/VzfXlocEesFkY+w37Yr1N ERGc0L6yy+pEtv/bU0FjPZu4cxyP4Tr4NxM2Nh2aTK/SCCFCPfe97yhPmIbkkPRhjGHuaDv+/7c 4evZaMYVGT47Xi3UuBYWUpP3Uw0OO+aMTKT25gkZZ4u1XAQRLLRW1xdRqzp7tJ0sn+3p06UeNCz o1r58FAMrHk2t6Lmx6g== X-Proofpoint-ORIG-GUID: nqwzNvpfmO9t77N10D3QYxb8ATh0kHlm X-Proofpoint-GUID: nqwzNvpfmO9t77N10D3QYxb8ATh0kHlm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-31_05,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 malwarescore=0 impostorscore=0 suspectscore=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 adultscore=0 bulkscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607310139 PMIC5 Gen4 ADC is similar to PMIC5 Gen3 ADC, with several changes made for improved performance, mostly at the hardware level. The main differences are increased ratiometric conversion resolution (from 14 bits to 16 bits) and increased bit field width for PMIC SID (to allow communication with an increased number of PMICs, supported on latest SoCs). Signed-off-by: Jishnu Prakash --- .../bindings/iio/adc/qcom,spmi-adc5-gen3.yaml | 47 ++++++++++++++++++= +++- 1 file changed, 46 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.= yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml index 149f4af8f4b8..e79ddc2acca0 100644 --- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml @@ -21,9 +21,14 @@ description: | All boards using a particular (SOC + master PMIC) combination will have = the same number of ADC SDAMs supported on that PMIC. =20 + PMIC5 Gen4 ADC is similar to Gen3 ADC, with some differences such as + improved ratiometric conversion resolution. + properties: compatible: - const: qcom,spmi-adc5-gen3 + enum: + - qcom,spmi-adc5-gen3 + - qcom,spmi-adc5-gen4 =20 reg: items: @@ -83,6 +88,46 @@ patternProperties: This property indicates ADC_TM monitoring is done on this channe= l. type: boolean =20 + qcom,adc5-gen4: + description: + Indicates channel is of type ADC5 Gen4. This may be needed in ca= ses where the + master PMIC has an ADC peripheral of type Gen3, but some of the = other PMICs it + communicates with have ADC peripherals of type Gen4, so channels= of those PMICs + need to be marked as Gen4 to ensure their conversions are handle= d correctly. + type: boolean + + qcom,adc5-gen3: + description: + Indicates channel is of type ADC5 Gen3. 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Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Bjorn Andersson , Konrad Dybcio Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, Kamal Wadhwa , Anjelique Melendez , Manaf Meethalavalappu Pallikunhi , Priyansh Jain , Jishnu Prakash X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1785521244; l=18544; i=jishnu.prakash@oss.qualcomm.com; s=20251014; h=from:subject:message-id; bh=UFSKypV+EtK0Ea55Kg/sZknatS3o/XIcr3mC/cv7DuI=; b=puidsO+/c7J+yEyqr1nMvupJ0PizizTg5F1oxK22bAIwy5BC4MFWMMvpVmm7OwOgPvQ9H8rxK CuDarxx3dY3DdBxLQQEN+M+xOZZ6MG7Bnq8a9t101gCa8ShM4iW2jAw X-Developer-Key: i=jishnu.prakash@oss.qualcomm.com; a=ed25519; pk=g89pXdLVwRjdTeQ+uX1QzvBO346E3hQAc1N7fcTXgmk= X-Proofpoint-Spam-Info: AW1haW4tMjYwNzMxMDEzOSBTYWx0ZWRfXxZ4IQ5CycJAJ e4Bc7HdV46Xv2lhhAVa6uCD8bVvNsUonoowrho8XFNrK4y6ZCERbBj9OFVks5xVF9lMBlR7Sl4M qa3bPpOk/XJ8P3Gx+j8nYXoiKUqqmhk= X-Authority-Analysis: v=2.4 cv=TcamcxQh c=1 sm=1 tr=0 ts=6a6ce475 cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=VL9c4Isk2NYVz5x_yekA:9 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzMxMDEzOSBTYWx0ZWRfX8tCBU85WATQb uZRrVWnu9OkZrUY1nPADqZ9E6XPTZ7vYjZY+RDHXQOJtckLAI4/J7yiczduczGvJEfSpufXw+mc mmboAeU4fT6Coo8YcrJU12IoCsL7tcT/5JRMCZsn5JpAh/Hhl8zSJJSGTdSuGG7UvZ0cXpeZaze suiSTc38CZf2EzargCnt7H/HFibLNGa60UQWZDxjEq0r+h5JKRQKCKDVOYPD2cFSFZCb6Hb431/ I4IVVBvs78A88jY6124oosGZUUrowSI+IrkkL8O+BEowU6yLhjnOrX7Mh8KH27emF+KchMeV44p rdk0gCggSWACN+w0ntrYvAuvceqP0AUeNhUxyFrUr2lVeFI6WRWoyrjdnyZ1ZHbhleAtIfSugUe qeZ1Ug6dvZFXFHgrKz7JTWmQctKvUL4hy+2tVsJN5WyjJeYORcM2P55m3eZ9z9H+B7ZboaeLRJ8 9YWTAf1kPm1NQ0zEvUA== X-Proofpoint-ORIG-GUID: WFBqUxojANZw4upr2C4nUJC7km0531Hz X-Proofpoint-GUID: WFBqUxojANZw4upr2C4nUJC7km0531Hz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-31_05,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 malwarescore=0 phishscore=0 priorityscore=1501 suspectscore=0 spamscore=0 adultscore=0 clxscore=1015 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607310139 PMIC5 Gen4 ADC is similar to PMIC5 Gen3 ADC, with several changes made for improved performance, mostly at the hardware level. One significant software change is that ratiometric conversion resolution has been increased from 14 bits to 16 bits, so the maximum value of these measurements needs to be updated for Gen4. Add a new scaling function for thermistor channels which use this type of conversion. In the latest PMIC arbiter version (v8), there can be up to 4 buses under the PMIC arbiter and 32 PMICs under each bus. In order to support communication between ADC on the master PMIC and ADCs on any of the other PMICs, a field of width 2 bits is added for bus index and the bits for SID are extended from 4 to 5 bits, in the SID register. Add support for this. In addition, it is possible that the master PMIC has ADC of one generation and it needs to communicate with another PMIC with ADC of a different generation. Add new DT properties "qcom,adc5-gen3" and "qcom,adc5-gen4", to distinguish Gen3 channels under a Gen4 master and Gen4 channels under a Gen3 master respectively, to ensure that their conversions are hand= led correctly. Co-developed-by: Anjelique Melendez Signed-off-by: Anjelique Melendez Signed-off-by: Jishnu Prakash --- drivers/iio/adc/qcom-spmi-adc5-gen3.c | 165 +++++++++++++++++++---= ---- drivers/iio/adc/qcom-vadc-common.c | 32 +++++ include/linux/iio/adc/qcom-adc5-gen3-common.h | 44 ++++++- include/linux/iio/adc/qcom-vadc-common.h | 4 + 4 files changed, 195 insertions(+), 50 deletions(-) diff --git a/drivers/iio/adc/qcom-spmi-adc5-gen3.c b/drivers/iio/adc/qcom-s= pmi-adc5-gen3.c index c68c6c5f6aca..810d25b665b1 100644 --- a/drivers/iio/adc/qcom-spmi-adc5-gen3.c +++ b/drivers/iio/adc/qcom-spmi-adc5-gen3.c @@ -86,7 +86,9 @@ int adc5_gen3_write(struct adc5_device_data *adc, unsigne= d int sdam_index, } EXPORT_SYMBOL_NS_GPL(adc5_gen3_write, "QCOM_SPMI_ADC5_GEN3"); =20 -static int adc5_gen3_read_voltage_data(struct adc5_chip *adc, u16 *data) +static int adc5_gen3_read_voltage_data(struct adc5_chip *adc, + struct adc5_channel_common_prop *prop, + u16 *data) { u8 rslt[2]; int ret; @@ -99,8 +101,10 @@ static int adc5_gen3_read_voltage_data(struct adc5_chip= *adc, u16 *data) *data =3D get_unaligned_le16(rslt); =20 if (*data =3D=3D ADC5_USR_DATA_CHECK) { - dev_err(adc->dev, "Invalid data:%#x\n", *data); - return -EINVAL; + if (!(prop->generation =3D=3D ADC5_GEN4 && prop->cal_method =3D=3D ADC5_= RATIOMETRIC_CAL)) { + dev_err(adc->dev, "Invalid data:%#x\n", *data); + return -EINVAL; + } } =20 dev_dbg(adc->dev, "voltage raw code:%#x\n", *data); @@ -131,8 +135,9 @@ static int adc5_gen3_configure(struct adc5_chip *adc, if (ret) return ret; =20 - /* Write SID */ - buf[0] =3D FIELD_PREP(ADC5_GEN3_SID_MASK, prop->sid); + /* Write SID and bus_id*/ + buf[0] =3D FIELD_PREP(ADC5_GEN4_BUS_INDEX_MASK, prop->bus_index) | + FIELD_PREP(ADC5_GEN4_SID_MASK, prop->sid); =20 /* * Use channel 0 by default for immediate conversion and to indicate @@ -268,7 +273,7 @@ static int adc5_gen3_do_conversion(struct adc5_chip *ad= c, return -ETIMEDOUT; } =20 - ret =3D adc5_gen3_read_voltage_data(adc, data_volt); + ret =3D adc5_gen3_read_voltage_data(adc, prop, data_volt); if (ret) return ret; =20 @@ -325,7 +330,7 @@ static int adc5_gen3_fwnode_xlate(struct iio_dev *indio= _dev, int i, v_channel; =20 for (i =3D 0; i < adc->nchannels; i++) { - v_channel =3D ADC5_GEN3_V_CHAN(adc->chan_props[i].common_props); + v_channel =3D ADC5_GEN4_V_CHAN(adc->chan_props[i].common_props); if (v_channel =3D=3D iiospec->args[0]) return i; } @@ -351,7 +356,7 @@ static int adc5_gen3_read_raw(struct iio_dev *indio_dev, return ret; =20 ret =3D qcom_adc5_hw_scale(prop->scale_fn_type, prop->prescale, - adc->data, adc_code_volt, val); + prop->data, adc_code_volt, val); if (ret) return ret; =20 @@ -433,15 +438,89 @@ static const struct adc5_channels adc5_gen3_chans_pmi= c[ADC5_MAX_CHANNEL] =3D { SCALE_HW_CALIB_THERM_100K_PU_PM7) }; =20 +static const struct adc5_channels adc5_gen4_chans_pmic[ADC5_MAX_CHANNEL] = =3D { + [ADC5_GEN4_OFFSET_REF] =3D ADC5_CHAN_VOLT(0, + SCALE_HW_CALIB_DEFAULT) + [ADC5_GEN4_1P25VREF] =3D ADC5_CHAN_VOLT(0, + SCALE_HW_CALIB_DEFAULT) + [ADC5_GEN4_VPH_PWR] =3D ADC5_CHAN_VOLT(1, + SCALE_HW_CALIB_DEFAULT) + [ADC5_GEN4_VBAT_SNS_QBG] =3D ADC5_CHAN_VOLT(1, + SCALE_HW_CALIB_DEFAULT) + [ADC5_GEN4_DIE_TEMP] =3D ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_PMIC_THERM_PM7) + [ADC5_GEN4_AMUX1_THM_100K_PU] =3D ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_THERM_100K_PU_GEN4) + [ADC5_GEN4_AMUX2_THM_100K_PU] =3D ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_THERM_100K_PU_GEN4) + [ADC5_GEN4_AMUX3_THM_100K_PU] =3D ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_THERM_100K_PU_GEN4) + [ADC5_GEN4_AMUX4_THM_100K_PU] =3D ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_THERM_100K_PU_GEN4) + [ADC5_GEN4_AMUX5_THM_100K_PU] =3D ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_THERM_100K_PU_GEN4) + [ADC5_GEN4_AMUX6_THM_100K_PU] =3D ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_THERM_100K_PU_GEN4) + [ADC5_GEN4_AMUX1_GPIO_100K_PU] =3D ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_THERM_100K_PU_GEN4) + [ADC5_GEN4_AMUX2_GPIO_100K_PU] =3D ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_THERM_100K_PU_GEN4) + [ADC5_GEN4_AMUX3_GPIO_100K_PU] =3D ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_THERM_100K_PU_GEN4) + [ADC5_GEN4_AMUX4_GPIO_100K_PU] =3D ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_THERM_100K_PU_GEN4) + [ADC5_GEN4_AMUX5_GPIO_100K_PU] =3D ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_THERM_100K_PU_GEN4) +}; + +static const struct adc5_data adc5_gen3_data_pmic =3D { + .full_scale_code_volt =3D 0x70e4, + .adc_chans =3D adc5_gen3_chans_pmic, + .info =3D &adc5_gen3_info, + .decimation =3D (unsigned int [ADC5_DECIMATION_SAMPLES_MAX]) + { 85, 340, 1360 }, + .hw_settle_1 =3D (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX]) + { 15, 100, 200, 300, + 400, 500, 600, 700, + 1000, 2000, 4000, 8000, + 16000, 32000, 64000, 128000 }, +}; + +static const struct adc5_data adc5_gen4_data_pmic =3D { + .full_scale_code_volt =3D 0x70e4, + .adc_chans =3D adc5_gen4_chans_pmic, + .info =3D &adc5_gen3_info, + .decimation =3D (unsigned int [ADC5_DECIMATION_SAMPLES_MAX]) + { 85, 340, 1360 }, + .hw_settle_1 =3D (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX]) + { 15, 100, 200, 300, + 400, 500, 600, 700, + 1000, 2000, 4000, 8000, + 16000, 32000, 64000, 128000 }, +}; + +static const struct of_device_id adc5_match_table[] =3D { + { + .compatible =3D "qcom,spmi-adc5-gen3", + .data =3D &adc5_gen3_data_pmic, + }, + { + .compatible =3D "qcom,spmi-adc5-gen4", + .data =3D &adc5_gen4_data_pmic, + }, + { } +}; +MODULE_DEVICE_TABLE(of, adc5_match_table); + static int adc5_gen3_get_fw_channel_data(struct adc5_chip *adc, struct adc5_channel_prop *prop, struct fwnode_handle *fwnode) { const char *name =3D fwnode_get_name(fwnode); - const struct adc5_data *data =3D adc->data; + const struct adc5_data *data; + u32 chan, value, sid, bus_index; struct device *dev =3D adc->dev; const char *channel_name; - u32 chan, value, sid; u32 varr[2]; int ret; =20 @@ -452,27 +531,46 @@ static int adc5_gen3_get_fw_channel_data(struct adc5_= chip *adc, =20 /* * Value read from "reg" is virtual channel number - * virtual channel number =3D sid << 8 | channel number + * virtual channel number =3D bus index << 13 | sid << 8 | channel number + * For ADC5 GEN3 channels, bus index =3D 0 */ - sid =3D FIELD_GET(ADC5_GEN3_VIRTUAL_SID_MASK, chan); - chan =3D FIELD_GET(ADC5_GEN3_CHANNEL_MASK, chan); + bus_index =3D FIELD_GET(ADC5_GEN4_V_CHAN_BUS_INDEX_MASK, chan); + sid =3D FIELD_GET(ADC5_GEN4_V_CHAN_SID_MASK, chan); + chan =3D FIELD_GET(ADC5_GEN4_V_CHAN_CHANNEL_MASK, chan); =20 if (chan >=3D ADC5_MAX_CHANNEL) return dev_err_probe(dev, -EINVAL, "%s invalid channel number %d\n", name, chan); =20 + prop->common_props.bus_index =3D bus_index; prop->common_props.channel =3D chan; prop->common_props.sid =3D sid; =20 - if (!adc->data->adc_chans[chan].info_mask) + if (fwnode_property_read_bool(fwnode, "qcom,adc5-gen4")) { + prop->common_props.generation =3D ADC5_GEN4; + data =3D &adc5_gen4_data_pmic; + } else if (fwnode_property_read_bool(fwnode, "qcom,adc5-gen3")) { + prop->common_props.generation =3D ADC5_GEN3; + data =3D &adc5_gen3_data_pmic; + } else { + prop->common_props.generation =3D (adc->data =3D=3D &adc5_gen3_data_pmic= ) ? + ADC5_GEN3 : ADC5_GEN4; + data =3D adc->data; + } + prop->common_props.data =3D data; + + if (!data->adc_chans[chan].info_mask) return dev_err_probe(dev, -EINVAL, "Channel %#x not supported\n", chan); =20 channel_name =3D name; fwnode_property_read_string(fwnode, "label", &channel_name); prop->common_props.label =3D channel_name; =20 - value =3D data->decimation[ADC5_DECIMATION_DEFAULT]; + if (prop->common_props.generation =3D=3D ADC5_GEN3) + value =3D data->decimation[ADC5_DECIMATION_DEFAULT]; + else + value =3D data->decimation[ADC5_GEN4_DECIMATION_DEFAULT]; fwnode_property_read_u32(fwnode, "qcom,decimation", &value); ret =3D qcom_adc5_decimation_from_dt(value, data->decimation); if (ret < 0) @@ -480,7 +578,7 @@ static int adc5_gen3_get_fw_channel_data(struct adc5_ch= ip *adc, chan, value); prop->common_props.decimation =3D ret; =20 - prop->common_props.prescale =3D adc->data->adc_chans[chan].prescale_index; + prop->common_props.prescale =3D data->adc_chans[chan].prescale_index; ret =3D fwnode_property_read_u32_array(fwnode, "qcom,pre-scaling", varr, = 2); if (!ret) { ret =3D qcom_adc5_prescaling_from_dt(varr[0], varr[1]); @@ -526,34 +624,13 @@ static int adc5_gen3_get_fw_channel_data(struct adc5_= chip *adc, return 0; } =20 -static const struct adc5_data adc5_gen3_data_pmic =3D { - .full_scale_code_volt =3D 0x70e4, - .adc_chans =3D adc5_gen3_chans_pmic, - .info =3D &adc5_gen3_info, - .decimation =3D (unsigned int [ADC5_DECIMATION_SAMPLES_MAX]) - { 85, 340, 1360 }, - .hw_settle_1 =3D (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX]) - { 15, 100, 200, 300, - 400, 500, 600, 700, - 1000, 2000, 4000, 8000, - 16000, 32000, 64000, 128000 }, -}; - -static const struct of_device_id adc5_match_table[] =3D { - { - .compatible =3D "qcom,spmi-adc5-gen3", - .data =3D &adc5_gen3_data_pmic, - }, - { } -}; -MODULE_DEVICE_TABLE(of, adc5_match_table); - static int adc5_get_fw_data(struct adc5_chip *adc) { const struct adc5_channels *adc_chan; struct adc5_channel_prop *chan_props; struct iio_chan_spec *iio_chan; struct device *dev =3D adc->dev; + const struct adc5_data *data; unsigned int index =3D 0; int ret; =20 @@ -582,10 +659,11 @@ static int adc5_get_fw_data(struct adc5_chip *adc) return ret; =20 chan_props->chip =3D adc; - adc_chan =3D &adc->data->adc_chans[chan_props->common_props.channel]; + data =3D chan_props->common_props.data; + adc_chan =3D &data->adc_chans[chan_props->common_props.channel]; chan_props->common_props.scale_fn_type =3D adc_chan->scale_fn_type; =20 - iio_chan->channel =3D ADC5_GEN3_V_CHAN(chan_props->common_props); + iio_chan->channel =3D ADC5_GEN4_V_CHAN(chan_props->common_props); iio_chan->info_mask_separate =3D adc_chan->info_mask; iio_chan->type =3D adc_chan->type; iio_chan->address =3D index; @@ -697,7 +775,7 @@ int adc5_gen3_get_scaled_reading(struct device *dev, =20 return qcom_adc5_hw_scale(common_props->scale_fn_type, common_props->prescale, - adc->data, adc_code_volt, val); + common_props->data, adc_code_volt, val); } EXPORT_SYMBOL_NS_GPL(adc5_gen3_get_scaled_reading, "QCOM_SPMI_ADC5_GEN3"); =20 @@ -705,12 +783,9 @@ int adc5_gen3_therm_code_to_temp(struct device *dev, struct adc5_channel_common_prop *common_props, u16 code, int *val) { - struct iio_dev *indio_dev =3D dev_get_drvdata(dev->parent); - struct adc5_chip *adc =3D iio_priv(indio_dev); - return qcom_adc5_hw_scale(common_props->scale_fn_type, common_props->prescale, - adc->data, code, val); + common_props->data, code, val); } EXPORT_SYMBOL_NS_GPL(adc5_gen3_therm_code_to_temp, "QCOM_SPMI_ADC5_GEN3"); =20 diff --git a/drivers/iio/adc/qcom-vadc-common.c b/drivers/iio/adc/qcom-vadc= -common.c index b03cf584b165..cb23d0d178c7 100644 --- a/drivers/iio/adc/qcom-vadc-common.c +++ b/drivers/iio/adc/qcom-vadc-common.c @@ -301,6 +301,10 @@ static const struct u32_fract adc5_prescale_ratios[] = =3D { { .numerator =3D 1, .denominator =3D 16 }, }; =20 +static int qcom_adc5_gen4_scale_hw_calib_therm( + const struct u32_fract *prescale, + const struct adc5_data *data, + u16 adc_code, int *result_mdec); static int qcom_vadc_scale_hw_calib_volt( const struct u32_fract *prescale, const struct adc5_data *data, @@ -341,6 +345,8 @@ static const struct qcom_adc5_scale_type scale_adc5_fn[= ] =3D { qcom_vadc7_scale_hw_calib_die_temp}, [SCALE_HW_CALIB_PM5_CHG_TEMP] =3D {qcom_vadc_scale_hw_chg5_temp}, [SCALE_HW_CALIB_PM5_SMB_TEMP] =3D {qcom_vadc_scale_hw_smb_temp}, + [SCALE_HW_CALIB_THERM_100K_PU_GEN4] =3D { + qcom_adc5_gen4_scale_hw_calib_therm}, }; =20 static int qcom_vadc_map_voltage_temp(const struct vadc_map_pt *pts, @@ -556,6 +562,32 @@ static int qcom_vadc7_scale_hw_calib_therm( return 0; } =20 +static int qcom_adc5_gen4_scale_hw_calib_therm( + const struct u32_fract *prescale, + const struct adc5_data *data, + u16 adc_code, int *result_mdec) +{ + s64 resistance =3D adc_code; + int ret, result; + + if (adc_code >=3D RATIO_MAX_ADC5_GEN4) + return -EINVAL; + + /* (ADC code * R_PULLUP (100Kohm)) / (full_scale_code - ADC code)*/ + resistance *=3D R_PU_100K; + resistance =3D div64_s64(resistance, RATIO_MAX_ADC5_GEN4 - adc_code); + + ret =3D qcom_vadc_map_voltage_temp(adcmap7_100k, + ARRAY_SIZE(adcmap7_100k), + resistance, &result); + if (ret) + return ret; + + *result_mdec =3D result; + + return 0; +} + static int qcom_vadc_scale_hw_calib_volt( const struct u32_fract *prescale, const struct adc5_data *data, diff --git a/include/linux/iio/adc/qcom-adc5-gen3-common.h b/include/linux/= iio/adc/qcom-adc5-gen3-common.h index 39cbfcbdb101..5d8e38350827 100644 --- a/include/linux/iio/adc/qcom-adc5-gen3-common.h +++ b/include/linux/iio/adc/qcom-adc5-gen3-common.h @@ -40,7 +40,8 @@ #define ADC5_GEN3_CONV_ERR_CLR_REQ BIT(0) =20 #define ADC5_GEN3_SID 0x4f -#define ADC5_GEN3_SID_MASK GENMASK(3, 0) +#define ADC5_GEN4_SID_MASK GENMASK(4, 0) +#define ADC5_GEN4_BUS_INDEX_MASK GENMASK(6, 5) =20 #define ADC5_GEN3_PERPH_CH 0x50 #define ADC5_GEN3_CHAN_CONV_REQ BIT(7) @@ -51,6 +52,7 @@ #define ADC5_GEN3_DIG_PARAM 0x52 #define ADC5_GEN3_DIG_PARAM_CAL_SEL_MASK GENMASK(5, 4) #define ADC5_GEN3_DIG_PARAM_DEC_RATIO_SEL_MASK GENMASK(3, 2) +#define ADC5_GEN4_DECIMATION_DEFAULT 1 =20 #define ADC5_GEN3_FAST_AVG 0x53 #define ADC5_GEN3_FAST_AVG_CTL_EN BIT(7) @@ -75,10 +77,13 @@ #define ADC5_GEN3_CONV_REQ 0xe5 #define ADC5_GEN3_CONV_REQ_REQ BIT(0) =20 -#define ADC5_GEN3_VIRTUAL_SID_MASK GENMASK(15, 8) -#define ADC5_GEN3_CHANNEL_MASK GENMASK(7, 0) -#define ADC5_GEN3_V_CHAN(x) \ - (FIELD_PREP(ADC5_GEN3_VIRTUAL_SID_MASK, (x).sid) | (x).channel) +#define ADC5_GEN4_V_CHAN_BUS_INDEX_MASK GENMASK(14, 13) +#define ADC5_GEN4_V_CHAN_SID_MASK GENMASK(12, 8) +#define ADC5_GEN4_V_CHAN_CHANNEL_MASK GENMASK(7, 0) +#define ADC5_GEN4_V_CHAN(x) \ + (FIELD_PREP(ADC5_GEN4_V_CHAN_BUS_INDEX_MASK, (x).bus_index) | \ + FIELD_PREP(ADC5_GEN4_V_CHAN_SID_MASK, (x).sid) | \ + FIELD_PREP(ADC5_GEN4_V_CHAN_CHANNEL_MASK, (x).channel)) =20 /* ADC channels for PMIC5 Gen3 */ #define ADC5_GEN3_REF_GND 0x00 @@ -102,6 +107,27 @@ =20 #define ADC5_MAX_CHANNEL 0xc0 =20 +/* ADC channels for PMIC5 Gen4 */ +#define ADC5_GEN4_OFFSET_REF 0x00 +#define ADC5_GEN4_1P25VREF 0x01 +#define ADC5_GEN4_DIE_TEMP 0x03 +#define ADC5_GEN4_USB_SNS_DIV20 0x11 +#define ADC5_GEN4_VIN_DIV20_MUX 0x12 +#define ADC5_GEN4_VPH_PWR 0x8e +#define ADC5_GEN4_VBAT_SNS_QBG 0x8f +/* 100k pull-up channels */ +#define ADC5_GEN4_AMUX1_THM_100K_PU 0x44 +#define ADC5_GEN4_AMUX2_THM_100K_PU 0x45 +#define ADC5_GEN4_AMUX3_THM_100K_PU 0x46 +#define ADC5_GEN4_AMUX4_THM_100K_PU 0x47 +#define ADC5_GEN4_AMUX5_THM_100K_PU 0x48 +#define ADC5_GEN4_AMUX6_THM_100K_PU 0x49 +#define ADC5_GEN4_AMUX1_GPIO_100K_PU 0x4a +#define ADC5_GEN4_AMUX2_GPIO_100K_PU 0x4b +#define ADC5_GEN4_AMUX3_GPIO_100K_PU 0x4c +#define ADC5_GEN4_AMUX4_GPIO_100K_PU 0x4d +#define ADC5_GEN4_AMUX5_GPIO_100K_PU 0x5e + enum adc5_cal_method { ADC5_NO_CAL =3D 0, ADC5_RATIOMETRIC_CAL, @@ -117,6 +143,11 @@ enum adc5_time_select { MEAS_INT_NONE, }; =20 +enum adc_generation { + ADC5_GEN3 =3D 0, + ADC5_GEN4, +}; + /** * struct adc5_sdam_data - data per SDAM allocated for adc usage * @base_addr: base address for the ADC SDAM peripheral. @@ -166,6 +197,9 @@ struct adc5_channel_common_prop { unsigned int hw_settle_time_us; unsigned int avg_samples; enum vadc_scale_fn_type scale_fn_type; + enum adc_generation generation; + unsigned int bus_index; + const struct adc5_data *data; }; =20 /** diff --git a/include/linux/iio/adc/qcom-vadc-common.h b/include/linux/iio/a= dc/qcom-vadc-common.h index 3bf4c49726a7..4be682083843 100644 --- a/include/linux/iio/adc/qcom-vadc-common.h +++ b/include/linux/iio/adc/qcom-vadc-common.h @@ -54,6 +54,7 @@ =20 #define R_PU_100K 100000 #define RATIO_MAX_ADC7 BIT(14) +#define RATIO_MAX_ADC5_GEN4 0xffff =20 /* * VADC_CALIB_ABSOLUTE: uses the 625mV and 1.25V as reference channels. @@ -105,6 +106,8 @@ struct vadc_linear_graph { * charger temperature. * @SCALE_HW_CALIB_PM5_SMB_TEMP: Returns result in millidegrees for PMIC5 * SMB1390 temperature. + * @SCALE_HW_CALIB_THERM_100K_PU_GEN4: Returns temperature in millidegC us= ing + * lookup table for PMIC5 Gen4 ADC. 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One significant software change is that ratiometric conversion resolution has been increased from 14 bits to 16 bits. Add a reverse scaling function for Gen4 ADC thermistor channels. In the latest PMIC arbiter version (v8), there can be up to 4 buses under the PMIC arbiter and 32 PMICs under each bus. In order to support communication between ADC on the master PMIC and ADCs on any of the other PMICs, a field of width 2 bits is added for bus index and the bits for SID are extended from 4 to 5 bits, in the SID register. Add support for this. Co-developed-by: Anjelique Melendez Signed-off-by: Anjelique Melendez Signed-off-by: Jishnu Prakash --- drivers/iio/adc/qcom-vadc-common.c | 11 +++++++++++ drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c | 19 ++++++++++++++----- include/linux/iio/adc/qcom-vadc-common.h | 2 ++ 3 files changed, 27 insertions(+), 5 deletions(-) diff --git a/drivers/iio/adc/qcom-vadc-common.c b/drivers/iio/adc/qcom-vadc= -common.c index cb23d0d178c7..25bd4622c389 100644 --- a/drivers/iio/adc/qcom-vadc-common.c +++ b/drivers/iio/adc/qcom-vadc-common.c @@ -720,6 +720,17 @@ u16 qcom_adc_tm5_gen2_temp_res_scale(int temp) } EXPORT_SYMBOL(qcom_adc_tm5_gen2_temp_res_scale); =20 +u16 qcom_adc_tm5_gen4_temp_res_scale(int temp) +{ + s64 resistance; + + resistance =3D qcom_vadc_map_temp_voltage(adcmap7_100k, + ARRAY_SIZE(adcmap7_100k), temp); + + return div64_s64(resistance * RATIO_MAX_ADC5_GEN4, resistance + R_PU_100K= ); +} +EXPORT_SYMBOL(qcom_adc_tm5_gen4_temp_res_scale); + int qcom_adc5_hw_scale(enum vadc_scale_fn_type scaletype, unsigned int prescale_ratio, const struct adc5_data *data, diff --git a/drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c b/drivers/therma= l/qcom/qcom-spmi-adc-tm5-gen3.c index 9cf552d36868..80e820b6dc4b 100644 --- a/drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c +++ b/drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c @@ -207,15 +207,23 @@ static int adc_tm5_gen3_disable_channel(struct adc_tm= 5_gen3_channel_props *prop) ADC5_GEN3_CONV_REQ, &val, sizeof(val)); } =20 +typedef u16 (*temp_res_scale)(int temp); + static int adc_tm5_gen3_configure(struct adc_tm5_gen3_channel_props *prop, int low_temp, int high_temp) { struct adc_tm5_gen3_chip *adc_tm5 =3D prop->chip; u8 buf[ADC_TM5_GEN3_CONFIG_REGS]; + temp_res_scale tm_scal_fn; u8 conv_req; u16 adc_code; int ret; =20 + if (prop->common_props.generation =3D=3D ADC5_GEN4) + tm_scal_fn =3D qcom_adc_tm5_gen4_temp_res_scale; + else + tm_scal_fn =3D qcom_adc_tm5_gen2_temp_res_scale; + ret =3D adc5_gen3_poll_wait_hs(adc_tm5->dev_data, prop->sdam_index); if (ret < 0) return ret; @@ -225,8 +233,9 @@ static int adc_tm5_gen3_configure(struct adc_tm5_gen3_c= hannel_props *prop, if (ret < 0) return ret; =20 - /* Write SID */ - buf[0] =3D FIELD_PREP(ADC5_GEN3_SID_MASK, prop->common_props.sid); + /* Write SID and bus_id*/ + buf[0] =3D FIELD_PREP(ADC5_GEN4_BUS_INDEX_MASK, prop->common_props.bus_in= dex) | + FIELD_PREP(ADC5_GEN4_SID_MASK, prop->common_props.sid); =20 /* Select TM channel and indicate there is an actual conversion request */ buf[1] =3D ADC5_GEN3_CHAN_CONV_REQ | prop->tm_chan_index; @@ -252,7 +261,7 @@ static int adc_tm5_gen3_configure(struct adc_tm5_gen3_c= hannel_props *prop, /* High temperature corresponds to low voltage threshold */ prop->low_thr_en =3D (high_temp !=3D INT_MAX); if (prop->low_thr_en) { - adc_code =3D qcom_adc_tm5_gen2_temp_res_scale(high_temp); + adc_code =3D tm_scal_fn(high_temp); put_unaligned_le16(adc_code, &buf[8]); buf[7] |=3D ADC5_GEN3_LOW_THR_INT_EN; } @@ -260,7 +269,7 @@ static int adc_tm5_gen3_configure(struct adc_tm5_gen3_c= hannel_props *prop, /* Low temperature corresponds to high voltage threshold */ prop->high_thr_en =3D (low_temp !=3D -INT_MAX); if (prop->high_thr_en) { - adc_code =3D qcom_adc_tm5_gen2_temp_res_scale(low_temp); + adc_code =3D tm_scal_fn(low_temp); put_unaligned_le16(adc_code, &buf[10]); buf[7] |=3D ADC5_GEN3_HIGH_THR_INT_EN; } @@ -306,7 +315,7 @@ static int adc_tm5_register_tzd(struct adc_tm5_gen3_chi= p *adc_tm5) int ret; =20 for (int i =3D 0; i < adc_tm5->nchannels; i++) { - channel =3D ADC5_GEN3_V_CHAN(adc_tm5->chan_props[i].common_props); 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Signed-off-by: Jishnu Prakash --- arch/arm64/boot/dts/qcom/qcom-adc5-gen4.h | 96 +++++++++++++++++++++++++++= ++++ 1 file changed, 96 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcom-adc5-gen4.h b/arch/arm64/boot/dt= s/qcom/qcom-adc5-gen4.h new file mode 100644 index 000000000000..cf94e3185e21 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcom-adc5-gen4.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __DTS_ARM64_QCOM_ADC5_GEN4_H__ +#define __DTS_ARM64_QCOM_ADC5_GEN4_H__ + +/* ADC channels for PMIC5 Gen4 */ + +#define ADC5_GEN4_VIRT_CHAN(bus_id, sid, chan) ((bus_id) << 13 | (sid) << = 8 | (chan)) + +#define ADC5_GEN4_OFFSET_REF(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_id, sid,= 0x00) +#define ADC5_GEN4_1P25VREF(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_id, sid, = 0x01) +#define ADC5_GEN4_VREF_VADC(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_id, sid, = 0x02) +#define ADC5_GEN4_DIE_TEMP(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_id, sid, = 0x03) + +#define ADC5_GEN4_AMUX1_THM(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_id, sid, = 0x04) +#define ADC5_GEN4_AMUX2_THM(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_id, sid, = 0x05) +#define ADC5_GEN4_AMUX3_THM(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_id, sid, = 0x06) +#define ADC5_GEN4_AMUX4_THM(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_id, sid, = 0x07) +#define ADC5_GEN4_AMUX5_THM(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_id, sid, = 0x08) +#define ADC5_GEN4_AMUX6_THM(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_id, sid, = 0x09) +#define ADC5_GEN4_AMUX1_GPIO(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_id, sid,= 0x0a) +#define ADC5_GEN4_AMUX2_GPIO(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_id, sid,= 0x0b) +#define ADC5_GEN4_AMUX3_GPIO(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_id, sid,= 0x0c) +#define ADC5_GEN4_AMUX4_GPIO(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_id, sid,= 0x0d) +#define ADC5_GEN4_AMUX5_GPIO(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_id, sid,= 0x1e) + +#define ADC5_GEN4_CHG_TEMP(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_id, sid, = 0x10) +#define ADC5_GEN4_USB_SNS_DIV20(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_id, s= id, 0x11) +#define ADC5_GEN4_VIN_DIV20_MUX(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_id, s= id, 0x12) +#define ADC5_GEN4_USBC_MUX(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_id, sid, = 0x13) +#define ADC5_GEN4_VREF_BAT_THERM(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_id, = sid, 0x15) +#define ADC5_GEN4_IIN(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_id, sid, 0x17) + +#define ADC5_GEN4_VREF_BAT2_THERM(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_id,= sid, 0x1a) +#define ADC5_GEN4_ATEST1(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_id, sid, 0x= 1b) +#define ADC5_GEN4_ATEST2(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_id, sid, 0x= 1c) +#define ADC5_GEN4_VBAT_2S_MID_CHGR(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_id= , sid, 0x1d) + +/* 10k pull-up1 */ +#define ADC5_GEN4_AMUX1_THM_10K_PU(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_i= d, sid, 0x24) +#define ADC5_GEN4_AMUX2_THM_10K_PU(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_i= d, sid, 0x25) +#define ADC5_GEN4_AMUX3_THM_10K_PU(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_i= d, sid, 0x26) +#define ADC5_GEN4_AMUX4_THM_10K_PU(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_i= d, sid, 0x27) +#define ADC5_GEN4_AMUX5_THM_10K_PU(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_i= d, sid, 0x28) +#define ADC5_GEN4_AMUX6_THM_10K_PU(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_i= d, sid, 0x29) +#define ADC5_GEN4_AMUX1_GPIO_10K_PU(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_i= d, sid, 0x2a) +#define ADC5_GEN4_AMUX2_GPIO_10K_PU(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_i= d, sid, 0x2b) +#define ADC5_GEN4_AMUX3_GPIO_10K_PU(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_i= d, sid, 0x2c) +#define ADC5_GEN4_AMUX4_GPIO_10K_PU(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_i= d, sid, 0x2d) +#define ADC5_GEN4_USBC_MUX_10K_PU(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_id= , sid, 0x33) +#define ADC5_GEN4_AMUX5_GPIO_10K_PU(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_i= d, sid, 0x3e) + +/* 100k pull-up2 */ +#define ADC5_GEN4_AMUX1_THM_100K_PU(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_i= d, sid, 0x44) +#define ADC5_GEN4_AMUX2_THM_100K_PU(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_i= d, sid, 0x45) +#define ADC5_GEN4_AMUX3_THM_100K_PU(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_i= d, sid, 0x46) +#define ADC5_GEN4_AMUX4_THM_100K_PU(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_i= d, sid, 0x47) +#define ADC5_GEN4_AMUX5_THM_100K_PU(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_i= d, sid, 0x48) +#define ADC5_GEN4_AMUX6_THM_100K_PU(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_i= d, sid, 0x49) +#define ADC5_GEN4_AMUX1_GPIO_100K_PU(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_= id, sid, 0x4a) +#define ADC5_GEN4_AMUX2_GPIO_100K_PU(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_= id, sid, 0x4b) +#define ADC5_GEN4_AMUX3_GPIO_100K_PU(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_= id, sid, 0x4c) +#define ADC5_GEN4_AMUX4_GPIO_100K_PU(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_= id, sid, 0x4d) +#define ADC5_GEN4_USBC_MUX_100K_PU(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_i= d, sid, 0x53) +#define ADC5_GEN4_AMUX5_GPIO_100K_PU(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_= id, sid, 0x5e) + +/* 400k pull-up3 */ +#define ADC5_GEN4_AMUX1_THM_400K_PU(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_i= d, sid, 0x64) +#define ADC5_GEN4_AMUX2_THM_400K_PU(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_i= d, sid, 0x65) +#define ADC5_GEN4_AMUX3_THM_400K_PU(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_i= d, sid, 0x66) +#define ADC5_GEN4_AMUX4_THM_400K_PU(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_i= d, sid, 0x67) +#define ADC5_GEN4_AMUX5_THM_400K_PU(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_i= d, sid, 0x68) +#define ADC5_GEN4_AMUX6_THM_400K_PU(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_i= d, sid, 0x69) +#define ADC5_GEN4_AMUX1_GPIO_400K_PU(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_= id, sid, 0x6a) +#define ADC5_GEN4_AMUX2_GPIO_400K_PU(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_= id, sid, 0x6b) +#define ADC5_GEN4_AMUX3_GPIO_400K_PU(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_= id, sid, 0x6c) +#define ADC5_GEN4_AMUX4_GPIO_400K_PU(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_= id, sid, 0x6d) +#define ADC5_GEN4_USBC_MUX_400K_PU(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_i= d, sid, 0x73) +#define ADC5_GEN4_AMUX5_GPIO_400K_PU(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_= id, sid, 0x7e) + +/* 1/3 Divider */ +#define ADC5_GEN4_AMUX1_GPIO_DIV3(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_id,= sid, 0x8a) +#define ADC5_GEN4_VPH_PWR(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_id, sid, 0= x8e) +#define ADC5_GEN4_VBAT_SNS_QBG(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_id, si= d, 0x8f) +#define ADC5_GEN4_VBAT_SNS_CHG(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_id, si= d, 0x94) +#define ADC5_GEN4_VBAT_2S_MID_QBG(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_id,= sid, 0x96) +#define ADC5_GEN4_VPH2_PWR(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_id, sid, = 0x99) +#define ADC5_GEN4_VBAT_2S_MID_CHGR_DIV3(bus_id, sid) ADC5_GEN4_VIRT_CHAN(b= us_id, sid, 0x9d) +#define ADC5_GEN4_VBAT_2S_MID2(bus_id, sid) ADC5_GEN4_VIRT_CHAN(bus_id, si= d, 0x9f) + +#define ADC5_GEN4_ICHG_FB(bus_id, sid) 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Fri, 31 Jul 2026 11:08:10 -0700 (PDT) From: Jishnu Prakash Date: Fri, 31 Jul 2026 23:36:18 +0530 Subject: [PATCH 5/7] arm64: dts: qcom: pmk8850: Add ADC5 Gen4 peripheral Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260731-pmic5_gen4_adc-v1-5-9c49b2eea6f9@oss.qualcomm.com> References: <20260731-pmic5_gen4_adc-v1-0-9c49b2eea6f9@oss.qualcomm.com> In-Reply-To: <20260731-pmic5_gen4_adc-v1-0-9c49b2eea6f9@oss.qualcomm.com> To: Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Amit Kucheria , Thara Gopinath , "Rafael J. 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Add the ADC peripheral node with PMK8850 die_temp and xo_therm channel nodes under it initially. Signed-off-by: Jishnu Prakash Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/pmk8850.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pmk8850.dtsi b/arch/arm64/boot/dts/qc= om/pmk8850.dtsi index c7ba72fd48bc..44d1d1957f8a 100644 --- a/arch/arm64/boot/dts/qcom/pmk8850.dtsi +++ b/arch/arm64/boot/dts/qcom/pmk8850.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include "qcom-adc5-gen4.h" =20 &spmi_bus0 { pmic@0 { @@ -45,6 +46,30 @@ pmk8850_gpios: gpio@b800 { #interrupt-cells =3D <2>; }; =20 + pmk8850_vadc: adc@9000 { + compatible =3D "qcom,spmi-adc5-gen4"; + reg =3D <0x9000>, <0x9100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D <0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>, + <0x0 0x91 0x1 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells =3D <1>; + #io-channel-cells =3D <1>; + + channel@3 { + reg =3D ; + label =3D "pmk8850_die_temp"; + }; + + channel@44 { + reg =3D ; + label =3D "pmk8850_therm_0"; + qcom,ratiometric; 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This includes die temperature and VPH power channels per PMIC. Add a thermal zone corresponding to the PMK8850 xo_therm ADC thermistor channel to enable temperature monitoring. Also add io-channels and io-channel-names properties to the temp_alarm nodes so that they can get temperature reading from the newly added ADC die_temp channels. Signed-off-by: Jishnu Prakash --- arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 143 +++++++++++++++++++++++++++= ++++ 1 file changed, 143 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts= /qcom/glymur-crd.dtsi index e784b538f42e..1487864482f8 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi @@ -11,6 +11,7 @@ #include "smb2370.dtsi" /* SPMI2: SID-9/10/11 */ =20 #include +#include "qcom-adc5-gen4.h" =20 / { model =3D "Qualcomm Technologies, Inc. Glymur CRD"; @@ -68,6 +69,26 @@ switch-lid { }; }; =20 + thermal-zones { + sys-0-thermal { + thermal-sensors =3D <&pmk8850_vadc ADC5_GEN4_AMUX1_THM_100K_PU(0, 0)>; + + trips { + trip0 { + temperature =3D <70000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + trip1 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + }; + vreg_nvme: regulator-nvme { compatible =3D "regulator-fixed"; =20 @@ -537,6 +558,26 @@ &pcie6_port0 { wake-gpios =3D <&tlmm 151 GPIO_ACTIVE_LOW>; }; =20 +&pmcx0102_c_e0_temp_alarm { + io-channels =3D <&pmk8850_vadc ADC5_GEN4_DIE_TEMP(0, 2)>; + io-channel-names =3D "thermal"; +}; + +&pmcx0102_c_e1_temp_alarm { + io-channels =3D <&pmk8850_vadc ADC5_GEN4_DIE_TEMP(1, 2)>; + io-channel-names =3D "thermal"; +}; + +&pmcx0102_d_e0_temp_alarm { + io-channels =3D <&pmk8850_vadc ADC5_GEN4_DIE_TEMP(0, 3)>; + io-channel-names =3D "thermal"; +}; + +&pmcx0102_d_e1_temp_alarm { + io-channels =3D <&pmk8850_vadc ADC5_GEN4_DIE_TEMP(1, 3)>; + io-channel-names =3D "thermal"; +}; + &pmh0101_gpios { nvme_reg_en: nvme-reg-en-state { pins =3D "gpio14"; @@ -545,6 +586,11 @@ nvme_reg_en: nvme-reg-en-state { }; }; =20 +&pmh0101_temp_alarm { + io-channels =3D <&pmk8850_vadc ADC5_GEN4_DIE_TEMP(0, 1)>; + io-channel-names =3D "thermal"; +}; + &pmh0110_f_e1_gpios { nvme_sec_reg_en: nvme-reg-en-state { pins =3D "gpio14"; @@ -562,10 +608,107 @@ key_vol_up_default: key-vol-up-default-state { }; }; =20 +&pmh0110_f_e0_temp_alarm { + io-channels =3D <&pmk8850_vadc ADC5_GEN4_DIE_TEMP(0, 5)>; + io-channel-names =3D "thermal"; +}; + +&pmh0110_f_e1_temp_alarm { + io-channels =3D <&pmk8850_vadc ADC5_GEN4_DIE_TEMP(1, 5)>; + io-channel-names =3D "thermal"; +}; + +&pmh0110_h_e0_temp_alarm { + io-channels =3D <&pmk8850_vadc ADC5_GEN4_DIE_TEMP(0, 7)>; + io-channel-names =3D "thermal"; +}; + &pmk8850_rtc { qcom,no-alarm; }; =20 +&pmk8850_vadc { + channel@103 { + reg =3D ; + label =3D "pmh0101_die_temp"; + }; + + channel@18e { + reg =3D ; + label =3D "pmh0101_vph_pwr"; + }; + + channel@203 { + reg =3D ; + label =3D "pmcx0102_c_e0_die_temp"; + }; + + channel@28e { + reg =3D ; + label =3D "pmcx0102_c_e0_vph_pwr"; + }; + + channel@303 { + reg =3D ; + label =3D "pmcx0102_d_e0_die_temp"; + }; + + channel@38e { + reg =3D ; + label =3D "pmcx0102_d_e0_vph_pwr"; + }; + + channel@503 { + reg =3D ; + label =3D "pmh0110_f_e0_die_temp"; + }; + + channel@58e { + reg =3D ; + label =3D "pmh0110_f_e0_vph_pwr"; + }; + + channel@703 { + reg =3D ; + label =3D "pmh0110_h_e0_die_temp"; + }; + + channel@78e { + reg =3D ; + label =3D "pmh0110_h_e0_vph_pwr"; + }; + + channel@2203 { + reg =3D ; + label =3D "pmcx0102_c_e1_die_temp"; + }; + + channel@228e { + reg =3D ; + label =3D "pmcx0102_c_e1_vph_pwr"; + }; + + channel@2303 { + reg =3D ; + label =3D "pmcx0102_d_e1_die_temp"; + }; + + channel@238e { + reg =3D ; + label =3D "pmcx0102_d_e1_vph_pwr"; + }; + + channel@2503 { + reg =3D ; + label =3D "pmh0110_f_e1_die_temp"; + }; + + channel@258e { + reg =3D ; + label =3D "pmh0110_f_e1_vph_pwr"; + }; +}; + &pon_resin { linux,code =3D ; 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This includes die temperature and VPH power channels per PMIC and channels for available system thermistors. Add thermal zones corresponding to the thermistor channels to enable temperature monitoring. Also add io-channels and io-channel-names properties to the temp_alarm nodes so that they can get temperature reading from the newly added ADC die_temp channels. Signed-off-by: Jishnu Prakash --- arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 312 +++++++++++++++++++++++++= ++++ arch/arm64/boot/dts/qcom/kaanapali-qrd.dts | 312 +++++++++++++++++++++++++= ++++ 2 files changed, 624 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/d= ts/qcom/kaanapali-mtp.dts index f9b5b5718b90..41636641f1ce 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts @@ -8,8 +8,10 @@ #include #include #include +#include #include #include "kaanapali.dtsi" +#include "qcom-adc5-gen4.h" =20 #include "pm8010-kaanapali.dtsi" /* SPMI1: SID-12/13 */ #include "pmd8028-kaanapali.dtsi" /* SPMI1: SID-4 */ @@ -163,6 +165,152 @@ platform { }; }; =20 + thermal-zones { + sys-0-thermal { + thermal-sensors =3D <&pmk8850_vadc ADC5_GEN4_AMUX1_THM_100K_PU(0, 0)>; + + trips { + trip0 { + temperature =3D <70000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + trip1 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + sys-1-thermal { + thermal-sensors =3D <&pmk8850_vadc ADC5_GEN4_AMUX1_THM_100K_PU(0, 1)>; + + trips { + trip0 { + temperature =3D <70000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + trip1 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + sys-2-thermal { + thermal-sensors =3D <&pmk8850_vadc ADC5_GEN4_AMUX2_THM_100K_PU(0, 1)>; + + trips { + trip0 { + temperature =3D <70000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + trip1 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + sys-3-thermal { + thermal-sensors =3D <&pmk8850_vadc ADC5_GEN4_AMUX3_THM_100K_PU(0, 1)>; + + trips { + trip0 { + temperature =3D <70000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + trip1 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + sys-4-thermal { + thermal-sensors =3D <&pmk8850_vadc ADC5_GEN4_AMUX4_THM_100K_PU(0, 1)>; + + trips { + trip0 { + temperature =3D <70000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + trip1 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + sys-5-thermal { + thermal-sensors =3D <&pmk8850_vadc ADC5_GEN4_AMUX6_THM_100K_PU(0, 1)>; + + trips { + trip0 { + temperature =3D <70000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + trip1 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + sys-6-thermal { + thermal-sensors =3D <&pmk8850_vadc ADC5_GEN4_AMUX4_THM_100K_PU(1, 7)>; + + trips { + trip0 { + temperature =3D <70000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + trip1 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + sys-7-thermal { + thermal-sensors =3D <&pmk8850_vadc ADC5_GEN4_AMUX4_GPIO_100K_PU(1, 7)>; + + trips { + trip0 { + temperature =3D <70000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + trip1 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + }; + wcd939x: audio-codec { compatible =3D "qcom,wcd9395-codec", "qcom,wcd9390-codec"; =20 @@ -981,6 +1129,14 @@ led-1 { }; }; =20 +&pmh0101_gpios { + sys_therm_5_gpio3: sys-therm-5-gpio3-state { + pins =3D "gpio3"; + function =3D PMIC_GPIO_FUNC_NORMAL; + bias-high-impedance; + }; +}; + &pmh0101_pwm { status =3D "okay"; =20 @@ -1008,6 +1164,11 @@ led@3 { }; }; =20 +&pmh0101_temp_alarm { + io-channels =3D <&pmk8850_vadc ADC5_GEN4_DIE_TEMP(0, 1)>; + io-channel-names =3D "thermal"; +}; + &pmh0104_j_e1_gpios { bt_default: bt-default-state { pins =3D "gpio5"; @@ -1038,6 +1199,11 @@ sde_mdp_vsync_p_1p8_active: sde-mdp-vsync-p-1p8-acti= ve-state { }; }; =20 +&pmh0110_d_e0_temp_alarm { + io-channels =3D <&pmk8850_vadc ADC5_GEN4_DIE_TEMP(0, 3)>; + io-channel-names =3D "thermal"; +}; + &pmh0110_f_e0_gpios { sde_disp0_rst_1p2_active: sde-disp0-rst-1p2-active-state { pins =3D "gpio9"; @@ -1056,6 +1222,152 @@ sde_disp0_rst_1p8_active: sde-disp0-rst-1p8-active-= state { }; }; =20 +&pmh0110_f_e0_temp_alarm { + io-channels =3D <&pmk8850_vadc ADC5_GEN4_DIE_TEMP(0, 5)>; + io-channel-names =3D "thermal"; +}; + +&pmh0110_g_e0_temp_alarm { + io-channels =3D <&pmk8850_vadc ADC5_GEN4_DIE_TEMP(0, 6)>; + io-channel-names =3D "thermal"; +}; + +&pmh0110_i_e0_temp_alarm { + io-channels =3D <&pmk8850_vadc ADC5_GEN4_DIE_TEMP(0, 8)>; + io-channel-names =3D "thermal"; +}; + +&pmih0108_e1_temp_alarm { + io-channels =3D <&pmk8850_vadc ADC5_GEN4_DIE_TEMP(1, 7)>; + io-channel-names =3D "thermal"; +}; + +&pmk8850_vadc { + pinctrl-0 =3D <&sys_therm_5_gpio3>; + pinctrl-names =3D "default"; + + channel@103 { + reg =3D ; + label =3D "pmh0101_die_temp"; + }; + + channel@18e { + reg =3D ; + label =3D "pmh0101_vph_pwr"; + }; + + channel@303 { + reg =3D ; + label =3D "pmh0110_3_die_temp"; + }; + + channel@38e { + reg =3D ; + label =3D "pmh0110_3_vph_pwr"; + }; + + channel@503 { + reg =3D ; + label =3D "pmh0110_5_die_temp"; + }; + + channel@58e { + reg =3D ; + label =3D "pmh0110_5_vph_pwr"; + }; + + channel@603 { + reg =3D ; + label =3D "pmh0110_6_die_temp"; + }; + + channel@68e { + reg =3D ; + label =3D "pmh0110_6_vph_pwr"; + }; + + channel@803 { + reg =3D ; + label =3D "pmh0110_8_die_temp"; + }; + + channel@88e { + reg =3D ; + label =3D "pmh0110_8_vph_pwr"; + }; + + channel@2703 { + reg =3D ; + label =3D "pmih0108_e1_die_temp"; + }; + + channel@278e { + reg =3D ; + label =3D "pmih0108_e1_vph_pwr"; + }; + + channel@278f { + reg =3D ; + label =3D "pmih0108_e1_vbat_sns_qbg"; + }; + + channel@144 { + reg =3D ; + label =3D "pmh0101_therm_1"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + qcom,adc-tm; + }; + + channel@145 { + reg =3D ; + label =3D "pmh0101_therm_2"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + qcom,adc-tm; + }; + + channel@146 { + reg =3D ; + label =3D "pmh0101_therm_3"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + qcom,adc-tm; + }; + + channel@147 { + reg =3D ; + label =3D "pmh0101_therm_4"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + qcom,adc-tm; + }; + + channel@149 { + reg =3D ; + label =3D "pmh0101_therm_5"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + qcom,adc-tm; + }; + + channel@2747 { + reg =3D ; + label =3D "pmih0108_e1_therm_6"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + qcom,adc-tm; + }; + + channel@274d { + reg =3D ; + label =3D "pmih0108_e1_therm_7"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + qcom,adc-tm; + }; +}; + &pon_resin { linux,code =3D ; =20 diff --git a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts b/arch/arm64/boot/d= ts/qcom/kaanapali-qrd.dts index 55d02219ef4e..303e7b316901 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts +++ b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts @@ -8,8 +8,10 @@ #include #include #include +#include #include #include "kaanapali.dtsi" +#include "qcom-adc5-gen4.h" =20 #include "pm8010-kaanapali.dtsi" /* SPMI1: SID-12/13 */ #include "pmd8028-kaanapali.dtsi" /* SPMI1: SID-4 */ @@ -80,6 +82,152 @@ key-volume-up { wakeup-source; }; }; + + thermal-zones { + sys-0-thermal { + thermal-sensors =3D <&pmk8850_vadc ADC5_GEN4_AMUX1_THM_100K_PU(0, 0)>; + + trips { + trip0 { + temperature =3D <70000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + trip1 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + sys-1-thermal { + thermal-sensors =3D <&pmk8850_vadc ADC5_GEN4_AMUX1_THM_100K_PU(0, 1)>; + + trips { + trip0 { + temperature =3D <70000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + trip1 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + sys-2-thermal { + thermal-sensors =3D <&pmk8850_vadc ADC5_GEN4_AMUX2_THM_100K_PU(0, 1)>; + + trips { + trip0 { + temperature =3D <70000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + trip1 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + sys-3-thermal { + thermal-sensors =3D <&pmk8850_vadc ADC5_GEN4_AMUX3_THM_100K_PU(0, 1)>; + + trips { + trip0 { + temperature =3D <70000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + trip1 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + sys-4-thermal { + thermal-sensors =3D <&pmk8850_vadc ADC5_GEN4_AMUX4_THM_100K_PU(0, 1)>; + + trips { + trip0 { + temperature =3D <70000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + trip1 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + sys-5-thermal { + thermal-sensors =3D <&pmk8850_vadc ADC5_GEN4_AMUX6_THM_100K_PU(0, 1)>; + + trips { + trip0 { + temperature =3D <70000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + trip1 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + sys-6-thermal { + thermal-sensors =3D <&pmk8850_vadc ADC5_GEN4_AMUX4_THM_100K_PU(1, 7)>; + + trips { + trip0 { + temperature =3D <70000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + trip1 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + sys-7-thermal { + thermal-sensors =3D <&pmk8850_vadc ADC5_GEN4_AMUX4_GPIO_100K_PU(1, 7)>; + + trips { + trip0 { + temperature =3D <70000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + trip1 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + }; }; =20 &apps_rsc { @@ -717,6 +865,14 @@ led-1 { }; }; =20 +&pmh0101_gpios { + sys_therm_5_gpio3: sys-therm-5-gpio3-state { + pins =3D "gpio3"; + function =3D PMIC_GPIO_FUNC_NORMAL; + bias-high-impedance; + }; +}; + &pmh0101_pwm { status =3D "okay"; =20 @@ -744,11 +900,167 @@ led@3 { }; }; =20 +&pmh0101_temp_alarm { + io-channels =3D <&pmk8850_vadc ADC5_GEN4_DIE_TEMP(0, 1)>; + io-channel-names =3D "thermal"; +}; + +&pmh0110_d_e0_temp_alarm { + io-channels =3D <&pmk8850_vadc ADC5_GEN4_DIE_TEMP(0, 3)>; + io-channel-names =3D "thermal"; +}; + +&pmh0110_f_e0_temp_alarm { + io-channels =3D <&pmk8850_vadc ADC5_GEN4_DIE_TEMP(0, 5)>; + io-channel-names =3D "thermal"; +}; + +&pmh0110_g_e0_temp_alarm { + io-channels =3D <&pmk8850_vadc ADC5_GEN4_DIE_TEMP(0, 6)>; + io-channel-names =3D "thermal"; +}; + +&pmh0110_i_e0_temp_alarm { + io-channels =3D <&pmk8850_vadc ADC5_GEN4_DIE_TEMP(0, 8)>; + io-channel-names =3D "thermal"; +}; + &pmih0108_e1_eusb2_repeater { vdd18-supply =3D <&vreg_l15b_1p8>; vdd3-supply =3D <&vreg_l5b_3p1>; }; =20 +&pmih0108_e1_temp_alarm { + io-channels =3D <&pmk8850_vadc ADC5_GEN4_DIE_TEMP(1, 7)>; + io-channel-names =3D "thermal"; +}; + +&pmk8850_vadc { + pinctrl-0 =3D <&sys_therm_5_gpio3>; + pinctrl-names =3D "default"; + + channel@103 { + reg =3D ; + label =3D "pmh0101_die_temp"; + }; + + channel@18e { + reg =3D ; + label =3D "pmh0101_vph_pwr"; + }; + + channel@303 { + reg =3D ; + label =3D "pmh0110_3_die_temp"; + }; + + channel@38e { + reg =3D ; + label =3D "pmh0110_3_vph_pwr"; + }; + + channel@503 { + reg =3D ; + label =3D "pmh0110_5_die_temp"; + }; + + channel@58e { + reg =3D ; + label =3D "pmh0110_5_vph_pwr"; + }; + + channel@603 { + reg =3D ; + label =3D "pmh0110_6_die_temp"; + }; + + channel@68e { + reg =3D ; + label =3D "pmh0110_6_vph_pwr"; + }; + + channel@803 { + reg =3D ; + label =3D "pmh0110_8_die_temp"; + }; + + channel@88e { + reg =3D ; + label =3D "pmh0110_8_vph_pwr"; + }; + + channel@2703 { + reg =3D ; + label =3D "pmih0108_e1_die_temp"; + }; + + channel@278e { + reg =3D ; + label =3D "pmih0108_e1_vph_pwr"; + }; + + channel@278f { + reg =3D ; + label =3D "pmih0108_e1_vbat_sns_qbg"; + }; + + channel@144 { + reg =3D ; + label =3D "pmh0101_therm_1"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + qcom,adc-tm; + }; + + channel@145 { + reg =3D ; + label =3D "pmh0101_therm_2"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + qcom,adc-tm; + }; + + channel@146 { + reg =3D ; + label =3D "pmh0101_therm_3"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + qcom,adc-tm; + }; + + channel@147 { + reg =3D ; + label =3D "pmh0101_therm_4"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + qcom,adc-tm; + }; + + channel@149 { + reg =3D ; + label =3D "pmh0101_therm_5"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + qcom,adc-tm; + }; + + channel@2747 { + reg =3D ; + label =3D "pmih0108_e1_therm_6"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + qcom,adc-tm; + }; + + channel@274d { + reg =3D ; + label =3D "pmih0108_e1_therm_7"; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + qcom,adc-tm; + }; +}; + &pon_resin { linux,code =3D ; =20 --=20 2.43.0