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Revert the commit, it will be replaced by the better version. Fixes: 412a2e5955e0 ("media: iris: Add Gen2 firmware autodetect and fallbac= k") Signed-off-by: Dmitry Baryshkov Reviewed-by: Bryan O'Donoghue Reviewed-by: Vishnu Reddy Tested-by: Gourav Kumar --- drivers/media/platform/qcom/iris/iris_firmware.c | 119 +++--------------= ---- .../platform/qcom/iris/iris_platform_common.h | 6 +- .../media/platform/qcom/iris/iris_platform_vpu2.c | 11 +- .../media/platform/qcom/iris/iris_platform_vpu3x.c | 10 +- drivers/media/platform/qcom/iris/iris_probe.c | 4 + drivers/media/platform/qcom/iris/iris_vidc.c | 3 - 6 files changed, 33 insertions(+), 120 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_firmware.c b/drivers/med= ia/platform/qcom/iris/iris_firmware.c index 965384fdd339..1a476146d758 100644 --- a/drivers/media/platform/qcom/iris/iris_firmware.c +++ b/drivers/media/platform/qcom/iris/iris_firmware.c @@ -16,109 +16,20 @@ =20 #define MAX_FIRMWARE_NAME_SIZE 128 =20 -/* Detect Gen2 firmware by scanning the blob for: - * QC_IMAGE_VERSION_STRING=3D - * and then checking: - * - version starts with "vfw", OR - * - version matches "video-firmware.N.M" with N >=3D 2 - */ - -static bool iris_detect_gen2_from_fwdata(const u8 *data, size_t size) -{ - static const char *marker =3D "QC_IMAGE_VERSION_STRING=3D"; - const size_t mlen =3D strlen(marker); - static const char *vfw =3D "vfw"; - const size_t vfwlen =3D strlen(vfw); - static const char *vf =3D "video-firmware."; - const size_t vflen =3D strlen(vf); - - for (size_t i =3D 0; i + mlen < size; i++) { - const char *found; - - if (memcmp(data + i, marker, mlen)) - continue; - - found =3D data + i + mlen; - size -=3D i + mlen; - - /* vfw =3D> Gen2 */ - if (size > vfwlen && !memcmp(found, vfw, vfwlen)) - return true; - - if (size < vflen || - memcmp(found, vf, vflen)) - return false; - - found +=3D vflen; - size -=3D vflen; - - /* - * video-firmware.1.x is Gen1. - * video-firmware.2.x and video-firmware.10.x are Gen2. - */ - return size >=3D 2 && - (*found >=3D '2' || (*found =3D=3D '1' && found[1] !=3D '.')); - } - - return false; -} - -static const struct firmware *iris_detect_firmware(struct iris_core *core, - const char **fw_name) -{ - const struct firmware *firmware; - bool has_both_gens; - int ret; - - *fw_name =3D NULL; - if (core->iris_platform_data->firmware_desc_gen2) - core->iris_firmware_desc =3D core->iris_platform_data->firmware_desc_gen= 2; - else if (core->iris_platform_data->firmware_desc_gen1) - core->iris_firmware_desc =3D core->iris_platform_data->firmware_desc_gen= 1; - else - return ERR_PTR(-EINVAL); - - has_both_gens =3D core->iris_platform_data->firmware_desc_gen2 && - core->iris_platform_data->firmware_desc_gen1; - - ret =3D of_property_read_string_index(dev_of_node(core->dev), "firmware-n= ame", 0, fw_name); - if (ret) { - *fw_name =3D core->iris_firmware_desc->fwname; - ret =3D request_firmware(&firmware, *fw_name, core->dev); - if (ret && has_both_gens) { - core->iris_firmware_desc =3D core->iris_platform_data->firmware_desc_ge= n1; - *fw_name =3D core->iris_firmware_desc->fwname; - ret =3D request_firmware(&firmware, *fw_name, core->dev); - } - - return ret ? ERR_PTR(ret) : firmware; - } - - ret =3D request_firmware(&firmware, *fw_name, core->dev); - if (ret) - return ERR_PTR(ret); - - if (has_both_gens && - !iris_detect_gen2_from_fwdata((const u8 *)firmware->data, firmware->s= ize)) { - dev_info(core->dev, "Gen1 FW detected in %s\n", *fw_name); - core->iris_firmware_desc =3D core->iris_platform_data->firmware_desc_gen= 1; - } - - return firmware; -} - -static int iris_load_fw_to_memory(struct iris_core *core) +static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_n= ame) { const struct firmware *firmware =3D NULL; struct device *dev =3D core->dev; struct resource res; phys_addr_t mem_phys; - const char *fw_name; size_t res_size; ssize_t fw_size; void *mem_virt; int ret; =20 + if (strlen(fw_name) >=3D MAX_FIRMWARE_NAME_SIZE - 4) + return -EINVAL; + ret =3D of_reserved_mem_region_to_resource(dev->of_node, 0, &res); if (ret) return ret; @@ -126,11 +37,9 @@ static int iris_load_fw_to_memory(struct iris_core *cor= e) mem_phys =3D res.start; res_size =3D resource_size(&res); =20 - firmware =3D iris_detect_firmware(core, &fw_name); - if (IS_ERR(firmware)) - return PTR_ERR(firmware); - - core->iris_firmware_data =3D core->iris_firmware_desc->firmware_data; + ret =3D request_firmware(&firmware, fw_name, dev); + if (ret) + return ret; =20 fw_size =3D qcom_mdt_get_size(firmware); if (fw_size < 0 || res_size < (size_t)fw_size) { @@ -157,12 +66,18 @@ static int iris_load_fw_to_memory(struct iris_core *co= re) int iris_fw_load(struct iris_core *core) { const struct tz_cp_config *cp_config; + const char *fwpath =3D NULL; int i, ret; =20 - ret =3D iris_load_fw_to_memory(core); + ret =3D of_property_read_string_index(core->dev->of_node, "firmware-name"= , 0, + &fwpath); + if (ret) + fwpath =3D core->iris_firmware_desc->fwname; + + ret =3D iris_load_fw_to_memory(core, fwpath); if (ret) { - dev_err(core->dev, "firmware download failed %d\n", ret); - return ret; + dev_err(core->dev, "firmware download failed\n"); + return -ENOMEM; } =20 ret =3D qcom_scm_pas_auth_and_reset(IRIS_PAS_ID); @@ -184,7 +99,7 @@ int iris_fw_load(struct iris_core *core) } } =20 - return 0; + return ret; } =20 int iris_fw_unload(struct iris_core *core) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 974809509146..a9453d539fc2 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -292,7 +292,11 @@ struct iris_firmware_desc { }; =20 struct iris_platform_data { - const struct iris_firmware_desc *firmware_desc_gen1, *firmware_desc_gen2; + /* + * XXX: replace with gen1 / gen2 pointers once we have platforms + * supporting both firmware kinds. + */ + const struct iris_firmware_desc *firmware_desc; =20 const struct vpu_ops *vpu_ops; const struct icc_info *icc_tbl; diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c b/driver= s/media/platform/qcom/iris/iris_platform_vpu2.c index bbdbf21961d7..fa5bb143158d 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c @@ -29,12 +29,6 @@ static const struct iris_firmware_desc iris_vpu20_p1_gen= 1_desc =3D { .fwname =3D "qcom/vpu/vpu20_p1.mbn", }; =20 -static const struct iris_firmware_desc iris_vpu20_p1_gen2_s6_desc =3D { - .firmware_data =3D &iris_hfi_gen2_data, - .get_vpu_buffer_size =3D iris_vpu33_buf_size, - .fwname =3D "qcom/vpu/vpu20_p1_gen2_s6.mbn", -}; - static const struct iris_firmware_desc iris_vpu20_p4_gen1_desc =3D { .firmware_data =3D &iris_hfi_gen1_data, .get_vpu_buffer_size =3D iris_vpu_buf_size, @@ -106,8 +100,7 @@ const struct iris_platform_data milos_data =3D { }; =20 const struct iris_platform_data sc7280_data =3D { - .firmware_desc_gen1 =3D &iris_vpu20_p1_gen1_desc, - .firmware_desc_gen2 =3D &iris_vpu20_p1_gen2_s6_desc, + .firmware_desc =3D &iris_vpu20_p1_gen1_desc, .vpu_ops =3D &iris_vpu2_ops, .icc_tbl =3D iris_icc_info_vpu2, .icc_tbl_size =3D ARRAY_SIZE(iris_icc_info_vpu2), @@ -136,7 +129,7 @@ const struct iris_platform_data sc7280_data =3D { }; =20 const struct iris_platform_data sm8250_data =3D { - .firmware_desc_gen1 =3D &iris_vpu20_p4_gen1_desc, + .firmware_desc =3D &iris_vpu20_p4_gen1_desc, .vpu_ops =3D &iris_vpu2_ops, .icc_tbl =3D iris_icc_info_vpu2, .icc_tbl_size =3D ARRAY_SIZE(iris_icc_info_vpu2), diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c b/drive= rs/media/platform/qcom/iris/iris_platform_vpu3x.c index 74626b35d9cb..2c63adbc5579 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c @@ -90,7 +90,7 @@ static const struct tz_cp_config tz_cp_config_vpu3[] =3D { * - inst_caps to platform_inst_cap_qcs8300 */ const struct iris_platform_data qcs8300_data =3D { - .firmware_desc_gen2 =3D &iris_vpu30_p4_s6_gen2_desc, + .firmware_desc =3D &iris_vpu30_p4_s6_gen2_desc, .vpu_ops =3D &iris_vpu3_ops, .icc_tbl =3D iris_icc_info_vpu3x, .icc_tbl_size =3D ARRAY_SIZE(iris_icc_info_vpu3x), @@ -119,7 +119,7 @@ const struct iris_platform_data qcs8300_data =3D { }; =20 const struct iris_platform_data sm8550_data =3D { - .firmware_desc_gen2 =3D &iris_vpu30_p4_gen2_desc, + .firmware_desc =3D &iris_vpu30_p4_gen2_desc, .vpu_ops =3D &iris_vpu3_ops, .icc_tbl =3D iris_icc_info_vpu3x, .icc_tbl_size =3D ARRAY_SIZE(iris_icc_info_vpu3x), @@ -154,7 +154,7 @@ const struct iris_platform_data sm8550_data =3D { * - controller_rst_tbl to sm8650_controller_reset_table */ const struct iris_platform_data sm8650_data =3D { - .firmware_desc_gen2 =3D &iris_vpu33_p4_gen2_desc, + .firmware_desc =3D &iris_vpu33_p4_gen2_desc, .vpu_ops =3D &iris_vpu33_ops, .icc_tbl =3D iris_icc_info_vpu3x, .icc_tbl_size =3D ARRAY_SIZE(iris_icc_info_vpu3x), @@ -185,7 +185,7 @@ const struct iris_platform_data sm8650_data =3D { }; =20 const struct iris_platform_data sm8750_data =3D { - .firmware_desc_gen2 =3D &iris_vpu35_p4_gen2_desc, + .firmware_desc =3D &iris_vpu35_p4_gen2_desc, .vpu_ops =3D &iris_vpu35_ops, .icc_tbl =3D iris_icc_info_vpu3x, .icc_tbl_size =3D ARRAY_SIZE(iris_icc_info_vpu3x), @@ -220,7 +220,7 @@ const struct iris_platform_data sm8750_data =3D { * - different num_vpp_pipe */ const struct iris_platform_data x1p42100_data =3D { - .firmware_desc_gen2 =3D &iris_vpu30_p1_gen2_desc, + .firmware_desc =3D &iris_vpu30_p1_gen2_desc, .vpu_ops =3D &iris_vpu3_ops, .icc_tbl =3D iris_icc_info_vpu3x, .icc_tbl_size =3D ARRAY_SIZE(iris_icc_info_vpu3x), diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/= platform/qcom/iris/iris_probe.c index 5db6398433a4..81cccb756b94 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -253,6 +253,8 @@ static int iris_probe(struct platform_device *pdev) return core->irq; =20 core->iris_platform_data =3D of_device_get_match_data(core->dev); + core->iris_firmware_desc =3D core->iris_platform_data->firmware_desc; + core->iris_firmware_data =3D core->iris_firmware_desc->firmware_data; =20 core->ubwc_cfg =3D qcom_ubwc_config_get_data(); if (IS_ERR(core->ubwc_cfg)) @@ -271,6 +273,8 @@ static int iris_probe(struct platform_device *pdev) if (ret) return ret; =20 + iris_session_init_caps(core); + ret =3D v4l2_device_register(dev, &core->v4l2_dev); if (ret) return ret; diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/p= latform/qcom/iris/iris_vidc.c index fcbc60016bee..1c052ca235be 100644 --- a/drivers/media/platform/qcom/iris/iris_vidc.c +++ b/drivers/media/platform/qcom/iris/iris_vidc.c @@ -9,7 +9,6 @@ #include #include =20 -#include "iris_ctrls.h" #include "iris_vidc.h" #include "iris_instance.h" #include "iris_vdec.h" @@ -197,8 +196,6 @@ int iris_open(struct file *filp) goto fail_m2m_release; } =20 - iris_session_init_caps(core); - if (inst->domain =3D=3D DECODER) ret =3D iris_vdec_inst_init(inst); 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Update the firmware loading logic to handle this generically by preferring Gen2 when available, while safely falling back to Gen1 when required. The firmware loading logic is updated with the following priority: 1. Device Tree (`firmware-name`): If specified, load unconditionally. 2. Gen2 default : If no DT override exists, select the Gen2 firmware descriptor when present and attempt to load the corresponding firmware image. 3. Gen1 Fallback: If loading the Gen2 firmware fails and a Gen1 descriptor is available, retry with the Gen1 firmware image. Loading and generation detection are split into two steps. iris_load_firmware() applies the priority above and returns the loaded image together with a candidate descriptor. iris_detect_firmware() then runs only after qcom_mdt_load() has succeeded and publishes the chosen descriptor, so the driver commits to a HFI generation only for an image that has actually been loaded. When a platform provides both Gen1 and Gen2 firmware descriptors and the firmware is loaded via a DT override, the candidate descriptor is only a default: iris_detect_firmware() inspects the loaded image to pick the generation, before authentication. It scans the memory populated by qcom_mdt_load() rather than the request_firmware() blob, so that a split .mdt image, whose version string lives in the .bNN data segments and not in the ELF headers, is classified correctly. The firmware is classified as Gen2 if the QC_IMAGE_VERSION_STRING starts with "vfw" or matches the "video-firmware.N.M" format with N >=3D 2. If a Gen1 firmware image is detected in this case, the driver switches to the Gen1 firmware descriptor and associated platform data so that the correct HFI implementation is used. This change makes firmware generation detection platform=E2=80=91agnostic, preserves DT overrides, prefers newer Gen2 firmware when available, and maintains compatibility with platforms that only support Gen1. Signed-off-by: Dikshita Agarwal Reviewed-by: Bryan O'Donoghue Co-developed-by: Dmitry Baryshkov Signed-off-by: Dmitry Baryshkov Reviewed-by: Vikash Garodia Reviewed-by: Vishnu Reddy Tested-by: Gourav Kumar --- drivers/media/platform/qcom/iris/iris_core.c | 2 + drivers/media/platform/qcom/iris/iris_firmware.c | 188 +++++++++++++++++= ++-- .../platform/qcom/iris/iris_platform_common.h | 6 +- .../media/platform/qcom/iris/iris_platform_vpu2.c | 11 +- .../media/platform/qcom/iris/iris_platform_vpu3x.c | 10 +- drivers/media/platform/qcom/iris/iris_probe.c | 4 - drivers/media/platform/qcom/iris/iris_vidc.c | 1 + 7 files changed, 188 insertions(+), 34 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_core.c b/drivers/media/p= latform/qcom/iris/iris_core.c index 8c335dbfce16..676baa8087a8 100644 --- a/drivers/media/platform/qcom/iris/iris_core.c +++ b/drivers/media/platform/qcom/iris/iris_core.c @@ -6,6 +6,7 @@ #include =20 #include "iris_core.h" +#include "iris_ctrls.h" #include "iris_firmware.h" #include "iris_state.h" #include "iris_vpu_common.h" @@ -85,6 +86,7 @@ int iris_core_init(struct iris_core *core) goto error_unload_fw; =20 core->iris_firmware_data->init_hfi_ops(core); + iris_session_init_caps(core); =20 ret =3D iris_hfi_core_init(core); if (ret) diff --git a/drivers/media/platform/qcom/iris/iris_firmware.c b/drivers/med= ia/platform/qcom/iris/iris_firmware.c index 1a476146d758..ea3b3a9793e8 100644 --- a/drivers/media/platform/qcom/iris/iris_firmware.c +++ b/drivers/media/platform/qcom/iris/iris_firmware.c @@ -14,22 +14,175 @@ =20 #define IRIS_PAS_ID 9 =20 -#define MAX_FIRMWARE_NAME_SIZE 128 +/* Detect Gen2 firmware by scanning the blob for: + * QC_IMAGE_VERSION_STRING=3D + * and then checking: + * - version starts with "vfw", OR + * - version matches "video-firmware.N.M" with N >=3D 2 + */ + +static bool iris_detect_gen2_from_fwdata(const u8 *data, size_t size) +{ + static const char *marker =3D "QC_IMAGE_VERSION_STRING=3D"; + const size_t mlen =3D strlen(marker); + static const char *vfw =3D "vfw"; + const size_t vfwlen =3D strlen(vfw); + static const char *vf =3D "video-firmware."; + const size_t vflen =3D strlen(vf); + + for (size_t i =3D 0; i + mlen < size; i++) { + const char *found; + + if (memcmp(data + i, marker, mlen)) + continue; + + found =3D data + i + mlen; + size -=3D i + mlen; + + /* vfw =3D> Gen2 */ + if (size > vfwlen && !memcmp(found, vfw, vfwlen)) + return true; + + if (size < vflen || + memcmp(found, vf, vflen)) + return false; + + found +=3D vflen; + size -=3D vflen; + + /* + * video-firmware.1.x is Gen1. + * video-firmware.2.x and video-firmware.10.x are Gen2. + */ + return size >=3D 2 && + (*found >=3D '2' || (*found =3D=3D '1' && found[1] !=3D '.')); + } + + return false; +} =20 -static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_n= ame) +/* + * Load the firmware image and return the descriptor that was used to pick= the + * file. On a platform that provides only one generation, or when no DT + * firmware-name override is present, the returned descriptor is final. Wi= th a + * DT override on a dual-generation platform the returned descriptor is on= ly a + * default; iris_detect_firmware() inspects the loaded image to confirm it. + */ +static const struct firmware *iris_load_firmware(struct iris_core *core, + const char **fw_name, + const struct iris_firmware_desc **fw_desc) { + const struct iris_firmware_desc *desc; + const struct firmware *firmware; + bool has_both_gens; + int ret; + + *fw_name =3D NULL; + ret =3D of_property_read_string_index(dev_of_node(core->dev), "firmware-n= ame", 0, fw_name); + + /* + * A platform may support both Gen1 and Gen2 firmware; which one is used + * depends on the firmware image installed on the system, not on the + * hardware. That installed image does not change while the device is + * bound, so the generation is detected only once and the chosen + * descriptor is reused on later core bring-ups (e.g. after a system + * error recovery). + */ + if (core->iris_firmware_desc) { + if (ret) + *fw_name =3D core->iris_firmware_desc->fwname; + ret =3D request_firmware(&firmware, *fw_name, core->dev); + if (ret) + return ERR_PTR(ret); + *fw_desc =3D core->iris_firmware_desc; + return firmware; + } + + has_both_gens =3D core->iris_platform_data->firmware_desc_gen2 && + core->iris_platform_data->firmware_desc_gen1; + + if (core->iris_platform_data->firmware_desc_gen2) + desc =3D core->iris_platform_data->firmware_desc_gen2; + else if (core->iris_platform_data->firmware_desc_gen1) + desc =3D core->iris_platform_data->firmware_desc_gen1; + else + return ERR_PTR(-EINVAL); + + if (ret) { + /* No firmware-name in DT: select by probing Gen2 then Gen1. */ + *fw_name =3D desc->fwname; + if (has_both_gens) + ret =3D firmware_request_nowarn(&firmware, *fw_name, core->dev); + else + ret =3D request_firmware(&firmware, *fw_name, core->dev); + if (ret && has_both_gens) { + desc =3D core->iris_platform_data->firmware_desc_gen1; + *fw_name =3D desc->fwname; + ret =3D request_firmware(&firmware, *fw_name, core->dev); + } + } else { + /* firmware-name given: iris_detect_firmware() picks the gen. */ + ret =3D request_firmware(&firmware, *fw_name, core->dev); + } + if (ret) + return ERR_PTR(ret); + + *fw_desc =3D desc; + return firmware; +} + +/* + * Detect the firmware generation and publish the descriptor. Run only aft= er + * qcom_mdt_load() has succeeded, so the driver commits to a HFI generation + * only for a firmware image that has actually been loaded. + * + * The generation is detected from the loaded image (@data / @size point a= t the + * reserved memory region populated by qcom_mdt_load()) rather than from t= he + * request_firmware() blob: for a split .mdt the latter holds only the ELF + * headers, while QC_IMAGE_VERSION_STRING lives in the .bNN data segments. + * + * The descriptor and firmware data are published exactly once, before any + * session exists, so the lockless readers in the ioctl paths never observ= e a + * reassignment. Later bring-ups reuse the already published descriptor. + */ +static void iris_detect_firmware(struct iris_core *core, const char *fw_na= me, + const u8 *data, size_t size, + const struct iris_firmware_desc *desc) +{ + if (core->iris_firmware_desc) + return; + + /* + * With a DT firmware-name override on a dual-generation platform the + * image on disk decides the generation, so inspect it and switch to the + * Gen1 descriptor when a Gen1 image was loaded. + */ + if (desc =3D=3D core->iris_platform_data->firmware_desc_gen2 && + core->iris_platform_data->firmware_desc_gen1 && + of_property_present(dev_of_node(core->dev), "firmware-name") && + !iris_detect_gen2_from_fwdata(data, size)) { + dev_info(core->dev, "Gen1 FW detected in %s\n", fw_name); + desc =3D core->iris_platform_data->firmware_desc_gen1; + } + + /* Publish iris_firmware_data first, then iris_firmware_desc (the guard).= */ + core->iris_firmware_data =3D desc->firmware_data; + core->iris_firmware_desc =3D desc; +} + +static int iris_load_fw_to_memory(struct iris_core *core) +{ + const struct iris_firmware_desc *desc; const struct firmware *firmware =3D NULL; struct device *dev =3D core->dev; struct resource res; phys_addr_t mem_phys; + const char *fw_name; size_t res_size; ssize_t fw_size; void *mem_virt; int ret; =20 - if (strlen(fw_name) >=3D MAX_FIRMWARE_NAME_SIZE - 4) - return -EINVAL; - ret =3D of_reserved_mem_region_to_resource(dev->of_node, 0, &res); if (ret) return ret; @@ -37,9 +190,9 @@ static int iris_load_fw_to_memory(struct iris_core *core= , const char *fw_name) mem_phys =3D res.start; res_size =3D resource_size(&res); =20 - ret =3D request_firmware(&firmware, fw_name, dev); - if (ret) - return ret; + firmware =3D iris_load_firmware(core, &fw_name, &desc); + if (IS_ERR(firmware)) + return PTR_ERR(firmware); =20 fw_size =3D qcom_mdt_get_size(firmware); if (fw_size < 0 || res_size < (size_t)fw_size) { @@ -53,9 +206,14 @@ static int iris_load_fw_to_memory(struct iris_core *cor= e, const char *fw_name) goto err_release_fw; } =20 + memset(mem_virt, 0, res_size); + ret =3D qcom_mdt_load(dev, firmware, fw_name, IRIS_PAS_ID, mem_virt, mem_phys, res_size, NULL); =20 + if (!ret) + iris_detect_firmware(core, fw_name, mem_virt, res_size, desc); + memunmap(mem_virt); err_release_fw: release_firmware(firmware); @@ -66,18 +224,12 @@ static int iris_load_fw_to_memory(struct iris_core *co= re, const char *fw_name) int iris_fw_load(struct iris_core *core) { const struct tz_cp_config *cp_config; - const char *fwpath =3D NULL; int i, ret; =20 - ret =3D of_property_read_string_index(core->dev->of_node, "firmware-name"= , 0, - &fwpath); - if (ret) - fwpath =3D core->iris_firmware_desc->fwname; - - ret =3D iris_load_fw_to_memory(core, fwpath); + ret =3D iris_load_fw_to_memory(core); if (ret) { - dev_err(core->dev, "firmware download failed\n"); - return -ENOMEM; + dev_err(core->dev, "firmware download failed %d\n", ret); + return ret; } =20 ret =3D qcom_scm_pas_auth_and_reset(IRIS_PAS_ID); @@ -99,7 +251,7 @@ int iris_fw_load(struct iris_core *core) } } =20 - return ret; + return 0; } =20 int iris_fw_unload(struct iris_core *core) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index a9453d539fc2..974809509146 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -292,11 +292,7 @@ struct iris_firmware_desc { }; =20 struct iris_platform_data { - /* - * XXX: replace with gen1 / gen2 pointers once we have platforms - * supporting both firmware kinds. - */ - const struct iris_firmware_desc *firmware_desc; + const struct iris_firmware_desc *firmware_desc_gen1, *firmware_desc_gen2; =20 const struct vpu_ops *vpu_ops; const struct icc_info *icc_tbl; diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c b/driver= s/media/platform/qcom/iris/iris_platform_vpu2.c index fa5bb143158d..bbdbf21961d7 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c @@ -29,6 +29,12 @@ static const struct iris_firmware_desc iris_vpu20_p1_gen= 1_desc =3D { .fwname =3D "qcom/vpu/vpu20_p1.mbn", }; =20 +static const struct iris_firmware_desc iris_vpu20_p1_gen2_s6_desc =3D { + .firmware_data =3D &iris_hfi_gen2_data, + .get_vpu_buffer_size =3D iris_vpu33_buf_size, + .fwname =3D "qcom/vpu/vpu20_p1_gen2_s6.mbn", +}; + static const struct iris_firmware_desc iris_vpu20_p4_gen1_desc =3D { .firmware_data =3D &iris_hfi_gen1_data, .get_vpu_buffer_size =3D iris_vpu_buf_size, @@ -100,7 +106,8 @@ const struct iris_platform_data milos_data =3D { }; =20 const struct iris_platform_data sc7280_data =3D { - .firmware_desc =3D &iris_vpu20_p1_gen1_desc, + .firmware_desc_gen1 =3D &iris_vpu20_p1_gen1_desc, + .firmware_desc_gen2 =3D &iris_vpu20_p1_gen2_s6_desc, .vpu_ops =3D &iris_vpu2_ops, .icc_tbl =3D iris_icc_info_vpu2, .icc_tbl_size =3D ARRAY_SIZE(iris_icc_info_vpu2), @@ -129,7 +136,7 @@ const struct iris_platform_data sc7280_data =3D { }; =20 const struct iris_platform_data sm8250_data =3D { - .firmware_desc =3D &iris_vpu20_p4_gen1_desc, + .firmware_desc_gen1 =3D &iris_vpu20_p4_gen1_desc, .vpu_ops =3D &iris_vpu2_ops, .icc_tbl =3D iris_icc_info_vpu2, .icc_tbl_size =3D ARRAY_SIZE(iris_icc_info_vpu2), diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c b/drive= rs/media/platform/qcom/iris/iris_platform_vpu3x.c index 2c63adbc5579..74626b35d9cb 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c @@ -90,7 +90,7 @@ static const struct tz_cp_config tz_cp_config_vpu3[] =3D { * - inst_caps to platform_inst_cap_qcs8300 */ const struct iris_platform_data qcs8300_data =3D { - .firmware_desc =3D &iris_vpu30_p4_s6_gen2_desc, + .firmware_desc_gen2 =3D &iris_vpu30_p4_s6_gen2_desc, .vpu_ops =3D &iris_vpu3_ops, .icc_tbl =3D iris_icc_info_vpu3x, .icc_tbl_size =3D ARRAY_SIZE(iris_icc_info_vpu3x), @@ -119,7 +119,7 @@ const struct iris_platform_data qcs8300_data =3D { }; =20 const struct iris_platform_data sm8550_data =3D { - .firmware_desc =3D &iris_vpu30_p4_gen2_desc, + .firmware_desc_gen2 =3D &iris_vpu30_p4_gen2_desc, .vpu_ops =3D &iris_vpu3_ops, .icc_tbl =3D iris_icc_info_vpu3x, .icc_tbl_size =3D ARRAY_SIZE(iris_icc_info_vpu3x), @@ -154,7 +154,7 @@ const struct iris_platform_data sm8550_data =3D { * - controller_rst_tbl to sm8650_controller_reset_table */ const struct iris_platform_data sm8650_data =3D { - .firmware_desc =3D &iris_vpu33_p4_gen2_desc, + .firmware_desc_gen2 =3D &iris_vpu33_p4_gen2_desc, .vpu_ops =3D &iris_vpu33_ops, .icc_tbl =3D iris_icc_info_vpu3x, .icc_tbl_size =3D ARRAY_SIZE(iris_icc_info_vpu3x), @@ -185,7 +185,7 @@ const struct iris_platform_data sm8650_data =3D { }; =20 const struct iris_platform_data sm8750_data =3D { - .firmware_desc =3D &iris_vpu35_p4_gen2_desc, + .firmware_desc_gen2 =3D &iris_vpu35_p4_gen2_desc, .vpu_ops =3D &iris_vpu35_ops, .icc_tbl =3D iris_icc_info_vpu3x, .icc_tbl_size =3D ARRAY_SIZE(iris_icc_info_vpu3x), @@ -220,7 +220,7 @@ const struct iris_platform_data sm8750_data =3D { * - different num_vpp_pipe */ const struct iris_platform_data x1p42100_data =3D { - .firmware_desc =3D &iris_vpu30_p1_gen2_desc, + .firmware_desc_gen2 =3D &iris_vpu30_p1_gen2_desc, .vpu_ops =3D &iris_vpu3_ops, .icc_tbl =3D iris_icc_info_vpu3x, .icc_tbl_size =3D ARRAY_SIZE(iris_icc_info_vpu3x), diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/= platform/qcom/iris/iris_probe.c index 81cccb756b94..5db6398433a4 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -253,8 +253,6 @@ static int iris_probe(struct platform_device *pdev) return core->irq; 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[2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5b2db9ba724sm634487e87.45.2026.07.30.16.48.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jul 2026 16:48:36 -0700 (PDT) From: Dmitry Baryshkov Date: Fri, 31 Jul 2026 02:48:24 +0300 Subject: [PATCH v9 03/19] media: iris: Skip UBWC configuration when not supported Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260731-iris-ar50lt-v9-3-d71a782001c0@oss.qualcomm.com> References: <20260731-iris-ar50lt-v9-0-d71a782001c0@oss.qualcomm.com> In-Reply-To: <20260731-iris-ar50lt-v9-0-d71a782001c0@oss.qualcomm.com> To: Vikash Garodia , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vishnu Reddy Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Dikshita Agarwal , Konrad Dybcio X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1263; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=SkhEj21efbGwh1OhN+7NneptPnsqOcydi7iGjY56ptE=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBqa+LKqIP3rXIJpdK1F4/DYlNSjb10J2CiKzkCP 26vfq2iGbmJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCamviygAKCRCLPIo+Aiko 1eXnB/9rtGaAUpkLSqm2Apz9FksXprYCvFgna3L97Qo4WnL5wZb02ctDTinYSnQ+X3PEzBC9K0p aa/ZT4BaUhi4vWxQcpvS7hzE2eGsXF6/hgUVn2nQU/obzmh8/DjoqzLraJCmqJroL3rNXG8Czxu 0FIfYR7KuD0oqDoP/uhRGtMbKmP5/7Zy2CX2pNVgwAqad0rbLUJL212zxYWmjqtVJJOsVi0R6vd XfAXPFrWwaYiZNZofTRob4lGNQdhDWZcKz2PWupnbJgf2hru1LkaV82ONQ997MZDH2eqC05legi 0JdQLgEk4CX9esFhhXJNvZKdr/z+lZE1DLuJxAcFfdngNLI3 X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzMwMDE2OCBTYWx0ZWRfX/OGCxHPOtMG8 AuHUZk/LbB9deR68/LPZ6ZqkMtRX7is1BE8epjd2eZCjmdY0UAF5DzjzjklCs13boz99dS6y/B1 YF0CQdvBe0BY2ZtOHREZ8G7x1nebIw/J0EgOlf7XLI1cxl4MVquh6819Pk7ogXmA+N7kTuEu57N 8uJ54AG0lazt+nVfIkYbVmUSCXF0QsXjjJP/D4c+NeLZ6eLyZtuH4vR7s+HU0j103SpMzfJCbpX 4ug8Gwx3aF1/X4Glh0nM6F2Qtb0HpkQKADLdhdbnMHxZ77XLo54/aekcOiBRzZaOv1uBj6ZANtw lDDNPslzpf/ZRVZYPQKIcOx9sGRNxnVqfA5Mg/wMc9itFtTiaJXOnfCHE5cyK0JQ/vQeTuKcXPt 0vb2YDt5z+Tq2eXsbzNqU5lufN1Luex1nsnrIbB1hYoh2t1rPyLVUgNHwmF+P2DqQXx8V4V3rEY bpE2lokWk7Gh3eRbOGQ== X-Proofpoint-ORIG-GUID: kkIeetm5skIVfttOPy8GLTjdlDicL3Pn X-Authority-Analysis: v=2.4 cv=Irkutr/g c=1 sm=1 tr=0 ts=6a6be2d8 cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=wrkyJH6U6m0Jdbs6q_kA:9 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-GUID: kkIeetm5skIVfttOPy8GLTjdlDicL3Pn X-Proofpoint-Spam-Info: AW1haW4tMjYwNzMwMDE2OCBTYWx0ZWRfXwJLMQEHAFJdX L90z1se3UMMa6Qvsb99hl8wJRUUTDRqUh7QXqtbRCSPoPOZ3NBF30qHsF7GqvrFqdfXTw5ENlTZ GxTKyhXRxBPHr6Or01ZpnFr33mITsJY= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-30_07,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 lowpriorityscore=0 phishscore=0 impostorscore=0 bulkscore=0 priorityscore=1501 spamscore=0 clxscore=1015 malwarescore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607300168 From: Dikshita Agarwal UBWC configuration is not applicable to all SoCs. Add a check to avoid configuring UBWC during sys init on unsupported platforms. Reviewed-by: Dmitry Baryshkov Signed-off-by: Dikshita Agarwal Reviewed-by: Vishnu Reddy Reviewed-by: Vikash Garodia Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Tested-by: Gourav Kumar --- drivers/media/platform/qcom/iris/iris_hfi_gen2_packet.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_packet.c b/driv= ers/media/platform/qcom/iris/iris_hfi_gen2_packet.c index 0d05dd2afc07..6e04175eb904 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_packet.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_packet.c @@ -140,6 +140,9 @@ void iris_hfi_gen2_packet_sys_init(struct iris_core *co= re, struct iris_hfi_heade &payload, sizeof(u32)); =20 + if (!ubwc->ubwc_enc_version) + return; + payload =3D qcom_ubwc_macrotile_mode(ubwc) ? 8 : 4; iris_hfi_gen2_create_packet(hdr, HFI_PROP_UBWC_MAX_CHANNELS, --=20 2.47.3 From nobody Fri Oct 2 14:03:53 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 42B973D810C for ; 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[2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5b2db9ba724sm634487e87.45.2026.07.30.16.48.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jul 2026 16:48:39 -0700 (PDT) From: Dmitry Baryshkov Date: Fri, 31 Jul 2026 02:48:25 +0300 Subject: [PATCH v9 04/19] media: iris: drop IRIS_FMT_foo enumeration Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260731-iris-ar50lt-v9-4-d71a782001c0@oss.qualcomm.com> References: <20260731-iris-ar50lt-v9-0-d71a782001c0@oss.qualcomm.com> In-Reply-To: <20260731-iris-ar50lt-v9-0-d71a782001c0@oss.qualcomm.com> To: Vikash Garodia , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vishnu Reddy Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Dikshita Agarwal X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4515; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=l0/lfLbQNiyyqQ8kXdTopoSs0dF+CQUlVAKRACqlzE0=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBqa+LK5KPfce2Hu7u791nJbh9RDcHPzrXZE7Blz HNcatbeQ76JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCamviygAKCRCLPIo+Aiko 1a/4CACoAadyPaTR1l1nGkXAvgHI3E5Udm74e0fsWzgxYP6ot2rytjFG7mRPWhH5GVWn3VJY+BG uf84+9P1vWltASqryj5sUI4GSRE3gKN5ObvZUhPg2ZjO9ySHVuHy82ewtorkjZUg/hVlD3+4eqk kcIyr3HRoX27XmmNeSXankDFkPcbKGyf57mlQ0FqpO793OAHGsEujC/zJgi93y+glzFVEOJza55 4q53N6o4Ac2zOUpJ/IMNyZ6gDk47IJunqE/Ac5cF/W7dB3xyT1eWw46wsmMNOmwaliqOcKtm0c6 927onb7v8ZWT/yGbZavrn3J/ESpI8Iwuy02PWtpc/DUHMgRy X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-ORIG-GUID: a86IkvdXjte-IJd0z1x1mXSBUCQHWJAt X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzMwMDE2OCBTYWx0ZWRfX2xUu2SVl1vhE 051ebl+wAUnt5vAN6AXwmPq3UCG8X9mOTDFxqd+ld8atvK/zGnzGsimDIfXxCPoUXZgYoDLoic+ 4lNX2TIe7b+2A8tiutoFLhEW7sZo9r7p0M7fEtCKiCLo0+0hlii2s82opHTMGvrpuuhpD9s08R2 Ni9myp+96LdOlQsCnAtuivkP984ziM2kTKHzReGpBchEApBB5Klhs0RJQGUYHHiXteXJ1ZtAPew OP/I0kr7Cvf3R7TYwTiT/xe26fnUrNDUUIx70at8caHCzS/fQg4C7CB6Oj2KZIW+M9flJcHFf2H 1kWEnV5CQDeQaTy8oBl1hHYTU+8jMcVT0GJY2BOyuYnQbGrGuRFcHeGylMOcq9qiO/TjU6QGmMs omJpi381qjP17wH6oHPYfZO1LWrv5MWwCR+gKacSlB5cgdOyPXf5slh9r9kTV6xrVOq1mu8k9ZW ++BEzHjEYF3Auf9nT7A== X-Proofpoint-GUID: a86IkvdXjte-IJd0z1x1mXSBUCQHWJAt X-Proofpoint-Spam-Info: AW1haW4tMjYwNzMwMDE2OCBTYWx0ZWRfX3+aH7bEtn+JI RSBz/fWFy+T33TP+PRcj1xvvf6YsohQKUsEbrjHl+PD6atodPjiJpYEP7e113Usrmz8Xu0B4l89 dcgJE3Po9N3eEfkTQ8y+3w1ncoUGSsQ= X-Authority-Analysis: v=2.4 cv=XtzK/1F9 c=1 sm=1 tr=0 ts=6a6be2da cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=Azqn4rg6zLMgtGihcfEA:9 a=QEXdDO2ut3YA:10 a=kacYvNCVWA4VmyqE58fU:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-30_07,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 malwarescore=0 impostorscore=0 priorityscore=1501 bulkscore=0 suspectscore=0 spamscore=0 adultscore=0 clxscore=1015 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607300168 The IRIS_FMT_foo defines are only used for indexing values in the format enumeration arrays. However this kind of enumeration doesn't follow the V4L2 logic (which expects an array with consequtive indexing rather than a sparse array) and complicates adding support for platforms which support different sets of formats. Drop this enumeration and use flat lists of supported formats. Reviewed-by: Vikash Garodia Reviewed-by: Vishnu Reddy Signed-off-by: Dmitry Baryshkov Tested-by: Gourav Kumar --- drivers/media/platform/qcom/iris/iris_instance.h | 14 -------------- drivers/media/platform/qcom/iris/iris_platform_vpu2.c | 6 +++--- drivers/media/platform/qcom/iris/iris_platform_vpu3x.c | 8 ++++---- drivers/media/platform/qcom/iris/iris_vdec.c | 8 ++++---- drivers/media/platform/qcom/iris/iris_venc.c | 8 ++++---- 5 files changed, 15 insertions(+), 29 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_instance.h b/drivers/med= ia/platform/qcom/iris/iris_instance.h index a770331d1675..ffdbbd20901a 100644 --- a/drivers/media/platform/qcom/iris/iris_instance.h +++ b/drivers/media/platform/qcom/iris/iris_instance.h @@ -17,20 +17,6 @@ =20 struct iris_hfi_session_ops; =20 -enum iris_fmt_type_out { - IRIS_FMT_H264, - IRIS_FMT_HEVC, - IRIS_FMT_VP9, - IRIS_FMT_AV1, -}; - -enum iris_fmt_type_cap { - IRIS_FMT_NV12, - IRIS_FMT_QC08C, - IRIS_FMT_TP10, - IRIS_FMT_QC10C, -}; - /** * struct iris_inst - holds per video instance parameters * diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c b/driver= s/media/platform/qcom/iris/iris_platform_vpu2.c index bbdbf21961d7..ee80bc5decaa 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c @@ -42,9 +42,9 @@ static const struct iris_firmware_desc iris_vpu20_p4_gen1= _desc =3D { }; =20 static const u32 iris_fmts_vpu2_dec[] =3D { - [IRIS_FMT_H264] =3D V4L2_PIX_FMT_H264, - [IRIS_FMT_HEVC] =3D V4L2_PIX_FMT_HEVC, - [IRIS_FMT_VP9] =3D V4L2_PIX_FMT_VP9, + V4L2_PIX_FMT_H264, + V4L2_PIX_FMT_HEVC, + V4L2_PIX_FMT_VP9, }; =20 static struct platform_inst_caps platform_inst_cap_vpu2 =3D { diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c b/drive= rs/media/platform/qcom/iris/iris_platform_vpu3x.c index 74626b35d9cb..7098b652c117 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c @@ -49,10 +49,10 @@ static const struct iris_firmware_desc iris_vpu35_p4_ge= n2_desc =3D { }; =20 static const u32 iris_fmts_vpu3x_dec[] =3D { - [IRIS_FMT_H264] =3D V4L2_PIX_FMT_H264, - [IRIS_FMT_HEVC] =3D V4L2_PIX_FMT_HEVC, - [IRIS_FMT_VP9] =3D V4L2_PIX_FMT_VP9, - [IRIS_FMT_AV1] =3D V4L2_PIX_FMT_AV1, + V4L2_PIX_FMT_H264, + V4L2_PIX_FMT_HEVC, + V4L2_PIX_FMT_VP9, + V4L2_PIX_FMT_AV1, }; =20 static const struct icc_info iris_icc_info_vpu3x[] =3D { diff --git a/drivers/media/platform/qcom/iris/iris_vdec.c b/drivers/media/p= latform/qcom/iris/iris_vdec.c index 7f89e745a4b1..c4d13ae58336 100644 --- a/drivers/media/platform/qcom/iris/iris_vdec.c +++ b/drivers/media/platform/qcom/iris/iris_vdec.c @@ -63,10 +63,10 @@ int iris_vdec_inst_init(struct iris_inst *inst) } =20 static const u32 iris_vdec_formats_cap[] =3D { - [IRIS_FMT_NV12] =3D V4L2_PIX_FMT_NV12, - [IRIS_FMT_QC08C] =3D V4L2_PIX_FMT_QC08C, - [IRIS_FMT_TP10] =3D V4L2_PIX_FMT_P010, - [IRIS_FMT_QC10C] =3D V4L2_PIX_FMT_QC10C, + V4L2_PIX_FMT_NV12, + V4L2_PIX_FMT_QC08C, + V4L2_PIX_FMT_P010, + V4L2_PIX_FMT_QC10C, }; =20 static bool check_format(struct iris_inst *inst, u32 pixfmt, u32 type) diff --git a/drivers/media/platform/qcom/iris/iris_venc.c b/drivers/media/p= latform/qcom/iris/iris_venc.c index a945992f63aa..16c52ad07e2c 100644 --- a/drivers/media/platform/qcom/iris/iris_venc.c +++ b/drivers/media/platform/qcom/iris/iris_venc.c @@ -80,13 +80,13 @@ int iris_venc_inst_init(struct iris_inst *inst) } =20 static const u32 iris_venc_formats_cap[] =3D { - [IRIS_FMT_H264] =3D V4L2_PIX_FMT_H264, - [IRIS_FMT_HEVC] =3D V4L2_PIX_FMT_HEVC, + V4L2_PIX_FMT_H264, + V4L2_PIX_FMT_HEVC, }; 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However, some platforms do not support UBWC which results in incorrect format capability exposure. Use the UBWC configuration provided by the platform to dynamically filter raw formats at runtime. If UBWC is not supported, UBWC-based formats are omitted from the advertised capability list, while linear formats remain available. Signed-off-by: Dikshita Agarwal Reviewed-by: Vishnu Reddy Signed-off-by: Dmitry Baryshkov Tested-by: Gourav Kumar --- drivers/media/platform/qcom/iris/iris_vdec.c | 26 ++++++++++++++++++++++--= -- drivers/media/platform/qcom/iris/iris_venc.c | 25 +++++++++++++++++++++---- 2 files changed, 43 insertions(+), 8 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_vdec.c b/drivers/media/p= latform/qcom/iris/iris_vdec.c index c4d13ae58336..0dd33ff447bb 100644 --- a/drivers/media/platform/qcom/iris/iris_vdec.c +++ b/drivers/media/platform/qcom/iris/iris_vdec.c @@ -3,6 +3,7 @@ * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights res= erved. */ =20 +#include #include #include =20 @@ -69,8 +70,14 @@ static const u32 iris_vdec_formats_cap[] =3D { V4L2_PIX_FMT_QC10C, }; =20 +static const u32 iris_vdec_formats_noubwc_cap[] =3D { + V4L2_PIX_FMT_NV12, + V4L2_PIX_FMT_P010, +}; + static bool check_format(struct iris_inst *inst, u32 pixfmt, u32 type) { + const struct qcom_ubwc_cfg_data *ubwc =3D inst->core->ubwc_cfg; unsigned int size, i; const u32 *fmt; =20 @@ -80,8 +87,13 @@ static bool check_format(struct iris_inst *inst, u32 pix= fmt, u32 type) size =3D inst->core->iris_platform_data->inst_iris_fmts_size; break; case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE: - fmt =3D iris_vdec_formats_cap; - size =3D ARRAY_SIZE(iris_vdec_formats_cap); + if (ubwc->ubwc_enc_version) { + fmt =3D iris_vdec_formats_cap; + size =3D ARRAY_SIZE(iris_vdec_formats_cap); + } else { + fmt =3D iris_vdec_formats_noubwc_cap; + size =3D ARRAY_SIZE(iris_vdec_formats_noubwc_cap); + } break; default: return false; @@ -100,6 +112,7 @@ static bool check_format(struct iris_inst *inst, u32 pi= xfmt, u32 type) =20 static u32 find_format_by_index(struct iris_inst *inst, u32 index, u32 typ= e) { + const struct qcom_ubwc_cfg_data *ubwc =3D inst->core->ubwc_cfg; unsigned int size; const u32 *fmt; =20 @@ -109,8 +122,13 @@ static u32 find_format_by_index(struct iris_inst *inst= , u32 index, u32 type) size =3D inst->core->iris_platform_data->inst_iris_fmts_size; break; case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE: - fmt =3D iris_vdec_formats_cap; - size =3D ARRAY_SIZE(iris_vdec_formats_cap); + if (ubwc->ubwc_enc_version) { + fmt =3D iris_vdec_formats_cap; + size =3D ARRAY_SIZE(iris_vdec_formats_cap); + } else { + fmt =3D iris_vdec_formats_noubwc_cap; + size =3D ARRAY_SIZE(iris_vdec_formats_noubwc_cap); + } break; default: return 0; diff --git a/drivers/media/platform/qcom/iris/iris_venc.c b/drivers/media/p= latform/qcom/iris/iris_venc.c index 16c52ad07e2c..2f2c56bf9122 100644 --- a/drivers/media/platform/qcom/iris/iris_venc.c +++ b/drivers/media/platform/qcom/iris/iris_venc.c @@ -3,6 +3,7 @@ * Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights res= erved. */ =20 +#include #include #include =20 @@ -89,15 +90,25 @@ static const u32 iris_venc_formats_out[] =3D { V4L2_PIX_FMT_QC08C, }; =20 +static const u32 iris_venc_formats_noubwc_out[] =3D { + V4L2_PIX_FMT_NV12, +}; + static bool check_format(struct iris_inst *inst, u32 pixfmt, u32 type) { + const struct qcom_ubwc_cfg_data *ubwc =3D inst->core->ubwc_cfg; unsigned int size, i; const u32 *fmt; =20 switch (type) { case V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE: - fmt =3D iris_venc_formats_out; - size =3D ARRAY_SIZE(iris_venc_formats_out); + if (ubwc->ubwc_enc_version) { + fmt =3D iris_venc_formats_out; + size =3D ARRAY_SIZE(iris_venc_formats_out); + } else { + fmt =3D iris_venc_formats_noubwc_out; + size =3D ARRAY_SIZE(iris_venc_formats_noubwc_out); + } break; case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE: fmt =3D iris_venc_formats_cap; @@ -117,13 +128,19 @@ static bool check_format(struct iris_inst *inst, u32 = pixfmt, u32 type) =20 static u32 find_format_by_index(struct iris_inst *inst, u32 index, u32 typ= e) { + const struct qcom_ubwc_cfg_data *ubwc =3D inst->core->ubwc_cfg; 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[2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5b2db9ba724sm634487e87.45.2026.07.30.16.48.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jul 2026 16:48:42 -0700 (PDT) From: Dmitry Baryshkov Date: Fri, 31 Jul 2026 02:48:27 +0300 Subject: [PATCH v9 06/19] media: iris: Introduce set_preset_register as a vpu_op Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260731-iris-ar50lt-v9-6-d71a782001c0@oss.qualcomm.com> References: <20260731-iris-ar50lt-v9-0-d71a782001c0@oss.qualcomm.com> In-Reply-To: <20260731-iris-ar50lt-v9-0-d71a782001c0@oss.qualcomm.com> To: Vikash Garodia , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vishnu Reddy Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Dikshita Agarwal X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4447; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=LLqeRAsiXvNKhG2Og2KDbIVpdb/v6/FkTza6aNnn3Bc=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBqa+LKpGKNZ+7JUcWW7TkiqapLK6iUbS79fx+Cw dg0Fid58N+JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCamviygAKCRCLPIo+Aiko 1WbSCACEClWE9ivMYeExtnvKjGXVyPTx8XCehvGjd9Unske+C55If7Dfce+NHDgcqrWsRbq4m6F d2AafODa1YvYFZxg366ryCyHL6LhMIA0iRXqB0NDAHeS5THxWF9IWuSFP21ds+BSVhHumdSs5vQ bWZClouqROuA9M0U6kb2lANndOdBxOa1vih51CFOn+CCenb3XqDQ821uZYfIWwNWrxKklIiyEa/ esijF/wO0Yu3HLiTmxdeYe49tP4vpbGuxZ/yeqL4iqxPP/lWdbGy+CQD7W/OiUhBuuX+6w41GZW 1KDh498dm5VhKpFf8B7VIT+zhlQ1ooVI6bFhiY1goIHaOY4Z X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-Spam-Info: AW1haW4tMjYwNzMwMDE2OCBTYWx0ZWRfX864WmwXCaBHg 2Q2v1iUqGIxXijHH2glKi2BWju+vS06jm4+e4m1yt8bgnQrdXkPriE9foGvTuowH703zoC2evZS UshFsxyY2cKoPU+DPDZw779atxWsMzg= X-Authority-Analysis: v=2.4 cv=evjvCIpX c=1 sm=1 tr=0 ts=6a6be2dd cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=4Uh0hlRDs2lXuULb_e4A:9 a=QEXdDO2ut3YA:10 a=kacYvNCVWA4VmyqE58fU:22 X-Proofpoint-GUID: GacFSOH6DkUM64xPXrKdHIWGSr90doOd X-Proofpoint-ORIG-GUID: GacFSOH6DkUM64xPXrKdHIWGSr90doOd X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzMwMDE2OCBTYWx0ZWRfXweuQVZcC52MZ uELje20gllqHHgKsoesC/+kVgcohWran4j8SJgQWo8pT40Brk6fPVDz1faFl+A+mmV0DyDxNVWs Ert9ezMwhe6urOsYFv0ocIqqOu40CVE9Vm1zY/BqWsXU4rwiD2aoVpCYQeH8MOgKxeno1BNaPIE ueADvBFvFBVvegx9BIrGyk0z4D6xjDXkjT0hsPSSQ0uYZeiTGqk7X+2riMB4plSvRJywhwUlqv4 b2O2vZEZhfsMkELcP2Nzxw12p6k0boo8lXGNHRPQHlF+Oa04H8QI+Tini0lZK+l1e3a4W88LoiB ZRUIW6HwEhCNGCXhHIGFuHrgQcSN224dz9fblUHRRdKwveTXY73RLCtSNKsSzUAykWNul3li9cC uSTKXB8xOZlJmP0JuNTmiwd9wxeenfN2a20+9eTUUFRG1uHSxjtonRsQhMPfXrJwzKKg197OGSx XS1BvKgpB+hxS+L6cGA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-30_07,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 spamscore=0 clxscore=1015 adultscore=0 suspectscore=0 bulkscore=0 impostorscore=0 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607300168 From: Dikshita Agarwal The set_preset_registers sequence is currently shared across all supported devices. Starting with Qualcomm QCM2290 (AR50LT), the register programming would differ. Move set_preset_register into a vpu_op to allow per-device customization. This change prepares the driver for upcoming hardware variants. No functional change so far for existing devices. Reviewed-by: Dmitry Baryshkov Signed-off-by: Dikshita Agarwal Reviewed-by: Vishnu Reddy Reviewed-by: Vikash Garodia Signed-off-by: Dmitry Baryshkov Tested-by: Gourav Kumar --- drivers/media/platform/qcom/iris/iris_vpu2.c | 1 + drivers/media/platform/qcom/iris/iris_vpu3x.c | 3 +++ drivers/media/platform/qcom/iris/iris_vpu4x.c | 1 + drivers/media/platform/qcom/iris/iris_vpu_common.c | 2 +- drivers/media/platform/qcom/iris/iris_vpu_common.h | 1 + 5 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/iris/iris_vpu2.c b/drivers/media/p= latform/qcom/iris/iris_vpu2.c index b8714dcbad10..2dc121a3f5e8 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu2.c +++ b/drivers/media/platform/qcom/iris/iris_vpu2.c @@ -45,4 +45,5 @@ const struct vpu_ops iris_vpu2_ops =3D { .power_on_controller =3D iris_vpu_power_on_controller, .calc_freq =3D iris_vpu2_calc_freq, .set_hwmode =3D iris_vpu_set_hwmode, + .set_preset_registers =3D iris_vpu_set_preset_registers, }; diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/= platform/qcom/iris/iris_vpu3x.c index 3dad47be78b5..dc02ced1b931 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c @@ -261,6 +261,7 @@ const struct vpu_ops iris_vpu3_ops =3D { .power_on_controller =3D iris_vpu_power_on_controller, .calc_freq =3D iris_vpu3x_vpu4x_calculate_frequency, .set_hwmode =3D iris_vpu_set_hwmode, + .set_preset_registers =3D iris_vpu_set_preset_registers, }; =20 const struct vpu_ops iris_vpu33_ops =3D { @@ -270,6 +271,7 @@ const struct vpu_ops iris_vpu33_ops =3D { .power_on_controller =3D iris_vpu_power_on_controller, .calc_freq =3D iris_vpu3x_vpu4x_calculate_frequency, .set_hwmode =3D iris_vpu_set_hwmode, + .set_preset_registers =3D iris_vpu_set_preset_registers, }; =20 const struct vpu_ops iris_vpu35_ops =3D { @@ -280,4 +282,5 @@ const struct vpu_ops iris_vpu35_ops =3D { .program_bootup_registers =3D iris_vpu35_vpu4x_program_bootup_registers, .calc_freq =3D iris_vpu3x_vpu4x_calculate_frequency, .set_hwmode =3D iris_vpu_set_hwmode, + .set_preset_registers =3D iris_vpu_set_preset_registers, }; diff --git a/drivers/media/platform/qcom/iris/iris_vpu4x.c b/drivers/media/= platform/qcom/iris/iris_vpu4x.c index 02e100a4045f..f608a297d4a3 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu4x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu4x.c @@ -368,4 +368,5 @@ const struct vpu_ops iris_vpu4x_ops =3D { .program_bootup_registers =3D iris_vpu35_vpu4x_program_bootup_registers, .calc_freq =3D iris_vpu3x_vpu4x_calculate_frequency, .set_hwmode =3D iris_vpu4x_set_hwmode, + .set_preset_registers =3D iris_vpu_set_preset_registers, }; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.c index e4847c107709..39adf8aa91a7 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -483,7 +483,7 @@ int iris_vpu_power_on(struct iris_core *core) =20 iris_opp_set_rate(core->dev, freq); =20 - iris_vpu_set_preset_registers(core); + core->iris_platform_data->vpu_ops->set_preset_registers(core); =20 iris_vpu_interrupt_init(core); core->intr_status =3D 0; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.h index 09799a375c14..21ed4c9bd5e3 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h @@ -22,6 +22,7 @@ struct vpu_ops { void (*program_bootup_registers)(struct iris_core *core); u64 (*calc_freq)(struct iris_inst *inst, size_t data_size); int (*set_hwmode)(struct iris_core *core); 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Starting with Qualcomm QCM2290 (AR50LT), the register programming would differ. Move interrupt_init into a vpu_op to allow per-device customization. This change prepares the driver for upcoming hardware variants. No functional change so far for existing devices. Reviewed-by: Dmitry Baryshkov Signed-off-by: Dikshita Agarwal Reviewed-by: Vikash Garodia Reviewed-by: Vishnu Reddy Signed-off-by: Dmitry Baryshkov Tested-by: Gourav Kumar --- drivers/media/platform/qcom/iris/iris_vpu2.c | 1 + drivers/media/platform/qcom/iris/iris_vpu3x.c | 3 +++ drivers/media/platform/qcom/iris/iris_vpu4x.c | 1 + drivers/media/platform/qcom/iris/iris_vpu_common.c | 4 ++-- drivers/media/platform/qcom/iris/iris_vpu_common.h | 2 ++ 5 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_vpu2.c b/drivers/media/p= latform/qcom/iris/iris_vpu2.c index 2dc121a3f5e8..dd2eeae0d9eb 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu2.c +++ b/drivers/media/platform/qcom/iris/iris_vpu2.c @@ -46,4 +46,5 @@ const struct vpu_ops iris_vpu2_ops =3D { .calc_freq =3D iris_vpu2_calc_freq, .set_hwmode =3D iris_vpu_set_hwmode, .set_preset_registers =3D iris_vpu_set_preset_registers, + .interrupt_init =3D iris_vpu_interrupt_init, }; diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/= platform/qcom/iris/iris_vpu3x.c index dc02ced1b931..c3b760730c98 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c @@ -262,6 +262,7 @@ const struct vpu_ops iris_vpu3_ops =3D { .calc_freq =3D iris_vpu3x_vpu4x_calculate_frequency, .set_hwmode =3D iris_vpu_set_hwmode, .set_preset_registers =3D iris_vpu_set_preset_registers, + .interrupt_init =3D iris_vpu_interrupt_init, }; =20 const struct vpu_ops iris_vpu33_ops =3D { @@ -272,6 +273,7 @@ const struct vpu_ops iris_vpu33_ops =3D { .calc_freq =3D iris_vpu3x_vpu4x_calculate_frequency, .set_hwmode =3D iris_vpu_set_hwmode, .set_preset_registers =3D iris_vpu_set_preset_registers, + .interrupt_init =3D iris_vpu_interrupt_init, }; =20 const struct vpu_ops iris_vpu35_ops =3D { @@ -283,4 +285,5 @@ const struct vpu_ops iris_vpu35_ops =3D { .calc_freq =3D iris_vpu3x_vpu4x_calculate_frequency, .set_hwmode =3D iris_vpu_set_hwmode, .set_preset_registers =3D iris_vpu_set_preset_registers, + .interrupt_init =3D iris_vpu_interrupt_init, }; diff --git a/drivers/media/platform/qcom/iris/iris_vpu4x.c b/drivers/media/= platform/qcom/iris/iris_vpu4x.c index f608a297d4a3..90ccdc0d2a07 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu4x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu4x.c @@ -369,4 +369,5 @@ const struct vpu_ops iris_vpu4x_ops =3D { .calc_freq =3D iris_vpu3x_vpu4x_calculate_frequency, .set_hwmode =3D iris_vpu4x_set_hwmode, .set_preset_registers =3D iris_vpu_set_preset_registers, + .interrupt_init =3D iris_vpu_interrupt_init, }; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.c index 39adf8aa91a7..9a89e8ae06ce 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -31,7 +31,7 @@ #define UC_REGION_ADDR (CPU_CS_BASE_OFFS + 0x64) #define UC_REGION_SIZE (CPU_CS_BASE_OFFS + 0x68) =20 -static void iris_vpu_interrupt_init(struct iris_core *core) +void iris_vpu_interrupt_init(struct iris_core *core) { u32 mask_val; =20 @@ -485,7 +485,7 @@ int iris_vpu_power_on(struct iris_core *core) =20 core->iris_platform_data->vpu_ops->set_preset_registers(core); =20 - iris_vpu_interrupt_init(core); + core->iris_platform_data->vpu_ops->interrupt_init(core); core->intr_status =3D 0; enable_irq(core->irq); =20 diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.h index 21ed4c9bd5e3..9151545065cd 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h @@ -23,6 +23,7 @@ struct vpu_ops { u64 (*calc_freq)(struct iris_inst *inst, size_t data_size); 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In preparation of adding support for AR50LT platforms, add an optional disable_arp callback to the VPU ops and invoke it from core init and resume paths. No functional change for existing platforms. Reviewed-by: Dmitry Baryshkov Signed-off-by: Dikshita Agarwal Reviewed-by: Vishnu Reddy Reviewed-by: Vikash Garodia Signed-off-by: Dmitry Baryshkov Tested-by: Gourav Kumar --- drivers/media/platform/qcom/iris/iris_core.c | 4 ++++ drivers/media/platform/qcom/iris/iris_hfi_common.c | 4 ++++ drivers/media/platform/qcom/iris/iris_vpu_common.h | 1 + 3 files changed, 9 insertions(+) diff --git a/drivers/media/platform/qcom/iris/iris_core.c b/drivers/media/p= latform/qcom/iris/iris_core.c index 676baa8087a8..d558475986ff 100644 --- a/drivers/media/platform/qcom/iris/iris_core.c +++ b/drivers/media/platform/qcom/iris/iris_core.c @@ -52,6 +52,7 @@ static int iris_wait_for_system_response(struct iris_core= *core) =20 int iris_core_init(struct iris_core *core) { + const struct vpu_ops *vpu_ops =3D core->iris_platform_data->vpu_ops; int ret; =20 mutex_lock(&core->lock); @@ -85,6 +86,9 @@ int iris_core_init(struct iris_core *core) if (ret) goto error_unload_fw; =20 + if (vpu_ops->disable_arp) + vpu_ops->disable_arp(core); + core->iris_firmware_data->init_hfi_ops(core); iris_session_init_caps(core); =20 diff --git a/drivers/media/platform/qcom/iris/iris_hfi_common.c b/drivers/m= edia/platform/qcom/iris/iris_hfi_common.c index 8769ec61f117..8f04f3793d9a 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_common.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_common.c @@ -144,6 +144,7 @@ int iris_hfi_pm_suspend(struct iris_core *core) =20 int iris_hfi_pm_resume(struct iris_core *core) { + const struct vpu_ops *vpu_ops =3D core->iris_platform_data->vpu_ops; const struct iris_hfi_sys_ops *ops =3D core->hfi_sys_ops; int ret; =20 @@ -163,6 +164,9 @@ int iris_hfi_pm_resume(struct iris_core *core) if (ret) goto err_suspend_hw; =20 + if (vpu_ops->disable_arp) + vpu_ops->disable_arp(core); + ret =3D ops->sys_interframe_powercollapse(core); if (ret) goto err_suspend_hw; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.h index 9151545065cd..71d96921ed37 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h @@ -24,6 +24,7 @@ struct vpu_ops { int (*set_hwmode)(struct iris_core *core); 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In preparation for adding AR50LT support in subsequent patches, introduce a platform data field, wd_intr_mask, to capture the watchdog interrupt bitmask per platform. Signed-off-by: Dikshita Agarwal Reviewed-by: Vishnu Reddy Reviewed-by: Vikash Garodia Signed-off-by: Dmitry Baryshkov Tested-by: Gourav Kumar --- drivers/media/platform/qcom/iris/iris_platform_common.h | 1 + drivers/media/platform/qcom/iris/iris_platform_vpu2.c | 4 ++++ drivers/media/platform/qcom/iris/iris_platform_vpu3x.c | 7 +++++++ drivers/media/platform/qcom/iris/iris_vpu_common.c | 8 +++++--- drivers/media/platform/qcom/iris/iris_vpu_register_defines.h | 1 - 5 files changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 974809509146..a35b487b50ee 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -318,6 +318,7 @@ struct iris_platform_data { u32 tz_cp_config_data_size; u32 num_vpp_pipe; bool no_aon; + u32 wd_intr_mask; u32 max_session_count; /* max number of macroblocks per frame supported */ u32 max_core_mbpf; diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c b/driver= s/media/platform/qcom/iris/iris_platform_vpu2.c index ee80bc5decaa..562ff0d6716b 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c @@ -17,6 +17,8 @@ #include "iris_platform_sc7280.h" #include "iris_platform_sm8250.h" =20 +#define WRAPPER_INTR_STATUS_A2HWD_BMSK BIT(3) + static const struct iris_firmware_desc iris_milos_desc =3D { .firmware_data =3D &iris_hfi_milos_data, .get_vpu_buffer_size =3D iris_vpu_buf_size, @@ -129,6 +131,7 @@ const struct iris_platform_data sc7280_data =3D { .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_vpu2), .num_vpp_pipe =3D 1, .no_aon =3D true, + .wd_intr_mask =3D WRAPPER_INTR_STATUS_A2HWD_BMSK, .max_session_count =3D 16, .max_core_mbpf =3D 4096 * 2176 / 256 * 2 + 1920 * 1088 / 256, /* max spec for SC7280 is 4096x2176@60fps */ @@ -159,6 +162,7 @@ const struct iris_platform_data sm8250_data =3D { .tz_cp_config_data =3D tz_cp_config_vpu2, .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_vpu2), .num_vpp_pipe =3D 4, + .wd_intr_mask =3D WRAPPER_INTR_STATUS_A2HWD_BMSK, .max_session_count =3D 16, .max_core_mbpf =3D NUM_MBS_8K, .max_core_mbps =3D ((7680 * 4320) / 256) * 60, diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c b/drive= rs/media/platform/qcom/iris/iris_platform_vpu3x.c index 7098b652c117..eeedde8fc9ce 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c @@ -18,6 +18,8 @@ #include "iris_platform_sm8750.h" #include "iris_platform_x1p42100.h" =20 +#define WRAPPER_INTR_STATUS_A2HWD_BMSK BIT(3) + static const struct iris_firmware_desc iris_vpu30_p4_s6_gen2_desc =3D { .firmware_data =3D &iris_hfi_gen2_data, .get_vpu_buffer_size =3D iris_vpu_buf_size, @@ -113,6 +115,7 @@ const struct iris_platform_data qcs8300_data =3D { .tz_cp_config_data =3D tz_cp_config_vpu3, .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_vpu3), .num_vpp_pipe =3D 2, + .wd_intr_mask =3D WRAPPER_INTR_STATUS_A2HWD_BMSK, .max_session_count =3D 16, .max_core_mbpf =3D ((4096 * 2176) / 256) * 4, .max_core_mbps =3D (((3840 * 2176) / 256) * 120), @@ -142,6 +145,7 @@ const struct iris_platform_data sm8550_data =3D { .tz_cp_config_data =3D tz_cp_config_vpu3, .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_vpu3), .num_vpp_pipe =3D 4, + .wd_intr_mask =3D WRAPPER_INTR_STATUS_A2HWD_BMSK, .max_session_count =3D 16, .max_core_mbpf =3D NUM_MBS_8K * 2, .max_core_mbps =3D ((7680 * 4320) / 256) * 60, @@ -179,6 +183,7 @@ const struct iris_platform_data sm8650_data =3D { .tz_cp_config_data =3D tz_cp_config_vpu3, .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_vpu3), .num_vpp_pipe =3D 4, + .wd_intr_mask =3D WRAPPER_INTR_STATUS_A2HWD_BMSK, .max_session_count =3D 16, .max_core_mbpf =3D NUM_MBS_8K * 2, .max_core_mbps =3D ((7680 * 4320) / 256) * 60, @@ -208,6 +213,7 @@ const struct iris_platform_data sm8750_data =3D { .tz_cp_config_data =3D tz_cp_config_vpu3, .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_vpu3), .num_vpp_pipe =3D 4, + .wd_intr_mask =3D WRAPPER_INTR_STATUS_A2HWD_BMSK, .max_session_count =3D 16, .max_core_mbpf =3D NUM_MBS_8K * 2, .max_core_mbps =3D ((7680 * 4320) / 256) * 60, @@ -243,6 +249,7 @@ const struct iris_platform_data x1p42100_data =3D { .tz_cp_config_data =3D tz_cp_config_vpu3, .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_vpu3), .num_vpp_pipe =3D 1, + .wd_intr_mask =3D WRAPPER_INTR_STATUS_A2HWD_BMSK, .max_session_count =3D 16, .max_core_mbpf =3D NUM_MBS_8K * 2, .max_core_mbps =3D ((7680 * 4320) / 256) * 60, diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.c index 9a89e8ae06ce..3fa1a3cd4de9 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -109,11 +109,11 @@ void iris_vpu_raise_interrupt(struct iris_core *core) =20 void iris_vpu_clear_interrupt(struct iris_core *core) { + u32 wd_intr_mask =3D core->iris_platform_data->wd_intr_mask; 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This requirement is due to QSB (Qualcomm System Bus) 128b to QNS ( Qualcomm Network Switch) 256b conversion at video noc in AR50LT which is not needed for other IRIS cores. In preparation of adding support for AR50LT core, introduce platform-configurable IB multiplier and enable IB voting for all SoCs. Existing platforms default to IB =3D=3D AB, while AR50LT requires 2x peak bandwidth. Signed-off-by: Dikshita Agarwal Reviewed-by: Vikash Garodia Reviewed-by: Vishnu Reddy Signed-off-by: Dmitry Baryshkov Tested-by: Gourav Kumar --- drivers/media/platform/qcom/iris/iris_platform_common.h | 1 + drivers/media/platform/qcom/iris/iris_platform_vpu2.c | 2 ++ drivers/media/platform/qcom/iris/iris_platform_vpu3x.c | 5 +++++ drivers/media/platform/qcom/iris/iris_resources.c | 2 ++ 4 files changed, 10 insertions(+) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index a35b487b50ee..4246c2dc5cd4 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -319,6 +319,7 @@ struct iris_platform_data { u32 num_vpp_pipe; bool no_aon; u32 wd_intr_mask; + u32 icc_ib_multiplier; u32 max_session_count; /* max number of macroblocks per frame supported */ u32 max_core_mbpf; diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c b/driver= s/media/platform/qcom/iris/iris_platform_vpu2.c index 562ff0d6716b..e594c7a25db3 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c @@ -132,6 +132,7 @@ const struct iris_platform_data sc7280_data =3D { .num_vpp_pipe =3D 1, .no_aon =3D true, .wd_intr_mask =3D WRAPPER_INTR_STATUS_A2HWD_BMSK, + .icc_ib_multiplier =3D 1, .max_session_count =3D 16, .max_core_mbpf =3D 4096 * 2176 / 256 * 2 + 1920 * 1088 / 256, /* max spec for SC7280 is 4096x2176@60fps */ @@ -163,6 +164,7 @@ const struct iris_platform_data sm8250_data =3D { .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_vpu2), .num_vpp_pipe =3D 4, .wd_intr_mask =3D WRAPPER_INTR_STATUS_A2HWD_BMSK, + .icc_ib_multiplier =3D 1, .max_session_count =3D 16, .max_core_mbpf =3D NUM_MBS_8K, .max_core_mbps =3D ((7680 * 4320) / 256) * 60, diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c b/drive= rs/media/platform/qcom/iris/iris_platform_vpu3x.c index eeedde8fc9ce..b8099d7ce556 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c @@ -116,6 +116,7 @@ const struct iris_platform_data qcs8300_data =3D { .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_vpu3), .num_vpp_pipe =3D 2, .wd_intr_mask =3D WRAPPER_INTR_STATUS_A2HWD_BMSK, + .icc_ib_multiplier =3D 1, .max_session_count =3D 16, .max_core_mbpf =3D ((4096 * 2176) / 256) * 4, .max_core_mbps =3D (((3840 * 2176) / 256) * 120), @@ -146,6 +147,7 @@ const struct iris_platform_data sm8550_data =3D { .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_vpu3), .num_vpp_pipe =3D 4, .wd_intr_mask =3D WRAPPER_INTR_STATUS_A2HWD_BMSK, + .icc_ib_multiplier =3D 1, .max_session_count =3D 16, .max_core_mbpf =3D NUM_MBS_8K * 2, .max_core_mbps =3D ((7680 * 4320) / 256) * 60, @@ -184,6 +186,7 @@ const struct iris_platform_data sm8650_data =3D { .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_vpu3), .num_vpp_pipe =3D 4, .wd_intr_mask =3D WRAPPER_INTR_STATUS_A2HWD_BMSK, + .icc_ib_multiplier =3D 1, .max_session_count =3D 16, .max_core_mbpf =3D NUM_MBS_8K * 2, .max_core_mbps =3D ((7680 * 4320) / 256) * 60, @@ -214,6 +217,7 @@ const struct iris_platform_data sm8750_data =3D { .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_vpu3), .num_vpp_pipe =3D 4, .wd_intr_mask =3D WRAPPER_INTR_STATUS_A2HWD_BMSK, + .icc_ib_multiplier =3D 1, .max_session_count =3D 16, .max_core_mbpf =3D NUM_MBS_8K * 2, .max_core_mbps =3D ((7680 * 4320) / 256) * 60, @@ -250,6 +254,7 @@ const struct iris_platform_data x1p42100_data =3D { .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_vpu3), .num_vpp_pipe =3D 1, .wd_intr_mask =3D WRAPPER_INTR_STATUS_A2HWD_BMSK, + .icc_ib_multiplier =3D 1, .max_session_count =3D 16, .max_core_mbpf =3D NUM_MBS_8K * 2, .max_core_mbps =3D ((7680 * 4320) / 256) * 60, diff --git a/drivers/media/platform/qcom/iris/iris_resources.c b/drivers/me= dia/platform/qcom/iris/iris_resources.c index 2c4d34c7bd77..883ef7e75291 100644 --- a/drivers/media/platform/qcom/iris/iris_resources.c +++ b/drivers/media/platform/qcom/iris/iris_resources.c @@ -18,6 +18,7 @@ =20 int iris_set_icc_bw(struct iris_core *core, unsigned long icc_bw) { + u32 icc_ib_multiplier =3D core->iris_platform_data->icc_ib_multiplier; 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Tables for AR50LT won't have corresponding entry in the capability tables. Let iris_set_pipe() silently skip propgramming the property if there is no corresponding capability. Reviewed-by: Vishnu Reddy Reviewed-by: Vikash Garodia Signed-off-by: Dmitry Baryshkov Tested-by: Gourav Kumar --- drivers/media/platform/qcom/iris/iris_ctrls.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/media/platform/qcom/iris/iris_ctrls.c b/drivers/media/= platform/qcom/iris/iris_ctrls.c index bf17d310eac0..cdd02328cb71 100644 --- a/drivers/media/platform/qcom/iris/iris_ctrls.c +++ b/drivers/media/platform/qcom/iris/iris_ctrls.c @@ -538,6 +538,9 @@ int iris_set_pipe(struct iris_inst *inst, enum platform= _inst_fw_cap_type cap_id) u32 work_route =3D inst->fw_caps[PIPE].value; u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; =20 + if (!hfi_id) + return 0; + return hfi_ops->session_set_property(inst, hfi_id, HFI_HOST_FLAGS_NONE, iris_get_port_info(inst, cap_id), --=20 2.47.3 From nobody Fri Oct 2 14:03:53 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D31FB414A15 for ; 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Add register handling for ar50lt by hooking up vpu op with ar50lt specific implemtation or resue from earlier generation wherever feasible. Signed-off-by: Dikshita Agarwal Reviewed-by: Vishnu Reddy Reviewed-by: Vikash Garodia Signed-off-by: Dmitry Baryshkov Tested-by: Gourav Kumar --- drivers/media/platform/qcom/iris/Makefile | 1 + .../platform/qcom/iris/iris_platform_common.h | 2 + drivers/media/platform/qcom/iris/iris_vpu2.c | 28 +---- drivers/media/platform/qcom/iris/iris_vpu_ar50lt.c | 130 +++++++++++++++++= ++++ drivers/media/platform/qcom/iris/iris_vpu_common.c | 29 ++++- drivers/media/platform/qcom/iris/iris_vpu_common.h | 2 + 6 files changed, 164 insertions(+), 28 deletions(-) diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/plat= form/qcom/iris/Makefile index 48e415cbc439..f1b204b95694 100644 --- a/drivers/media/platform/qcom/iris/Makefile +++ b/drivers/media/platform/qcom/iris/Makefile @@ -26,6 +26,7 @@ qcom-iris-objs +=3D iris_buffer.o \ iris_vpu2.o \ iris_vpu3x.o \ iris_vpu4x.o \ + iris_vpu_ar50lt.o \ iris_vpu_buffer.o \ iris_vpu_common.o \ =20 diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 4246c2dc5cd4..4ed0709ec381 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -76,6 +76,7 @@ enum platform_clk_type { IRIS_VPP0_HW_CLK, IRIS_VPP1_HW_CLK, IRIS_APV_HW_CLK, + IRIS_THROTTLE_CLK, }; =20 struct platform_clk_data { @@ -318,6 +319,7 @@ struct iris_platform_data { u32 tz_cp_config_data_size; u32 num_vpp_pipe; bool no_aon; + bool no_rpmh; u32 wd_intr_mask; u32 icc_ib_multiplier; u32 max_session_count; diff --git a/drivers/media/platform/qcom/iris/iris_vpu2.c b/drivers/media/p= latform/qcom/iris/iris_vpu2.c index dd2eeae0d9eb..5419a5096b00 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu2.c +++ b/drivers/media/platform/qcom/iris/iris_vpu2.c @@ -12,38 +12,12 @@ =20 #include "iris_vpu_register_defines.h" =20 -static u64 iris_vpu2_calc_freq(struct iris_inst *inst, size_t data_size) -{ - struct platform_inst_caps *caps =3D inst->core->iris_platform_data->inst_= caps; - struct v4l2_format *inp_f =3D inst->fmt_src; - u32 mbs_per_second, mbpf, height, width; - unsigned long vpp_freq, vsp_freq; - u32 fps =3D inst->frame_rate; - - width =3D max(inp_f->fmt.pix_mp.width, inst->crop.width); - height =3D max(inp_f->fmt.pix_mp.height, inst->crop.height); - - mbpf =3D NUM_MBS_PER_FRAME(height, width); - mbs_per_second =3D mbpf * fps; - - vpp_freq =3D mbs_per_second * caps->mb_cycles_vpp; - - /* 21 / 20 is overhead factor */ - vpp_freq +=3D vpp_freq / 20; - vsp_freq =3D mbs_per_second * caps->mb_cycles_vsp; - - /* 10 / 7 is overhead factor */ - vsp_freq +=3D ((fps * data_size * 8) * 10) / 7; - - return max(vpp_freq, vsp_freq); -} - const struct vpu_ops iris_vpu2_ops =3D { .power_off_hw =3D iris_vpu_power_off_hw, .power_on_hw =3D iris_vpu_power_on_hw, .power_off_controller =3D iris_vpu_power_off_controller, .power_on_controller =3D iris_vpu_power_on_controller, - .calc_freq =3D iris_vpu2_calc_freq, + .calc_freq =3D iris_vpu2_calculate_frequency, .set_hwmode =3D iris_vpu_set_hwmode, .set_preset_registers =3D iris_vpu_set_preset_registers, .interrupt_init =3D iris_vpu_interrupt_init, diff --git a/drivers/media/platform/qcom/iris/iris_vpu_ar50lt.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_ar50lt.c new file mode 100644 index 000000000000..e084a5b49f2e --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_vpu_ar50lt.c @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2026 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include + +#include "iris_instance.h" +#include "iris_vpu_common.h" + +#include "iris_vpu_register_defines.h" + +#define WRAPPER_INTR_MASK_A2HVCODEC_BMSK_AR50LT BIT(3) + +#define WRAPPER_VCODEC0_CLOCK_CONFIG_AR50LT 0xb0080 + +#define CPU_CS_VCICMD 0xa0020 +#define CPU_CS_VCICMD_ARP_OFF 0x1 + +static void iris_vpu_ar50lt_set_preset_registers(struct iris_core *core) +{ + writel(0x0, core->reg_base + WRAPPER_VCODEC0_CLOCK_CONFIG_AR50LT); +} + +static void iris_vpu_ar50lt_interrupt_init(struct iris_core *core) +{ + writel(WRAPPER_INTR_MASK_A2HVCODEC_BMSK_AR50LT, core->reg_base + WRAPPER_= INTR_MASK); +} + +static void iris_vpu_ar50lt_disable_arp(struct iris_core *core) +{ + writel(CPU_CS_VCICMD_ARP_OFF, core->reg_base + CPU_CS_VCICMD); +} + +static int iris_vpu_ar50lt_power_off_controller(struct iris_core *core) +{ + iris_disable_unprepare_clock(core, IRIS_AHB_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_CLK); + iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_PO= WER_DOMAIN]); + + return 0; +} + +static void iris_vpu_ar50lt_power_off_hw(struct iris_core *core) +{ + dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]= , false); + iris_disable_unprepare_clock(core, IRIS_THROTTLE_CLK); + iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK); + iris_disable_unprepare_clock(core, IRIS_HW_CLK); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWE= R_DOMAIN]); +} + +static int iris_vpu_ar50lt_power_on_controller(struct iris_core *core) +{ + int ret; + + ret =3D iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_= CTRL_POWER_DOMAIN]); + if (ret) + return ret; + + ret =3D iris_prepare_enable_clock(core, IRIS_CTRL_CLK); + if (ret) + goto err_disable_power; + + ret =3D iris_prepare_enable_clock(core, IRIS_AXI_CLK); + if (ret && ret !=3D -ENOENT) + goto err_disable_ctrl_clock; + + ret =3D iris_prepare_enable_clock(core, IRIS_AHB_CLK); + if (ret) + goto err_disable_axi_clock; + + return 0; + +err_disable_axi_clock: + iris_disable_unprepare_clock(core, IRIS_AXI_CLK); +err_disable_ctrl_clock: + iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); +err_disable_power: + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_PO= WER_DOMAIN]); + + return ret; +} + +static int iris_vpu_ar50lt_power_on_hw(struct iris_core *core) +{ + int ret; + + ret =3D iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_= HW_POWER_DOMAIN]); + if (ret) + return ret; + + ret =3D iris_prepare_enable_clock(core, IRIS_HW_CLK); + if (ret) + goto err_disable_power; + + ret =3D iris_prepare_enable_clock(core, IRIS_HW_AHB_CLK); + if (ret) + goto err_disable_hw_clock; + + ret =3D iris_prepare_enable_clock(core, IRIS_THROTTLE_CLK); + if (ret) + goto err_disable_hw_ahb_clock; + + return 0; + +err_disable_hw_ahb_clock: + iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK); +err_disable_hw_clock: + iris_disable_unprepare_clock(core, IRIS_HW_CLK); +err_disable_power: + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWE= R_DOMAIN]); + + return ret; +} + +const struct vpu_ops iris_vpu_ar50lt_ops =3D { + .power_off_hw =3D iris_vpu_ar50lt_power_off_hw, + .power_on_hw =3D iris_vpu_ar50lt_power_on_hw, + .power_off_controller =3D iris_vpu_ar50lt_power_off_controller, + .power_on_controller =3D iris_vpu_ar50lt_power_on_controller, + .calc_freq =3D iris_vpu2_calculate_frequency, + .set_hwmode =3D iris_vpu_set_hwmode, + .set_preset_registers =3D iris_vpu_ar50lt_set_preset_registers, + .interrupt_init =3D iris_vpu_ar50lt_interrupt_init, + .disable_arp =3D iris_vpu_ar50lt_disable_arp, +}; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.c index 3fa1a3cd4de9..606f5e1ad7aa 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -97,7 +97,8 @@ int iris_vpu_boot_firmware(struct iris_core *core) } =20 writel(HOST2XTENSA_INTR_ENABLE, core->reg_base + CPU_CS_H2XSOFTINTEN); - writel(0x0, core->reg_base + CPU_CS_X2RPMH); + if (!core->iris_platform_data->no_rpmh) + writel(0x0, core->reg_base + CPU_CS_X2RPMH); =20 return 0; } @@ -422,6 +423,32 @@ void iris_vpu35_vpu4x_program_bootup_registers(struct = iris_core *core) writel(0x1, core->reg_base + WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0); } =20 +u64 iris_vpu2_calculate_frequency(struct iris_inst *inst, size_t data_size) +{ + struct platform_inst_caps *caps =3D inst->core->iris_platform_data->inst_= caps; + struct v4l2_format *inp_f =3D inst->fmt_src; + u32 mbs_per_second, mbpf, height, width; + unsigned long vpp_freq, vsp_freq; + u32 fps =3D inst->frame_rate; + + width =3D max(inp_f->fmt.pix_mp.width, inst->crop.width); + height =3D max(inp_f->fmt.pix_mp.height, inst->crop.height); + + mbpf =3D NUM_MBS_PER_FRAME(height, width); + mbs_per_second =3D mbpf * fps; + + vpp_freq =3D mbs_per_second * caps->mb_cycles_vpp; + + /* 21 / 20 is overhead factor */ + vpp_freq +=3D vpp_freq / 20; + vsp_freq =3D mbs_per_second * caps->mb_cycles_vsp; + + /* 10 / 7 is overhead factor */ + vsp_freq +=3D ((fps * data_size * 8) * 10) / 7; + + return max(vpp_freq, vsp_freq); +} + u64 iris_vpu3x_vpu4x_calculate_frequency(struct iris_inst *inst, size_t da= ta_size) { struct platform_inst_caps *caps =3D inst->core->iris_platform_data->inst_= caps; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.h index 71d96921ed37..a62b6184bde7 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h @@ -13,6 +13,7 @@ extern const struct vpu_ops iris_vpu3_ops; extern const struct vpu_ops iris_vpu33_ops; extern const struct vpu_ops iris_vpu35_ops; extern const struct vpu_ops iris_vpu4x_ops; +extern const struct vpu_ops iris_vpu_ar50lt_ops; =20 struct vpu_ops { void (*power_off_hw)(struct iris_core *core); @@ -40,6 +41,7 @@ int iris_vpu_power_on(struct iris_core *core); int iris_vpu_power_off_controller(struct iris_core *core); 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Implement minimal support for querying the properties from the firmware. It is used by one of the following patches, adding support for Agatti. Reviewed-by: Vikash Garodia Reviewed-by: Vishnu Reddy Signed-off-by: Dmitry Baryshkov Tested-by: Gourav Kumar --- drivers/media/platform/qcom/iris/iris_hfi_common.h | 1 + .../platform/qcom/iris/iris_hfi_gen1_command.c | 21 +++++++++++++++++= ++++ .../platform/qcom/iris/iris_hfi_gen1_defines.h | 15 +++++++++++++++ .../platform/qcom/iris/iris_hfi_gen1_response.c | 6 ++++++ 4 files changed, 43 insertions(+) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_common.h b/drivers/m= edia/platform/qcom/iris/iris_hfi_common.h index a27447eb2519..16099f9a25b6 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_common.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_common.h @@ -121,6 +121,7 @@ struct iris_hfi_session_ops { int (*session_set_property)(struct iris_inst *inst, u32 packet_type, u32 flag, u32 plane, u32 payload_type, void *payload, u32 payload_size); + int (*session_get_property)(struct iris_inst *inst, u32 packet_type); int (*session_open)(struct iris_inst *inst); int (*session_start)(struct iris_inst *inst, u32 plane); int (*session_queue_buf)(struct iris_inst *inst, struct iris_buffer *buff= er); diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen1_command.c index f6e9cbfccd09..5650645f9f65 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c @@ -1120,10 +1120,31 @@ static int iris_hfi_gen1_session_set_config_params(= struct iris_inst *inst, u32 p return 0; } =20 +static int iris_hfi_gen1_session_get_property(struct iris_inst *inst, u32 = packet_type) +{ + struct hfi_session_get_property_pkt pkt; + int ret; + + pkt.shdr.hdr.size =3D sizeof(pkt); + pkt.shdr.hdr.pkt_type =3D HFI_CMD_SESSION_GET_PROPERTY; + pkt.shdr.session_id =3D inst->session_id; + pkt.num_properties =3D 1; + pkt.data =3D packet_type; + + reinit_completion(&inst->completion); + + ret =3D iris_hfi_queue_cmd_write(inst->core, &pkt, pkt.shdr.hdr.size); + if (ret) + return ret; + + return iris_wait_for_session_response(inst, false); +} + static const struct iris_hfi_session_ops iris_hfi_gen1_session_ops =3D { .session_open =3D iris_hfi_gen1_session_open, .session_set_config_params =3D iris_hfi_gen1_session_set_config_params, .session_set_property =3D iris_hfi_gen1_session_set_property, + .session_get_property =3D iris_hfi_gen1_session_get_property, .session_start =3D iris_hfi_gen1_session_start, .session_queue_buf =3D iris_hfi_gen1_session_queue_buffer, .session_release_buf =3D iris_hfi_gen1_session_unset_buffers, diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_defines.h b/dri= vers/media/platform/qcom/iris/iris_hfi_gen1_defines.h index 275f3fea3d2a..6981e6e84fd8 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_defines.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_defines.h @@ -35,6 +35,7 @@ #define HFI_CMD_SESSION_EMPTY_BUFFER 0x211004 #define HFI_CMD_SESSION_FILL_BUFFER 0x211005 #define HFI_CMD_SESSION_FLUSH 0x211008 +#define HFI_CMD_SESSION_GET_PROPERTY 0x211009 #define HFI_CMD_SESSION_RELEASE_BUFFERS 0x21100b #define HFI_CMD_SESSION_RELEASE_RESOURCES 0x21100c #define HFI_CMD_SESSION_CONTINUE 0x21100d @@ -113,6 +114,7 @@ #define HFI_MSG_SESSION_FLUSH 0x221006 #define HFI_MSG_SESSION_EMPTY_BUFFER 0x221007 #define HFI_MSG_SESSION_FILL_BUFFER 0x221008 +#define HFI_MSG_SESSION_PROPERTY_INFO 0x221009 #define HFI_MSG_SESSION_RELEASE_RESOURCES 0x22100a #define HFI_MSG_SESSION_RELEASE_BUFFERS 0x22100c =20 @@ -206,6 +208,12 @@ struct hfi_session_set_property_pkt { u32 data[]; }; =20 +struct hfi_session_get_property_pkt { + struct hfi_session_hdr_pkt shdr; + u32 num_properties; + u32 data; +}; + struct hfi_sys_pc_prep_pkt { struct hfi_pkt_hdr hdr; }; @@ -575,6 +583,13 @@ struct hfi_msg_session_fbd_uncompressed_plane0_pkt { u32 data[]; }; =20 +struct hfi_msg_session_property_info_pkt { + struct hfi_session_hdr_pkt shdr; + u32 num_properties; + u32 property; + u8 data[]; +}; + struct hfi_msg_session_release_buffers_done_pkt { struct hfi_msg_session_hdr_pkt shdr; u32 num_buffers; diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c b/dr= ivers/media/platform/qcom/iris/iris_hfi_gen1_response.c index bfd7495bf44f..23fc7194b1e3 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c @@ -591,6 +591,10 @@ static const struct iris_hfi_gen1_response_pkt_info pk= t_infos[] =3D { .pkt =3D HFI_MSG_SESSION_RELEASE_BUFFERS, .pkt_sz =3D sizeof(struct hfi_msg_session_release_buffers_done_pkt), }, + { + .pkt =3D HFI_MSG_SESSION_PROPERTY_INFO, + .pkt_sz =3D sizeof(struct hfi_msg_session_property_info_pkt), + }, }; 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Implement corresponding functionality updating buffers data. This will be used for upcoming support of AR50Lt platforms with Gen1 firmware. Reviewed-by: Vikash Garodia Signed-off-by: Dmitry Baryshkov Tested-by: Gourav Kumar --- .../platform/qcom/iris/iris_hfi_gen1_response.c | 76 ++++++++++++++++++= +++- 1 file changed, 75 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c b/dr= ivers/media/platform/qcom/iris/iris_hfi_gen1_response.c index 23fc7194b1e3..7ad6f0bb4677 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c @@ -533,6 +533,80 @@ static void iris_hfi_gen1_session_ftb_done(struct iris= _inst *inst, void *packet) dev_err(core->dev, "error in ftb done\n"); } =20 +static enum iris_buffer_type iris_hfi_gen1_buf_type(struct iris_inst *inst= , u32 type) +{ + switch (type) { + case HFI_BUFFER_INPUT: + return BUF_INPUT; + case HFI_BUFFER_OUTPUT: + if (iris_split_mode_enabled(inst)) + return BUF_DPB; + return BUF_OUTPUT; + case HFI_BUFFER_OUTPUT2: + if (iris_split_mode_enabled(inst)) + return BUF_OUTPUT; + return BUF_DPB; + case HFI_BUFFER_INTERNAL_PERSIST_1: + return BUF_PERSIST; + case HFI_BUFFER_INTERNAL_SCRATCH: + return BUF_BIN; + case HFI_BUFFER_INTERNAL_SCRATCH_1: + return BUF_SCRATCH_1; + case HFI_BUFFER_INTERNAL_SCRATCH_2: + return BUF_SCRATCH_2; + case HFI_BUFFER_INTERNAL_PERSIST: + return BUF_ARP; + default: + return BUF_TYPE_MAX; + } +} + +static void iris_hfi_gen1_session_buffer_requirements(struct iris_inst *in= st, + void *data, size_t size) +{ + struct hfi_buffer_requirements *req; + + if (!size || size % sizeof(*req)) + return; + + for (req =3D data; size; size -=3D sizeof(*req), req++) { + enum iris_buffer_type type =3D iris_hfi_gen1_buf_type(inst, req->type); + + if (type =3D=3D BUF_TYPE_MAX) + continue; + + /* on relevant platforms hold_count and min_count are swapped */ + inst->buffers[type].min_count =3D req->hold_count; + inst->buffers[type].size =3D req->size; + + if (type =3D=3D BUF_OUTPUT) + inst->fw_min_count =3D req->count_actual; + } +} + +static void iris_hfi_gen1_session_property_info(struct iris_inst *inst, vo= id *packet) +{ + struct hfi_msg_session_property_info_pkt *pkt =3D packet; + + if (pkt->num_properties !=3D 1) { + dev_warn_ratelimited(inst->core->dev, "%s: expected 1 property, got %u\n= ", + __func__, pkt->num_properties); + goto out; + } + + switch (pkt->property) { + case HFI_PROPERTY_CONFIG_BUFFER_REQUIREMENTS: + iris_hfi_gen1_session_buffer_requirements(inst, pkt->data, + pkt->shdr.hdr.size - sizeof(*pkt)); + break; + default: + dev_warn(inst->core->dev, "unknown property id: %x\n", pkt->property); + } + +out: + complete(&inst->completion); +} + struct iris_hfi_gen1_response_pkt_info { u32 pkt; u32 pkt_sz; @@ -657,7 +731,7 @@ static void iris_hfi_gen1_handle_response(struct iris_c= ore *core, void *response } else if (hdr->pkt_type =3D=3D HFI_MSG_SESSION_FILL_BUFFER) { iris_hfi_gen1_session_ftb_done(inst, hdr); } else if (hdr->pkt_type =3D=3D HFI_MSG_SESSION_PROPERTY_INFO) { - complete(&inst->completion); + iris_hfi_gen1_session_property_info(inst, hdr); } else { struct hfi_msg_session_hdr_pkt *shdr; =20 --=20 2.47.3 From nobody Fri Oct 2 14:03:53 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AD45D408026 for ; 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Unlike more recent cores this generation doesn't have the PIPE property (as it always has only one pipe). Also, unlike newer platforms, buffer sizes are requested from the firmware instead of being calculated by the driver. Co-developed-by: Dikshita Agarwal Signed-off-by: Dikshita Agarwal Reviewed-by: Vikash Garodia Signed-off-by: Dmitry Baryshkov Tested-by: Gourav Kumar --- drivers/media/platform/qcom/iris/Makefile | 1 + drivers/media/platform/qcom/iris/iris_hfi_gen1.c | 404 +++++++++++++++++= ++++ .../platform/qcom/iris/iris_hfi_gen1_command.c | 9 + .../platform/qcom/iris/iris_platform_common.h | 9 + .../platform/qcom/iris/iris_platform_vpu_ar50lt.c | 110 ++++++ drivers/media/platform/qcom/iris/iris_probe.c | 4 + drivers/media/platform/qcom/iris/iris_vpu_buffer.c | 5 + drivers/media/platform/qcom/iris/iris_vpu_buffer.h | 1 + 8 files changed, 543 insertions(+) diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/plat= form/qcom/iris/Makefile index f1b204b95694..bbd1f724963e 100644 --- a/drivers/media/platform/qcom/iris/Makefile +++ b/drivers/media/platform/qcom/iris/Makefile @@ -14,6 +14,7 @@ qcom-iris-objs +=3D iris_buffer.o \ iris_hfi_queue.o \ iris_platform_vpu2.o \ iris_platform_vpu3x.o \ + iris_platform_vpu_ar50lt.o \ iris_power.o \ iris_probe.o \ iris_resources.o \ diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1.c b/drivers/med= ia/platform/qcom/iris/iris_hfi_gen1.c index 0f7e7d6b25f4..548609315b85 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1.c @@ -445,3 +445,407 @@ const struct iris_firmware_data iris_hfi_gen1_data = =3D { .enc_ip_int_buf_tbl =3D sm8250_enc_ip_int_buf_tbl, .enc_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl), }; + +static const struct platform_inst_fw_cap iris_inst_fw_cap_gen1_ar50lt_dec[= ] =3D { + { + .cap_id =3D STAGE, + .min =3D STAGE_1, + .max =3D STAGE_2, + .step_or_mask =3D 1, + .value =3D STAGE_2, + .hfi_id =3D HFI_PROPERTY_PARAM_WORK_MODE, + .set =3D iris_set_stage, + }, +}; + +static const struct platform_inst_fw_cap inst_fw_cap_gen1_ar50lt_enc[] =3D= { + { + .cap_id =3D STAGE, + .min =3D STAGE_1, + .max =3D STAGE_2, + .step_or_mask =3D 1, + .value =3D STAGE_2, + .hfi_id =3D HFI_PROPERTY_PARAM_WORK_MODE, + .set =3D iris_set_stage, + }, + { + .cap_id =3D PROFILE_H264, + .min =3D V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, + .max =3D V4L2_MPEG_VIDEO_H264_PROFILE_MULTIVIEW_HIGH, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_STEREO_HIGH) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MULTIVIEW_HIGH), + .value =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, + .hfi_id =3D HFI_PROPERTY_PARAM_PROFILE_LEVEL_CURRENT, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_profile_level_gen1, + }, + { + .cap_id =3D PROFILE_HEVC, + .min =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, + .max =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) | + BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE), + .value =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, + .hfi_id =3D HFI_PROPERTY_PARAM_PROFILE_LEVEL_CURRENT, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_profile_level_gen1, + }, + { + .cap_id =3D LEVEL_H264, + .min =3D V4L2_MPEG_VIDEO_H264_LEVEL_1_0, + .max =3D V4L2_MPEG_VIDEO_H264_LEVEL_4_2, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2), + .value =3D V4L2_MPEG_VIDEO_H264_LEVEL_1_0, + .hfi_id =3D HFI_PROPERTY_PARAM_PROFILE_LEVEL_CURRENT, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_profile_level_gen1, + }, + { + .cap_id =3D LEVEL_HEVC, + .min =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_1, + .max =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1), + .value =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_1, + .hfi_id =3D HFI_PROPERTY_PARAM_PROFILE_LEVEL_CURRENT, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_profile_level_gen1, + }, + { + .cap_id =3D HEADER_MODE, + .min =3D V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE, + .max =3D V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) | + BIT(V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME), + .value =3D V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME, + .hfi_id =3D HFI_PROPERTY_CONFIG_VENC_SYNC_FRAME_SEQUENCE_HEADER, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_header_mode_gen1, + }, + { + .cap_id =3D BITRATE, + .min =3D BITRATE_MIN, + .max =3D BITRATE_MAX_AR50LT, + .step_or_mask =3D BITRATE_STEP, + .value =3D BITRATE_DEFAULT_AR50LT, + .hfi_id =3D HFI_PROPERTY_CONFIG_VENC_TARGET_BITRATE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_bitrate_gen1, + }, + { + .cap_id =3D BITRATE_MODE, + .min =3D V4L2_MPEG_VIDEO_BITRATE_MODE_VBR, + .max =3D V4L2_MPEG_VIDEO_BITRATE_MODE_CBR, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) | + BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_CBR), + .value =3D V4L2_MPEG_VIDEO_BITRATE_MODE_VBR, + .hfi_id =3D HFI_PROPERTY_PARAM_VENC_RATE_CONTROL, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_bitrate_mode_gen1, + }, + { + .cap_id =3D FRAME_SKIP_MODE, + .min =3D V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED, + .max =3D V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED) | + BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT), + .value =3D V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + }, + { + .cap_id =3D FRAME_RC_ENABLE, + .min =3D 0, + .max =3D 1, + .step_or_mask =3D 1, + .value =3D 1, + }, + { + .cap_id =3D GOP_SIZE, + .min =3D 0, + .max =3D (1 << 16) - 1, + .step_or_mask =3D 1, + .value =3D 30, + .hfi_id =3D HFI_PROPERTY_CONFIG_VENC_INTRA_PERIOD, + .flags =3D CAP_FLAG_OUTPUT_PORT, + .set =3D iris_set_intra_period, + }, + { + .cap_id =3D ENTROPY_MODE, + .min =3D V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC, + .max =3D V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC) | + BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC), + .value =3D V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC, + .hfi_id =3D HFI_PROPERTY_PARAM_VENC_H264_ENTROPY_CONTROL, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_entropy_mode_gen1, + }, + { + .cap_id =3D MIN_FRAME_QP_H264, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT_AR50LT, + .hfi_id =3D HFI_PROPERTY_PARAM_VENC_SESSION_QP_RANGE_V2, + .flags =3D CAP_FLAG_OUTPUT_PORT, + .set =3D iris_set_qp_range, + }, + { + .cap_id =3D MIN_FRAME_QP_HEVC, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP_HEVC, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT_AR50LT, + .hfi_id =3D HFI_PROPERTY_PARAM_VENC_SESSION_QP_RANGE_V2, + .flags =3D CAP_FLAG_OUTPUT_PORT, + .set =3D iris_set_qp_range, + }, + { + .cap_id =3D MAX_FRAME_QP_H264, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + .hfi_id =3D HFI_PROPERTY_PARAM_VENC_SESSION_QP_RANGE_V2, + .flags =3D CAP_FLAG_OUTPUT_PORT, + .set =3D iris_set_qp_range, + }, + { + .cap_id =3D MAX_FRAME_QP_HEVC, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP_HEVC, + .step_or_mask =3D 1, + .value =3D MAX_QP_HEVC, + .hfi_id =3D HFI_PROPERTY_PARAM_VENC_SESSION_QP_RANGE_V2, + .flags =3D CAP_FLAG_OUTPUT_PORT, + .set =3D iris_set_qp_range, + }, + { + .cap_id =3D IR_TYPE, + .min =3D V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM, + .max =3D V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_CYCLIC, + .step_or_mask =3D BIT(V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RAND= OM) | + BIT(V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_CYCLIC), + .value =3D V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + }, + { + .cap_id =3D IR_PERIOD, + .min =3D 0, + .max =3D ((4096 * 2304) >> 8), + .step_or_mask =3D 1, + .value =3D 0, + .hfi_id =3D HFI_PROPERTY_PARAM_VENC_INTRA_REFRESH, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_ir_period_gen1, + }, + { + .cap_id =3D LTR_COUNT, + .min =3D 0, + .max =3D MAX_LTR_FRAME_COUNT_GEN1, + .step_or_mask =3D 1, + .value =3D 0, + .hfi_id =3D HFI_PROPERTY_PARAM_VENC_LTRMODE, + .flags =3D CAP_FLAG_OUTPUT_PORT, + .set =3D iris_set_ltr_count_gen1, + }, + { + .cap_id =3D USE_LTR, + .min =3D 0, + .max =3D ((1 << MAX_LTR_FRAME_COUNT_GEN1) - 1), + .step_or_mask =3D 0, + .value =3D 0, + .hfi_id =3D HFI_PROPERTY_CONFIG_VENC_USELTRFRAME, + .flags =3D CAP_FLAG_INPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_use_ltr, + }, + { + .cap_id =3D MARK_LTR, + .min =3D 0, + .max =3D (MAX_LTR_FRAME_COUNT_GEN1 - 1), + .step_or_mask =3D 1, + .value =3D 0, + .hfi_id =3D HFI_PROPERTY_CONFIG_VENC_MARKLTRFRAME, + .flags =3D CAP_FLAG_INPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_mark_ltr, + }, + { + .cap_id =3D B_FRAME, + .min =3D 0, + .max =3D 3, + .step_or_mask =3D 1, + .value =3D 0, + .flags =3D CAP_FLAG_OUTPUT_PORT, + }, + { + .cap_id =3D LAYER_ENABLE, + .min =3D 0, + .max =3D 1, + .step_or_mask =3D 1, + .value =3D 0, + .flags =3D CAP_FLAG_OUTPUT_PORT, + }, + { + .cap_id =3D LAYER_TYPE_H264, + .min =3D V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_P, + .max =3D V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_P, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_P), + .value =3D V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_P, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + }, + { + .cap_id =3D LAYER_COUNT_H264, + .min =3D 0, + .max =3D MAX_HIER_CODING_LAYER_GEN1, + .step_or_mask =3D 1, + .value =3D 0, + .hfi_id =3D HFI_PROPERTY_CONFIG_VENC_HIER_P_ENH_LAYER, + .flags =3D CAP_FLAG_OUTPUT_PORT, + .set =3D iris_set_layer_count_gen1, + }, + { + .cap_id =3D LAYER0_BITRATE_H264, + .min =3D 1, + .max =3D BITRATE_MAX_AR50LT, + .step_or_mask =3D 1, + .value =3D BITRATE_DEFAULT, + .hfi_id =3D HFI_PROPERTY_CONFIG_VENC_TARGET_BITRATE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_bitrate_gen1, + }, + { + .cap_id =3D LAYER1_BITRATE_H264, + .min =3D 1, + .max =3D BITRATE_MAX_AR50LT, + .step_or_mask =3D 1, + .value =3D BITRATE_DEFAULT, + .hfi_id =3D HFI_PROPERTY_CONFIG_VENC_TARGET_BITRATE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_bitrate_gen1, + }, + { + .cap_id =3D LAYER2_BITRATE_H264, + .min =3D 1, + .max =3D BITRATE_MAX_AR50LT, + .step_or_mask =3D 1, + .value =3D BITRATE_DEFAULT, + .hfi_id =3D HFI_PROPERTY_CONFIG_VENC_TARGET_BITRATE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_bitrate_gen1, + }, + { + .cap_id =3D LAYER3_BITRATE_H264, + .min =3D 1, + .max =3D BITRATE_MAX_AR50LT, + .step_or_mask =3D 1, + .value =3D BITRATE_DEFAULT, + .hfi_id =3D HFI_PROPERTY_CONFIG_VENC_TARGET_BITRATE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_bitrate_gen1, + }, + { + .cap_id =3D LAYER4_BITRATE_H264, + .min =3D 1, + .max =3D BITRATE_MAX_AR50LT, + .step_or_mask =3D 1, + .value =3D BITRATE_DEFAULT, + .hfi_id =3D HFI_PROPERTY_CONFIG_VENC_TARGET_BITRATE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_bitrate_gen1, + }, + { + .cap_id =3D LAYER5_BITRATE_H264, + .min =3D 1, + .max =3D BITRATE_MAX_AR50LT, + .step_or_mask =3D 1, + .value =3D BITRATE_DEFAULT, + .hfi_id =3D HFI_PROPERTY_CONFIG_VENC_TARGET_BITRATE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_bitrate_gen1, + }, + { + .cap_id =3D REQUEST_SYNC_FRAME, + .min =3D 0, + .max =3D 1, + .step_or_mask =3D 1, + .value =3D 0, + .hfi_id =3D HFI_PROPERTY_CONFIG_VENC_REQUEST_SYNC_FRAME, + .flags =3D CAP_FLAG_INPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_req_sync_frame, + }, +}; + +static const u32 iris_hfi_gen1_ar50lt_dec_ip_int_buf_tbl[] =3D { + BUF_BIN, + BUF_SCRATCH_1, +}; + +/* + * Unlike sm8250, on AR50Lt the internal buffer sizes are provided by the + * firmware. Request HFI_PROPERTY_PARAM_BUFFER_SIZE_ACTUAL so that the enc= oder + * queries HFI_PROPERTY_CONFIG_BUFFER_REQUIREMENTS before allocating them. + */ +static const u32 iris_hfi_gen1_ar50lt_venc_input_config_param[] =3D { + HFI_PROPERTY_CONFIG_FRAME_RATE, + HFI_PROPERTY_PARAM_UNCOMPRESSED_PLANE_ACTUAL_INFO, + HFI_PROPERTY_PARAM_FRAME_SIZE, + HFI_PROPERTY_PARAM_UNCOMPRESSED_FORMAT_SELECT, + HFI_PROPERTY_PARAM_BUFFER_COUNT_ACTUAL, + HFI_PROPERTY_PARAM_BUFFER_SIZE_ACTUAL, +}; + +const struct iris_firmware_data iris_hfi_gen1_ar50lt_data =3D { + .init_hfi_ops =3D &iris_hfi_gen1_sys_ops_init, + + .query_buffer_requirements =3D true, + + .inst_fw_caps_dec =3D iris_inst_fw_cap_gen1_ar50lt_dec, + .inst_fw_caps_dec_size =3D ARRAY_SIZE(iris_inst_fw_cap_gen1_ar50lt_dec), + .inst_fw_caps_enc =3D inst_fw_cap_gen1_ar50lt_enc, + .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_gen1_ar50lt_enc), + + .dec_input_config_params_default =3D + sm8250_vdec_input_config_param_default, + .dec_input_config_params_default_size =3D + ARRAY_SIZE(sm8250_vdec_input_config_param_default), + .enc_input_config_params =3D iris_hfi_gen1_ar50lt_venc_input_config_param, + .enc_input_config_params_size =3D + ARRAY_SIZE(iris_hfi_gen1_ar50lt_venc_input_config_param), + + .dec_ip_int_buf_tbl =3D iris_hfi_gen1_ar50lt_dec_ip_int_buf_tbl, + .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(iris_hfi_gen1_ar50lt_dec_ip_int_b= uf_tbl), + .dec_op_int_buf_tbl =3D sm8250_dec_op_int_buf_tbl, + .dec_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_dec_op_int_buf_tbl), + + .enc_ip_int_buf_tbl =3D sm8250_enc_ip_int_buf_tbl, + .enc_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl), +}; diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen1_command.c index 5650645f9f65..47e9147a9b6d 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c @@ -973,6 +973,13 @@ static int iris_hfi_gen1_set_bufsize(struct iris_inst = *inst, u32 plane) struct hfi_buffer_size_actual bufsz; int ret; =20 + if (inst->core->iris_firmware_data->query_buffer_requirements) { + ret =3D inst->hfi_session_ops->session_get_property(inst, + HFI_PROPERTY_CONFIG_BUFFER_REQUIREMENTS); + if (ret) + return ret; + } + if (iris_split_mode_enabled(inst)) { bufsz.type =3D HFI_BUFFER_OUTPUT; bufsz.size =3D inst->core->iris_firmware_desc->get_vpu_buffer_size(inst,= BUF_DPB); @@ -1087,6 +1094,8 @@ static int iris_hfi_gen1_session_set_config_params(st= ruct iris_inst *inst, u32 p iris_hfi_gen1_set_raw_format}, {HFI_PROPERTY_PARAM_BUFFER_COUNT_ACTUAL, iris_hfi_gen1_set_num_bufs}, + {HFI_PROPERTY_PARAM_BUFFER_SIZE_ACTUAL, + iris_hfi_gen1_set_bufsize}, }; =20 if (inst->domain =3D=3D DECODER) { diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 4ed0709ec381..07cd02d6bfc8 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -39,6 +39,10 @@ struct iris_inst; #define MAX_HEVC_VBR_LAYER_HP_SLIDING_WINDOW 5 #define MAX_HIER_CODING_LAYER_GEN1 6 =20 +#define BITRATE_MAX_AR50LT 100000000 +#define BITRATE_DEFAULT_AR50LT 20000000 +#define MIN_QP_8BIT_AR50LT 0 + enum stage_type { STAGE_1 =3D 1, STAGE_2 =3D 2, @@ -51,10 +55,12 @@ enum pipe_type { }; =20 extern const struct iris_firmware_data iris_hfi_gen1_data; +extern const struct iris_firmware_data iris_hfi_gen1_ar50lt_data; extern const struct iris_firmware_data iris_hfi_gen2_data; extern const struct iris_firmware_data iris_hfi_milos_data; =20 extern const struct iris_platform_data milos_data; +extern const struct iris_platform_data qcm2290_data; extern const struct iris_platform_data qcs8300_data; extern const struct iris_platform_data sc7280_data; extern const struct iris_platform_data sm8250_data; @@ -245,6 +251,9 @@ struct iris_firmware_data { =20 u32 core_arch; =20 + /* Query buffer sizes from the firmware (pre-Iris HFI Gen1 platforms). */ + bool query_buffer_requirements; + const struct platform_inst_fw_cap *inst_fw_caps_dec; u32 inst_fw_caps_dec_size; const struct platform_inst_fw_cap *inst_fw_caps_enc; diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu_ar50lt.c b/= drivers/media/platform/qcom/iris/iris_platform_vpu_ar50lt.c new file mode 100644 index 000000000000..92f7e2546539 --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu_ar50lt.c @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "iris_core.h" +#include "iris_ctrls.h" +#include "iris_hfi_gen2.h" +#include "iris_hfi_gen2_defines.h" +#include "iris_platform_common.h" +#include "iris_vpu_buffer.h" +#include "iris_vpu_common.h" + +#define WRAPPER_INTR_STATUS_A2HWD_BMSK 0x10 + +static const struct iris_firmware_desc iris_vpu_ar50lt_p1_gen1_s6_desc =3D= { + .firmware_data =3D &iris_hfi_gen1_ar50lt_data, + .get_vpu_buffer_size =3D iris_vpu_ar50lt_gen1_buf_size, + .fwname =3D "qcom/venus-6.0/venus.mbn", +}; + +static const u32 iris_fmts_ar50lt_dec[] =3D { + V4L2_PIX_FMT_H264, + V4L2_PIX_FMT_HEVC, + V4L2_PIX_FMT_VP9, +}; + +static const struct bw_info iris_bw_table_dec_ar50lt[] =3D { + { ((1920 * 1080) / 256) * 60, 1564000, }, + { ((1920 * 1080) / 256) * 30, 791000, }, + { ((1280 * 720) / 256) * 60, 688000, }, + { ((1280 * 720) / 256) * 30, 347000, }, +}; + +static const struct icc_info iris_icc_info_ar50lt[] =3D { + { "cpu-cfg", 1000, 1000 }, + { "video-mem", 1000, 6500000 }, +}; + +static const char * const iris_pmdomain_table_ar50lt[] =3D { "venus", "vco= dec0" }; + +static const char * const iris_opp_pd_table_ar50lt[] =3D { "cx" }; + +static const struct platform_clk_data iris_clk_table_ar50lt[] =3D { + {IRIS_CTRL_CLK, "core" }, + {IRIS_AXI_CLK, "iface" }, + {IRIS_AHB_CLK, "bus" }, + {IRIS_HW_CLK, "vcodec0_core" }, + {IRIS_HW_AHB_CLK, "vcodec0_bus" }, + {IRIS_THROTTLE_CLK, "throttle" }, +}; + +static const char * const iris_opp_clk_table_ar50lt[] =3D { + "vcodec0_core", + NULL, +}; + +static const struct tz_cp_config tz_cp_config_ar50lt[] =3D { + { + .cp_start =3D 0, + .cp_size =3D 0x25800000, + .cp_nonpixel_start =3D 0x01000000, + .cp_nonpixel_size =3D 0x24800000, + }, +}; + +static struct platform_inst_caps platform_inst_cap_ar50lt =3D { + .min_frame_width =3D 128, + .max_frame_width =3D 1920, + .min_frame_height =3D 128, + .max_frame_height =3D 1920, + .max_mbpf =3D (1920 * 1088) / 256, + .mb_cycles_vpp =3D 440, + .mb_cycles_fw =3D 733003, + .mb_cycles_fw_vpp =3D 225975, + .max_frame_rate =3D 120, + .max_operating_rate =3D 120, +}; + +const struct iris_platform_data qcm2290_data =3D { + .firmware_desc_gen1 =3D &iris_vpu_ar50lt_p1_gen1_s6_desc, + .vpu_ops =3D &iris_vpu_ar50lt_ops, + .icc_tbl =3D iris_icc_info_ar50lt, + .icc_tbl_size =3D ARRAY_SIZE(iris_icc_info_ar50lt), + .bw_tbl_dec =3D iris_bw_table_dec_ar50lt, + .bw_tbl_dec_size =3D ARRAY_SIZE(iris_bw_table_dec_ar50lt), + .pmdomain_tbl =3D iris_pmdomain_table_ar50lt, + .pmdomain_tbl_size =3D ARRAY_SIZE(iris_pmdomain_table_ar50lt), + .opp_pd_tbl =3D iris_opp_pd_table_ar50lt, + .opp_pd_tbl_size =3D ARRAY_SIZE(iris_opp_pd_table_ar50lt), + .clk_tbl =3D iris_clk_table_ar50lt, + .clk_tbl_size =3D ARRAY_SIZE(iris_clk_table_ar50lt), + .opp_clk_tbl =3D iris_opp_clk_table_ar50lt, + /* Upper bound of DMA address range */ + .dma_mask =3D 0xe0000000 - 1, + .inst_iris_fmts =3D iris_fmts_ar50lt_dec, + .inst_iris_fmts_size =3D ARRAY_SIZE(iris_fmts_ar50lt_dec), + .inst_caps =3D &platform_inst_cap_ar50lt, + .tz_cp_config_data =3D tz_cp_config_ar50lt, + .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_ar50lt), + .num_vpp_pipe =3D 1, + .no_rpmh =3D true, + .wd_intr_mask =3D WRAPPER_INTR_STATUS_A2HWD_BMSK, + .icc_ib_multiplier =3D 2, + .max_session_count =3D 8, + .max_core_mbpf =3D ((1920 * 1088) / 256) * 4, + /* Concurrency: 1080p@30 decode + 1080p@30 encode */ + /* Concurrency: 3 * 1080p@30 decode */ + .max_core_mbps =3D (((1920 * 1088) / 256) * 90), +}; diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/= platform/qcom/iris/iris_probe.c index 5db6398433a4..5adb9dfb70fc 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -362,6 +362,10 @@ static const struct of_device_id iris_dt_match[] =3D { .compatible =3D "qcom,milos-iris", .data =3D &milos_data, }, + { + .compatible =3D "qcom,qcm2290-venus", + .data =3D &qcm2290_data, + }, { .compatible =3D "qcom,qcs8300-iris", .data =3D &qcs8300_data, diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_buffer.c index faebb5472866..83dc4a1db954 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c @@ -2194,6 +2194,11 @@ u32 iris_vpu4x_buf_size(struct iris_inst *inst, enum= iris_buffer_type buffer_typ return size; } =20 +u32 iris_vpu_ar50lt_gen1_buf_size(struct iris_inst *inst, enum iris_buffer= _type buffer_type) +{ + return inst->buffers[buffer_type].size; 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Reuse the buffer size calculation which are common, while adding the AR50LT specific ones separately. Signed-off-by: Dikshita Agarwal Reviewed-by: Vikash Garodia Signed-off-by: Dmitry Baryshkov Tested-by: Gourav Kumar --- drivers/media/platform/qcom/iris/iris_vpu_buffer.c | 365 +++++++++++++++++= ++++ drivers/media/platform/qcom/iris/iris_vpu_buffer.h | 37 +++ 2 files changed, 402 insertions(+) diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_buffer.c index 83dc4a1db954..a8170e5fa9e6 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c @@ -50,6 +50,26 @@ static u32 hfi_buffer_bin_h264d(u32 frame_width, u32 fra= me_height, u32 num_vpp_p return size_h264d_hw_bin_buffer(n_aligned_w, n_aligned_h, num_vpp_pipes); } =20 +static u32 hfi_buffer_bin_h264d_ar50lt(u32 frame_width, u32 frame_height) +{ + u32 n_aligned_h =3D ALIGN(frame_height, 16); + u32 n_aligned_w =3D ALIGN(frame_width, 16); + u32 size_yuv, size_bin_hdr, size_bin_res; + + size_yuv =3D ((n_aligned_w * n_aligned_h * 3) >> 1); + if (size_yuv <=3D 1920 * 1088 * 3 / 2) { + size_bin_hdr =3D size_yuv * H264_CABAC_HDR_RATIO_SM_TOT; + size_bin_res =3D size_yuv * H264_CABAC_RES_RATIO_SM_TOT; + } else { + size_bin_hdr =3D (size_yuv * 3) / 5; + size_bin_res =3D (size_yuv * 3) / 2; + } + size_bin_hdr =3D ALIGN(size_bin_hdr, DMA_ALIGNMENT); + size_bin_res =3D ALIGN(size_bin_res, DMA_ALIGNMENT); + + return size_bin_hdr + size_bin_res; +} + static u32 size_av1d_hw_bin_buffer(u32 frame_width, u32 frame_height, u32 = num_vpp_pipes) { u32 size_yuv, size_bin_hdr, size_bin_res; @@ -103,6 +123,19 @@ static u32 hfi_buffer_bin_vp9d(u32 frame_width, u32 fr= ame_height, u32 num_vpp_pi return _size * num_vpp_pipes; } =20 +static u32 hfi_buffer_bin_vp9d_ar50lt(u32 frame_width, u32 frame_height) +{ + u32 size_yuv, size; + + size_yuv =3D ALIGN(frame_width, 16) * ALIGN(frame_height, 16) * 3 / 2; + size_yuv =3D ALIGN(size_yuv, DMA_ALIGNMENT); + + size =3D ALIGN(((max(size_yuv, VPX_DECODER_FRAME_BIN_BUFFER_SIZE)) * 6) /= 5, DMA_ALIGNMENT) + + ALIGN(((max(size_yuv, VPX_DECODER_FRAME_BIN_BUFFER_SIZE)) * 4), DMA_ALIG= NMENT); + + return size; +} + static u32 hfi_buffer_bin_h265d(u32 frame_width, u32 frame_height, u32 num= _vpp_pipes) { u32 n_aligned_w =3D ALIGN(frame_width, 16); @@ -111,6 +144,27 @@ static u32 hfi_buffer_bin_h265d(u32 frame_width, u32 f= rame_height, u32 num_vpp_p return size_h265d_hw_bin_buffer(n_aligned_w, n_aligned_h, num_vpp_pipes); } =20 +static u32 hfi_buffer_bin_h265d_ar50lt(u32 frame_width, u32 frame_height) +{ + u32 n_aligned_w =3D ALIGN(frame_width, 16); + u32 n_aligned_h =3D ALIGN(frame_height, 16); + + u32 size_yuv, size_bin_hdr, size_bin_res; + + size_yuv =3D ((n_aligned_w * n_aligned_h * 3) >> 1); + if (size_yuv <=3D ((BIN_BUFFER_THRESHOLD * 3) >> 1)) { + size_bin_hdr =3D size_yuv * H265_CABAC_HDR_RATIO_SM_TOT; + size_bin_res =3D size_yuv * H265_CABAC_RES_RATIO_SM_TOT; + } else { + size_bin_hdr =3D (size_yuv * 41) / 50; + size_bin_res =3D (size_yuv * 59) / 50; + } + size_bin_hdr =3D ALIGN(size_bin_hdr, DMA_ALIGNMENT); + size_bin_res =3D ALIGN(size_bin_res, DMA_ALIGNMENT); + + return size_bin_hdr + size_bin_res; +} + static u32 hfi_buffer_comv_h264d(u32 frame_width, u32 frame_height, u32 _c= omv_bufcount) { u32 frame_height_in_mbs =3D DIV_ROUND_UP(frame_height, 16); @@ -174,6 +228,14 @@ static u32 size_h264d_bse_cmd_buf(u32 frame_height) SIZE_H264D_BSE_CMD_PER_BUF; } =20 +static u32 size_h264d_bse_cmd_buf_ar50lt(u32 frame_height) +{ + u32 height =3D ALIGN(frame_height, 32); + + return min_t(u32, (DIV_ROUND_UP(height, 16) * 12), H264D_MAX_SLICE) * + SIZE_H264D_BSE_CMD_PER_BUF; +} + static u32 size_h265d_bse_cmd_buf(u32 frame_width, u32 frame_height) { u32 _size =3D ALIGN(((ALIGN(frame_width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZ= E_PELS) * @@ -185,6 +247,18 @@ static u32 size_h265d_bse_cmd_buf(u32 frame_width, u32= frame_height) return _size; } =20 +static u32 size_h265d_bse_cmd_buf_ar50lt(u32 frame_width, u32 frame_height) +{ + u32 _size =3D ALIGN(((ALIGN(frame_width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZ= E_PELS) * + (ALIGN(frame_height, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS)) * + NUM_HW_PIC_BUF, DMA_ALIGNMENT); + + _size =3D min_t(u32, _size, H265D_MAX_SLICE_AR50LT + 1); + _size =3D 2 * _size * SIZE_H265D_BSE_CMD_PER_BUF; + + return _size; +} + static u32 hfi_buffer_persist_h265d(u32 rpu_enabled) { return ALIGN((SIZE_SLIST_BUF_H265 * NUM_SLIST_BUF_H265 + @@ -195,6 +269,13 @@ static u32 hfi_buffer_persist_h265d(u32 rpu_enabled) DMA_ALIGNMENT); } =20 +static u32 hfi_buffer_persist_h265d_ar50lt(void) +{ + return ALIGN((SIZE_SLIST_BUF_H265 * NUM_SLIST_BUF_H265 + + H265_NUM_TILE * sizeof(u32) + NUM_HW_PIC_BUF * SIZE_SEI_USERDATA), + DMA_ALIGNMENT); +} + static inline u32 hfi_iris3_vp9d_comv_size(void) { @@ -212,6 +293,13 @@ static u32 hfi_buffer_persist_vp9d(void) HDR10_HIST_EXTRADATA_SIZE; } =20 +static u32 hfi_buffer_persist_vp9d_ar50lt(void) +{ + return ALIGN(VP9_NUM_PROBABILITY_TABLE_BUF * VP9_PROB_TABLE_SIZE, DMA_ALI= GNMENT) + + ALIGN(hfi_iris3_vp9d_comv_size(), DMA_ALIGNMENT) + + ALIGN(MAX_SUPERFRAME_HEADER_LEN, DMA_ALIGNMENT); +} + static u32 size_h264d_vpp_cmd_buf(u32 frame_height) { u32 size, height =3D ALIGN(frame_height, 32); @@ -222,6 +310,16 @@ static u32 size_h264d_vpp_cmd_buf(u32 frame_height) return size > VPP_CMD_MAX_SIZE ? VPP_CMD_MAX_SIZE : size; } =20 +static u32 size_h264d_vpp_cmd_buf_ar50lt(u32 frame_height) +{ + u32 size, height =3D ALIGN(frame_height, 32); + + size =3D min_t(u32, (DIV_ROUND_UP(height, 16) * 12), H264D_MAX_SLICE) * + SIZE_H264D_VPP_CMD_PER_BUF; + + return size > VPP_CMD_MAX_SIZE ? VPP_CMD_MAX_SIZE : size; +} + static u32 hfi_buffer_persist_h264d(void) { return ALIGN(SIZE_SLIST_BUF_H264 * NUM_SLIST_BUF_H264 + @@ -230,6 +328,11 @@ static u32 hfi_buffer_persist_h264d(void) DMA_ALIGNMENT); } =20 +static u32 hfi_buffer_persist_h264d_ar50lt(void) +{ + return ALIGN((SIZE_SLIST_BUF_H264 * NUM_SLIST_BUF_H264), DMA_ALIGNMENT); +} + static u32 hfi_buffer_persist_av1d(u32 max_width, u32 max_height, u32 tota= l_ref_count) { u32 comv_size, size; @@ -255,6 +358,17 @@ static u32 hfi_buffer_non_comv_h264d(u32 frame_width, = u32 frame_height, u32 num_ return ALIGN(size, DMA_ALIGNMENT); } =20 +static u32 hfi_buffer_non_comv_h264d_ar50lt(u32 frame_width, u32 frame_hei= ght) +{ + u32 size_bse =3D size_h264d_bse_cmd_buf_ar50lt(frame_height); + u32 size_vpp =3D size_h264d_vpp_cmd_buf_ar50lt(frame_height); + u32 size =3D ALIGN(size_bse, DMA_ALIGNMENT) + + ALIGN(size_vpp, DMA_ALIGNMENT) + + ALIGN(SIZE_HW_PIC(SIZE_H264D_HW_PIC_T), DMA_ALIGNMENT); + + return ALIGN(size, DMA_ALIGNMENT); +} + static u32 size_h265d_vpp_cmd_buf(u32 frame_width, u32 frame_height) { u32 _size =3D ALIGN(((ALIGN(frame_width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZ= E_PELS) * @@ -269,6 +383,20 @@ static u32 size_h265d_vpp_cmd_buf(u32 frame_width, u32= frame_height) return _size; } =20 +static u32 size_h265d_vpp_cmd_buf_ar50lt(u32 frame_width, u32 frame_height) +{ + u32 _size =3D ALIGN(((ALIGN(frame_width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZ= E_PELS) * + (ALIGN(frame_height, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS)) * + NUM_HW_PIC_BUF, DMA_ALIGNMENT); + _size =3D min_t(u32, _size, H265D_MAX_SLICE_AR50LT + 1); + _size =3D ALIGN(_size, 4); + _size =3D 2 * _size * SIZE_H265D_VPP_CMD_PER_BUF_AR50LT; + if (_size > VPP_CMD_MAX_SIZE) + _size =3D VPP_CMD_MAX_SIZE; + + return _size; +} + static u32 hfi_buffer_non_comv_h265d(u32 frame_width, u32 frame_height, u3= 2 num_vpp_pipes) { u32 _size_bse =3D size_h265d_bse_cmd_buf(frame_width, frame_height); @@ -285,6 +413,20 @@ static u32 hfi_buffer_non_comv_h265d(u32 frame_width, = u32 frame_height, u32 num_ return ALIGN(_size, DMA_ALIGNMENT); } =20 +static u32 hfi_buffer_non_comv_h265d_ar50lt(u32 frame_width, u32 frame_hei= ght) +{ + u32 _size_bse =3D size_h265d_bse_cmd_buf_ar50lt(frame_width, frame_height= ); + u32 _size_vpp =3D size_h265d_vpp_cmd_buf_ar50lt(frame_width, frame_height= ); + u32 _size =3D ALIGN(_size_bse, DMA_ALIGNMENT) + + ALIGN(_size_vpp, DMA_ALIGNMENT) + + ALIGN(2 * sizeof(u16) * + (ALIGN(frame_width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS) * + (ALIGN(frame_height, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS), DMA_ALIGNM= ENT) + + ALIGN(SIZE_HW_PIC(SIZE_H265D_HW_PIC_T), DMA_ALIGNMENT); + + return ALIGN(_size, DMA_ALIGNMENT); +} + static u32 size_vpss_lb(u32 frame_width, u32 frame_height) { u32 opb_lb_wr_llb_y_buffer_size, opb_lb_wr_llb_uv_buffer_size; @@ -317,6 +459,13 @@ u32 size_h265d_lb_fe_top_data(u32 frame_width, u32 fra= me_height) (ALIGN(frame_width, 64) + 8) * 2; } =20 +static inline +u32 size_h265d_lb_fe_top_data_ar50lt(u32 frame_width, u32 frame_height) +{ + return ALIGN(MAX_FE_NBR_DATA_LUMA_LINE_BUFFER_SIZE * + (ALIGN(frame_width, 64) + 8), DMA_ALIGNMENT) * 2; +} + static inline u32 size_h265d_lb_fe_top_ctrl(u32 frame_width, u32 frame_height) { @@ -348,6 +497,17 @@ u32 size_h265d_lb_se_left_ctrl(u32 frame_width, u32 fr= ame_height) MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE)); } =20 +static inline +u32 size_h265d_lb_se_left_ctrl_ar50lt(u32 frame_width, u32 frame_height) +{ + return max_t(u32, ((frame_height + 16 - 1) / 8) * + MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE_AR50LT, + max_t(u32, ((frame_height + 32 - 1) / 8) * + MAX_SE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE_AR50LT, + ((frame_height + 64 - 1) / 8) * + MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE_AR50LT)); +} + static inline u32 size_h265d_lb_pe_top_data(u32 frame_width, u32 frame_height) { @@ -355,6 +515,13 @@ u32 size_h265d_lb_pe_top_data(u32 frame_width, u32 fra= me_height) (ALIGN(frame_width, LCU_MIN_SIZE_PELS) / LCU_MIN_SIZE_PELS); } =20 +static inline +u32 size_h265d_lb_pe_top_data_ar50lt(u32 frame_width, u32 frame_height) +{ + return MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE_AR50LT * + (ALIGN(frame_width, LCU_MIN_SIZE_PELS) / LCU_MIN_SIZE_PELS); +} + static inline u32 size_h265d_lb_vsp_top(u32 frame_width, u32 frame_height) { @@ -404,6 +571,25 @@ u32 hfi_buffer_line_h265d(u32 frame_width, u32 frame_h= eight, bool is_opb, u32 nu return ALIGN((_size + vpss_lb_size), DMA_ALIGNMENT); } =20 +static inline +u32 hfi_buffer_line_h265d_ar50lt(u32 frame_width, u32 frame_height) +{ + u32 size; + + size =3D ALIGN(size_h265d_lb_fe_top_data_ar50lt(frame_width, frame_height= ), DMA_ALIGNMENT) + + ALIGN(size_h265d_lb_fe_top_ctrl(frame_width, frame_height), DMA_ALIGNMEN= T) + + ALIGN(size_h265d_lb_fe_left_ctrl(frame_width, frame_height), DMA_ALIGNME= NT) + + ALIGN(size_h265d_lb_se_left_ctrl_ar50lt(frame_width, frame_height), DMA_= ALIGNMENT) + + ALIGN(size_h265d_lb_se_top_ctrl(frame_width, frame_height), DMA_ALIGNMEN= T) + + ALIGN(size_h265d_lb_pe_top_data_ar50lt(frame_width, frame_height), DMA_A= LIGNMENT) + + ALIGN(size_h265d_lb_vsp_top(frame_width, frame_height), DMA_ALIGNMENT) + + ALIGN(size_h265d_lb_vsp_left(frame_width, frame_height), DMA_ALIGNMENT) + + ALIGN(size_h265d_lb_recon_dma_metadata_wr(frame_width, frame_height), DM= A_ALIGNMENT) * 4 + + ALIGN(size_h265d_qp(frame_width, frame_height), DMA_ALIGNMENT); + + return ALIGN(size, DMA_ALIGNMENT); +} + static inline u32 size_vpxd_lb_fe_left_ctrl(u32 frame_width, u32 frame_height) { @@ -438,6 +624,17 @@ u32 size_vpxd_lb_se_left_ctrl(u32 frame_width, u32 fra= me_height) MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE)); } =20 +static inline +u32 size_vpxd_lb_se_left_ctrl_ar50lt(u32 frame_width, u32 frame_height) +{ + return max_t(u32, ((frame_height + 15) >> 4) * + MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE_AR50LT, + max_t(u32, ((frame_height + 31) >> 5) * + MAX_SE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE_AR50LT, + ((frame_height + 63) >> 6) * + MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE_AR50LT)); +} + static inline u32 size_vpxd_lb_recon_dma_metadata_wr(u32 frame_width, u32 frame_height) { @@ -492,6 +689,17 @@ u32 hfi_iris3_vp9d_lb_size(u32 frame_width, u32 frame_= height, u32 num_vpp_pipes) ALIGN(size_vp9d_qp(frame_width, frame_height), DMA_ALIGNMENT); } =20 +static inline +u32 hfi_buffer_line_vp9d_ar50lt(u32 frame_width, u32 frame_height, u32 _yu= v_bufcount_min) +{ + return ALIGN(size_vpxd_lb_fe_left_ctrl(frame_width, frame_height), DMA_AL= IGNMENT) + + ALIGN(size_vpxd_lb_se_left_ctrl_ar50lt(frame_width, frame_height), DMA_A= LIGNMENT) + + ALIGN(size_vp9d_lb_vsp_top(frame_width, frame_height), DMA_ALIGNMENT) + + ALIGN(size_vpxd_lb_se_top_ctrl(frame_width, frame_height), DMA_ALIGNMENT= ) + + ALIGN(size_vp9d_lb_pe_top_data(frame_width, frame_height), DMA_ALIGNMENT= ) + + ALIGN(size_vp9d_lb_fe_top_data(frame_width, frame_height), DMA_ALIGNMENT= ); +} + static inline u32 hfi_buffer_line_vp9d(u32 frame_width, u32 frame_height, u32 _yuv_bufco= unt_min, bool is_opb, u32 num_vpp_pipes) @@ -529,6 +737,23 @@ static u32 hfi_buffer_line_h264d(u32 frame_width, u32 = frame_height, return ALIGN((size + vpss_lb_size), DMA_ALIGNMENT); } =20 +static u32 hfi_buffer_line_h264d_ar50lt(u32 frame_width, u32 frame_height) +{ + u32 size; + + size =3D ALIGN(size_h264d_lb_fe_top_data_ar50lt(frame_width), DMA_ALIGNME= NT) + + ALIGN(size_h264d_lb_fe_top_ctrl_ar50lt(frame_width), DMA_ALIGNMENT) + + ALIGN(size_h264d_lb_fe_left_ctrl(frame_height), DMA_ALIGNMENT) + + ALIGN(size_h264d_lb_se_top_ctrl_ar50lt(frame_width), DMA_ALIGNMENT) + + ALIGN(size_h264d_lb_se_left_ctrl_ar50lt(frame_height), DMA_ALIGNMENT) + + ALIGN(size_h264d_lb_pe_top_data_ar50lt(frame_width), DMA_ALIGNMENT) + + ALIGN(size_h264d_lb_vsp_top(frame_width), DMA_ALIGNMENT) + + ALIGN(size_h264d_lb_recon_dma_metadata_wr(frame_height), DMA_ALIGNMENT) = * 2 + + ALIGN(size_h264d_qp(frame_width, frame_height), DMA_ALIGNMENT); + + return ALIGN(size, DMA_ALIGNMENT); +} + static u32 size_av1d_lb_opb_wr1_nv12_ubwc(u32 frame_width, u32 frame_heigh= t) { u32 size, y_width, y_width_a =3D 128; @@ -724,6 +949,22 @@ static u32 iris_vpu_dec_bin_size(struct iris_inst *ins= t) return 0; } =20 +static u32 iris_vpu_ar50lt_dec_bin_size(struct iris_inst *inst) +{ + struct v4l2_format *f =3D inst->fmt_src; + u32 height =3D f->fmt.pix_mp.height; + u32 width =3D f->fmt.pix_mp.width; + + if (inst->codec =3D=3D V4L2_PIX_FMT_H264) + return hfi_buffer_bin_h264d_ar50lt(width, height); + else if (inst->codec =3D=3D V4L2_PIX_FMT_HEVC) + return hfi_buffer_bin_h265d_ar50lt(width, height); + else if (inst->codec =3D=3D V4L2_PIX_FMT_VP9) + return hfi_buffer_bin_vp9d_ar50lt(width, height); + + return 0; +} + static u32 iris_vpu_dec_comv_size(struct iris_inst *inst) { u32 num_comv =3D VIDEO_MAX_FRAME; @@ -785,6 +1026,18 @@ static u32 iris_vpu_dec_persist_size(struct iris_inst= *inst) return 0; } =20 +static u32 iris_vpu_ar50lt_dec_persist_size(struct iris_inst *inst) +{ + if (inst->codec =3D=3D V4L2_PIX_FMT_H264) + return hfi_buffer_persist_h264d_ar50lt(); + else if (inst->codec =3D=3D V4L2_PIX_FMT_HEVC) + return hfi_buffer_persist_h265d_ar50lt(); + else if (inst->codec =3D=3D V4L2_PIX_FMT_VP9) + return hfi_buffer_persist_vp9d_ar50lt(); + + return 0; +} + static u32 iris_vpu_dec_dpb_size(struct iris_inst *inst) { if (iris_split_mode_enabled(inst)) @@ -808,6 +1061,20 @@ static u32 iris_vpu_dec_non_comv_size(struct iris_ins= t *inst) return 0; } =20 +static u32 iris_vpu_ar50lt_dec_non_comv_size(struct iris_inst *inst) +{ + struct v4l2_format *f =3D inst->fmt_src; + u32 height =3D f->fmt.pix_mp.height; + u32 width =3D f->fmt.pix_mp.width; + + if (inst->codec =3D=3D V4L2_PIX_FMT_H264) + return hfi_buffer_non_comv_h264d_ar50lt(width, height); + else if (inst->codec =3D=3D V4L2_PIX_FMT_HEVC) + return hfi_buffer_non_comv_h265d_ar50lt(width, height); + + return 0; +} + static u32 iris_vpu_dec_line_size(struct iris_inst *inst) { u32 num_vpp_pipes =3D inst->core->iris_platform_data->num_vpp_pipe; @@ -833,6 +1100,23 @@ static u32 iris_vpu_dec_line_size(struct iris_inst *i= nst) return 0; } =20 +static u32 iris_vpu_ar50lt_dec_line_size(struct iris_inst *inst) +{ + struct v4l2_format *f =3D inst->fmt_src; + u32 height =3D f->fmt.pix_mp.height; + u32 width =3D f->fmt.pix_mp.width; + u32 out_min_count =3D inst->buffers[BUF_OUTPUT].min_count; + + if (inst->codec =3D=3D V4L2_PIX_FMT_H264) + return hfi_buffer_line_h264d_ar50lt(width, height); + else if (inst->codec =3D=3D V4L2_PIX_FMT_HEVC) + return hfi_buffer_line_h265d_ar50lt(width, height); + else if (inst->codec =3D=3D V4L2_PIX_FMT_VP9) + return hfi_buffer_line_vp9d_ar50lt(width, height, out_min_count); + + return 0; +} + static u32 iris_vpu_dec_scratch1_size(struct iris_inst *inst) { return iris_vpu_dec_comv_size(inst) + @@ -840,6 +1124,13 @@ static u32 iris_vpu_dec_scratch1_size(struct iris_ins= t *inst) iris_vpu_dec_line_size(inst); } =20 +static u32 iris_vpu_ar50lt_dec_scratch1_size(struct iris_inst *inst) +{ + return iris_vpu_dec_comv_size(inst) + + iris_vpu_ar50lt_dec_non_comv_size(inst) + + iris_vpu_ar50lt_dec_line_size(inst); +} + static inline u32 iris_vpu_enc_get_bitstream_width(struct iris_inst *inst) { if (is_rotation_90_or_270(inst)) @@ -1470,6 +1761,15 @@ u32 hfi_buffer_dpb_enc(u32 frame_width, u32 frame_he= ight, bool is_ten_bit) return size; } =20 +static inline +u32 hfi_buffer_dpb_enc_ar50lt(u32 frame_width, u32 frame_height, bool is_t= en_bit) +{ + if (!is_ten_bit) + return size_enc_ref_buffer(frame_width, frame_height); + else + return size_enc_ten_bit_ref_buffer(frame_width, frame_height); +} + static u32 iris_vpu_enc_arp_size(struct iris_inst *inst) { return HFI_BUFFER_ARP_ENC; @@ -1494,6 +1794,16 @@ u32 hfi_buffer_vpss_enc(u32 dswidth, u32 dsheight, b= ool ds_enable, return 0; } =20 +static inline +u32 hfi_buffer_vpss_enc_ar50lt(u32 dswidth, u32 dsheight, bool ds_enable, + u32 blur, bool is_ten_bit) +{ + if (ds_enable || blur) + return hfi_buffer_dpb_enc_ar50lt(dswidth, dsheight, is_ten_bit); + + return 0; +} + static inline u32 hfi_buffer_scratch1_enc(u32 frame_width, u32 frame_heigh= t, u32 lcu_size, u32 num_ref, bool ten_bit, u32 num_vpp_pipes, @@ -1752,6 +2062,16 @@ static u32 iris_vpu_enc_vpss_size(struct iris_inst *= inst) return hfi_buffer_vpss_enc(width, height, ds_enable, 0, 0); } =20 +static u32 iris_vpu_ar50lt_enc_vpss_size(struct iris_inst *inst) +{ + u32 ds_enable =3D is_scaling_enabled(inst); + struct v4l2_format *f =3D inst->fmt_dst; + u32 height =3D f->fmt.pix_mp.height; + u32 width =3D f->fmt.pix_mp.width; + + return hfi_buffer_vpss_enc_ar50lt(width, height, ds_enable, 0, 0); +} + static inline u32 size_dpb_opb(u32 height, u32 lcu_size) { u32 max_tile_height =3D ((height + lcu_size - 1) / lcu_size) * lcu_size += 8; @@ -2199,6 +2519,51 @@ u32 iris_vpu_ar50lt_gen1_buf_size(struct iris_inst *= inst, enum iris_buffer_type return inst->buffers[buffer_type].size; } =20 +u32 iris_vpu_ar50lt_gen2_buf_size(struct iris_inst *inst, enum iris_buffer= _type buffer_type) +{ + const struct iris_vpu_buf_type_handle *buf_type_handle_arr =3D NULL; + u32 size =3D 0, buf_type_handle_size =3D 0, i; + + static const struct iris_vpu_buf_type_handle dec_internal_buf_type_handle= [] =3D { + {BUF_BIN, iris_vpu_ar50lt_dec_bin_size }, + {BUF_COMV, iris_vpu_dec_comv_size }, + {BUF_NON_COMV, iris_vpu_ar50lt_dec_non_comv_size }, + {BUF_LINE, iris_vpu_ar50lt_dec_line_size }, + {BUF_PERSIST, iris_vpu_ar50lt_dec_persist_size }, + {BUF_DPB, iris_vpu_dec_dpb_size }, + {BUF_SCRATCH_1, iris_vpu_ar50lt_dec_scratch1_size }, + {BUF_PARTIAL, iris_vpu_dec_partial_size }, + }; + + static const struct iris_vpu_buf_type_handle enc_internal_buf_type_handle= [] =3D { + {BUF_BIN, iris_vpu_enc_bin_size }, + {BUF_COMV, iris_vpu_enc_comv_size }, + {BUF_NON_COMV, iris_vpu_enc_non_comv_size }, + {BUF_LINE, iris_vpu_enc_line_size }, + {BUF_ARP, iris_vpu_enc_arp_size }, + {BUF_VPSS, iris_vpu_ar50lt_enc_vpss_size }, + {BUF_SCRATCH_1, iris_vpu_enc_scratch1_size }, + {BUF_SCRATCH_2, iris_vpu_enc_scratch2_size }, + }; + + if (inst->domain =3D=3D DECODER) { + buf_type_handle_size =3D ARRAY_SIZE(dec_internal_buf_type_handle); + buf_type_handle_arr =3D dec_internal_buf_type_handle; + } else if (inst->domain =3D=3D ENCODER) { + buf_type_handle_size =3D ARRAY_SIZE(enc_internal_buf_type_handle); + buf_type_handle_arr =3D enc_internal_buf_type_handle; + } + + for (i =3D 0; i < buf_type_handle_size; i++) { + if (buf_type_handle_arr[i].type =3D=3D buffer_type) { + size =3D buf_type_handle_arr[i].handle(inst); + break; + } + } + + return size; +} + static u32 internal_buffer_count(struct iris_inst *inst, enum iris_buffer_type buffer_type) { diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.h b/drivers/m= edia/platform/qcom/iris/iris_vpu_buffer.h index 1d07137c70cd..2085e316a6bd 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.h @@ -61,17 +61,26 @@ struct iris_inst; #define MAX_FE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE 64 #define MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE (128 / 8) #define MAX_SE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE (128 / 8) +#define MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE_AR50LT (8 / 8) +#define MAX_SE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE_AR50LT (16 / 8) +#define MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE_AR50LT (32 / 8) #define VP9_UDC_HEADER_BUF_SIZE (3 * 128) =20 #define SIZE_SEI_USERDATA 4096 #define SIZE_DOLBY_RPU_METADATA (41 * 1024) #define H264_CABAC_HDR_RATIO_HD_TOT 1 #define H264_CABAC_RES_RATIO_HD_TOT 3 +#define H264_CABAC_HDR_RATIO_SM_TOT 1 +#define H264_CABAC_RES_RATIO_SM_TOT 2 #define H265D_MAX_SLICE 3600 +#define H265D_MAX_SLICE_AR50LT 600 #define SIZE_H265D_HW_PIC_T SIZE_H264D_HW_PIC_T #define H265_CABAC_HDR_RATIO_HD_TOT 2 #define H265_CABAC_RES_RATIO_HD_TOT 2 +#define H265_CABAC_HDR_RATIO_SM_TOT 1 +#define H265_CABAC_RES_RATIO_SM_TOT 6 #define SIZE_H265D_VPP_CMD_PER_BUF (256) +#define SIZE_H265D_VPP_CMD_PER_BUF_AR50LT (192) #define SIZE_THREE_DIMENSION_USERDATA 768 #define SIZE_H265D_ARP 9728 =20 @@ -81,6 +90,7 @@ struct iris_inst; #define VPX_DECODER_FRAME_BIN_DENOMINATOR 2 =20 #define VPX_DECODER_FRAME_BIN_RES_BUDGET_RATIO (3 / 2) +#define VPX_DECODER_FRAME_BIN_BUFFER_SIZE (1024 * 1024) =20 #define SIZE_H264D_HW_PIC_T (BIT(11)) =20 @@ -99,6 +109,7 @@ struct iris_inst; #define MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE 64 #define MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE 16 #define MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE 384 +#define MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE_AR50LT 176 #define MAX_FE_NBR_DATA_LUMA_LINE_BUFFER_SIZE 640 =20 #define AV1_CABAC_HDR_RATIO_HD_TOT 2 @@ -155,11 +166,21 @@ static inline u32 size_h264d_lb_fe_top_data(u32 frame= _width) return MAX_FE_NBR_DATA_LUMA_LINE_BUFFER_SIZE * ALIGN(frame_width, 16) * 3; } =20 +static inline u32 size_h264d_lb_fe_top_data_ar50lt(u32 frame_width) +{ + return 16 * ALIGN(frame_width, 16) * 2; +} + static inline u32 size_h264d_lb_fe_top_ctrl(u32 frame_width) { return MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_width,= 16); } =20 +static inline u32 size_h264d_lb_fe_top_ctrl_ar50lt(u32 frame_width) +{ + return 16 * DIV_ROUND_UP(frame_width, 16); +} + static inline u32 size_h264d_lb_fe_left_ctrl(u32 frame_height) { return MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_height= , 16); @@ -170,16 +191,31 @@ static inline u32 size_h264d_lb_se_top_ctrl(u32 frame= _width) return MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_width,= 16); } =20 +static inline u32 size_h264d_lb_se_top_ctrl_ar50lt(u32 frame_width) +{ + return MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE_AR50LT * DIV_ROUND_UP(frame= _width, 16); +} + static inline u32 size_h264d_lb_se_left_ctrl(u32 frame_height) { return MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_height= , 16); } =20 +static inline u32 size_h264d_lb_se_left_ctrl_ar50lt(u32 frame_height) +{ + return MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE_AR50LT * DIV_ROUND_UP(frame= _height, 16); +} + static inline u32 size_h264d_lb_pe_top_data(u32 frame_width) { return MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_width,= 16); } =20 +static inline u32 size_h264d_lb_pe_top_data_ar50lt(u32 frame_width) +{ + return 64 * DIV_ROUND_UP(frame_width, 16); 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Follow the example of the SC7280 platform and extend the driver with supporting both HFI Gen1 and Gen2 firmwares for this platform. Like HFI Gen1 this firmware doesn't have PIPE property (but unlike Gen1 buffer sizes are calculated on the driver side). Add the Gen2 encoder controls supported by this firmware: the Long-Term Reference control and hierarchical (layered) coding. Signed-off-by: Dikshita Agarwal Co-developed-by: Vishnu Reddy Signed-off-by: Vishnu Reddy Reviewed-by: Vikash Garodia Signed-off-by: Dmitry Baryshkov Tested-by: Gourav Kumar --- drivers/media/platform/qcom/iris/iris_hfi_gen2.c | 859 +++++++++++++++++= ++++ .../platform/qcom/iris/iris_platform_common.h | 1 + .../platform/qcom/iris/iris_platform_vpu_ar50lt.c | 7 + 3 files changed, 867 insertions(+) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2.c b/drivers/med= ia/platform/qcom/iris/iris_hfi_gen2.c index 3b8fbefb8b93..3e752f69e414 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2.c @@ -2021,3 +2021,862 @@ const struct iris_firmware_data iris_hfi_milos_data= =3D { .enc_op_int_buf_tbl =3D sm8550_enc_op_int_buf_tbl, .enc_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; + +static const struct platform_inst_fw_cap inst_fw_cap_gen2_ar50lt_dec[] =3D= { + { + .cap_id =3D PROFILE_H264, + .min =3D V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, + .max =3D V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH), + .value =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, + .hfi_id =3D HFI_PROP_PROFILE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_u32_enum, + }, + { + .cap_id =3D PROFILE_HEVC, + .min =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, + .max =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) | + BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE), + .value =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, + .hfi_id =3D HFI_PROP_PROFILE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_u32_enum, + }, + { + .cap_id =3D PROFILE_VP9, + .min =3D V4L2_MPEG_VIDEO_VP9_PROFILE_0, + .max =3D V4L2_MPEG_VIDEO_VP9_PROFILE_0, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_VP9_PROFILE_0), + .value =3D V4L2_MPEG_VIDEO_VP9_PROFILE_0, + .hfi_id =3D HFI_PROP_PROFILE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_u32_enum, + }, + { + .cap_id =3D LEVEL_H264, + .min =3D V4L2_MPEG_VIDEO_H264_LEVEL_1_0, + .max =3D V4L2_MPEG_VIDEO_H264_LEVEL_4_2, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2), + .value =3D V4L2_MPEG_VIDEO_H264_LEVEL_4_2, + .hfi_id =3D HFI_PROP_LEVEL, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_u32_enum, + }, + { + .cap_id =3D LEVEL_HEVC, + .min =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_1, + .max =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1), + .value =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1, + .hfi_id =3D HFI_PROP_LEVEL, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_u32_enum, + }, + { + .cap_id =3D LEVEL_VP9, + .min =3D V4L2_MPEG_VIDEO_VP9_LEVEL_1_0, + .max =3D V4L2_MPEG_VIDEO_VP9_LEVEL_4_1, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_0) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_1) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_2_0) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_3_0) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_0) | + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_1), + .value =3D V4L2_MPEG_VIDEO_VP9_LEVEL_4_1, + .hfi_id =3D HFI_PROP_LEVEL, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_u32_enum, + }, + { + .cap_id =3D TIER, + .min =3D V4L2_MPEG_VIDEO_HEVC_TIER_MAIN, + .max =3D V4L2_MPEG_VIDEO_HEVC_TIER_HIGH, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEVC_TIER_MAIN) | + BIT(V4L2_MPEG_VIDEO_HEVC_TIER_HIGH), + .value =3D V4L2_MPEG_VIDEO_HEVC_TIER_HIGH, + .hfi_id =3D HFI_PROP_TIER, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_u32_enum, + }, + { + .cap_id =3D INPUT_BUF_HOST_MAX_COUNT, + .min =3D DEFAULT_MAX_HOST_BUF_COUNT, + .max =3D DEFAULT_MAX_HOST_BURST_BUF_COUNT, + .step_or_mask =3D 1, + .value =3D DEFAULT_MAX_HOST_BUF_COUNT, + .hfi_id =3D HFI_PROP_BUFFER_HOST_MAX_COUNT, + .flags =3D CAP_FLAG_INPUT_PORT, + .set =3D iris_set_u32, + }, + { + .cap_id =3D STAGE, + .min =3D STAGE_1, + .max =3D STAGE_2, + .step_or_mask =3D 1, + .value =3D STAGE_2, + .hfi_id =3D HFI_PROP_STAGE, + .set =3D iris_set_stage, + }, + { + .cap_id =3D POC, + .min =3D 0, + .max =3D 2, + .step_or_mask =3D 1, + .value =3D 1, + .hfi_id =3D HFI_PROP_PIC_ORDER_CNT_TYPE, + }, + { + .cap_id =3D CODED_FRAMES, + .min =3D CODED_FRAMES_PROGRESSIVE, + .max =3D CODED_FRAMES_PROGRESSIVE, + .step_or_mask =3D 0, + .value =3D CODED_FRAMES_PROGRESSIVE, + .hfi_id =3D HFI_PROP_CODED_FRAMES, + }, + { + .cap_id =3D BIT_DEPTH, + .min =3D BIT_DEPTH_8, + .max =3D BIT_DEPTH_8, + .step_or_mask =3D 1, + .value =3D BIT_DEPTH_8, + .hfi_id =3D HFI_PROP_LUMA_CHROMA_BIT_DEPTH, + }, + { + .cap_id =3D RAP_FRAME, + .min =3D 0, + .max =3D 1, + .step_or_mask =3D 1, + .value =3D 1, + .hfi_id =3D HFI_PROP_DEC_START_FROM_RAP_FRAME, + .flags =3D CAP_FLAG_INPUT_PORT, + .set =3D iris_set_u32, + }, +}; + +static const struct platform_inst_fw_cap inst_fw_cap_gen2_ar50lt_enc[] =3D= { + { + .cap_id =3D PROFILE_H264, + .min =3D V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, + .max =3D V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH), + .value =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, + .hfi_id =3D HFI_PROP_PROFILE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_profile, + }, + { + .cap_id =3D PROFILE_HEVC, + .min =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, + .max =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) | + BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE), + .value =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, + .hfi_id =3D HFI_PROP_PROFILE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_profile, + }, + { + .cap_id =3D LEVEL_H264, + .min =3D V4L2_MPEG_VIDEO_H264_LEVEL_1_0, + .max =3D V4L2_MPEG_VIDEO_H264_LEVEL_4_2, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2), + .value =3D V4L2_MPEG_VIDEO_H264_LEVEL_4_2, + .hfi_id =3D HFI_PROP_LEVEL, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_level, + }, + { + .cap_id =3D LEVEL_HEVC, + .min =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_1, + .max =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1), + .value =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1, + .hfi_id =3D HFI_PROP_LEVEL, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_level, + }, + { + .cap_id =3D STAGE, + .min =3D STAGE_1, + .max =3D STAGE_2, + .step_or_mask =3D 1, + .value =3D STAGE_2, + .hfi_id =3D HFI_PROP_STAGE, + .set =3D iris_set_stage, + }, + { + .cap_id =3D HEADER_MODE, + .min =3D V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE, + .max =3D V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) | + BIT(V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME), + .value =3D V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME, + .hfi_id =3D HFI_PROP_SEQ_HEADER_MODE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_header_mode_gen2, + }, + { + .cap_id =3D PREPEND_SPSPPS_TO_IDR, + .min =3D 0, + .max =3D 1, + .step_or_mask =3D 1, + .value =3D 0, + }, + { + .cap_id =3D BITRATE, + .min =3D 1, + .max =3D BITRATE_MAX_AR50LT, + .step_or_mask =3D 1, + .value =3D BITRATE_DEFAULT_AR50LT, + .hfi_id =3D HFI_PROP_TOTAL_BITRATE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_bitrate_gen2, + }, + { + .cap_id =3D BITRATE_PEAK, + .min =3D 1, + .max =3D BITRATE_MAX_AR50LT, + .step_or_mask =3D 1, + .value =3D BITRATE_DEFAULT_AR50LT, + .hfi_id =3D HFI_PROP_TOTAL_PEAK_BITRATE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_peak_bitrate, + }, + { + .cap_id =3D BITRATE_MODE, + .min =3D V4L2_MPEG_VIDEO_BITRATE_MODE_VBR, + .max =3D V4L2_MPEG_VIDEO_BITRATE_MODE_CBR, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) | + BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_CBR), + .value =3D V4L2_MPEG_VIDEO_BITRATE_MODE_VBR, + .hfi_id =3D HFI_PROP_RATE_CONTROL, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_bitrate_mode_gen2, + }, + { + .cap_id =3D TIME_DELTA_BASED_RC, + .min =3D 0, + .max =3D 1, + .step_or_mask =3D 1, + .value =3D 0, + .hfi_id =3D HFI_PROP_TIME_DELTA_BASED_RATE_CONTROL, + .flags =3D CAP_FLAG_OUTPUT_PORT, + .set =3D iris_set_time_delta_based_rc, + }, + { + .cap_id =3D FRAME_SKIP_MODE, + .min =3D V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED, + .max =3D V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED) | + BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_LEVEL_LIMIT) | + BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT), + .value =3D V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + }, + { + .cap_id =3D FRAME_RC_ENABLE, + .min =3D 0, + .max =3D 1, + .step_or_mask =3D 1, + .value =3D 1, + }, + { + .cap_id =3D GOP_SIZE, + .min =3D 0, + .max =3D INT_MAX, + .step_or_mask =3D 1, + .value =3D 2 * DEFAULT_FPS - 1, + .hfi_id =3D HFI_PROP_MAX_GOP_FRAMES, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_u32, + }, + { + .cap_id =3D ENTROPY_MODE, + .min =3D V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC, + .max =3D V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC) | + BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC), + .value =3D V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC, + .hfi_id =3D HFI_PROP_CABAC_SESSION, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_entropy_mode_gen2, + }, + { + .cap_id =3D MIN_FRAME_QP_H264, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT_AR50LT, + .hfi_id =3D HFI_PROP_MIN_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT, + .set =3D iris_set_min_qp, + }, + { + .cap_id =3D MIN_FRAME_QP_HEVC, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT_AR50LT, + .hfi_id =3D HFI_PROP_MIN_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT, + .set =3D iris_set_min_qp, + }, + { + .cap_id =3D MAX_FRAME_QP_H264, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + .hfi_id =3D HFI_PROP_MAX_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT, + .set =3D iris_set_max_qp, + }, + { + .cap_id =3D MAX_FRAME_QP_HEVC, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + .hfi_id =3D HFI_PROP_MAX_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT, + .set =3D iris_set_max_qp, + }, + { + .cap_id =3D I_FRAME_MIN_QP_H264, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT_AR50LT, + }, + { + .cap_id =3D I_FRAME_MIN_QP_HEVC, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT_AR50LT, + }, + { + .cap_id =3D P_FRAME_MIN_QP_H264, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT_AR50LT, + }, + { + .cap_id =3D P_FRAME_MIN_QP_HEVC, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT_AR50LT, + }, + { + .cap_id =3D B_FRAME_MIN_QP_H264, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT_AR50LT, + }, + { + .cap_id =3D B_FRAME_MIN_QP_HEVC, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT_AR50LT, + }, + { + .cap_id =3D I_FRAME_MAX_QP_H264, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + }, + { + .cap_id =3D I_FRAME_MAX_QP_HEVC, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + }, + { + .cap_id =3D P_FRAME_MAX_QP_H264, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + }, + { + .cap_id =3D P_FRAME_MAX_QP_HEVC, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + }, + { + .cap_id =3D B_FRAME_MAX_QP_H264, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + }, + { + .cap_id =3D B_FRAME_MAX_QP_HEVC, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + }, + { + .cap_id =3D I_FRAME_QP_H264, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D DEFAULT_QP, + .hfi_id =3D HFI_PROP_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_frame_qp, + }, + { + .cap_id =3D I_FRAME_QP_HEVC, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D DEFAULT_QP, + .hfi_id =3D HFI_PROP_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_frame_qp, + }, + { + .cap_id =3D P_FRAME_QP_H264, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D DEFAULT_QP, + .hfi_id =3D HFI_PROP_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_frame_qp, + }, + { + .cap_id =3D P_FRAME_QP_HEVC, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D DEFAULT_QP, + .hfi_id =3D HFI_PROP_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_frame_qp, + }, + { + .cap_id =3D B_FRAME_QP_H264, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D DEFAULT_QP, + .hfi_id =3D HFI_PROP_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_frame_qp, + }, + { + .cap_id =3D B_FRAME_QP_HEVC, + .min =3D MIN_QP_8BIT_AR50LT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D DEFAULT_QP, + .hfi_id =3D HFI_PROP_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_frame_qp, + }, + { + .cap_id =3D INPUT_BUF_HOST_MAX_COUNT, + .min =3D DEFAULT_MAX_HOST_BUF_COUNT, + .max =3D DEFAULT_MAX_HOST_BURST_BUF_COUNT, + .step_or_mask =3D 1, + .value =3D DEFAULT_MAX_HOST_BUF_COUNT, + .hfi_id =3D HFI_PROP_BUFFER_HOST_MAX_COUNT, + .flags =3D CAP_FLAG_INPUT_PORT, + .set =3D iris_set_u32, + }, + { + .cap_id =3D OUTPUT_BUF_HOST_MAX_COUNT, + .min =3D DEFAULT_MAX_HOST_BUF_COUNT, + .max =3D DEFAULT_MAX_HOST_BURST_BUF_COUNT, + .step_or_mask =3D 1, + .value =3D DEFAULT_MAX_HOST_BUF_COUNT, + .hfi_id =3D HFI_PROP_BUFFER_HOST_MAX_COUNT, + .flags =3D CAP_FLAG_OUTPUT_PORT, + .set =3D iris_set_u32, + }, + { + .cap_id =3D IR_TYPE, + .min =3D V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM, + .max =3D V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM, + .step_or_mask =3D BIT(V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RAND= OM), + .value =3D V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + }, + { + .cap_id =3D IR_PERIOD, + .min =3D 0, + .max =3D INT_MAX, + .step_or_mask =3D 1, + .value =3D 0, + .flags =3D CAP_FLAG_OUTPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_ir_period_gen2, + }, + { + .cap_id =3D LTR_COUNT, + .min =3D 0, + .max =3D MAX_LTR_FRAME_COUNT_GEN2, + .step_or_mask =3D 1, + .value =3D 0, + .hfi_id =3D HFI_PROP_LTR_COUNT, + .flags =3D CAP_FLAG_OUTPUT_PORT, + .set =3D iris_set_ltr_count_gen2, + }, + { + .cap_id =3D USE_LTR, + .min =3D 0, + .max =3D ((1 << MAX_LTR_FRAME_COUNT_GEN2) - 1), + .step_or_mask =3D 0, + .value =3D 0, + .hfi_id =3D HFI_PROP_LTR_USE, + .flags =3D CAP_FLAG_INPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_use_and_mark_ltr, + }, + { + .cap_id =3D MARK_LTR, + .min =3D INVALID_DEFAULT_MARK_OR_USE_LTR, + .max =3D (MAX_LTR_FRAME_COUNT_GEN2 - 1), + .step_or_mask =3D 1, + .value =3D INVALID_DEFAULT_MARK_OR_USE_LTR, + .hfi_id =3D HFI_PROP_LTR_MARK, + .flags =3D CAP_FLAG_INPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_use_and_mark_ltr, + }, + { + .cap_id =3D B_FRAME, + .min =3D 0, + .max =3D 1, + .step_or_mask =3D 1, + .value =3D 0, + .hfi_id =3D HFI_PROP_MAX_B_FRAMES, + .flags =3D CAP_FLAG_OUTPUT_PORT, + .set =3D iris_set_u32, + }, + { + .cap_id =3D LAYER_ENABLE, + .min =3D 0, + .max =3D 1, + .step_or_mask =3D 1, + .value =3D 0, + .flags =3D CAP_FLAG_OUTPUT_PORT, + }, + { + .cap_id =3D LAYER_TYPE_H264, + .min =3D V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_B, + .max =3D V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_P, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_B) | + BIT(V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_P), + .value =3D V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_P, + .hfi_id =3D HFI_PROP_LAYER_ENCODING_TYPE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_layer_type, + }, + { + .cap_id =3D LAYER_TYPE_HEVC, + .min =3D V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_B, + .max =3D V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_P, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_B) | + BIT(V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_P), + .value =3D V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_P, + .hfi_id =3D HFI_PROP_LAYER_ENCODING_TYPE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_layer_type, + }, + { + .cap_id =3D LAYER_COUNT_H264, + .min =3D 0, + .max =3D 5, + .step_or_mask =3D 1, + .value =3D 0, + .hfi_id =3D HFI_PROP_LAYER_COUNT, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_layer_count_gen2, + }, + { + .cap_id =3D LAYER_COUNT_HEVC, + .min =3D 0, + .max =3D 5, + .step_or_mask =3D 1, + .value =3D 0, + .hfi_id =3D HFI_PROP_LAYER_COUNT, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_layer_count_gen2, + }, + { + .cap_id =3D LAYER0_BITRATE_H264, + .min =3D 1, + .max =3D BITRATE_MAX_AR50LT, + .step_or_mask =3D 1, + .value =3D BITRATE_DEFAULT_AR50LT, + .hfi_id =3D HFI_PROP_BITRATE_LAYER1, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_layer_bitrate, + }, + { + .cap_id =3D LAYER1_BITRATE_H264, + .min =3D 1, + .max =3D BITRATE_MAX_AR50LT, + .step_or_mask =3D 1, + .value =3D BITRATE_DEFAULT_AR50LT, + .hfi_id =3D HFI_PROP_BITRATE_LAYER2, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_layer_bitrate, + }, + { + .cap_id =3D LAYER2_BITRATE_H264, + .min =3D 1, + .max =3D BITRATE_MAX_AR50LT, + .step_or_mask =3D 1, + .value =3D BITRATE_DEFAULT_AR50LT, + .hfi_id =3D HFI_PROP_BITRATE_LAYER3, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_layer_bitrate, + }, + { + .cap_id =3D LAYER3_BITRATE_H264, + .min =3D 1, + .max =3D BITRATE_MAX_AR50LT, + .step_or_mask =3D 1, + .value =3D BITRATE_DEFAULT_AR50LT, + .hfi_id =3D HFI_PROP_BITRATE_LAYER4, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_layer_bitrate, + }, + { + .cap_id =3D LAYER4_BITRATE_H264, + .min =3D 1, + .max =3D BITRATE_MAX_AR50LT, + .step_or_mask =3D 1, + .value =3D BITRATE_DEFAULT_AR50LT, + .hfi_id =3D HFI_PROP_BITRATE_LAYER5, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_layer_bitrate, + }, + { + .cap_id =3D LAYER5_BITRATE_H264, + .min =3D 1, + .max =3D BITRATE_MAX_AR50LT, + .step_or_mask =3D 1, + .value =3D BITRATE_DEFAULT_AR50LT, + .hfi_id =3D HFI_PROP_BITRATE_LAYER6, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_layer_bitrate, + }, + { + .cap_id =3D LAYER0_BITRATE_HEVC, + .min =3D 1, + .max =3D BITRATE_MAX_AR50LT, + .step_or_mask =3D 1, + .value =3D BITRATE_DEFAULT_AR50LT, + .hfi_id =3D HFI_PROP_BITRATE_LAYER1, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_layer_bitrate, + }, + { + .cap_id =3D LAYER1_BITRATE_HEVC, + .min =3D 1, + .max =3D BITRATE_MAX_AR50LT, + .step_or_mask =3D 1, + .value =3D BITRATE_DEFAULT_AR50LT, + .hfi_id =3D HFI_PROP_BITRATE_LAYER2, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_layer_bitrate, + }, + { + .cap_id =3D LAYER2_BITRATE_HEVC, + .min =3D 1, + .max =3D BITRATE_MAX_AR50LT, + .step_or_mask =3D 1, + .value =3D BITRATE_DEFAULT_AR50LT, + .hfi_id =3D HFI_PROP_BITRATE_LAYER3, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_layer_bitrate, + }, + { + .cap_id =3D LAYER3_BITRATE_HEVC, + .min =3D 1, + .max =3D BITRATE_MAX_AR50LT, + .step_or_mask =3D 1, + .value =3D BITRATE_DEFAULT_AR50LT, + .hfi_id =3D HFI_PROP_BITRATE_LAYER4, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_layer_bitrate, + }, + { + .cap_id =3D LAYER4_BITRATE_HEVC, + .min =3D 1, + .max =3D BITRATE_MAX_AR50LT, + .step_or_mask =3D 1, + .value =3D BITRATE_DEFAULT_AR50LT, + .hfi_id =3D HFI_PROP_BITRATE_LAYER5, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_layer_bitrate, + }, + { + .cap_id =3D LAYER5_BITRATE_HEVC, + .min =3D 1, + .max =3D BITRATE_MAX_AR50LT, + .step_or_mask =3D 1, + .value =3D BITRATE_DEFAULT_AR50LT, + .hfi_id =3D HFI_PROP_BITRATE_LAYER6, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_layer_bitrate, + }, + { + .cap_id =3D REQUEST_SYNC_FRAME, + .min =3D 0, + .max =3D 1, + .step_or_mask =3D 1, + .value =3D 0, + .hfi_id =3D HFI_PROP_REQUEST_SYNC_FRAME, + .flags =3D CAP_FLAG_INPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_req_sync_frame, + }, +}; + +static const u32 iris_hfi_gen2_ar50lt_dec_ip_int_buf_tbl[] =3D { + BUF_BIN, + BUF_COMV, + BUF_NON_COMV, + BUF_LINE, +}; + +const struct iris_firmware_data iris_hfi_gen2_ar50lt_data =3D { + .init_hfi_ops =3D iris_hfi_gen2_sys_ops_init, + + .core_arch =3D VIDEO_ARCH_LX, + + .inst_fw_caps_dec =3D inst_fw_cap_gen2_ar50lt_dec, + .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_gen2_ar50lt_dec), + .inst_fw_caps_enc =3D inst_fw_cap_gen2_ar50lt_enc, + .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_gen2_ar50lt_enc), + .dec_input_config_params_default =3D + sm8550_vdec_input_config_params_default, + .dec_input_config_params_default_size =3D + ARRAY_SIZE(sm8550_vdec_input_config_params_default), + .dec_input_config_params_hevc =3D + sm8550_vdec_input_config_param_hevc, + .dec_input_config_params_hevc_size =3D + ARRAY_SIZE(sm8550_vdec_input_config_param_hevc), + .dec_input_config_params_vp9 =3D + sm8550_vdec_input_config_param_vp9, + .dec_input_config_params_vp9_size =3D + ARRAY_SIZE(sm8550_vdec_input_config_param_vp9), + .dec_output_config_params =3D + sm8550_vdec_output_config_params, + .dec_output_config_params_size =3D + ARRAY_SIZE(sm8550_vdec_output_config_params), + + .enc_input_config_params =3D + sm8550_venc_input_config_params, + .enc_input_config_params_size =3D + ARRAY_SIZE(sm8550_venc_input_config_params), + .enc_output_config_params =3D + sm8550_venc_output_config_params, + .enc_output_config_params_size =3D + ARRAY_SIZE(sm8550_venc_output_config_params), + + .dec_input_prop =3D sm8550_vdec_subscribe_input_properties, + .dec_input_prop_size =3D ARRAY_SIZE(sm8550_vdec_subscribe_input_propertie= s), + .dec_output_prop_avc =3D sm8550_vdec_subscribe_output_properties_avc, + .dec_output_prop_avc_size =3D + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc), + .dec_output_prop_hevc =3D sm8550_vdec_subscribe_output_properties_hevc, + .dec_output_prop_hevc_size =3D + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc), + .dec_output_prop_vp9 =3D sm8550_vdec_subscribe_output_properties_vp9, + .dec_output_prop_vp9_size =3D + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9), + + .dec_ip_int_buf_tbl =3D iris_hfi_gen2_ar50lt_dec_ip_int_buf_tbl, + .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(iris_hfi_gen2_ar50lt_dec_ip_int_b= uf_tbl), + .dec_op_int_buf_tbl =3D sm8550_dec_op_int_buf_tbl, + .dec_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), + + .enc_ip_int_buf_tbl =3D sm8550_enc_ip_int_buf_tbl, + .enc_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_ip_int_buf_tbl), + .enc_op_int_buf_tbl =3D sm8550_enc_op_int_buf_tbl, + .enc_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), +}; diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 07cd02d6bfc8..5593820bbf8a 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -58,6 +58,7 @@ extern const struct iris_firmware_data iris_hfi_gen1_data; extern const struct iris_firmware_data iris_hfi_gen1_ar50lt_data; extern const struct iris_firmware_data iris_hfi_gen2_data; extern const struct iris_firmware_data iris_hfi_milos_data; +extern const struct iris_firmware_data iris_hfi_gen2_ar50lt_data; =20 extern const struct iris_platform_data milos_data; extern const struct iris_platform_data qcm2290_data; diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu_ar50lt.c b/= drivers/media/platform/qcom/iris/iris_platform_vpu_ar50lt.c index 92f7e2546539..99c839a0424f 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu_ar50lt.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu_ar50lt.c @@ -19,6 +19,12 @@ static const struct iris_firmware_desc iris_vpu_ar50lt_p= 1_gen1_s6_desc =3D { .fwname =3D "qcom/venus-6.0/venus.mbn", }; =20 +static const struct iris_firmware_desc iris_vpu_ar50lt_p1_gen2_s6_desc =3D= { + .firmware_data =3D &iris_hfi_gen2_ar50lt_data, + .get_vpu_buffer_size =3D iris_vpu_ar50lt_gen2_buf_size, + .fwname =3D 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Follow the approach used by other platforms and skip QCM2290 in the Venus driver if Iris is enabled. Reviewed-by: Dikshita Agarwal Reviewed-by: Vikash Garodia Signed-off-by: Dmitry Baryshkov Tested-by: Gourav Kumar --- drivers/media/platform/qcom/venus/core.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/venus/core.c b/drivers/media/platf= orm/qcom/venus/core.c index 243e342b0ae7..3c88594eb1d0 100644 --- a/drivers/media/platform/qcom/venus/core.c +++ b/drivers/media/platform/qcom/venus/core.c @@ -1118,7 +1118,6 @@ static const struct venus_resources sc7280_res =3D { .dec_nodename =3D "video-decoder", .enc_nodename =3D "video-encoder", }; -#endif =20 static const struct bw_tbl qcm2290_bw_table_dec[] =3D { { 352800, 597000, 0, 746000, 0 }, /* 1080p@30 + 720p@30 */ @@ -1169,13 +1168,16 @@ static const struct venus_resources qcm2290_res =3D= { .enc_nodename =3D "video-encoder", .min_fw =3D &min_fw, }; +#endif =20 static const struct of_device_id venus_dt_match[] =3D { { .compatible =3D "qcom,msm8916-venus", .data =3D &msm8916_res, }, { .compatible =3D "qcom,msm8939-venus", .data =3D &msm8939_res, }, { .compatible =3D "qcom,msm8996-venus", .data =3D &msm8996_res, }, { .compatible =3D "qcom,msm8998-venus", .data =3D &msm8998_res, }, +#if (!IS_ENABLED(CONFIG_VIDEO_QCOM_IRIS)) { .compatible =3D "qcom,qcm2290-venus", .data =3D &qcm2290_res, }, +#endif { .compatible =3D "qcom,sc7180-venus", .data =3D &sc7180_res, }, { .compatible =3D "qcom,sdm660-venus", .data =3D &sdm660_res, }, { .compatible =3D "qcom,sdm845-venus", .data =3D &sdm845_res, }, --=20 2.47.3 From nobody Fri Oct 2 14:03:53 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C290F477E55 for ; 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Suggested-by: Vishnu Reddy Reviewed-by: Vikash Garodia Signed-off-by: Dmitry Baryshkov Tested-by: Gourav Kumar --- drivers/media/platform/qcom/iris/iris_hfi_gen1.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1.c b/drivers/med= ia/platform/qcom/iris/iris_hfi_gen1.c index 548609315b85..1f87cef986ef 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1.c @@ -13,7 +13,7 @@ #define BITRATE_MAX 160000000 #define BITRATE_STEP 100 =20 -static struct platform_inst_fw_cap inst_fw_cap_sm8250_dec[] =3D { +static const struct platform_inst_fw_cap inst_fw_cap_sm8250_dec[] =3D { { .cap_id =3D PIPE, /* .max, .min and .value are set via platform data */ --=20 2.47.3