From nobody Fri Oct 2 13:13:38 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 901933CB56F; Fri, 31 Jul 2026 09:52:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785491530; cv=none; b=kV3++yHWavu13kmKymbALOyqn+CMig2IOh5uLGkuA4654/OBfkDIXhCCbVakxyH/gasfOgo3Owo8612TghfhNfafA+r3G9Ce2Dm5EUwX0PxkXSV5FLBjYlJhvIH659/+h9474gtAamriavb5zCpZuDjwVqZhRFEnD+QsI/Bf17c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785491530; c=relaxed/simple; bh=R74AtMbgpIt0PXlHo1ostqIg4CNWpHDt6Sacj9pb7Sw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZiE/fmwtWehrjZ6WwnG3QtfoRj8IrAgOmftaeszBsGBnkVV+/zeCCPfcQ7c+yzgjLTAAyYtKINDb+NH9uXVVw7aCM/+WUzgdEUDlNws5KeN8gDkugiY6HTwbXLPdHeQzNfxEAgA0Y/5Zts17F51QbIVAgIYCc69O2sUTLVjnUFE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=WvpybG+B; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="WvpybG+B" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id E98DF1A1354; Fri, 31 Jul 2026 09:52:03 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id BCE2B6039A; Fri, 31 Jul 2026 09:52:03 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 2A47411C16646; Fri, 31 Jul 2026 11:51:56 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1785491518; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=TE6fxPaU+LUiziMgyvgeiYBZXwhy0M3LvlV9yMFf+Sk=; b=WvpybG+BjrNKPw5z8j5KqhVd1uz8+y+O7cLuUpeAKVW541ueFiOWUb45sFRV9UuBg/DRLe 6DCRkMrGGmWBTljGoWJzEWGYT37ka+BSKhNya5THHqgx5T1sHQNN6r4gfk5bFh2uuhF2ZD EXnusE8yD8AhIPW0fwA+3H9VlSgKiO2g6AoqVVaGolLdER+H55oqDlPGI6Ql69rDn9zjaZ ISdLPlFFuwpBiueVHRhLq86vN5kgCe/A2qnvSQLAFV0RkY6CXOjC+xaDYkvt0RO6PkxzMv u/Zhpew4QL27ErkNQRCMxCbhJyDtP29ZA1qS5QjMcwZ+8+mYPi8Yz089p5/jYw== From: "Thomas Perrot (Schneider Electric)" Date: Fri, 31 Jul 2026 11:51:41 +0200 Subject: [PATCH v8 1/5] dt-bindings: vendor-prefixes: Add AAEON vendor prefix Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260731-dev-b4-aaeon-mcu-driver-v8-1-9ab00e80df2a@bootlin.com> References: <20260731-dev-b4-aaeon-mcu-driver-v8-0-9ab00e80df2a@bootlin.com> In-Reply-To: <20260731-dev-b4-aaeon-mcu-driver-v8-0-9ab00e80df2a@bootlin.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , =?utf-8?q?J=C3=A9r=C3=A9mie_Dautheribes?= , Wim Van Sebroeck , Guenter Roeck , Lee Jones Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-watchdog@vger.kernel.org, Thomas Petazzoni , Miquel Raynal , "Thomas Perrot (Schneider Electric)" , Krzysztof Kozlowski X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Add the AAEON vendor prefix to support the AAEON SRG-IMX8P MCU driver devicetree bindings. Acked-by: Krzysztof Kozlowski Signed-off-by: Thomas Perrot (Schneider Electric) --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index c7591b2aec2a..0f84ee93b3a8 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -32,6 +32,8 @@ patternProperties: description: 8devices, UAB "^9tripod,.*": description: Shenzhen 9Tripod Innovation and Development CO., LTD. + "^aaeon,.*": + description: AAEON "^abb,.*": description: ABB "^abilis,.*": --=20 2.55.0 From nobody Fri Oct 2 13:13:38 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E062D3C3F6A for ; Fri, 31 Jul 2026 09:52:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785491537; cv=none; b=FqSsq6jjoGp9rxERsxVH4fdUqFtvxn03oTFiu2JPRbEKt3i3qARzEEwapev5yQdJFQNKTKT24hNS+Kbzvmip2ujG/xCfaZAId2evcBF3eVNVQy83UC20PlIUIx2dknP9hFhSj8sOnr7rRIw9BF7T5cQqpELn9yB05N1tR5UBzHE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785491537; c=relaxed/simple; bh=1XSlkopDD8hgacc2fQinF3x7ZXQZ7mJqQB/vEJrEaWA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=TcsSWArGXwGNmq0rfTOXXhHWdK1jlPgNTO9q1ReGTUmqv/1G3YVgpSdEemr1AWKg9DPg52Il4e2NdNAbRrjoMkApijr1qJPR5OnzJlNf/hjwIYNkv2SSBE7jvSLSgBVc8JZisfgo6UKozbW5qS/sABxJDbgwmN02fE41BPIJiC4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=UgPbg4LV; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="UgPbg4LV" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 65D274E41048; Fri, 31 Jul 2026 09:52:10 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 3237E6039A; Fri, 31 Jul 2026 09:52:10 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id B85EF11C1664B; Fri, 31 Jul 2026 11:52:02 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1785491525; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=cGECx7XBlb4XEZT9olLrpyfAunE/XtJfgEve/LPx17Q=; b=UgPbg4LVCVrSjUNFutD2s7D6Ma6TpQYzsZMoMV9W8h5grJXoM6XijykAO9iS+r+WXA7Ndw c3G/zZOxJQ4ncpTcsM9667zgounkAlXbZ2qpq5nk4TcXP8V85KZDEVuIouxmIQkVt9aQ/C ppG6BEIamzCsDCjV5hLwETBvXjLlNs9GpsiFQPYfrD3RFw/u6ofpYbwn5XtM7VrsnWDuaS Wnt9IY7pp2abZc/2jBHv2WLvv45HWmLAzKoqeeMlMrw8oIUEq/ELDE8TUzLZ7n7fqWjYAw u+rUY78nmco6LFRXiARGyHeeKOyNGyachRozU+RIFpWqbVWHta2hyTYcGT0TKw== From: "Thomas Perrot (Schneider Electric)" Date: Fri, 31 Jul 2026 11:51:42 +0200 Subject: [PATCH v8 2/5] dt-bindings: mfd: Add AAEON embedded controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260731-dev-b4-aaeon-mcu-driver-v8-2-9ab00e80df2a@bootlin.com> References: <20260731-dev-b4-aaeon-mcu-driver-v8-0-9ab00e80df2a@bootlin.com> In-Reply-To: <20260731-dev-b4-aaeon-mcu-driver-v8-0-9ab00e80df2a@bootlin.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , =?utf-8?q?J=C3=A9r=C3=A9mie_Dautheribes?= , Wim Van Sebroeck , Guenter Roeck , Lee Jones Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-watchdog@vger.kernel.org, Thomas Petazzoni , Miquel Raynal , "Thomas Perrot (Schneider Electric)" , Conor Dooley X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Add device tree binding documentation for the AAEON embedded controller (MCU). This microcontroller is found on AAEON embedded boards, it is connected via I2C and provides GPIO control and a watchdog timer. Reviewed-by: Conor Dooley Signed-off-by: Thomas Perrot (Schneider Electric) --- .../bindings/mfd/aaeon,srg-imx8p-mcu.yaml | 67 ++++++++++++++++++= ++++ MAINTAINERS | 6 ++ 2 files changed, 73 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/aaeon,srg-imx8p-mcu.yaml= b/Documentation/devicetree/bindings/mfd/aaeon,srg-imx8p-mcu.yaml new file mode 100644 index 000000000000..034fb7b42551 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/aaeon,srg-imx8p-mcu.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/aaeon,srg-imx8p-mcu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AAEON Embedded Controller + +maintainers: + - J=C3=A9r=C3=A9mie Dautheribes + - Thomas Perrot + +description: + AAEON embeds a microcontroller on Standard RISC Gateway with ARM i.MX8M = Plus + Quad-Core boards providing GPIO control and watchdog timer. + + This MCU is connected via I2C bus. + + Its GPIO controller provides 7 GPOs and 12 GPIOs. + + Its watchdog has a fixed maximum hardware heartbeat of 25 seconds and su= pports + a timeout of 240 seconds through automatic pinging. + The timeout is not programmable and cannot be changed via device tree pr= operties. + +properties: + compatible: + const: aaeon,srg-imx8p-mcu + + reg: + maxItems: 1 + + gpio-controller: true + + "#gpio-cells": + const: 2 + + gpio-line-names: + minItems: 1 + maxItems: 19 + +required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + +additionalProperties: false + +examples: + - | + i2c { + #address-cells =3D <1>; + #size-cells =3D <0>; + + embedded-controller@62 { + compatible =3D "aaeon,srg-imx8p-mcu"; + reg =3D <0x62>; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "gpo-1", "gpo-2", "gpo-3", "gpo-4", + "gpo-5", "gpo-6", "gpo-7", + "gpio-1", "gpio-2", "gpio-3", "gpio-4", + "gpio-5", "gpio-6", "gpio-7", "gpio-8", + "gpio-9", "gpio-10", "gpio-11", "gpio-12"; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index c9e416ba74c6..ea9d55f76f35 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -186,6 +186,12 @@ W: http://www.adaptec.com/ F: Documentation/scsi/aacraid.rst F: drivers/scsi/aacraid/ =20 +AAEON SRG-IMX8P CONTROLLER MFD DRIVER +M: Thomas Perrot +R: J=C3=A9r=C3=A9mie Dautheribes +S: Maintained +F: Documentation/devicetree/bindings/mfd/aaeon,srg-imx8p-mcu.yaml + AAEON UPBOARD FPGA MFD DRIVER M: Thomas Richard S: Maintained --=20 2.55.0 From nobody Fri Oct 2 13:13:38 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CFB063CC7FF; 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arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="rQSMTXIG" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 8A49E4E41047; Fri, 31 Jul 2026 09:52:12 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 573C66039A; Fri, 31 Jul 2026 09:52:12 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 74D7B11C1664E; Fri, 31 Jul 2026 11:52:09 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1785491531; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=Tp01llFLrHwugrD4kRWCdOslDQolqP63HCs3PmqTPHs=; b=rQSMTXIG+1RZaE7lu1q5nk/cysxG1L2ccO99ssROWCt1U6hQR1fwPmXBkWBxiIoGdczgY/ 6YSBhjcEQPGB4KoJN/ZLckvuHR0oIhbtOFnIYMB5VX+DlQzo2QmqD85t4oIxboT/ow2GB9 hBsCidgXVrLPONRYfv7TjCO8kw1Sdb4ok7mRlLhKWE/6Drt+RWYSeonvXMhYL68dc378YU f9TloBcl7SLhUwevf0/2u4Onfki2nEW45auYuGsz6I+BNlL04+tlgjm1WhF6JyAvfOAZ2F TAOzy0E0g+VE6s3PQ1auKNUHErIPWV49evbgKNQc1wpStwg6mH7q2j/si8CNuQ== From: "Thomas Perrot (Schneider Electric)" Date: Fri, 31 Jul 2026 11:51:43 +0200 Subject: [PATCH v8 3/5] mfd: aaeon: Add SRG-IMX8P MCU driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260731-dev-b4-aaeon-mcu-driver-v8-3-9ab00e80df2a@bootlin.com> References: <20260731-dev-b4-aaeon-mcu-driver-v8-0-9ab00e80df2a@bootlin.com> In-Reply-To: <20260731-dev-b4-aaeon-mcu-driver-v8-0-9ab00e80df2a@bootlin.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , =?utf-8?q?J=C3=A9r=C3=A9mie_Dautheribes?= , Wim Van Sebroeck , Guenter Roeck , Lee Jones Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-watchdog@vger.kernel.org, Thomas Petazzoni , Miquel Raynal , "Thomas Perrot (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Add Multi-Function Device (MFD) driver for the Aaeon SRG-IMX8P embedded controller. This driver provides the core I2C communication interface and registers child devices (GPIO and watchdog controllers). The driver implements a custom regmap bus over I2C to match the MCU's fixed 3-byte command format [opcode, arg, value]. Register addresses are encoded as 16-bit values (opcode << 8 | arg) using the AAEON_MCU_REG() macro defined in the shared header. The regmap instance is shared with child drivers via dev_get_regmap(). Concurrent I2C accesses from child drivers are serialized by regmap's built-in locking. I2C transfers use heap-allocated DMA-safe buffers rather than stack-allocated ones, as required by I2C controllers that perform DMA. Regmap caching is enabled (REGCACHE_MAPLE) with a volatile_reg callback that marks GPIO input read registers (opcode 0x72) and the watchdog status register (opcode 0x63, arg 0x02) as volatile. All other registers written by the driver (GPIO direction, GPO state, watchdog control) are stable and can be safely cached. Co-developed-by: J=C3=A9r=C3=A9mie Dautheribes (Schneider Electric) Signed-off-by: J=C3=A9r=C3=A9mie Dautheribes (Schneider Electric) Signed-off-by: Thomas Perrot (Schneider Electric) --- MAINTAINERS | 2 + drivers/mfd/Kconfig | 11 +++ drivers/mfd/Makefile | 1 + drivers/mfd/aaeon-mcu.c | 207 ++++++++++++++++++++++++++++++++++++++= ++++ include/linux/mfd/aaeon-mcu.h | 40 ++++++++ 5 files changed, 261 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index ea9d55f76f35..f91b6a1826d0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -191,6 +191,8 @@ M: Thomas Perrot R: J=C3=A9r=C3=A9mie Dautheribes S: Maintained F: Documentation/devicetree/bindings/mfd/aaeon,srg-imx8p-mcu.yaml +F: drivers/mfd/aaeon-mcu.c +F: include/linux/mfd/aaeon-mcu.h =20 AAEON UPBOARD FPGA MFD DRIVER M: Thomas Richard diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index aace5766b38a..66f2e7757748 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -1561,6 +1561,17 @@ config ABX500_CORE remain unchanged when IC changes. Binding of the functions to actual register access is done by the IC core driver. =20 +config MFD_AAEON_MCU + tristate "Aaeon SRG-IMX8P MCU Driver" + depends on I2C + select MFD_CORE + select REGMAP + help + Select this option to enable support for the Aaeon SRG-IMX8P + onboard microcontroller (MCU). This driver provides the core + functionality to communicate with the MCU over I2C. The MCU + provides GPIO and watchdog functionality. + config AB8500_CORE bool "ST-Ericsson AB8500 Mixed Signal Power Management chip" depends on ABX500_CORE && MFD_DB8500_PRCMU diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index e75e8045c28a..34db5b033584 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_MFD_88PM860X) +=3D 88pm860x.o obj-$(CONFIG_MFD_88PM800) +=3D 88pm800.o 88pm80x.o obj-$(CONFIG_MFD_88PM805) +=3D 88pm805.o 88pm80x.o obj-$(CONFIG_MFD_88PM886_PMIC) +=3D 88pm886.o +obj-$(CONFIG_MFD_AAEON_MCU) +=3D aaeon-mcu.o obj-$(CONFIG_MFD_ACT8945A) +=3D act8945a.o obj-$(CONFIG_MFD_SM501) +=3D sm501.o obj-$(CONFIG_ARCH_BCM2835) +=3D bcm2835-pm.o diff --git a/drivers/mfd/aaeon-mcu.c b/drivers/mfd/aaeon-mcu.c new file mode 100644 index 000000000000..c06c99d02d64 --- /dev/null +++ b/drivers/mfd/aaeon-mcu.c @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Aaeon MCU driver + * + * Copyright (C) 2026 Bootlin + * Author: J=C3=A9r=C3=A9mie Dautheribes + * Author: Thomas Perrot + */ + +#include +#include +#include +#include +#include +#include +#include + +struct aaeon_mcu { + struct i2c_client *client; + u8 *cmd; /* DMA-safe 3-byte write buffer [opcode, arg, value] */ + u8 *response; /* DMA-safe 1-byte read buffer for MCU acknowledgment */ +}; + +static const struct mfd_cell aaeon_mcu_devs[] =3D { + MFD_CELL_BASIC("aaeon-mcu-wdt", NULL, NULL, 0, 0), + MFD_CELL_BASIC("aaeon-mcu-gpio", NULL, NULL, 0, 0), +}; + +/* Number of bytes in a MCU command: [opcode, arg, value] */ +#define AAEON_MCU_CMD_LEN 3 + +/* + * Custom regmap bus for the Aaeon MCU I2C protocol. + * + * The MCU uses a fixed 3-byte command format [opcode, arg, value] followed + * by a 1-byte response. It requires a STOP condition between the command + * write and the response read, so two separate i2c_transfer() calls are + * issued. The regmap lock serialises concurrent accesses from the GPIO + * and watchdog child drivers. + * + * Register addresses are encoded as a 16-bit big-endian value where the + * high byte is the opcode and the low byte is the argument, matching the + * wire layout produced by regmap for reg_bits=3D16. + */ + +static int aaeon_mcu_regmap_write(void *context, const void *data, size_t = count) +{ + struct aaeon_mcu *mcu =3D context; + struct i2c_client *client =3D mcu->client; + struct i2c_msg write_msg; + /* The MCU always sends a response byte after each command; discard it. */ + struct i2c_msg response_msg; + int ret; + + memcpy(mcu->cmd, data, count); + + write_msg.addr =3D client->addr; + write_msg.flags =3D I2C_M_DMA_SAFE; + write_msg.buf =3D mcu->cmd; + write_msg.len =3D count; + + response_msg.addr =3D client->addr; + response_msg.flags =3D I2C_M_RD | I2C_M_DMA_SAFE; + response_msg.buf =3D mcu->response; + response_msg.len =3D 1; + + ret =3D i2c_transfer(client->adapter, &write_msg, 1); + if (ret < 0) + return ret; + if (ret !=3D 1) + return -EIO; + + ret =3D i2c_transfer(client->adapter, &response_msg, 1); + if (ret < 0) + return ret; + if (ret !=3D 1) + return -EIO; + + return 0; +} + +static int aaeon_mcu_regmap_read(void *context, const void *reg_buf, + size_t reg_size, void *val_buf, size_t val_size) +{ + struct aaeon_mcu *mcu =3D context; + struct i2c_client *client =3D mcu->client; + struct i2c_msg write_msg; + struct i2c_msg read_msg; + int ret; + + /* + * reg_buf holds the 2-byte big-endian register address [opcode, arg]. + * Append a trailing 0x00 to form the full 3-byte MCU command. + */ + mcu->cmd[0] =3D ((u8 *)reg_buf)[0]; + mcu->cmd[1] =3D ((u8 *)reg_buf)[1]; + mcu->cmd[2] =3D 0x00; + + write_msg.addr =3D client->addr; + write_msg.flags =3D I2C_M_DMA_SAFE; + write_msg.buf =3D mcu->cmd; + write_msg.len =3D AAEON_MCU_CMD_LEN; + + read_msg.addr =3D client->addr; + read_msg.flags =3D I2C_M_RD | I2C_M_DMA_SAFE; + read_msg.buf =3D val_buf; + read_msg.len =3D val_size; + + ret =3D i2c_transfer(client->adapter, &write_msg, 1); + if (ret < 0) + return ret; + if (ret !=3D 1) + return -EIO; + + ret =3D i2c_transfer(client->adapter, &read_msg, 1); + if (ret < 0) + return ret; + if (ret !=3D 1) + return -EIO; + + return 0; +} + +static const struct regmap_bus aaeon_mcu_regmap_bus =3D { + .write =3D aaeon_mcu_regmap_write, + .read =3D aaeon_mcu_regmap_read, +}; + +static bool aaeon_mcu_volatile_reg(struct device *dev, unsigned int reg) +{ + /* + * GPIO input registers are driven by external signals and can change + * at any time without CPU involvement, always read from hardware. + * + * The watchdog status register reflects hardware state and can change + * autonomously. + * + * All other registers are written by the driver and their values are + * stable, so they can be safely cached. + */ + if ((reg >> 8) =3D=3D AAEON_MCU_READ_GPIO_OPCODE) + return true; + if (reg =3D=3D AAEON_MCU_REG(AAEON_MCU_CONTROL_WDT_OPCODE, 0x02)) + return true; + return false; +} + +static const struct regmap_config aaeon_mcu_regmap_config =3D { + .reg_bits =3D 16, + .val_bits =3D 8, + .reg_format_endian =3D REGMAP_ENDIAN_BIG, + .max_register =3D AAEON_MCU_MAX_REGISTER, + .volatile_reg =3D aaeon_mcu_volatile_reg, + .cache_type =3D REGCACHE_MAPLE, + .use_single_write =3D true, + .use_single_read =3D true, +}; + +static int aaeon_mcu_probe(struct i2c_client *client) +{ + struct aaeon_mcu *ddata; + struct regmap *regmap; + + ddata =3D devm_kzalloc(&client->dev, sizeof(*ddata), GFP_KERNEL); + if (!ddata) + return -ENOMEM; + + ddata->client =3D client; + + ddata->cmd =3D devm_kcalloc(&client->dev, AAEON_MCU_CMD_LEN, sizeof(*ddat= a->cmd), + GFP_KERNEL); + if (!ddata->cmd) + return -ENOMEM; + + ddata->response =3D devm_kzalloc(&client->dev, sizeof(*ddata->response), = GFP_KERNEL); + if (!ddata->response) + return -ENOMEM; + + regmap =3D devm_regmap_init(&client->dev, &aaeon_mcu_regmap_bus, + ddata, &aaeon_mcu_regmap_config); + if (IS_ERR(regmap)) + return dev_err_probe(&client->dev, PTR_ERR(regmap), + "failed to initialize regmap\n"); + + return devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_AUTO, + aaeon_mcu_devs, ARRAY_SIZE(aaeon_mcu_devs), + NULL, 0, NULL); +} + +static const struct of_device_id aaeon_mcu_of_match[] =3D { + { .compatible =3D "aaeon,srg-imx8p-mcu" }, + {}, +}; +MODULE_DEVICE_TABLE(of, aaeon_mcu_of_match); + +static struct i2c_driver aaeon_mcu_driver =3D { + .driver =3D { + .name =3D "aaeon-mcu", + .of_match_table =3D aaeon_mcu_of_match, + }, + .probe =3D aaeon_mcu_probe, +}; +module_i2c_driver(aaeon_mcu_driver); + +MODULE_DESCRIPTION("Aaeon MCU Driver"); +MODULE_AUTHOR("J=C3=A9r=C3=A9mie Dautheribes "); +MODULE_LICENSE("GPL"); diff --git a/include/linux/mfd/aaeon-mcu.h b/include/linux/mfd/aaeon-mcu.h new file mode 100644 index 000000000000..3a1aeec85d60 --- /dev/null +++ b/include/linux/mfd/aaeon-mcu.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Aaeon MCU driver definitions + * + * Copyright (C) 2026 Bootlin + * Author: J=C3=A9r=C3=A9mie Dautheribes + * Author: Thomas Perrot + */ + +#ifndef __LINUX_MFD_AAEON_MCU_H +#define __LINUX_MFD_AAEON_MCU_H + +/* + * MCU register address: the high byte is the command opcode, the low + * byte is the argument. This matches the 3-byte wire format + * [opcode, arg, value] used by the MCU I2C protocol. + */ +#define AAEON_MCU_REG(op, arg) (((op) << 8) | (arg)) + +/* + * Opcode for GPIO input reads. These registers are volatile, their values + * are driven by external signals and can change without CPU involvement. + * Used by the MFD driver's volatile_reg callback to bypass the regmap cac= he. + */ +#define AAEON_MCU_READ_GPIO_OPCODE 0x72 + +/* + * Opcode for watchdog control and status commands. + * The status register (arg=3D0x02) reflects hardware state and is volatil= e. + */ +#define AAEON_MCU_CONTROL_WDT_OPCODE 0x63 + +/* + * Highest register address in the MCU register map. + * The WRITE_GPIO opcode (0x77) with the highest GPIO argument (0x0B =3D 1= 1, + * i.e. MAX_GPIOS - 1) produces the largest encoded address. + */ +#define AAEON_MCU_MAX_REGISTER AAEON_MCU_REG(0x77, 0x0B) + +#endif /* __LINUX_MFD_AAEON_MCU_H */ --=20 2.55.0 From nobody Fri Oct 2 13:13:38 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F5EF3C456F; Fri, 31 Jul 2026 09:52:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785491542; cv=none; b=Kc8Ad2nDce0vxcqHcoPjIveGJHW0QeRPsv3Ed5+CGLFdMbvQceX5opqa8dWBhXAUujfKxVAjMVYX8HlPV8MLUOdc5DOFJvNytAvCmCFpjWwR+JHyEODcup9DoRgKJi+17fR8S7KA7Tk/o/GVj72GqUZ9QgeY4E2LSZw2PnyH090= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785491542; c=relaxed/simple; bh=+l/K7GkecjCKx6nIA7HKJ2/vMEUVeEnxy+n3sA6Z+0E=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=gzGHC15MxcsxCnmGqM8hTqygyoyedBGSNjmqUS+eRCeWbTPhE3WS9zUwRSV+VBICKC9msmXtYGPzNpofHGPV6gK4F6uQ+dGjWMsYdD3CsPRKXQ9ld70VIVC7euwRpH4Q8XSuhwEaO8htRJne/UwLYmaT5QgdXIHIUfRGksZQJ9k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=cx4EAWZa; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="cx4EAWZa" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id DBF1B4E4104B; Fri, 31 Jul 2026 09:52:14 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id B10716039A; Fri, 31 Jul 2026 09:52:14 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 90A8D11C1664F; Fri, 31 Jul 2026 11:52:11 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1785491533; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=fBEwTYcc52+NN3xYVbQslUHBc7dgcc+fOwxRbhxvpBw=; b=cx4EAWZaXcVuc7FyGiqPIrQVB4TdlFNcYSG9WQbhIK/fuYgWawfdw2pTml+As3rwd1Wkvr 4CG39ZFj8OopChvD1bzt5sbdu6IBGGopr89ThFE7vHhcBiKHO7MM9kiMeaLWj4CxTcqzXX WaMu6sMy8sPR7QPpArUrQniOFKQ4vg1vl09xOZ/Pcwop2NCyw1jv2wnSqpD4rIHgGnepwq uROkXKTZmXsBClbhhhyhZWTiP6Mp8nrgWbwZl3mGzXrYXDMyXTjhKR7cBLu7ZbrLONBP4U bmGoqCc8iObLkiTAp+JfXLg9jeW3EF+wiLwGviOLECLePhxFQXlQPNTHnUUkrQ== From: "Thomas Perrot (Schneider Electric)" Date: Fri, 31 Jul 2026 11:51:44 +0200 Subject: [PATCH v8 4/5] gpio: aaeon: Add GPIO driver for SRG-IMX8P MCU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260731-dev-b4-aaeon-mcu-driver-v8-4-9ab00e80df2a@bootlin.com> References: <20260731-dev-b4-aaeon-mcu-driver-v8-0-9ab00e80df2a@bootlin.com> In-Reply-To: <20260731-dev-b4-aaeon-mcu-driver-v8-0-9ab00e80df2a@bootlin.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , =?utf-8?q?J=C3=A9r=C3=A9mie_Dautheribes?= , Wim Van Sebroeck , Guenter Roeck , Lee Jones Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-watchdog@vger.kernel.org, Thomas Petazzoni , Miquel Raynal , "Thomas Perrot (Schneider Electric)" , Bartosz Golaszewski X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Add GPIO driver for the Aaeon SRG-IMX8P embedded controller. This driver supports 7 GPO (General Purpose Output) pins and 12 GPIO pins that can be configured as inputs or outputs. The driver implements proper state management for GPO pins (which are output-only) and full direction control for GPIO pins. During probe, all pins are reset to a known state (GPOs low, GPIOs as inputs) to prevent undefined behavior across system reboots, as the MCU does not reset GPIO states on soft reboot. Co-developed-by: J=C3=A9r=C3=A9mie Dautheribes (Schneider Electric) Signed-off-by: J=C3=A9r=C3=A9mie Dautheribes (Schneider Electric) Acked-by: Bartosz Golaszewski Reviewed-by: Linus Walleij Signed-off-by: Thomas Perrot (Schneider Electric) --- MAINTAINERS | 1 + drivers/gpio/Kconfig | 9 ++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-aaeon-mcu.c | 230 ++++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 241 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index f91b6a1826d0..2538f8c4bc14 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -191,6 +191,7 @@ M: Thomas Perrot R: J=C3=A9r=C3=A9mie Dautheribes S: Maintained F: Documentation/devicetree/bindings/mfd/aaeon,srg-imx8p-mcu.yaml +F: drivers/gpio/gpio-aaeon-mcu.c F: drivers/mfd/aaeon-mcu.c F: include/linux/mfd/aaeon-mcu.h =20 diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index c74da29253e8..4b37b5a15958 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -157,6 +157,15 @@ config GPIO_74XX_MMIO 8 bits: 74244 (Input), 74273 (Output) 16 bits: 741624 (Input), 7416374 (Output) =20 +config GPIO_AAEON_MCU + tristate "Aaeon MCU GPIO support" + depends on MFD_AAEON_MCU + help + Select this option to enable GPIO support for the Aaeon SRG-IMX8P + onboard MCU. This driver provides access to GPIO pins and GPO + (General Purpose Output) pins controlled by the microcontroller. + The driver handles both input and output configuration. + config GPIO_ALTERA tristate "Altera GPIO" select GPIOLIB_IRQCHIP diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 2421a8fd3733..1ba6318bc558 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_GPIO_104_IDI_48) +=3D gpio-104-idi-48.o obj-$(CONFIG_GPIO_104_IDIO_16) +=3D gpio-104-idio-16.o obj-$(CONFIG_GPIO_74X164) +=3D gpio-74x164.o obj-$(CONFIG_GPIO_74XX_MMIO) +=3D gpio-74xx-mmio.o +obj-$(CONFIG_GPIO_AAEON_MCU) +=3D gpio-aaeon-mcu.o obj-$(CONFIG_GPIO_ADNP) +=3D gpio-adnp.o obj-$(CONFIG_GPIO_ADP5520) +=3D gpio-adp5520.o obj-$(CONFIG_GPIO_ADP5585) +=3D gpio-adp5585.o diff --git a/drivers/gpio/gpio-aaeon-mcu.c b/drivers/gpio/gpio-aaeon-mcu.c new file mode 100644 index 000000000000..a9e048c865f5 --- /dev/null +++ b/drivers/gpio/gpio-aaeon-mcu.c @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Aaeon MCU GPIO driver + * + * Copyright (C) 2026 Bootlin + * Author: J=C3=A9r=C3=A9mie Dautheribes + * Author: Thomas Perrot + */ + +#include +#include +#include +#include +#include +#include + +#define AAEON_MCU_CONFIG_GPIO_INPUT 0x69 +#define AAEON_MCU_CONFIG_GPIO_OUTPUT 0x6F +#define AAEON_MCU_READ_GPIO 0x72 +#define AAEON_MCU_WRITE_GPIO 0x77 + +#define AAEON_MCU_CONTROL_GPO 0x6C + +#define MAX_GPIOS 12 +#define MAX_GPOS 7 + +struct aaeon_mcu_gpio { + struct gpio_chip gc; + struct regmap *regmap; + DECLARE_BITMAP(dir_in, MAX_GPOS + MAX_GPIOS); + DECLARE_BITMAP(gpo_state, MAX_GPOS); +}; + +static int aaeon_mcu_gpio_config_input_cmd(struct aaeon_mcu_gpio *data, + unsigned int offset) +{ + return regmap_write(data->regmap, + AAEON_MCU_REG(AAEON_MCU_CONFIG_GPIO_INPUT, offset - 7), + 0); +} + +static int aaeon_mcu_gpo_set_cmd(struct aaeon_mcu_gpio *data, unsigned int= offset, int value) +{ + return regmap_write(data->regmap, + AAEON_MCU_REG(AAEON_MCU_CONTROL_GPO, offset + 1), + !!value); +} + +static int aaeon_mcu_gpio_direction_input(struct gpio_chip *gc, unsigned i= nt offset) +{ + struct aaeon_mcu_gpio *data =3D gpiochip_get_data(gc); + int ret; + + if (offset < MAX_GPOS) { + dev_err(gc->parent, + "offset %d is a GPO (output-only) pin, cannot be configured as input\n", + offset); + return -EOPNOTSUPP; + } + + ret =3D aaeon_mcu_gpio_config_input_cmd(data, offset); + if (ret < 0) + return ret; + + set_bit(offset, data->dir_in); + + return 0; +} + +static int aaeon_mcu_gpio_config_output_cmd(struct aaeon_mcu_gpio *data, + unsigned int offset, + int value) +{ + int ret; + + ret =3D regmap_write(data->regmap, + AAEON_MCU_REG(AAEON_MCU_WRITE_GPIO, offset - 7), + !!value); + if (ret < 0) + return ret; + + return regmap_write(data->regmap, + AAEON_MCU_REG(AAEON_MCU_CONFIG_GPIO_OUTPUT, offset - 7), + 0); +} + +static int aaeon_mcu_gpio_direction_output(struct gpio_chip *gc, unsigned = int offset, int value) +{ + struct aaeon_mcu_gpio *data =3D gpiochip_get_data(gc); + int ret; + + if (offset < MAX_GPOS) { + ret =3D aaeon_mcu_gpo_set_cmd(data, offset, value); + if (ret) + return ret; + assign_bit(offset, data->gpo_state, value); + return 0; + } + + ret =3D aaeon_mcu_gpio_config_output_cmd(data, offset, value); + if (ret < 0) + return ret; + + clear_bit(offset, data->dir_in); + + return 0; +} + +static int aaeon_mcu_gpio_get_direction(struct gpio_chip *gc, unsigned int= offset) +{ + struct aaeon_mcu_gpio *data =3D gpiochip_get_data(gc); + + return test_bit(offset, data->dir_in) ? + GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT; +} + +static int aaeon_mcu_gpio_get(struct gpio_chip *gc, unsigned int offset) +{ + struct aaeon_mcu_gpio *data =3D gpiochip_get_data(gc); + unsigned int rsp; + int ret; + + if (offset < MAX_GPOS) + return test_bit(offset, data->gpo_state); + + ret =3D regmap_read(data->regmap, + AAEON_MCU_REG(AAEON_MCU_READ_GPIO, offset - 7), + &rsp); + if (ret < 0) + return ret; + + return rsp; +} + +static int aaeon_mcu_gpio_set_cmd(struct aaeon_mcu_gpio *data, unsigned in= t offset, int value) +{ + return regmap_write(data->regmap, + AAEON_MCU_REG(AAEON_MCU_WRITE_GPIO, offset - 7), + !!value); +} + +static int aaeon_mcu_gpio_set(struct gpio_chip *gc, unsigned int offset, + int value) +{ + struct aaeon_mcu_gpio *data =3D gpiochip_get_data(gc); + int ret; + + if (offset >=3D MAX_GPOS) + return aaeon_mcu_gpio_set_cmd(data, offset, value); + + ret =3D aaeon_mcu_gpo_set_cmd(data, offset, value); + if (ret) + return ret; + assign_bit(offset, data->gpo_state, value); + return 0; +} + +static const struct gpio_chip aaeon_mcu_chip =3D { + .label =3D "gpio-aaeon-mcu", + .owner =3D THIS_MODULE, + .get_direction =3D aaeon_mcu_gpio_get_direction, + .direction_input =3D aaeon_mcu_gpio_direction_input, + .direction_output =3D aaeon_mcu_gpio_direction_output, + .get =3D aaeon_mcu_gpio_get, + .set =3D aaeon_mcu_gpio_set, + .base =3D -1, + .ngpio =3D MAX_GPOS + MAX_GPIOS, + .can_sleep =3D true, +}; + +static void aaeon_mcu_gpio_reset(struct aaeon_mcu_gpio *data, struct devic= e *dev) +{ + unsigned int i; + int ret; + + /* Reset all GPOs */ + for (i =3D 0; i < MAX_GPOS; i++) { + ret =3D aaeon_mcu_gpo_set_cmd(data, i, 0); + if (ret < 0) + dev_warn(dev, "Failed to reset GPO %u state: %d\n", i, ret); + clear_bit(i, data->dir_in); + } + + /* Reset all GPIOs */ + for (i =3D MAX_GPOS; i < MAX_GPOS + MAX_GPIOS; i++) { + ret =3D aaeon_mcu_gpio_config_input_cmd(data, i); + if (ret < 0) + dev_warn(dev, "Failed to reset GPIO %u state: %d\n", i, ret); + set_bit(i, data->dir_in); + } +} + +static int aaeon_mcu_gpio_probe(struct platform_device *pdev) +{ + struct aaeon_mcu_gpio *data; + + data =3D devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->regmap =3D dev_get_regmap(pdev->dev.parent, NULL); + if (!data->regmap) + return -ENODEV; + + data->gc =3D aaeon_mcu_chip; + data->gc.parent =3D pdev->dev.parent; + + /* + * Reset all GPIO states to a known configuration. The MCU does not + * reset GPIO state on soft reboot, only on power cycle (hard reboot). + * Without this reset, GPIOs would retain their previous state across + * reboots, which could lead to unexpected behavior. + */ + aaeon_mcu_gpio_reset(data, &pdev->dev); + + return devm_gpiochip_add_data(&pdev->dev, &data->gc, data); +} + +static struct platform_driver aaeon_mcu_gpio_driver =3D { + .driver =3D { + .name =3D "aaeon-mcu-gpio", + }, + .probe =3D aaeon_mcu_gpio_probe, +}; +module_platform_driver(aaeon_mcu_gpio_driver); + +MODULE_ALIAS("platform:aaeon-mcu-gpio"); +MODULE_DESCRIPTION("GPIO interface for Aaeon MCU"); +MODULE_AUTHOR("J=C3=A9r=C3=A9mie Dautheribes "); +MODULE_LICENSE("GPL"); --=20 2.55.0 From nobody Fri Oct 2 13:13:38 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 911DF3CBE9C; Fri, 31 Jul 2026 09:52:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785491544; cv=none; b=EWZ6/YQVBk4ibLV8YBNwwlwv0Qz/FLRDn1isoesI7uAIdB468OHtwvcfOtDSZXCFBF0UUzm6X+161du+sZezANtcu9miK/IdnsFfqqJ1Pj/7CqTQyekSTBhSNg/sLuWF70/MKRxTl+FkyMwHFahZi2C7g5GBD1kutXfHAPHywZw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785491544; c=relaxed/simple; bh=CvctG6QbAgTHiuEU0Fn1/DNfcUx25lCQVUYfmic5994=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=W5/5JpplsVvl/TmbW4YLg42QND4jAytR7f4Yr9boTA8mq8jYLIgtYTcmloAWaUhuMiI17muK2R6ZNMjjre+K9K1IcXJ6r3wiZETAIk+sLZN8PA97354Ap25DOcUIxu4BNSrqjTEK/KkXTa+NhlbofwR1Yb4MIU6VyHduPfT94Eo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=uTYR8iB7; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="uTYR8iB7" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 26EDD1A1354; Fri, 31 Jul 2026 09:52:17 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id EEACA6039A; Fri, 31 Jul 2026 09:52:16 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id D517C11C16653; Fri, 31 Jul 2026 11:52:13 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1785491535; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=6tzTwtIzcwNOGYqYYE5OkMxf/iAPgArnZ5FvnJjna6Q=; b=uTYR8iB7jFeWw7kdAcGrp3RNuxdIaqvrHiOwjjk7Q08w7c3CegBaRjkS436uJeE2phJhgi qV+X5Rxfa3Kg9+D8ZZRC72J/ki6dBFqI4uPLLn1Kjud/MdGkvPm+1rqbhHypUDcec1jpHK fJZrsmt7wC3P2U6/+EU1+8W+gPj/vVleD90cYCQjvR6AQ9RJvpqz9UTTwj+1K5lBL+QyB1 z+xRrtppTikqrb4oPvtkddM936qUkF6Lfb3zB3TLnWvQXA+s+6gQNcZhHsA1ltwu7EECDs G02pTGxR0BHJfvqj6CRhGJbjAEJ2XWrzrTlSPPDU6IV6dji0qvQlMFumFg90MA== From: "Thomas Perrot (Schneider Electric)" Date: Fri, 31 Jul 2026 11:51:45 +0200 Subject: [PATCH v8 5/5] watchdog: aaeon: Add watchdog driver for SRG-IMX8P MCU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260731-dev-b4-aaeon-mcu-driver-v8-5-9ab00e80df2a@bootlin.com> References: <20260731-dev-b4-aaeon-mcu-driver-v8-0-9ab00e80df2a@bootlin.com> In-Reply-To: <20260731-dev-b4-aaeon-mcu-driver-v8-0-9ab00e80df2a@bootlin.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , =?utf-8?q?J=C3=A9r=C3=A9mie_Dautheribes?= , Wim Van Sebroeck , Guenter Roeck , Lee Jones Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-watchdog@vger.kernel.org, Thomas Petazzoni , Miquel Raynal , "Thomas Perrot (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Add watchdog driver for the Aaeon SRG-IMX8P embedded controller. This driver provides system monitoring and recovery capabilities through the MCU's watchdog timer. The watchdog supports start, stop, and ping operations with a maximum hardware heartbeat of 25 seconds and a default timeout of 240 seconds. The software timeout can be changed via the WDIOC_SETTIMEOUT ioctl, the DT timeout-sec property, or the watchdog_timeout kernel boot parameter. Co-developed-by: J=C3=A9r=C3=A9mie Dautheribes (Schneider Electric) Signed-off-by: J=C3=A9r=C3=A9mie Dautheribes (Schneider Electric) Signed-off-by: Thomas Perrot (Schneider Electric) Acked-by: Guenter Roeck --- MAINTAINERS | 1 + drivers/watchdog/Kconfig | 10 +++ drivers/watchdog/Makefile | 1 + drivers/watchdog/aaeon_mcu_wdt.c | 168 +++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 180 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 2538f8c4bc14..7b92af42c9fd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -193,6 +193,7 @@ S: Maintained F: Documentation/devicetree/bindings/mfd/aaeon,srg-imx8p-mcu.yaml F: drivers/gpio/gpio-aaeon-mcu.c F: drivers/mfd/aaeon-mcu.c +F: drivers/watchdog/aaeon_mcu_wdt.c F: include/linux/mfd/aaeon-mcu.h =20 AAEON UPBOARD FPGA MFD DRIVER diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index d3b9df7d466b..f67a0b453316 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -420,6 +420,16 @@ config SL28CPLD_WATCHDOG =20 # ARM Architecture =20 +config AAEON_MCU_WATCHDOG + tristate "Aaeon MCU Watchdog" + depends on MFD_AAEON_MCU + select WATCHDOG_CORE + help + Select this option to enable watchdog timer support for the Aaeon + SRG-IMX8P onboard microcontroller (MCU). This driver provides + watchdog functionality through the MCU, allowing system monitoring + and automatic recovery from system hangs. + config AIROHA_WATCHDOG tristate "Airoha EN7581 Watchdog" depends on ARCH_AIROHA || COMPILE_TEST diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index ba52099b1253..2deec425d3ea 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_USBPCWATCHDOG) +=3D pcwd_usb.o # ALPHA Architecture =20 # ARM Architecture +obj-$(CONFIG_AAEON_MCU_WATCHDOG) +=3D aaeon_mcu_wdt.o obj-$(CONFIG_ARM_SP805_WATCHDOG) +=3D sp805_wdt.o obj-$(CONFIG_ARM_SBSA_WATCHDOG) +=3D sbsa_gwdt.o obj-$(CONFIG_ARMADA_37XX_WATCHDOG) +=3D armada_37xx_wdt.o diff --git a/drivers/watchdog/aaeon_mcu_wdt.c b/drivers/watchdog/aaeon_mcu_= wdt.c new file mode 100644 index 000000000000..661d14393c6e --- /dev/null +++ b/drivers/watchdog/aaeon_mcu_wdt.c @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Aaeon MCU Watchdog driver + * + * Copyright (C) 2026 Bootlin + * Author: J=C3=A9r=C3=A9mie Dautheribes + * Author: Thomas Perrot + */ + +#include +#include +#include +#include +#include + +#define AAEON_MCU_PING_WDT 0x73 + +#define AAEON_MCU_WDT_TIMEOUT 240 +#define AAEON_MCU_WDT_HEARTBEAT_MS 25000 +#define AAEON_MCU_WDT_MIN_TIMEOUT 1 + +static unsigned int timeout; +module_param(timeout, uint, 0); +MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds"); + +struct aaeon_mcu_wdt { + struct watchdog_device wdt; + struct regmap *regmap; +}; + +static int aaeon_mcu_wdt_cmd(struct aaeon_mcu_wdt *data, u8 opcode, u8 arg) +{ + return regmap_write(data->regmap, AAEON_MCU_REG(opcode, arg), 0); +} + +static int aaeon_mcu_wdt_start(struct watchdog_device *wdt) +{ + struct aaeon_mcu_wdt *data =3D watchdog_get_drvdata(wdt); + + return aaeon_mcu_wdt_cmd(data, AAEON_MCU_CONTROL_WDT_OPCODE, 0x01); +} + +static int aaeon_mcu_wdt_status(struct watchdog_device *wdt, bool *enabled) +{ + struct aaeon_mcu_wdt *data =3D watchdog_get_drvdata(wdt); + unsigned int rsp; + int ret; + + ret =3D regmap_read(data->regmap, + AAEON_MCU_REG(AAEON_MCU_CONTROL_WDT_OPCODE, 0x02), + &rsp); + if (ret) + return ret; + + *enabled =3D rsp =3D=3D 0x01; + return 0; +} + +static int aaeon_mcu_wdt_stop(struct watchdog_device *wdt) +{ + struct aaeon_mcu_wdt *data =3D watchdog_get_drvdata(wdt); + + return aaeon_mcu_wdt_cmd(data, AAEON_MCU_CONTROL_WDT_OPCODE, 0x00); +} + +static int aaeon_mcu_wdt_ping(struct watchdog_device *wdt) +{ + struct aaeon_mcu_wdt *data =3D watchdog_get_drvdata(wdt); + + return aaeon_mcu_wdt_cmd(data, AAEON_MCU_PING_WDT, 0x00); +} + +static const struct watchdog_info aaeon_mcu_wdt_info =3D { + .identity =3D "Aaeon MCU Watchdog", + .options =3D WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT +}; + +static const struct watchdog_ops aaeon_mcu_wdt_ops =3D { + .owner =3D THIS_MODULE, + .start =3D aaeon_mcu_wdt_start, + .stop =3D aaeon_mcu_wdt_stop, + .ping =3D aaeon_mcu_wdt_ping, +}; + +static int aaeon_mcu_wdt_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct watchdog_device *wdt; + struct aaeon_mcu_wdt *data; + bool enabled; + int ret; + + data =3D devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->regmap =3D dev_get_regmap(dev->parent, NULL); + if (!data->regmap) + return -ENODEV; + + wdt =3D &data->wdt; + wdt->parent =3D dev; + wdt->info =3D &aaeon_mcu_wdt_info; + wdt->ops =3D &aaeon_mcu_wdt_ops; + /* + * The MCU firmware has a fixed hardware timeout of 25 seconds that + * cannot be changed. The watchdog core handles automatic pinging to + * support software timeouts longer than the hardware limit. The default + * software timeout of 240 seconds can be overridden via the DT + * timeout-sec property or the watchdog_timeout kernel boot parameter. + */ + wdt->timeout =3D AAEON_MCU_WDT_TIMEOUT; + wdt->min_timeout =3D AAEON_MCU_WDT_MIN_TIMEOUT; + wdt->max_hw_heartbeat_ms =3D AAEON_MCU_WDT_HEARTBEAT_MS; + watchdog_init_timeout(wdt, timeout, dev->parent); + + watchdog_set_drvdata(wdt, data); + watchdog_stop_on_reboot(wdt); + watchdog_stop_ping_on_suspend(wdt); + dev_set_drvdata(dev, wdt); + + ret =3D aaeon_mcu_wdt_status(wdt, &enabled); + if (ret) + return ret; + + if (enabled) + set_bit(WDOG_HW_RUNNING, &wdt->status); + + return devm_watchdog_register_device(dev, wdt); +} + +static int aaeon_mcu_wdt_suspend(struct device *dev) +{ + struct watchdog_device *wdt =3D dev_get_drvdata(dev); + + if (watchdog_active(wdt) || watchdog_hw_running(wdt)) + return aaeon_mcu_wdt_stop(wdt); + + return 0; +} + +static int aaeon_mcu_wdt_resume(struct device *dev) +{ + struct watchdog_device *wdt =3D dev_get_drvdata(dev); + + if (watchdog_active(wdt) || watchdog_hw_running(wdt)) + return aaeon_mcu_wdt_start(wdt); + + return 0; +} + +static DEFINE_SIMPLE_DEV_PM_OPS(aaeon_mcu_wdt_pm_ops, + aaeon_mcu_wdt_suspend, aaeon_mcu_wdt_resume); + +static struct platform_driver aaeon_mcu_wdt_driver =3D { + .driver =3D { + .name =3D "aaeon-mcu-wdt", + .pm =3D pm_sleep_ptr(&aaeon_mcu_wdt_pm_ops), + }, + .probe =3D aaeon_mcu_wdt_probe, +}; + +module_platform_driver(aaeon_mcu_wdt_driver); + +MODULE_ALIAS("platform:aaeon-mcu-wdt"); +MODULE_DESCRIPTION("Aaeon MCU Watchdog Driver"); +MODULE_AUTHOR("J=C3=A9r=C3=A9mie Dautheribes "); +MODULE_LICENSE("GPL"); --=20 2.55.0