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Fri, 31 Jul 2026 09:30:47 -0700 (PDT) From: Jerome Brunet Date: Fri, 31 Jul 2026 18:30:26 +0200 Subject: [PATCH RFC/RFT 1/2] dt-bindings: net: sun8i-emac: Add A733 GMAC210 compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260731-allwinner-a733-gmac-support-v1-1-d0a8732bfa82@baylibre.com> References: <20260731-allwinner-a733-gmac-support-v1-0-d0a8732bfa82@baylibre.com> In-Reply-To: <20260731-allwinner-a733-gmac-support-v1-0-d0a8732bfa82@baylibre.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Richard Cochran , Maxime Ripard , Maxime Coquelin , Alexandre Torgue , Philipp Zabel Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, Jerome Brunet X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=6093; i=jbrunet@baylibre.com; h=from:subject:message-id; bh=0KxQNfxHtgxVP7p+J7kLnmloyIjqtkqU8bi4/9D5Pn4=; b=owEBbQKS/ZANAwAKAeb8Dxw38tqFAcsmYgBqbM2xquVAc309vSgKPGdFcjh7GkmzmsbHShAaG 2+Xz5vdSoWJAjMEAAEKAB0WIQT04VmuGPP1bV8btxvm/A8cN/LahQUCamzNsQAKCRDm/A8cN/La hVYjD/4h49mYaowx0kPXeu4N+tawC2LKn/y5trYsXdnPdHmdfzHZtHE1sbRZCKd4zo3VNEpCkUz 3ZEyvd1719+F3UGAqXAndBPgq/sN0WCV7/9y6m8XRfeJWGXcljWdJKIRPMme3g5XzvoyGUDCPAn aQ25LXLBhtvnGX5DXbWYSLrYr2lPMu6w1ZxqRMg3eBfZbOBvnwljx2Qv7GDAHlIrvGb3Kgj0AsM FOgHmSnW8iSWx/NtDXciYBKu5P4cgv+c20KktVmdANY27RVQsfkeb/ozqs972CE4uTNBkuaEMB0 ygkCAj2lRmHFKpVxapgG9YD4/UE5zwxVzKQaAzLHOjwVazmXCWdB9tPTUoyaAdAkkTnyqdoEail k6iP0hNqNcGam9TmyMkEJkNaHOdswDX/D+H6bHN5lBeUzEoz1AHaAXZi/iDauKKV3tooyukOuGH nB2hz5KVP8+VG+vwRZTZZKLsXQQM8568MopRMKciRUtT5HLwjRItUVwVpHwqlmroVhRYyYfwCMu 49z8l+11BmRDapU7WzzqrQXCoTfTpsTvHwUu18vrpQYAJbnUnkS6fRKbG0l3Hv2DiPncxZeF7Y4 xma9MDf3jBOllSMS4tgfuAK60M+ntQPUI+mO7GkQdc2RO6qfmwpYuqR5FccHOg2MZU6H0CxAQqr OgQSoMmlrTaSxNQ== X-Developer-Key: i=jbrunet@baylibre.com; a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 The A733 GMAC210 is a DesignWare MAC 5.20 close to the A523 GMAC200, with the following differences: * The glue configuration registers are a dedicated MMIO region of the controller instead of a syscon register, so a second reg entry replaces the syscon phandle. * The DMA channels and the LPI event have their own interrupt lines. * A PTP reference clock and an AHB reset are needed. * Unlike the A523, the controller does not appear to belong to a power domain. * The TX clock delay field is 5 bits wide, allowing up to 3100ps. Add the new compatible and describe those differences. Signed-off-by: Jerome Brunet --- .../bindings/net/allwinner,sun8i-a83t-emac.yaml | 130 +++++++++++++++++= +--- 1 file changed, 115 insertions(+), 15 deletions(-) diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-ema= c.yaml b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.ya= ml index 323a669fa982..fec42f46378a 100644 --- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml @@ -22,6 +22,7 @@ select: - allwinner,sun8i-v3s-emac - allwinner,sun50i-a64-emac - allwinner,sun55i-a523-gmac200 + - allwinner,sun60i-a733-gmac210 required: - compatible =20 @@ -44,25 +45,38 @@ properties: - items: - const: allwinner,sun55i-a523-gmac200 - const: snps,dwmac-4.20a + - items: + - const: allwinner,sun60i-a733-gmac210 + - const: snps,dwmac-5.20 =20 reg: - maxItems: 1 + minItems: 1 + items: + - description: MAC controller registers + - description: Glue configuration registers =20 interrupts: - maxItems: 1 + minItems: 1 + maxItems: 4 =20 interrupt-names: - const: macirq + minItems: 1 + items: + - const: macirq + - const: eth_lpi + - const: tx-queue-0 + - const: rx-queue-0 =20 clocks: minItems: 1 - maxItems: 2 + maxItems: 3 =20 clock-names: minItems: 1 items: - const: stmmaceth - const: mbus + - const: ptp_ref =20 phy-supply: description: PHY regulator @@ -87,7 +101,6 @@ required: - reset-names - phy-handle - phy-mode - - syscon =20 allOf: - $ref: snps,dwmac.yaml# @@ -219,36 +232,94 @@ allOf: properties: compatible: contains: - const: allwinner,sun55i-a523-gmac200 + enum: + - allwinner,sun55i-a523-gmac200 + - allwinner,sun60i-a733-gmac210 then: properties: - clocks: - minItems: 2 - clock-names: - minItems: 2 tx-internal-delay-ps: default: 0 minimum: 0 - maximum: 700 multipleOf: 100 description: - External RGMII PHY TX clock delay chain value in ps. + Internal RGMII PHY TX clock delay chain value in ps. rx-internal-delay-ps: default: 0 minimum: 0 maximum: 3100 multipleOf: 100 description: - External RGMII PHY TX clock delay chain value in ps. - required: - - power-domains + Internal RGMII PHY RX clock delay chain value in ps. else: properties: + reg: + maxItems: 1 + interrupts: + maxItems: 1 + interrupt-names: + maxItems: 1 clocks: maxItems: 1 clock-names: maxItems: 1 power-domains: false + required: + - syscon + + - if: + properties: + compatible: + contains: + const: allwinner,sun55i-a523-gmac200 + then: + properties: + reg: + maxItems: 1 + interrupts: + maxItems: 1 + interrupt-names: + maxItems: 1 + clocks: + minItems: 2 + maxItems: 2 + clock-names: + minItems: 2 + maxItems: 2 + resets: + maxItems: 1 + reset-names: + maxItems: 1 + tx-internal-delay-ps: + maximum: 700 + required: + - power-domains + - syscon + + - if: + properties: + compatible: + contains: + const: allwinner,sun60i-a733-gmac210 + then: + properties: + reg: + minItems: 2 + interrupts: + minItems: 4 + interrupt-names: + minItems: 4 + clocks: + minItems: 3 + clock-names: + minItems: 3 + resets: + minItems: 2 + reset-names: + minItems: 2 + tx-internal-delay-ps: + maximum: 3100 + syscon: false + power-domains: false =20 unevaluatedProperties: false =20 @@ -412,4 +483,33 @@ examples: }; }; }; + + - | + ethernet@4510000 { + compatible =3D "allwinner,sun60i-a733-gmac210", + "snps,dwmac-5.20"; + reg =3D <0x04510000 0x8000>, + <0x04518000 0x1000>; + clocks =3D <&ccu 58>, <&ccu 59>, <&ccu 60>; + clock-names =3D "stmmaceth", "mbus", "ptp_ref"; + resets =3D <&ccu 30>, <&ccu 31>; + reset-names =3D "stmmaceth", "ahb"; + interrupts =3D <0 175 4>, <0 179 4>, <0 176 4>, <0 177 4>; + interrupt-names =3D "macirq", "eth_lpi", "tx-queue-0", "rx-queue-0= "; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rgmii1_pins>; + phy-handle =3D <&ext_rgmii_phy_2>; + phy-mode =3D "rgmii-id"; + snps,fixed-burst; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + ext_rgmii_phy_2: ethernet-phy@1 { + reg =3D <1>; + }; + }; + }; ... --=20 2.47.3 From nobody Fri Oct 2 12:25:26 2026 Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8534446EC73 for ; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Richard Cochran , Maxime Ripard , Maxime Coquelin , Alexandre Torgue , Philipp Zabel Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, Jerome Brunet X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=8196; i=jbrunet@baylibre.com; h=from:subject:message-id; bh=R6z60t6FDjDvLZiOQXYefYIG0bNfh9SKw55q0G81SGM=; b=owEBbQKS/ZANAwAKAeb8Dxw38tqFAcsmYgBqbM2yrm2AuGpFLVpemVLX90B3DnBbzHrGoGWqT xiLTieBOeuJAjMEAAEKAB0WIQT04VmuGPP1bV8btxvm/A8cN/LahQUCamzNsgAKCRDm/A8cN/La hegtD/wPspDO73Xa87akPckAschP4dgHAyp7127Gd1baf5ZpC5mHrFkJXQpW9DiH5scwiM465l+ /kS8Z8F/V8xxYrn6InOmmg/dw3Im+JiNr+W1C1xOiEAwzmTNPdfFLIOAv0V8tsjCj9bpgFecs+P QOPV3JtzpAvELG9QPOWIxEnOYwEdvP7uKtEK5GdqccTQd4ICtdKau1GlPaXRKjaPxhv960YnUWl jJrW3w/jXAcgMkwJLB/y0OVjiziU5HKrnCmrAHcvvMDjeYRs+q6rO5kmTcaBBNPdfWrmCAKjfAx t+JIUu1mHbWuFIG4S78NQNN6J4X9I89doMc8xQ6/2LW68RfiEJQJzKVp2Q5E4XxUwYs8XSxBSZC vTzp79KWSngh19GFNZy8KDFx2Bp1kPSDKFxY2xuTFMGhyTj+JNeJ1hlPV9m1rTkesoKvhBiUSVx N4x+SYbDcm497L01W8ONCfXmClBY+JNsPFNjefBlt6MfBGSPl3z26CioYv8WRKxavAamQWnaXt8 AIKw2rFOKWxIf0i8jV6PHQgag5tkp+byybxhFHvdnTU9YQCshdOpxxtcZyFC9qMNxgDlq2qdx44 X/NwUNm2POmlNsmBFMBLdKzYyjYJOlByszNC50hS74Bz0CHcBhBoU0gNs649jNUCrhb/KUjN7h7 Zma6cXT7h4ab0HQ== X-Developer-Key: i=jbrunet@baylibre.com; a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 The A733 GMAC210 is a DesignWare MAC 5.20 using an Allwinner glue close to the A523 GMAC200 already supported by this driver, with the following differences to handle: * The glue configuration registers are a dedicated MMIO region of the controller instead of a syscon register. This new register region appears to be in the reset domain of stmmac's main reset. This requires the glue driver to handle the reset rather than letting stmmac deal with it. * The TX clock delay value is 5 bits wide, split over 2 register fields, allowing delays up to 3100ps. * The DMA channels have their own interrupt lines, so the per-DMA-channel interrupt mode is enabled, as the vendor SDK does. * TX LPI clock gating is supported, as the vendor SDK indicates. Follow the PHY capability with STMMAC_FLAG_EN_TX_LPI_CLK_PHY_CAP rather than forcing it on with the deprecated 'snps,en-tx-lpi-clockgating' DT property. Unlike the A523, both GMAC instances are supported by the same driver. Signed-off-by: Jerome Brunet --- drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c | 145 +++++++++++++++++= +--- 1 file changed, 127 insertions(+), 18 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c b/drivers/n= et/ethernet/stmicro/stmmac/dwmac-sun55i.c index 862df173d963..3d434a52fb02 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c @@ -10,21 +10,22 @@ */ =20 #include +#include #include #include #include #include #include #include +#include #include #include +#include #include =20 #include "stmmac.h" #include "stmmac_platform.h" =20 -#define SYSCON_REG 0x34 - /* RMII specific bits */ #define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */ /* Generic system control EMAC_CLK bits */ @@ -37,17 +38,99 @@ #define SYSCON_ETCS_EXT_GMII 0x1 #define SYSCON_ETCS_INT_GMII 0x2 =20 -static int sun55i_gmac200_set_syscon(struct device *dev, - struct plat_stmmacenet_data *plat) +struct sun55i_gmac_data { + struct regmap *(*get_regmap)(struct platform_device *pdev, + struct plat_stmmacenet_data *plat); + unsigned int flags; + u32 etxdc_ext_mask; + u32 offset; +}; + +static struct regmap *sun55i_gmac200_get_regmap(struct platform_device *pd= ev, + struct plat_stmmacenet_data *plat) +{ + struct regmap *map =3D + syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "syscon"); + + if (IS_ERR(map)) + dev_err_probe(&pdev->dev, PTR_ERR(map), "Unable to map syscon\n"); + + return map; +} + +static const struct regmap_config sun60i_a733_regmap_cfg =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, +}; + +static void sun60i_gmac210_reset_assert(void *data) { - struct device_node *node =3D dev->of_node; + struct reset_control *rst =3D data; + + reset_control_assert(rst); +} + +static struct regmap *sun60i_gmac210_get_regmap(struct platform_device *pd= ev, + struct plat_stmmacenet_data *plat) +{ + struct device *dev =3D &pdev->dev; + void __iomem *base; + int ret; + + base =3D devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(base)) { + dev_err_probe(dev, PTR_ERR(base), "unable to get glue memory region\n"); + return ERR_CAST(base); + } + + if (!plat->stmmac_rst || !plat->stmmac_ahb_rst) { + dev_err(dev, "missing required reset controls\n"); + return ERR_PTR(-EINVAL); + } + + /* + * The configuration registers are inside the controller + * reset domain, so the reset must happen before any write to them + * and should not be done again by stmmac or the configuration will + * be lost. + */ + ret =3D reset_control_assert(plat->stmmac_rst); + if (!ret) + ret =3D reset_control_deassert(plat->stmmac_rst); + + if (ret) { + dev_err_probe(dev, ret, "device reset failed\n"); + return ERR_PTR(ret); + } + + ret =3D devm_add_action_or_reset(dev, sun60i_gmac210_reset_assert, + plat->stmmac_rst); + if (ret) + return ERR_PTR(ret); + + plat->stmmac_rst =3D NULL; + + return devm_regmap_init_mmio(&pdev->dev, base, &sun60i_a733_regmap_cfg); +} + +static int sun55i_gmac200_setup(struct platform_device *pdev, + struct plat_stmmacenet_data *plat, + const struct sun55i_gmac_data *data) +{ + unsigned int lo_bits =3D hweight32(SYSCON_ETXDC_MASK); + struct device_node *node =3D pdev->dev.of_node; + struct device *dev =3D &pdev->dev; struct regmap *regmap; u32 val, reg =3D 0; + u32 max_delay; int ret; =20 - regmap =3D syscon_regmap_lookup_by_phandle(node, "syscon"); + max_delay =3D (1U << (lo_bits + hweight32(data->etxdc_ext_mask))) - 1; + + regmap =3D data->get_regmap(pdev, plat); if (IS_ERR(regmap)) - return dev_err_probe(dev, PTR_ERR(regmap), "Unable to map syscon\n"); + return PTR_ERR(regmap); =20 if (!of_property_read_u32(node, "tx-internal-delay-ps", &val)) { if (val % 100) @@ -55,12 +138,15 @@ static int sun55i_gmac200_set_syscon(struct device *de= v, "tx-delay must be a multiple of 100ps\n"); val /=3D 100; dev_dbg(dev, "set tx-delay to %x\n", val); - if (!FIELD_FIT(SYSCON_ETXDC_MASK, val)) + if (val > max_delay) return dev_err_probe(dev, -EINVAL, - "TX clock delay exceeds maximum (%u00ps > %lu00ps)\n", - val, FIELD_MAX(SYSCON_ETXDC_MASK)); + "TX clock delay exceeds maximum (%u00ps > %u00ps)\n", + val, max_delay); =20 - reg |=3D FIELD_PREP(SYSCON_ETXDC_MASK, val); + reg |=3D field_prep(SYSCON_ETXDC_MASK, val); + if (data->etxdc_ext_mask) + reg |=3D field_prep(data->etxdc_ext_mask, + val >> lo_bits); } =20 if (!of_property_read_u32(node, "rx-internal-delay-ps", &val)) { @@ -95,21 +181,29 @@ static int sun55i_gmac200_set_syscon(struct device *de= v, phy_modes(plat->phy_interface)); } =20 - ret =3D regmap_write(regmap, SYSCON_REG, reg); + ret =3D regmap_write(regmap, data->offset, reg); if (ret < 0) return dev_err_probe(dev, ret, "Failed to write to syscon\n"); =20 + plat->flags |=3D data->flags; + plat->host_dma_width =3D 32; + return 0; } =20 static int sun55i_gmac200_probe(struct platform_device *pdev) { struct plat_stmmacenet_data *plat_dat; + const struct sun55i_gmac_data *data; struct stmmac_resources stmmac_res; struct device *dev =3D &pdev->dev; struct clk *clk; int ret; =20 + data =3D device_get_match_data(dev); + if (!data) + return -EINVAL; + ret =3D stmmac_get_platform_resources(pdev, &stmmac_res); if (ret) return ret; @@ -118,11 +212,7 @@ static int sun55i_gmac200_probe(struct platform_device= *pdev) if (IS_ERR(plat_dat)) return PTR_ERR(plat_dat); =20 - /* BSP disables it */ - plat_dat->flags |=3D STMMAC_FLAG_SPH_DISABLE; - plat_dat->host_dma_width =3D 32; - - ret =3D sun55i_gmac200_set_syscon(dev, plat_dat); + ret =3D sun55i_gmac200_setup(pdev, plat_dat, data); if (ret) return ret; =20 @@ -138,8 +228,27 @@ static int sun55i_gmac200_probe(struct platform_device= *pdev) return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res); } =20 +static const struct sun55i_gmac_data sun55i_a523_gmac200_data =3D { + .get_regmap =3D sun55i_gmac200_get_regmap, + .flags =3D STMMAC_FLAG_SPH_DISABLE, + .offset =3D 0x34, + .etxdc_ext_mask =3D 0, +}; + +static const struct sun55i_gmac_data sun60i_a733_gmac210_data =3D { + .get_regmap =3D sun60i_gmac210_get_regmap, + .flags =3D (STMMAC_FLAG_SPH_DISABLE | + STMMAC_FLAG_MULTI_MSI_EN | + STMMAC_FLAG_EN_TX_LPI_CLK_PHY_CAP), + .offset =3D 0x0, + .etxdc_ext_mask =3D GENMASK(17, 16), +}; + static const struct of_device_id sun55i_gmac200_match[] =3D { - { .compatible =3D "allwinner,sun55i-a523-gmac200" }, + { .compatible =3D "allwinner,sun55i-a523-gmac200", + .data =3D &sun55i_a523_gmac200_data }, + { .compatible =3D "allwinner,sun60i-a733-gmac210", + .data =3D &sun60i_a733_gmac210_data }, { } }; MODULE_DEVICE_TABLE(of, sun55i_gmac200_match); --=20 2.47.3