From nobody Fri Oct 2 13:10:16 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6185B318EE2; Fri, 31 Jul 2026 09:08:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785488910; cv=none; b=d9tD9QTEwf0hb+tH+VSoSuvTAcuD5XkQoXaK/aOEGllObob15Nb5VaoIdu8m3H3FVNI1G7gu7os3pnvGMypCTjI3jh4NkCb2Pvotx+M7x4IA9RMVY47DrjzFaPLVDMPULfpao19o5QjOQL528lCDpFQBf9RacOY446sEcwvi5PI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785488910; c=relaxed/simple; bh=Mmb3oMAuheR21ckKDdPOPrg5ggrRiQ6j9iZ1meDpgMQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CD3jJo3aoGTmy1KiCrzY5xEgmyvUaj5OXCqkaLth7TGTuviA8NhzOjxOB3895N+zkek4ywbxZ5cZbEpAi5m4nWe8yMnJi2/OGEcCKx+QTRWN4g8Ka/mr10wjT19T1nssIvm6Z9Z3CJmPjRH1SLeBf+8nx+xuIHF6MgDuH6W3wHo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ud8y8e/r; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ud8y8e/r" Received: by smtp.kernel.org (Postfix) with ESMTPS id 011C3C2BCF4; Fri, 31 Jul 2026 09:08:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1785488910; bh=Mmb3oMAuheR21ckKDdPOPrg5ggrRiQ6j9iZ1meDpgMQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=ud8y8e/rOWlmmYP4+3ZmilFqCfz4oLvEn+kEJ+jiYL6k4qWiOjwb/Ygwjd5Pwot// kDJhgdzY9GnC76gOftXclMlvNjE8YYEnpIgdpBSo+goFPPJu4w1JMmaRTwaZb2oUV3 jvYLjqxBQg+D7QTpBTmafxMuHnzHuerK1Pgh+5MKL9p5Lv0GVw/7DqJUbZylUd19u7 o9dTcpoJio5etOiCr36nDHzM55lrCdLq4SAFAqdr9F0Eva2+T46y0eNsTfIVr58lU+ +PNerP3W7B85PMAXDGCWPAFI5UYR3WZAj1if0buuM+afVkdZhVatrkQIvIS9eb7mEd SjN+G37LyyxSA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D6698C5516D; Fri, 31 Jul 2026 09:08:29 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Fri, 31 Jul 2026 09:08:25 +0000 Subject: [PATCH v3 1/4] spi: dt-bindings: amlogic: spisg: Document A9-specific properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260731-a9-spisg-v3-1-a15da3f70029@amlogic.com> References: <20260731-a9-spisg-v3-0-a15da3f70029@amlogic.com> In-Reply-To: <20260731-a9-spisg-v3-0-a15da3f70029@amlogic.com> To: Sunny Luo , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-amlogic@lists.infradead.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Xianwei Zhao , Krzysztof Kozlowski X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1785488907; l=1955; i=xianwei.zhao@amlogic.com; s=20251216; h=from:subject:message-id; bh=QmBAAmHCz75ak/gTg3Z9nJO6Jq52E/H1aEusSVZgdR4=; b=6bqBPyY+DBxWpopJLpgnlBtH3rVrZ5+pz5Wlt8IJ1ilczXy3WgZjCdg9Gjx4dtyQzwq4Fyv+6 yK3E5ed6SLFBwOJq2eLWHDSc2TherqH/VVAuog4cO1XYJs5L8vxb1U8 X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=dWwxtWCxC6FHRurOmxEtr34SuBYU+WJowV/ZmRJ7H+k= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20251216 with auth_id=578 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao Document the Amlogic A9 SPISG controller and its additional Device Tree properties. Add the "amlogic,a9-spisg" compatible string and define the A9-specific "amlogic,mo-idle-output" property, which configure the MOSI idle output level. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Xianwei Zhao --- .../devicetree/bindings/spi/amlogic,a4-spisg.yaml | 30 ++++++++++++++++++= +--- 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/amlogic,a4-spisg.yaml b/= Documentation/devicetree/bindings/spi/amlogic,a4-spisg.yaml index 9bfb8089f7ea..427d8883009c 100644 --- a/Documentation/devicetree/bindings/spi/amlogic,a4-spisg.yaml +++ b/Documentation/devicetree/bindings/spi/amlogic,a4-spisg.yaml @@ -11,12 +11,11 @@ maintainers: - Xianwei Zhao - Sunny Luo =20 -allOf: - - $ref: spi-controller.yaml# - properties: compatible: - const: amlogic,a4-spisg + enum: + - amlogic,a4-spisg + - amlogic,a9-spisg =20 reg: maxItems: 1 @@ -35,6 +34,16 @@ properties: resets: maxItems: 1 =20 + amlogic,mo-idle-output: + description: | + Controls the MOSI output level when the controller is idle. + 0 - Drive MOSI low + 1 - Drive MOSI high + 2 - Follow the last transmitted bit + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + default: 0 + required: - compatible - reg @@ -42,6 +51,19 @@ required: - clocks - clock-names =20 +allOf: + - $ref: spi-controller.yaml# + - if: + not: + properties: + compatible: + contains: + enum: + - amlogic,a9-spisg + then: + properties: + amlogic,mo-idle-output: false + unevaluatedProperties: false =20 examples: --=20 2.52.0 From nobody Fri Oct 2 13:10:16 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 617D5314B8C; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qHzfLoYG" Received: by smtp.kernel.org (Postfix) with ESMTPS id 0DEAFC2BCF7; Fri, 31 Jul 2026 09:08:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1785488910; bh=rq/tb46DP924L/FjVCUkL1FIttRHuK8j2ySAzVvIQZM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=qHzfLoYGijlNkK5s6v2QAipdIJb70s6BBlSUGJpWG9oiN8o+2fk+LLTw4p9Fp9qNp j/RuJbcBVBjWyM08YY9nlin4F8CcmmY7LcsZDoWRYdLRBXQQ9cIQWOVi4rY2tZdQBJ kgf/RhF3kCbNrVGAf236v8y0SBIUBeH3Am7W6lhqHno7gWTDidr1Qlxc1mz7ZRmTRL +cFE3f3MrAsX/hNZQ8bKLkIJbwxcazFMJW+5ok+Us9FP/SneSdVWv7flQIEbV6vPgb GNFyWUIJPWytR1Ov0GgNFI68wGsv2lYgDZCEQEuz/X/rhnQf/egYp6Xr6yqbGot2eC 8WqCkKQe7aC9w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E4FC7C55172; Fri, 31 Jul 2026 09:08:29 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Fri, 31 Jul 2026 09:08:26 +0000 Subject: [PATCH v3 2/4] spi: amlogic: spisg: Fix transfer size limit and timeout handling Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260731-a9-spisg-v3-2-a15da3f70029@amlogic.com> References: <20260731-a9-spisg-v3-0-a15da3f70029@amlogic.com> In-Reply-To: <20260731-a9-spisg-v3-0-a15da3f70029@amlogic.com> To: Sunny Luo , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-amlogic@lists.infradead.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Xianwei Zhao X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1785488907; l=1947; i=xianwei.zhao@amlogic.com; s=20251216; h=from:subject:message-id; bh=BRq2nLOiEjtiR+0vj/uM6L8HPr1w32uaAGwS/r33K78=; b=+wtwSwKdGJ97TDwEtJc8168Lm+z187CiysDr9iVjlng+UZdwvgQC5anWhFOOEUIIOWvjCGJOh +41DdnUizsOCxC9uWXuNOE+9BqV72bytRXuxDN2WxCeKWtVKqyqoXQu X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=dWwxtWCxC6FHRurOmxEtr34SuBYU+WJowV/ZmRJ7H+k= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20251216 with auth_id=578 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao The CFG_BLOCK_NUM field can encode at most 20 bits, so reduce SPISG_BLOCK_MAX to 0xfffff to avoid programming a zero-length transfer. Perform the delay calculation in 64-bit arithmetic to avoid overflow when converting nanoseconds to SPI clock cycles. Stop the controller on transfer timeout by clearing the descriptor list register before returning an error. Fixes: cef9991e04ae ("spi: Add Amlogic SPISG driver") Signed-off-by: Xianwei Zhao --- drivers/spi/spi-amlogic-spisg.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-amlogic-spisg.c b/drivers/spi/spi-amlogic-spis= g.c index afc8af04638d..a6123975a37c 100644 --- a/drivers/spi/spi-amlogic-spisg.c +++ b/drivers/spi/spi-amlogic-spisg.c @@ -95,7 +95,7 @@ =20 #define SPISG_MAX_REG 0x40 =20 -#define SPISG_BLOCK_MAX 0x100000 +#define SPISG_BLOCK_MAX 0xFFFFF =20 #define SPISG_OP_MODE_WRITE_CMD 0 #define SPISG_OP_MODE_READ_STS 1 @@ -175,7 +175,7 @@ static int spi_delay_to_sclk(u32 slck_speed_hz, struct = spi_delay *delay) if (ns < 0) return 0; =20 - return DIV_ROUND_UP_ULL(slck_speed_hz * ns, NSEC_PER_SEC); + return DIV_ROUND_UP_ULL((u64)slck_speed_hz * ns, NSEC_PER_SEC); } =20 static inline u32 aml_spisg_sem_down_read(struct spisg_device *spisg) @@ -565,10 +565,13 @@ static int aml_spisg_transfer_one_message(struct spi_= controller *ctlr, aml_spisg_pending(spisg, descs_paddr, false, true); if (wait_for_completion_timeout(&spisg->completion, spi_controller_is_target(spisg->controller) ? - MAX_SCHEDULE_TIMEOUT : msecs_to_jiffies(ms))) + MAX_SCHEDULE_TIMEOUT : msecs_to_jiffies(ms))) { ret =3D spisg->status ? -EIO : 0; - else + } else { + /* stop transfer */ + regmap_write(spisg->map, SPISG_REG_DESC_LIST_H, 0); ret =3D -ETIMEDOUT; + } =20 dma_unmap_single(dev, descs_paddr, descs_len, DMA_TO_DEVICE); end: --=20 2.52.0 From nobody Fri Oct 2 13:10:16 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 617522F28FC; Fri, 31 Jul 2026 09:08:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785488910; cv=none; b=fE9uO0Ij1PIkJd0+b8TCrMqcQItR9JF0hmuUSBM3YULBDI4HieIPjAjfsU/owqQYng24HQvRnohVpH0qBo4koaNxBCc8bJIl8v1oHHq2gGUgc+v2o69MOJ1H78iDcXDBxlaTGWZvo80Jq7rq7KJGXrxgqjoaJKZr7RNkTVvZF6A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785488910; c=relaxed/simple; bh=3M0OnshwTVK0UfKz0PIBYXEPXb40nt8Uug0ad6cJ1QQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=NpFSoJ0xmwrn/0Gvger1A13fcVVzqo92FSQT7r7E5VbMl6gtZ7SVo2zBgyrfjh+lRmVpuOqHqfxEuMXHQkXKi2WFPJf3HMI4OeoJl+y5NqFU0eoeePfucS0RcAlK26ZWDNdDrGFjlSEwRzVLdEz8qs4MLXt7qheRjpYQfFkBOVs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=rm6XMt3B; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="rm6XMt3B" Received: by smtp.kernel.org (Postfix) with ESMTPS id 1B41BC2BCF6; Fri, 31 Jul 2026 09:08:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1785488910; bh=3M0OnshwTVK0UfKz0PIBYXEPXb40nt8Uug0ad6cJ1QQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=rm6XMt3BqhNnLZhuJ9S6awLugRr0iCduxdZoEQO6NLulWvmwrs/x8mXcZgVfNh+hz goLBGMRjNhZtE0qBMMgqNX7tMTpLo0AcfRnT5OPnSVNJDEOu6OzpJI0hlXPm3JBbdV CSFPh7qPJ0xn6Nmj4cgPhPohyraYvUxtEN6x/ne/neJgKerrM5T3vucDiGr+WTpRYw tsnoXXcqMgBJXcxnZ/fYYgL2gG5QOmLVuZJO3GCWp6pk6hQ3aGGdlX01I9X1PJc68z rLHusd4uXMaAYZaaw+mAc4ezKA25FJkvGFN56DchKWrRRGtsXqmzXYlMDuwNtxM5rw u+F9FoN5jVJEA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3D97C55167; Fri, 31 Jul 2026 09:08:29 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Fri, 31 Jul 2026 09:08:27 +0000 Subject: [PATCH v3 3/4] spi: amlogic: spisg: Fix the incorrect keep_ss of the last descriptor Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260731-a9-spisg-v3-3-a15da3f70029@amlogic.com> References: <20260731-a9-spisg-v3-0-a15da3f70029@amlogic.com> In-Reply-To: <20260731-a9-spisg-v3-0-a15da3f70029@amlogic.com> To: Sunny Luo , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-amlogic@lists.infradead.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Xianwei Zhao X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1785488907; l=2503; i=xianwei.zhao@amlogic.com; s=20251216; h=from:subject:message-id; bh=GYCmSYjNwUITh84G97V/SeftRuFlV+MEyMTKnf7GhHw=; b=lVAECaJvKgRMeRQSJ7cp31B0ZizVolRGdEKE+PFOZtDrv/2SYTmQ4/QTrKnPlX+s1LWxeHXp+ 5z/IwXUGxwCDRghrAStVH/NvNhKxbNOVHRyxX4xiExFtRDAnj/Z84ci X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=dWwxtWCxC6FHRurOmxEtr34SuBYU+WJowV/ZmRJ7H+k= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20251216 with auth_id=578 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Sunny Luo The driver currently unconditionally clears CFG_KEEP_SS on the last descriptor, causing the last transfer's cs_change setting to be ignored. Record the cs_change value of the last SPI transfer and use it to program CFG_KEEP_SS on the final descriptor. When a null descriptor is inserted to implement the cs-hold delay, keep CFG_KEEP_SS set on the preceding transfer descriptor and apply the recorded value to the final descriptor instead. This ensures the controller handles chip select correctly for the last transfer regardless of whether a cs-hold delay is required. Fixes: cef9991e04ae ("spi: Add Amlogic SPISG driver") Signed-off-by: Sunny Luo Signed-off-by: Xianwei Zhao --- drivers/spi/spi-amlogic-spisg.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-amlogic-spisg.c b/drivers/spi/spi-amlogic-spis= g.c index a6123975a37c..2d66f00dccd4 100644 --- a/drivers/spi/spi-amlogic-spisg.c +++ b/drivers/spi/spi-amlogic-spisg.c @@ -489,6 +489,7 @@ static int aml_spisg_transfer_one_message(struct spi_co= ntroller *ctlr, struct spisg_descriptor_extra *exdescs, *exdesc; dma_addr_t descs_paddr; int desc_num =3D 1, descs_len; + bool last_xfer_keep_ss =3D false; u32 cs_hold_in_sclk =3D 0; int ret =3D -EIO; =20 @@ -529,9 +530,11 @@ static int aml_spisg_transfer_one_message(struct spi_c= ontroller *ctlr, spi_delay_to_sclk(xfer->effective_speed_hz, &msg->spi->cs_setup)); =20 /* calculate cs-hold delay with the last xfer speed */ - if (list_is_last(&xfer->transfer_list, &msg->transfers)) + if (list_is_last(&xfer->transfer_list, &msg->transfers)) { cs_hold_in_sclk =3D spi_delay_to_sclk(xfer->effective_speed_hz, &msg->spi->cs_hold); + last_xfer_keep_ss =3D xfer->cs_change; + } =20 desc++; exdesc++; @@ -539,13 +542,17 @@ static int aml_spisg_transfer_one_message(struct spi_= controller *ctlr, xfer->effective_speed_hz); } =20 - if (cs_hold_in_sclk) + if (cs_hold_in_sclk) { /* additional null-descriptor to achieve the cs-hold delay */ aml_spisg_setup_null_desc(spisg, desc, cs_hold_in_sclk); - else desc--; + desc->cfg_bus |=3D FIELD_PREP(CFG_KEEP_SS, 1); + desc++; + } else { + desc--; + } =20 - desc->cfg_bus |=3D FIELD_PREP(CFG_KEEP_SS, 0); + FIELD_MODIFY(CFG_KEEP_SS, &desc->cfg_bus, last_xfer_keep_ss); desc->cfg_start |=3D FIELD_PREP(CFG_EOC, 1); =20 /* some tolerances */ --=20 2.52.0 From nobody Fri Oct 2 13:10:16 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A228330678; Fri, 31 Jul 2026 09:08:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260731-a9-spisg-v3-4-a15da3f70029@amlogic.com> References: <20260731-a9-spisg-v3-0-a15da3f70029@amlogic.com> In-Reply-To: <20260731-a9-spisg-v3-0-a15da3f70029@amlogic.com> To: Sunny Luo , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-amlogic@lists.infradead.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Xianwei Zhao X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1785488907; l=7031; i=xianwei.zhao@amlogic.com; s=20251216; h=from:subject:message-id; bh=naaiRceJgDJi2Bphth/AR2jIlvyI33awGvGfG8kRUgs=; b=5hNxJ5MEQhF4w3hxebJRQ/Oy1w3FHoud+O+aQl5gSa2zIMjmE5rRlCnVfRTBTBlW0Y6budADx qEGy3Q5BlRmDB6V68ylFxLJ55ZI6QspRUmx6zu3SEvgMtmhp4CLrjPU X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=dWwxtWCxC6FHRurOmxEtr34SuBYU+WJowV/ZmRJ7H+k= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20251216 with auth_id=578 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao The Amlogic A9 SPISG controller extends the A4 controller with additional configuration options, including: - Extended CS setup timing - Hardware-controlled CS hold timing - MOSI idle output configuration - Configurable word delay Add SoC-specific capability data and configure these features when they are supported by the underlying hardware while keeping compatibility with existing A4 controllers. Signed-off-by: Xianwei Zhao --- drivers/spi/spi-amlogic-spisg.c | 75 +++++++++++++++++++++++++++++++++++++= ---- 1 file changed, 68 insertions(+), 7 deletions(-) diff --git a/drivers/spi/spi-amlogic-spisg.c b/drivers/spi/spi-amlogic-spis= g.c index 2d66f00dccd4..729da11bc539 100644 --- a/drivers/spi/spi-amlogic-spisg.c +++ b/drivers/spi/spi-amlogic-spisg.c @@ -37,6 +37,12 @@ #define CFG_HW_POS BIT(6) /* start on vsync falling */ #define CFG_HW_NEG BIT(7) +#define CFG_WORD_GAP GENMASK(9, 8) +#define CFG_MO_IDLE_OUTPUT GENMASK(11, 10) +/* cs hold time in pclk */ +#define CFG_CS_HOLD GENMASK(26, 12) +/* high 4 bits of cs setup time in sclk */ +#define CFG_CS_SETUP_EXTEND GENMASK(30, 27) =20 #define SPISG_REG_CFG_START 0x08 #define CFG_BLOCK_NUM GENMASK(19, 0) @@ -143,6 +149,13 @@ struct spisg_descriptor_extra { int rx_ccsg_len; }; =20 +struct aml_spisg_data { + bool mo_idle_output_ctrl; + bool word_gap_ctrl; + bool cs_hold_ctrl; + bool cs_setup_extend_ctrl; +}; + struct spisg_device { struct spi_controller *controller; struct platform_device *pdev; @@ -152,6 +165,7 @@ struct spisg_device { struct clk *sclk; struct clk_div_table *tbl; struct completion completion; + const struct aml_spisg_data *data; u32 status; u32 speed_hz; u32 effective_speed_hz; @@ -424,7 +438,8 @@ static void aml_spisg_setup_null_desc(struct spisg_devi= ce *spisg, static void aml_spisg_pending(struct spisg_device *spisg, dma_addr_t desc_paddr, bool trig, - bool irq_en) + bool irq_en, + u32 delay) { u32 desc_l, desc_h, cfg_spi, irq_enable; =20 @@ -437,6 +452,13 @@ static void aml_spisg_pending(struct spisg_device *spi= sg, #endif =20 cfg_spi =3D spisg->cfg_spi; + + if (spisg->data && spisg->data->word_gap_ctrl) { + if (delay > 3) + delay =3D 3; + cfg_spi |=3D FIELD_PREP(CFG_WORD_GAP, delay); + } + if (trig) cfg_spi |=3D CFG_HW_POS; else @@ -483,6 +505,7 @@ static int aml_spisg_transfer_one_message(struct spi_co= ntroller *ctlr, { struct spisg_device *spisg =3D spi_controller_get_devdata(ctlr); struct device *dev =3D &spisg->pdev->dev; + const struct aml_spisg_data *data =3D spisg->data; unsigned long long ms =3D 0; struct spi_transfer *xfer; struct spisg_descriptor *descs, *desc; @@ -491,6 +514,7 @@ static int aml_spisg_transfer_one_message(struct spi_co= ntroller *ctlr, int desc_num =3D 1, descs_len; bool last_xfer_keep_ss =3D false; u32 cs_hold_in_sclk =3D 0; + u32 val, delay =3D 0; int ret =3D -EIO; =20 if (!aml_spisg_sem_down_read(spisg)) { @@ -524,10 +548,20 @@ static int aml_spisg_transfer_one_message(struct spi_= controller *ctlr, goto end; } =20 - /* calculate cs-setup delay with the first xfer speed */ - if (list_is_first(&xfer->transfer_list, &msg->transfers)) - desc->cfg_bus |=3D FIELD_PREP(CFG_CS_SETUP, - spi_delay_to_sclk(xfer->effective_speed_hz, &msg->spi->cs_setup)); + /* calculate cs-setup delay with the first xfer speed and word dealy*/ + if (list_is_first(&xfer->transfer_list, &msg->transfers)) { + val =3D spi_delay_to_sclk(xfer->effective_speed_hz, &msg->spi->cs_setup= ); + if (data && data->cs_setup_extend_ctrl) { + val =3D min_t(u32, 0xFF, val); + desc->cfg_bus |=3D FIELD_PREP(CFG_CS_SETUP, val & 0xF); + FIELD_MODIFY(CFG_CS_SETUP_EXTEND, &spisg->cfg_spi, val >> 4); + } else { + val =3D min_t(u32, 0xF, val); + desc->cfg_bus |=3D FIELD_PREP(CFG_CS_SETUP, val); + } + + delay =3D spi_delay_to_sclk(xfer->effective_speed_hz, &msg->spi->word_d= elay); + } =20 /* calculate cs-hold delay with the last xfer speed */ if (list_is_last(&xfer->transfer_list, &msg->transfers)) { @@ -542,7 +576,13 @@ static int aml_spisg_transfer_one_message(struct spi_c= ontroller *ctlr, xfer->effective_speed_hz); } =20 - if (cs_hold_in_sclk) { + if (data && data->cs_hold_ctrl) { + cs_hold_in_sclk =3D cs_hold_in_sclk ? : 1; + val =3D cs_hold_in_sclk * (FIELD_GET(CFG_CLK_DIV, spisg->cfg_bus) + 1); + val =3D min_t(u32, 0x7FFF, val); + FIELD_MODIFY(CFG_CS_HOLD, &spisg->cfg_spi, val); + desc--; + } else if (cs_hold_in_sclk) { /* additional null-descriptor to achieve the cs-hold delay */ aml_spisg_setup_null_desc(spisg, desc, cs_hold_in_sclk); desc--; @@ -569,7 +609,7 @@ static int aml_spisg_transfer_one_message(struct spi_co= ntroller *ctlr, } =20 reinit_completion(&spisg->completion); - aml_spisg_pending(spisg, descs_paddr, false, true); + aml_spisg_pending(spisg, descs_paddr, false, true, delay); if (wait_for_completion_timeout(&spisg->completion, spi_controller_is_target(spisg->controller) ? MAX_SCHEDULE_TIMEOUT : msecs_to_jiffies(ms))) { @@ -725,6 +765,7 @@ static int aml_spisg_probe(struct platform_device *pdev) struct spisg_device *spisg; struct device *dev =3D &pdev->dev; void __iomem *base; + u32 val =3D 0; int ret, irq; =20 const struct regmap_config aml_regmap_config =3D { @@ -743,6 +784,7 @@ static int aml_spisg_probe(struct platform_device *pdev) =20 spisg =3D spi_controller_get_devdata(ctlr); spisg->controller =3D ctlr; + spisg->data =3D (struct aml_spisg_data *)of_device_get_match_data(dev); =20 spisg->pdev =3D pdev; platform_set_drvdata(pdev, spisg); @@ -773,6 +815,14 @@ static int aml_spisg_probe(struct platform_device *pde= v) =20 spisg->cfg_spi =3D FIELD_PREP(CFG_SFLASH_WP, 1) | FIELD_PREP(CFG_SFLASH_HD, 1); + + if (spisg->data && spisg->data->mo_idle_output_ctrl) { + if (!of_property_read_u32(dev->of_node, "amlogic,mo-idle-output", &val)) + spisg->cfg_spi |=3D FIELD_PREP(CFG_MO_IDLE_OUTPUT, val); + else + spisg->cfg_spi |=3D FIELD_PREP(CFG_MO_IDLE_OUTPUT, 0); + } + if (spi_controller_is_target(ctlr)) { spisg->cfg_spi |=3D FIELD_PREP(CFG_SLAVE_EN, 1); spisg->cfg_bus =3D FIELD_PREP(CFG_TX_TUNING, 0xf); @@ -859,6 +909,13 @@ static int spisg_resume_runtime(struct device *dev) return 0; } =20 +static const struct aml_spisg_data a9_spisg_data =3D { + .mo_idle_output_ctrl =3D true, + .word_gap_ctrl =3D true, + .cs_hold_ctrl =3D true, + .cs_setup_extend_ctrl =3D true, +}; + static const struct dev_pm_ops amlogic_spisg_pm_ops =3D { .runtime_suspend =3D spisg_suspend_runtime, .runtime_resume =3D spisg_resume_runtime, @@ -868,6 +925,10 @@ static const struct of_device_id amlogic_spisg_of_matc= h[] =3D { { .compatible =3D "amlogic,a4-spisg", }, + { + .compatible =3D "amlogic,a9-spisg", + .data =3D &a9_spisg_data, + }, =20 { /* sentinel */ } }; --=20 2.52.0