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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3153dd9c96asm1643675eec.7.2026.07.30.22.53.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jul 2026 22:53:50 -0700 (PDT) From: Dongfang Zhao Date: Thu, 30 Jul 2026 22:53:48 -0700 Subject: [PATCH v2 1/2] dt-bindings: clock: qcom: Add Hawi GPU clock controllers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260730-gpucc-hawi-v2-1-7bf618ab8a34@oss.qualcomm.com> References: <20260730-gpucc-hawi-v2-0-7bf618ab8a34@oss.qualcomm.com> In-Reply-To: <20260730-gpucc-hawi-v2-0-7bf618ab8a34@oss.qualcomm.com> To: mturquette@baylibre.com, robh@kernel.org, andersson@kernel.org, conor+dt@kernel.org, sboyd@kernel.org, krzk+dt@kernel.org Cc: linux-kernel@vger.kernel.org, konrad.dybcio@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, taniya.das@oss.qualcomm.com, bmasney@redhat.com X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1785477228; l=6690; i=dongfang.zhao@oss.qualcomm.com; s=20260706; h=from:subject:message-id; bh=TbWn2omPVPJIUFrb413uT0CtEMn7ALcSOCfFDea8q0o=; b=Lpr4jff/WunGOZzFx51LAO2b7vBuX/mRxMATPtmKcSQw8y0hQsi014jobANWP5t3BXl4rSpLf 5Tjja03Y1yvB12BjBvWPsasxG+py0F+2kD1Obe+0s05xenvIizYm26t X-Developer-Key: i=dongfang.zhao@oss.qualcomm.com; a=ed25519; pk=oRbMthG8BHvTvcxks87U5rUBoZiRXWKs6KZR6lV5C64= X-Authority-Analysis: v=2.4 cv=ftzsol4f c=1 sm=1 tr=0 ts=6a6c386f cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=A1q_97lxy2FG9aqMPMkA:9 a=QEXdDO2ut3YA:10 a=3WC7DwWrALyhR5TkjVHa:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzMxMDAzOCBTYWx0ZWRfX/Je03TqECLkY 9sxbMCpSQ4MELg4UrH8HcrbRDyeXLvGCC264+iJs719oVVCpuL9CZQm3qX/1mGczVx4NX8uUXcA gC7pCiNHzSmZTpFjbnNtIgEQ3jGhdgE= X-Proofpoint-ORIG-GUID: jBX2Z9JzmJV_wNryWFDqHM0p6g4piOtQ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzMxMDAzOCBTYWx0ZWRfXwJJSVYMPV9Xr aNgdqeRtsATpFIuyI3PQphQuwLFdbi6TvZOO0o/3tiQvPjFXeTcKfyL7QJvH0R9AZslcvgb3yXm phTWGSvnpu2wqAuuKb1ph++G/YCJggh84tbY9zkSOpPEj3+ZQzQsmGbT6iZiKE4pKZXM+cosi0+ 87nT++auwusoeBRdHTOQvD0zxo2Sx13m+wJUyeRdkLvpzVJv8XvMD4lbDc4SRUyqXLinbKdTcxQ yUMH11OK37A8xfRYm5/hulJB5UpmPzEr6LijMLV3VTv1b6eMpZuQAUQlTQ6XhXhRCd9X9vtOj4C tMqEWQaXQ+rt0a9yDjVfklBHBiChoBG0N2yYNeYii4HF8ogHWh3sVKsQehaWNlwvm+7JCzsVTd0 BZQrPzyQV5PcjJMwH9NsgoSNbBE5Ig3hGTnH4121rO/XstSLyMAMvgjS8wfi5LoX04UxriKpuCJ DF57px/meI+MVwoe3pQ== X-Proofpoint-GUID: jBX2Z9JzmJV_wNryWFDqHM0p6g4piOtQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-31_02,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 suspectscore=0 bulkscore=0 adultscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607310038 Add the device tree binding and clock, reset and power-domain IDs for the Hawi graphics clock controller. This lets Hawi device trees describe the GPU clocks, resets and power domains, and lets dtbs_check validate those nodes. Add the qcom,hawi-gxclkctl compatible for the Hawi GX clock controller, using qcom,kaanapali-gxclkctl as the fallback because the register layout is identical. Signed-off-by: Dongfang Zhao Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/clock/qcom,hawi-gpucc.yaml | 78 ++++++++++++++++++= ++++ .../bindings/clock/qcom,kaanapali-gxclkctl.yaml | 22 +++--- include/dt-bindings/clock/qcom,hawi-gpucc.h | 47 +++++++++++++ 3 files changed, 139 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,hawi-gpucc.yaml b= /Documentation/devicetree/bindings/clock/qcom,hawi-gpucc.yaml new file mode 100644 index 000000000000..3e40bc3c061d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,hawi-gpucc.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,hawi-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on Hawi + +maintainers: + - Dongfang Zhao + +description: | + Qualcomm graphics clock control module provides the clocks, resets and p= ower + domains on Qualcomm SoCs. + + See also: include/dt-bindings/clock/qcom,hawi-gpucc.h + +properties: + compatible: + const: qcom,hawi-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 div branch source + + power-domains: + items: + - description: A phandle to the MX power-domain + - description: A phandle to the CX power-domain + - description: A phandle to the GMXC power-domain + + required-opps: + items: + - description: MX performance points + - description: CX performance points + - description: GMXC performance points + +required: + - compatible + - clocks + - power-domains + - required-opps + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + clock-controller@3d90000 { + compatible =3D "qcom,hawi-gpucc"; + reg =3D <0x0 0x03d90000 0x0 0x9800>; + clocks =3D <&bi_tcxo_div2>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + power-domains =3D <&rpmhpd RPMHPD_MX>, + <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_GMXC>; + required-opps =3D <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs_d3>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkct= l.yaml b/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.ya= ml index e868963f659b..28b653f6b64d 100644 --- a/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml @@ -4,25 +4,31 @@ $id: http://devicetree.org/schemas/clock/qcom,kaanapali-gxclkctl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Qualcomm Graphics power domain Controller on Kaanapali +title: Qualcomm Graphics GX Power Domain Controller =20 maintainers: - Taniya Das =20 description: | - Qualcomm GX(graphics) is a clock controller which has PLLs, clocks and - Power domains (GDSC). This module provides the power domains control - of gxclkctl on Qualcomm SoCs which helps the recovery of Graphics subsys= tem. + The Qualcomm graphics GX clock controller (GXCLKCTL) contains PLLs, cloc= ks + and power domains (GDSC). This module provides the power domain control = of + GXCLKCTL on Qualcomm SoCs, which helps the recovery of the graphics + subsystem. =20 See also: include/dt-bindings/clock/qcom,kaanapali-gxclkctl.h =20 properties: compatible: - enum: - - qcom,glymur-gxclkctl - - qcom,kaanapali-gxclkctl - - qcom,sm8750-gxclkctl + oneOf: + - enum: + - qcom,glymur-gxclkctl + - qcom,kaanapali-gxclkctl + - qcom,sm8750-gxclkctl + - items: + - enum: + - qcom,hawi-gxclkctl + - const: qcom,kaanapali-gxclkctl =20 power-domains: description: diff --git a/include/dt-bindings/clock/qcom,hawi-gpucc.h b/include/dt-bindi= ngs/clock/qcom,hawi-gpucc.h new file mode 100644 index 000000000000..181534771b10 --- /dev/null +++ b/include/dt-bindings/clock/qcom,hawi-gpucc.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_HAWI_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_HAWI_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CB_CLK 1 +#define GPU_CC_CX_ACCU_SHIFT_CLK 2 +#define GPU_CC_CX_GMU_CLK 3 +#define GPU_CC_CXO_AON_CLK 4 +#define GPU_CC_CXO_CLK 5 +#define GPU_CC_DEMET_CLK 6 +#define GPU_CC_DPM_CLK 7 +#define GPU_CC_FREQ_MEASURE_CLK 8 +#define GPU_CC_GMU_CLK_SRC 9 +#define GPU_CC_GPU_SMMU_VOTE_CLK 10 +#define GPU_CC_GX_ACCU_SHIFT_CLK 11 +#define GPU_CC_HUB_AON_CLK 12 +#define GPU_CC_HUB_CLK_SRC 13 +#define GPU_CC_HUB_CX_INT_CLK 14 +#define GPU_CC_HUB_DIV_CLK_SRC 15 +#define GPU_CC_MEMNOC_GFX_CLK 16 +#define GPU_CC_MXG_AHB_CLK 17 +#define GPU_CC_MXG_XO_CLK 18 +#define GPU_CC_PLL0 19 +#define GPU_CC_RSCC_HUB_AON_CLK 20 +#define GPU_CC_RSCC_XO_AON_CLK 21 +#define GPU_CC_SLEEP_CLK 22 + +/* GPU_CC power domains */ +#define GPU_CC_CX_GDSC 0 +#define GPU_CC_MXG_GDSC 1 + +/* GPU_CC resets */ +#define GPU_CC_CB_BCR 0 +#define GPU_CC_CX_BCR 1 +#define GPU_CC_FAST_HUB_BCR 2 +#define GPU_CC_GMU_BCR 3 +#define GPU_CC_GX_BCR 4 +#define GPU_CC_MXG_BCR 5 +#define GPU_CC_XO_BCR 6 + +#endif --=20 2.43.0 From nobody Fri Oct 2 13:14:00 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 28FA235C6AD for ; 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This provides the clocks, resets and power domains required by the GPU driver to enable the graphics subsystem. Reuse the existing gxclkctl-kaanapali driver for GX clock controller support and build it with the Hawi GPUCC driver. Signed-off-by: Dongfang Zhao Reviewed-by: Konrad Dybcio Reviewed-by: Taniya Das --- drivers/clk/qcom/Kconfig | 12 ++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gpucc-hawi.c | 461 ++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 474 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 63f271aff177..498d94837afe 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -391,6 +391,18 @@ config CLK_HAWI_GCC Say Y if you want to use peripheral devices such as UART, SPI, I2C, USB, UFS, SD/eMMC, PCIe, etc. =20 +config CLK_HAWI_GPUCC + tristate "Hawi Graphics Clock Controller" + depends on ARM64 || COMPILE_TEST + select CLK_HAWI_GCC + default m if ARCH_QCOM + help + Support for the graphics clock controller on Hawi devices. + Say Y if you want to support graphics controller devices and + functionality such as 3D graphics. It also provides GX clock + domain control required for GPU power management on Hawi-based + devices. + config CLK_HAWI_TCSRCC tristate "Hawi TCSR Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index fff069da16de..dd4e2700ee5f 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_CLK_GLYMUR_GPUCC) +=3D gpucc-glymur.o gxclkc= tl-kaanapali.o obj-$(CONFIG_CLK_GLYMUR_TCSRCC) +=3D tcsrcc-glymur.o obj-$(CONFIG_CLK_GLYMUR_VIDEOCC) +=3D videocc-glymur.o obj-$(CONFIG_CLK_HAWI_GCC) +=3D gcc-hawi.o +obj-$(CONFIG_CLK_HAWI_GPUCC) +=3D gpucc-hawi.o gxclkctl-kaanapali.o obj-$(CONFIG_CLK_HAWI_TCSRCC) +=3D tcsrcc-hawi.o obj-$(CONFIG_CLK_HAWI_VIDEOCC) +=3D videocc-hawi.o obj-$(CONFIG_CLK_KAANAPALI_CAMCC) +=3D cambistmclkcc-kaanapali.o camcc-kaa= napali.o diff --git a/drivers/clk/qcom/gpucc-hawi.c b/drivers/clk/qcom/gpucc-hawi.c new file mode 100644 index 000000000000..30b3ffb0638f --- /dev/null +++ b/drivers/clk/qcom/gpucc-hawi.c @@ -0,0 +1,461 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_GPLL0_OUT_MAIN, + DT_GPLL0_OUT_MAIN_DIV, +}; + +enum { + P_BI_TCXO, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_MAIN_DIV, + P_GPU_CC_PLL0_OUT_EVEN, + P_GPU_CC_PLL0_OUT_MAIN, + P_GPU_CC_PLL0_OUT_ODD, +}; + +static const struct pll_vco taycan_eha_t_vco[] =3D { + { 249600000, 2500000000, 0 }, +}; + +/* 788.0 MHz Configuration */ +static const struct alpha_pll_config gpu_cc_pll0_config =3D { + .l =3D 0x29, + .alpha =3D 0xaaa, + .config_ctl_val =3D 0xa5c400e7, + .config_ctl_hi_val =3D 0x0a8060e0, + .config_ctl_hi1_val =3D 0xf51dea20, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00000002, +}; + +static struct clk_alpha_pll gpu_cc_pll0 =3D { + .offset =3D 0x0, + .config =3D &gpu_cc_pll0_config, + .vco_table =3D taycan_eha_t_vco, + .num_vco =3D ARRAY_SIZE(taycan_eha_t_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_taycan_eha_t_ops, + }, + }, +}; + +static const struct parent_map gpu_cc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, + { P_GPU_CC_PLL0_OUT_EVEN, 2 }, + { P_GPU_CC_PLL0_OUT_ODD, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpu_cc_pll0.clkr.hw }, + { .hw =3D &gpu_cc_pll0.clkr.hw }, + { .hw =3D &gpu_cc_pll0.clkr.hw }, + { .index =3D DT_GPLL0_OUT_MAIN }, + { .index =3D DT_GPLL0_OUT_MAIN_DIV }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(788000000, P_GPU_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(825000000, P_GPU_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(880000000, P_GPU_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(917000000, P_GPU_CC_PLL0_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gmu_clk_src =3D { + .cmd_rcgr =3D 0x9318, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gpu_cc_parent_map_1, + .freq_tbl =3D ftbl_gpu_cc_gmu_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_gmu_clk_src", + .parent_data =3D gpu_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gpu_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] =3D { + F(150000000, P_GPLL0_OUT_MAIN_DIV, 2, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_hub_clk_src =3D { + .cmd_rcgr =3D 0x93f0, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gpu_cc_parent_map_1, + .freq_tbl =3D ftbl_gpu_cc_hub_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hub_clk_src", + .parent_data =3D gpu_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gpu_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div gpu_cc_hub_div_clk_src =3D { + .reg =3D 0x9430, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hub_div_clk_src", + .parent_hws =3D (const struct clk_hw *[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch gpu_cc_ahb_clk =3D { + .halt_reg =3D 0x90bc, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x90bc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_ahb_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &gpu_cc_hub_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_accu_shift_clk =3D { + .halt_reg =3D 0x9104, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9104, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_cx_accu_shift_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gmu_clk =3D { + .halt_reg =3D 0x90d4, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x90d4, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x90d4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_cx_gmu_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_demet_clk =3D { + .halt_reg =3D 0x9010, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_demet_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_dpm_clk =3D { + .halt_reg =3D 0x9108, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x9108, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_dpm_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_freq_measure_clk =3D { + .halt_reg =3D 0x900c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x900c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_freq_measure_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gpu_smmu_vote_clk =3D { + .halt_reg =3D 0x7000, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_gpu_smmu_vote_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_accu_shift_clk =3D { + .halt_reg =3D 0x9070, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9070, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_gx_accu_shift_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_aon_clk =3D { + .halt_reg =3D 0x93ec, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x93ec, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hub_aon_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_cx_int_clk =3D { + .halt_reg =3D 0x90e8, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x90e8, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x90e8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hub_cx_int_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_memnoc_gfx_clk =3D { + .halt_reg =3D 0x90ec, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x90ec, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x90ec, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_memnoc_gfx_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_mxg_ahb_clk =3D { + .halt_reg =3D 0x9744, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9744, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_mxg_ahb_clk", + .parent_hws =3D (const struct clk_hw *[]) { + &gpu_cc_hub_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc gpu_cc_cx_gdsc =3D { + .gdscr =3D 0x9080, + .gds_hw_ctrl =3D 0x9094, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "gpu_cc_cx_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc gpu_cc_mxg_gdsc =3D { + .gdscr =3D 0x961c, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "gpu_cc_mxg_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct clk_regmap *gpu_cc_hawi_clocks[] =3D { + [GPU_CC_AHB_CLK] =3D &gpu_cc_ahb_clk.clkr, + [GPU_CC_CX_ACCU_SHIFT_CLK] =3D &gpu_cc_cx_accu_shift_clk.clkr, + [GPU_CC_CX_GMU_CLK] =3D &gpu_cc_cx_gmu_clk.clkr, + [GPU_CC_DEMET_CLK] =3D &gpu_cc_demet_clk.clkr, + [GPU_CC_DPM_CLK] =3D &gpu_cc_dpm_clk.clkr, + [GPU_CC_FREQ_MEASURE_CLK] =3D &gpu_cc_freq_measure_clk.clkr, + [GPU_CC_GMU_CLK_SRC] =3D &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_GPU_SMMU_VOTE_CLK] =3D &gpu_cc_gpu_smmu_vote_clk.clkr, + [GPU_CC_GX_ACCU_SHIFT_CLK] =3D &gpu_cc_gx_accu_shift_clk.clkr, + [GPU_CC_HUB_AON_CLK] =3D &gpu_cc_hub_aon_clk.clkr, + [GPU_CC_HUB_CLK_SRC] =3D &gpu_cc_hub_clk_src.clkr, + [GPU_CC_HUB_CX_INT_CLK] =3D &gpu_cc_hub_cx_int_clk.clkr, + [GPU_CC_HUB_DIV_CLK_SRC] =3D &gpu_cc_hub_div_clk_src.clkr, + [GPU_CC_MEMNOC_GFX_CLK] =3D &gpu_cc_memnoc_gfx_clk.clkr, + [GPU_CC_MXG_AHB_CLK] =3D &gpu_cc_mxg_ahb_clk.clkr, + [GPU_CC_PLL0] =3D &gpu_cc_pll0.clkr, +}; + +static struct gdsc *gpu_cc_hawi_gdscs[] =3D { + [GPU_CC_CX_GDSC] =3D &gpu_cc_cx_gdsc, + [GPU_CC_MXG_GDSC] =3D &gpu_cc_mxg_gdsc, +}; + +static const struct qcom_reset_map gpu_cc_hawi_resets[] =3D { + [GPU_CC_CB_BCR] =3D { 0x93a0 }, + [GPU_CC_CX_BCR] =3D { 0x907c }, + [GPU_CC_FAST_HUB_BCR] =3D { 0x93e4 }, + [GPU_CC_GMU_BCR] =3D { 0x9314 }, + [GPU_CC_GX_BCR] =3D { 0x905c }, + [GPU_CC_MXG_BCR] =3D { 0x9618 }, + [GPU_CC_XO_BCR] =3D { 0x9000 }, +}; + +static struct clk_alpha_pll *gpu_cc_hawi_plls[] =3D { + &gpu_cc_pll0, +}; + +static u32 gpu_cc_hawi_critical_cbcrs[] =3D { + 0x93a4, /* GPU_CC_CB_CLK */ + 0x9704, /* GPU_CC_MXG_XO_CLK */ + 0x90e4, /* GPU_CC_CXO_CLK */ + 0x9008, /* GPU_CC_CXO_AON_CLK */ + 0x93e8, /* GPU_CC_RSCC_HUB_AON_CLK */ + 0x9004, /* GPU_CC_RSCC_XO_AON_CLK */ + 0x90cc, /* GPU_CC_SLEEP_CLK */ +}; + +static const struct regmap_config gpu_cc_hawi_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x9744, + .fast_io =3D true, +}; + +static struct qcom_cc_driver_data gpu_cc_hawi_driver_data =3D { + .alpha_plls =3D gpu_cc_hawi_plls, + .num_alpha_plls =3D ARRAY_SIZE(gpu_cc_hawi_plls), + .clk_cbcrs =3D gpu_cc_hawi_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(gpu_cc_hawi_critical_cbcrs), +}; + +static const struct qcom_cc_desc gpu_cc_hawi_desc =3D { + .config =3D &gpu_cc_hawi_regmap_config, + .clks =3D gpu_cc_hawi_clocks, + .num_clks =3D ARRAY_SIZE(gpu_cc_hawi_clocks), + .resets =3D gpu_cc_hawi_resets, + .num_resets =3D ARRAY_SIZE(gpu_cc_hawi_resets), + .gdscs =3D gpu_cc_hawi_gdscs, + .num_gdscs =3D ARRAY_SIZE(gpu_cc_hawi_gdscs), + .use_rpm =3D true, + .driver_data =3D &gpu_cc_hawi_driver_data, +}; + +static const struct of_device_id gpu_cc_hawi_match_table[] =3D { + { .compatible =3D "qcom,hawi-gpucc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpu_cc_hawi_match_table); + +static int gpu_cc_hawi_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &gpu_cc_hawi_desc); +} + +static struct platform_driver gpu_cc_hawi_driver =3D { + .probe =3D gpu_cc_hawi_probe, + .driver =3D { + .name =3D "gpucc-hawi", + .of_match_table =3D gpu_cc_hawi_match_table, + }, +}; + +module_platform_driver(gpu_cc_hawi_driver); + +MODULE_DESCRIPTION("QTI GPUCC HAWI Driver"); +MODULE_LICENSE("GPL"); --=20 2.43.0