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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3153e06f88fsm976435eec.20.2026.07.30.22.13.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jul 2026 22:13:54 -0700 (PDT) From: Qiang Yu Date: Thu, 30 Jul 2026 22:13:50 -0700 Subject: [PATCH v8 1/6] dt-bindings: phy: qcom: Add Glymur QMP PCIe multiple link-mode PHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260730-glymur_linkmode_0731-v8-1-a455265ad8bf@oss.qualcomm.com> References: <20260730-glymur_linkmode_0731-v8-0-a455265ad8bf@oss.qualcomm.com> In-Reply-To: <20260730-glymur_linkmode_0731-v8-0-a455265ad8bf@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , Philipp Zabel , Bjorn Andersson , Konrad Dybcio Cc: Qiang Yu , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam , Krzysztof Kozlowski X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1785474832; l=6637; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=jxxfUzpwxpcsF507GMs4HufzpqaCXog14p6kapOUu1k=; b=AqfFaFtX4vYRhYNkdzARenpXkwVTnVBhxzV0dQR9zdx+7me8Bsw+gX49gmdWwsq6wVoMSuYEF nbnU0RCQRsVCcQPQz6O2RGW+WFIzmXwcMaeoR1vcCcBaZWdWk7vFumA X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzMxMDAzMiBTYWx0ZWRfX8MGnbgO0HDfb BkHT7IXJzsugz8oUmAlRLANq8RqegtYhFBiI4VdthAnHe9AHWuHpYzLgSVQsAj+YbqsRzf2lgrE 740j6dtZWBh6Npp3xr6Mh8Zv/bfd0//XFoFxbahIQhyw3+asEPpknjSJGapRQn5rvPQjoTCW90B tIKLHuRwRm07Jp2p5/EDS92mBGtoJSgQPlZphNikLMcpPfIIEbe29Nd1yXVMckT7obS8xgidRCH ar5bkhLfLZPlxDxRUGByCrLPixiofGnOol05NFgV6/h40EBa53QhUz1sHZ/tS2+zDmbTNf1lj+I NrnPmI6mcOBE49b35sHHS/o3tkogF+sMJoR4YwfGMJ+sV1VYLP6GU8iB/PupP31RN5BeTOPm1wX gAaWAThlWe04rXl/tPhjyFQ30EubHTuWQ+YauKoEnaOTLypbi+iyCDuZV+GFhxrqiEgc+wdnThf PR11Jo4/Ngz/jtSOERA== X-Authority-Analysis: v=2.4 cv=GfknWwXL c=1 sm=1 tr=0 ts=6a6c2f14 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=gEfo2CItAAAA:8 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=TIvzfnD_jG5d2KfScrEA:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-ORIG-GUID: XFHgJBwYhksVNzGa_8n4Xj_tUgNlVa2E X-Proofpoint-GUID: XFHgJBwYhksVNzGa_8n4Xj_tUgNlVa2E X-Proofpoint-Spam-Info: AW1haW4tMjYwNzMxMDAzMiBTYWx0ZWRfX1Epk4xVnv4IM KesAQ0gdDB6w8T/lEnDa+IIQytsRhwyB6x9v3OXI+jgtXsRAK4529HdzZsmU/tcmJgi3516LLC9 6cT1klDeYUwJxnuOCbVmqnvvErZhSeI= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-31_02,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 malwarescore=0 phishscore=0 bulkscore=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 impostorscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607310032 Add qcom,glymur-qmp-gen5x8-pcie-phy.yaml as a standalone binding for the Glymur Gen5 PCIe PHY hardware block. This block supports two link modes, selected at runtime via a TCSR syscon register: 1. x8 - a single 8-lane PHY instance is exposed 2. x4+x4 - two independent 4-lane PHY instances are exposed Keep this as a separate schema from qcom,sc8280xp-qmp-pcie-phy.yaml rather than folding it into the shared compatible list there, since the two PHY instances active in x8 mode require twice as many clocks, resets, and power-domains as any other entry in that file, and adding Glymur-specific properties like qcom,link-mode and reg-names there would only apply to this one compatible. Document the required clocks, resets, and power-domains for both PHY instances, and use #phy-cells =3D <1>, where the cell value is the PHY index within the active link mode. Acked-by: Manivannan Sadhasivam Reviewed-by: Krzysztof Kozlowski Signed-off-by: Qiang Yu --- .../phy/qcom,glymur-qmp-gen5x8-pcie-phy.yaml | 177 +++++++++++++++++= ++++ 1 file changed, 177 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,glymur-qmp-gen5x8-p= cie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,glymur-qmp-gen5x8= -pcie-phy.yaml new file mode 100644 index 000000000000..759f7f979dc6 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,glymur-qmp-gen5x8-pcie-phy= .yaml @@ -0,0 +1,177 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,glymur-qmp-gen5x8-pcie-phy.yam= l# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QMP PCIe multiple link-mode PHY controller (PCIe, Glymur) + +maintainers: + - Qiang Yu + - Manivannan Sadhasivam + +description: | + The Glymur SoC uses a single PCIe Gen5 PHY hardware block for the + PCIe3a/PCIe3b controllers. This block supports two link modes, selected + at runtime via a TCSR syscon register: + + 1. x8 - a single 8-lane PHY instance is exposed (PCIe3a only) + 2. x4+x4 - two independent 4-lane PHY instances are exposed (PCIe3a and + PCIe3b) + + The node always describes both PHY instances ("port a" and "port b"), + regardless of which link mode is active on the board. + +properties: + compatible: + enum: + - qcom,glymur-qmp-gen5x8-pcie-phy + + reg: + maxItems: 2 + + reg-names: + items: + - const: port_a + - const: port_b + + clocks: + maxItems: 10 + + clock-names: + items: + - const: aux + - const: cfg_ahb + - const: ref + - const: rchng + - const: pipe + - const: phy_b_aux + - const: cfg_ahb_b + - const: rchng_b + - const: pipe_b + - const: pipediv2_b + + power-domains: + maxItems: 2 + + power-domain-names: + items: + - const: port_a + - const: port_b + + resets: + maxItems: 4 + + reset-names: + items: + - const: port_a + - const: port_a_nocsr + - const: port_b + - const: port_b_nocsr + + vdda-phy-supply: true + + vdda-pll-supply: true + + vdda-refgen0p9-supply: true + + vdda-refgen1p2-supply: true + + qcom,link-mode: + description: + Reference to a register in the TCSR syscon that reports the link + mode the PCIe PHY is currently configured for, either a single x8 + link or two independent x4 links. The link mode is programmed by + firmware before Linux boots; this property is only used to read + the active link mode, specified as a phandle to the syscon and + the register offset. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle of TCSR syscon + - description: offset of link mode register + + "#clock-cells": + const: 1 + + clock-output-names: + items: + - description: Name of the PHY A pipe clock output. + - description: Name of the PHY B pipe clock output. + + "#phy-cells": + const: 1 + description: + The cell is the index of the sub-PHY within the active link + mode, e.g. on Glymur, 0 for "port a" and 1 for "port b" in + x4x4 mode, and only index 0 (the single wide PHY) is valid in + x8 mode. + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - power-domains + - power-domain-names + - resets + - reset-names + - vdda-phy-supply + - vdda-pll-supply + - vdda-refgen0p9-supply + - vdda-refgen1p2-supply + - qcom,link-mode + - "#clock-cells" + - clock-output-names + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include + #include + + phy@f00000 { + compatible =3D "qcom,glymur-qmp-gen5x8-pcie-phy"; + reg =3D <0x00f00000 0x10000>, <0x00f10000 0x10000>; + reg-names =3D "port_a", "port_b"; + + clocks =3D <&gcc GCC_PCIE_PHY_3A_AUX_CLK>, + <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_3_CLKREF_EN>, + <&gcc GCC_PCIE_3A_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_3A_PIPE_CLK>, + <&gcc GCC_PCIE_PHY_3B_AUX_CLK>, + <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, + <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_3B_PIPE_CLK>, + <&gcc GCC_PCIE_3B_PIPE_DIV2_CLK>; + clock-names =3D "aux", "cfg_ahb", "ref", "rchng", "pipe", + "phy_b_aux", "cfg_ahb_b", "rchng_b", "pipe_b", + "pipediv2_b"; + + resets =3D <&gcc GCC_PCIE_3A_PHY_BCR>, + <&gcc GCC_PCIE_3A_NOCSR_COM_PHY_BCR>, + <&gcc GCC_PCIE_3B_PHY_BCR>, + <&gcc GCC_PCIE_3B_NOCSR_COM_PHY_BCR>; + reset-names =3D "port_a", "port_a_nocsr", "port_b", "port_b_nocsr"; + + power-domains =3D <&gcc GCC_PCIE_3A_PHY_GDSC>, + <&gcc GCC_PCIE_3B_PHY_GDSC>; + power-domain-names =3D "port_a", "port_b"; + + vdda-phy-supply =3D <&vreg_l3c>; + vdda-pll-supply =3D <&vreg_l2c>; + + vdda-refgen0p9-supply =3D <&vreg_l3c>; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3153e06f88fsm976435eec.20.2026.07.30.22.13.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jul 2026 22:13:54 -0700 (PDT) From: Qiang Yu Date: Thu, 30 Jul 2026 22:13:51 -0700 Subject: [PATCH v8 2/6] phy: qcom: qmp-pcie: Add QMP PCIe Multi-PHY driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260730-glymur_linkmode_0731-v8-2-a455265ad8bf@oss.qualcomm.com> References: <20260730-glymur_linkmode_0731-v8-0-a455265ad8bf@oss.qualcomm.com> In-Reply-To: <20260730-glymur_linkmode_0731-v8-0-a455265ad8bf@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , Philipp Zabel , Bjorn Andersson , Konrad Dybcio Cc: Qiang Yu , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam , Konrad Dybcio X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1785474832; l=23031; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=ZLP8kOXQOVfBDQlJCPwtg5BPcFfkuBwjBytqT/Re3E0=; b=d7Yq3ZKIyzVondrKyxdKxChIOvc4Wcwd9uRFVYOvhHNxP2r/lDKq/59QiQuwutgkswCJRqi2L x/6VrD0ZUuBA+9hFznNcSQFgHryNX1UO/NSEWSudymBWV452H5wPjcR X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzMxMDAzMiBTYWx0ZWRfX4D54lAe/ga99 xMhvfhi7SScDafk+yE6D3sCa6tYFEQDkof2qjxGLRNyUk8dSxuedEh8QFa/RLzaYNFHylSDNE3O h64UQx4RgZDfY7Jf8s+xHt0pkxV77yRHWbBLm3RyCPnxwTpwdg0dlEw77d0LEJ9Ia8QnDgsMjmn QpgG1UNGWCG9Tsj4HEhYhJ12RVh1yhP1HZuPCNUgNgGJa8VsZwKgzIFjifuLW6WfEFQQx1+7Xmi 6wSnLCjad98QSuMbxSO0QHi71j4VH6BH9jSXiFOnZB2pGTw13PBjabcDFqmnyDThe+n4CdRw4GQ 43rP3IeN8Y5/HdnOIF71Oi+ktQJkO5bBdkjTgEvQiV/bKM1iJTdTj31qW7Wlvpoe6FToRzZyTOR 83u9LSX9cct5buOgXg91yhE+nnI1o2vflLBC7ww+Iwl+RFzgkQW+RMjgkhUFw5SUWfFjE8uubYd awsuU7W9M5W9kOOTPeg== X-Authority-Analysis: v=2.4 cv=GfknWwXL c=1 sm=1 tr=0 ts=6a6c2f15 cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=mlzxmGbil-RpS_vCRPwA:9 a=QEXdDO2ut3YA:10 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-ORIG-GUID: m_LUYLXB3sP8C_rr_b4BtN5QHoZkYrzR X-Proofpoint-GUID: m_LUYLXB3sP8C_rr_b4BtN5QHoZkYrzR X-Proofpoint-Spam-Info: AW1haW4tMjYwNzMxMDAzMiBTYWx0ZWRfXxpbxmzakMekH Xyj4WJYIiztDX2gxYoK1azD0mpN4GMoH408U4dE6s8q3FL8QFSzYvmIm79KDdLC4WqarM3hd/lg Y1EJwHbrKqMjX56ZOAEdAKKDVsMPmAo= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-31_02,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 malwarescore=0 phishscore=0 bulkscore=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 impostorscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607310032 Some QMP PCIe PHY hardware blocks support multiple link topologies (e.g. x8 or x4+x4) selected via a TCSR register. The existing single-instance QMP PCIe PHY driver has no way to model this: it assumes a single cfg per DT node and instantiates exactly one PHY. Add a dedicated driver for this class of PHY. Match data carries a per-mode cfg table; qmp_pcie_multiphy_probe() reads the current link mode from the TCSR register pointed to by "qcom,link-mode", looks up the corresponding cfg array, and instantiates one qmp_pcie per sub-PHY required by that link mode, registering the clock and #phy-cells =3D <1> phy providers so consumers can address individual sub-PHYs by index. The driver inherits the phy setting and link-mode programmed by firmware, so only the no_csr reset is used and no phy setting tables are provided. Add the first match data and compatible, qcom,glymur-qmp-gen5x8-pcie-phy, for the Glymur Gen5 PCIe PHY that can bifurcate into two x4 links or operate as a single x8 link. Reviewed-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Qiang Yu --- drivers/phy/qualcomm/Kconfig | 11 + drivers/phy/qualcomm/Makefile | 1 + drivers/phy/qualcomm/phy-qcom-qmp-pcie-multiphy.c | 744 ++++++++++++++++++= ++++ 3 files changed, 756 insertions(+) diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig index 60a0ead127fa..8d45820bc84a 100644 --- a/drivers/phy/qualcomm/Kconfig +++ b/drivers/phy/qualcomm/Kconfig @@ -77,6 +77,17 @@ config PHY_QCOM_QMP_PCIE Enable this to support the QMP PCIe PHY transceiver that is used with PCIe controllers on Qualcomm chips. =20 +config PHY_QCOM_QMP_PCIE_MULTIPHY + tristate "Qualcomm QMP PCIe Multi PHY Driver" + depends on PCI || COMPILE_TEST + select GENERIC_PHY + default PHY_QCOM_QMP + help + Enable this to support the QMP PCIe PHY transceiver that is used + with PCIe controllers on Qualcomm chips. This PHY is a single + multi-lane QMP block that can be configured either as one wide + link or as multiple narrower independent links (bifurcation). + config PHY_QCOM_QMP_PCIE_8996 tristate "Qualcomm QMP PCIe 8996 PHY Driver" depends on PCI || COMPILE_TEST diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile index b71a6a0bed3f..8bf887d58ee4 100644 --- a/drivers/phy/qualcomm/Makefile +++ b/drivers/phy/qualcomm/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_PHY_QCOM_PCIE2) +=3D phy-qcom-pcie2.o =20 obj-$(CONFIG_PHY_QCOM_QMP_COMBO) +=3D phy-qcom-qmp-combo.o phy-qcom-qmp-us= bc.o obj-$(CONFIG_PHY_QCOM_QMP_PCIE) +=3D phy-qcom-qmp-pcie.o +obj-$(CONFIG_PHY_QCOM_QMP_PCIE_MULTIPHY) +=3D phy-qcom-qmp-pcie-multiphy.o obj-$(CONFIG_PHY_QCOM_QMP_PCIE_8996) +=3D phy-qcom-qmp-pcie-msm8996.o obj-$(CONFIG_PHY_QCOM_QMP_UFS) +=3D phy-qcom-qmp-ufs.o obj-$(CONFIG_PHY_QCOM_QMP_USB) +=3D phy-qcom-qmp-usb.o diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-multiphy.c b/drivers/ph= y/qualcomm/phy-qcom-qmp-pcie-multiphy.c new file mode 100644 index 000000000000..739c7c96aeed --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-multiphy.c @@ -0,0 +1,744 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "phy-qcom-qmp.h" + +#define PHY_INIT_COMPLETE_TIMEOUT_US 10000 + +enum qmp_pcie_glymur_link_mode { + QMP_PCIE_GLYMUR_MODE_X8, + QMP_PCIE_GLYMUR_MODE_X4X4, +}; + +enum qphy_reg_layout { + QPHY_PCS_STATUS, + QPHY_LAYOUT_SIZE +}; + +static const unsigned int pciephy_v8_50_regs_layout[QPHY_LAYOUT_SIZE] =3D { + [QPHY_PCS_STATUS] =3D QPHY_V8_50_PCS_STATUS1, +}; + +struct qmp_pcie_offsets { + u16 pcs; +}; + +struct qmp_phy_cfg { + const struct qmp_pcie_offsets *offsets; + const char * const *reg_names; + int num_regs; + const char * const *pd_names; + int num_pds; + const char * const *nocsr_reset_list; + int num_nocsr_resets; + const char * const *vreg_list; + int num_vregs; + const unsigned int *regs; + unsigned int phy_status; + const char * const *clk_list; + int num_clks; + const char * const *pipe_clk_list; + int num_pipe_clks; +}; + +struct qmp_pcie { + struct device *dev; + const struct qmp_phy_cfg *cfg; + void __iomem **base; + struct clk_bulk_data *clks; + struct clk_bulk_data *pipe_clks; + struct reset_control_bulk_data *nocsr_resets; + struct regulator_bulk_data *vregs; + struct device **pd_devs; +}; + +struct qmp_pcie_multiphy { + struct phy **phys; + const struct qmp_pcie_link_mode_cfg *mode_cfg; + int num_pipe_outputs; + struct clk_fixed_rate *pipe_out_clks; +}; + +struct qmp_pcie_link_mode_cfg { + const struct qmp_phy_cfg * const *cfgs; + u32 num_phys; +}; + +struct qmp_pcie_match_data { + const struct qmp_pcie_link_mode_cfg *mode_cfgs; + u32 num_modes; +}; + +static const char * const glymur_pciephy_clk_l[] =3D { + "aux", "cfg_ahb", "ref", "rchng", "phy_b_aux", +}; + +static const char * const glymur_pciephy_a_clk_l[] =3D { + "aux", "cfg_ahb", "ref", "rchng", +}; + +static const char * const glymur_pciephy_b_clk_l[] =3D { + "phy_b_aux", "cfg_ahb_b", "ref", "rchng_b", +}; + +static const char * const glymur_pciephy_pipeclk_l[] =3D { + "pipe", +}; + +static const char * const glymur_pipephy_b_pipeclk_l[] =3D { + "pipe_b", "pipediv2_b", +}; + +static const char * const glymur_vreg_l[] =3D { + "vdda-phy", "vdda-pll", "vdda-refgen0p9", "vdda-refgen1p2", +}; + +static const char * const glymur_pciephy_a_reg_l[] =3D { + "port_a", +}; + +static const char * const glymur_pciephy_b_reg_l[] =3D { + "port_b", +}; + +static const char * const glymur_pciephy_reg_l[] =3D { + "port_a", "port_b", +}; + +static const char * const glymur_pciephy_a_pd_l[] =3D { + "port_a", +}; + +static const char * const glymur_pciephy_b_pd_l[] =3D { + "port_b", +}; + +static const char * const glymur_pciephy_pd_l[] =3D { + "port_a", "port_b", +}; + +static const char * const glymur_pciephy_a_nocsr_reset_l[] =3D { + "port_a_nocsr", +}; + +static const char * const glymur_pciephy_nocsr_reset_l[] =3D { + "port_a_nocsr", "port_b_nocsr", +}; + +static const char * const glymur_pciephy_b_nocsr_reset_l[] =3D { + "port_b_nocsr", +}; + +static const struct qmp_pcie_offsets glymur_pcie_offsets_v8_50 =3D { + .pcs =3D 0x9000, +}; + +static const struct qmp_phy_cfg glymur_qmp_gen5x4_pciephy_a_cfg =3D { + .offsets =3D &glymur_pcie_offsets_v8_50, + .reg_names =3D glymur_pciephy_a_reg_l, + .num_regs =3D ARRAY_SIZE(glymur_pciephy_a_reg_l), + .pd_names =3D glymur_pciephy_a_pd_l, + .num_pds =3D ARRAY_SIZE(glymur_pciephy_a_pd_l), + .nocsr_reset_list =3D glymur_pciephy_a_nocsr_reset_l, + .num_nocsr_resets =3D ARRAY_SIZE(glymur_pciephy_a_nocsr_reset_l), + .vreg_list =3D glymur_vreg_l, + .num_vregs =3D ARRAY_SIZE(glymur_vreg_l), + .regs =3D pciephy_v8_50_regs_layout, + .phy_status =3D PHYSTATUS_4_20, + .pipe_clk_list =3D glymur_pciephy_pipeclk_l, + .num_pipe_clks =3D ARRAY_SIZE(glymur_pciephy_pipeclk_l), + .clk_list =3D glymur_pciephy_a_clk_l, + .num_clks =3D ARRAY_SIZE(glymur_pciephy_a_clk_l), +}; + +static const struct qmp_phy_cfg glymur_qmp_gen5x4_pciephy_b_cfg =3D { + .offsets =3D &glymur_pcie_offsets_v8_50, + .reg_names =3D glymur_pciephy_b_reg_l, + .num_regs =3D ARRAY_SIZE(glymur_pciephy_b_reg_l), + .pd_names =3D glymur_pciephy_b_pd_l, + .num_pds =3D ARRAY_SIZE(glymur_pciephy_b_pd_l), + .nocsr_reset_list =3D glymur_pciephy_b_nocsr_reset_l, + .num_nocsr_resets =3D ARRAY_SIZE(glymur_pciephy_b_nocsr_reset_l), + .vreg_list =3D glymur_vreg_l, + .num_vregs =3D ARRAY_SIZE(glymur_vreg_l), + .regs =3D pciephy_v8_50_regs_layout, + .phy_status =3D PHYSTATUS_4_20, + .pipe_clk_list =3D glymur_pipephy_b_pipeclk_l, + .num_pipe_clks =3D ARRAY_SIZE(glymur_pipephy_b_pipeclk_l), + .clk_list =3D glymur_pciephy_b_clk_l, + .num_clks =3D ARRAY_SIZE(glymur_pciephy_b_clk_l), +}; + +static const struct qmp_phy_cfg glymur_qmp_gen5x8_pciephy_cfg =3D { + .offsets =3D &glymur_pcie_offsets_v8_50, + .reg_names =3D glymur_pciephy_reg_l, + .num_regs =3D ARRAY_SIZE(glymur_pciephy_reg_l), + .pd_names =3D glymur_pciephy_pd_l, + .num_pds =3D ARRAY_SIZE(glymur_pciephy_pd_l), + .nocsr_reset_list =3D glymur_pciephy_nocsr_reset_l, + .num_nocsr_resets =3D ARRAY_SIZE(glymur_pciephy_nocsr_reset_l), + .vreg_list =3D glymur_vreg_l, + .num_vregs =3D ARRAY_SIZE(glymur_vreg_l), + .regs =3D pciephy_v8_50_regs_layout, + .phy_status =3D PHYSTATUS_4_20, + .pipe_clk_list =3D glymur_pciephy_pipeclk_l, + .num_pipe_clks =3D ARRAY_SIZE(glymur_pciephy_pipeclk_l), + .clk_list =3D glymur_pciephy_clk_l, + .num_clks =3D ARRAY_SIZE(glymur_pciephy_clk_l), +}; + +static const struct qmp_phy_cfg * const glymur_qmp_gen5x8_mode_x8_cfgs[] = =3D { + &glymur_qmp_gen5x8_pciephy_cfg, +}; + +static const struct qmp_phy_cfg * const glymur_qmp_gen5x8_mode_x4x4_cfgs[]= =3D { + &glymur_qmp_gen5x4_pciephy_a_cfg, + &glymur_qmp_gen5x4_pciephy_b_cfg, +}; + +static const struct qmp_pcie_link_mode_cfg glymur_qmp_gen5x8_mode_cfgs[] = =3D { + [QMP_PCIE_GLYMUR_MODE_X8] =3D { + .cfgs =3D glymur_qmp_gen5x8_mode_x8_cfgs, + .num_phys =3D ARRAY_SIZE(glymur_qmp_gen5x8_mode_x8_cfgs), + }, + [QMP_PCIE_GLYMUR_MODE_X4X4] =3D { + .cfgs =3D glymur_qmp_gen5x8_mode_x4x4_cfgs, + .num_phys =3D ARRAY_SIZE(glymur_qmp_gen5x8_mode_x4x4_cfgs), + }, +}; + +static const struct qmp_pcie_match_data glymur_qmp_gen5x8_match_data =3D { + .mode_cfgs =3D glymur_qmp_gen5x8_mode_cfgs, + .num_modes =3D ARRAY_SIZE(glymur_qmp_gen5x8_mode_cfgs), +}; + +static int qmp_pcie_pd_power_on(struct qmp_pcie *qmp) +{ + const struct qmp_phy_cfg *cfg =3D qmp->cfg; + int i, ret; + + for (i =3D 0; i < cfg->num_pds; i++) { + ret =3D pm_runtime_resume_and_get(qmp->pd_devs[i]); + if (ret < 0) { + dev_err(qmp->dev, "failed to power on %s domain: %d\n", + cfg->pd_names[i], ret); + goto err_power_off; + } + } + + return 0; + +err_power_off: + while (--i >=3D 0) + pm_runtime_put(qmp->pd_devs[i]); + + return ret; +} + +static void qmp_pcie_pd_power_off(struct qmp_pcie *qmp) +{ + const struct qmp_phy_cfg *cfg =3D qmp->cfg; + int i; + + for (i =3D cfg->num_pds - 1; i >=3D 0; i--) + pm_runtime_put(qmp->pd_devs[i]); +} + +static int qmp_pcie_init(struct phy *phy) +{ + struct qmp_pcie *qmp =3D phy_get_drvdata(phy); + const struct qmp_phy_cfg *cfg =3D qmp->cfg; + int ret; + + ret =3D qmp_pcie_pd_power_on(qmp); + if (ret) + return ret; + + ret =3D regulator_bulk_enable(cfg->num_vregs, qmp->vregs); + if (ret) { + dev_err(qmp->dev, "failed to enable regulators: %d\n", ret); + goto err_pd_power_off; + } + + ret =3D reset_control_bulk_assert(qmp->cfg->num_nocsr_resets, qmp->nocsr_= resets); + if (ret) { + dev_err(qmp->dev, "no-csr reset assert failed: %d\n", ret); + goto err_disable_regulators; + } + + usleep_range(200, 300); + + ret =3D clk_bulk_prepare_enable(qmp->cfg->num_clks, qmp->clks); + if (ret) + goto err_disable_regulators; + + return 0; + +err_disable_regulators: + regulator_bulk_disable(cfg->num_vregs, qmp->vregs); +err_pd_power_off: + qmp_pcie_pd_power_off(qmp); + + return ret; +} + +static int qmp_pcie_exit(struct phy *phy) +{ + struct qmp_pcie *qmp =3D phy_get_drvdata(phy); + const struct qmp_phy_cfg *cfg =3D qmp->cfg; + + reset_control_bulk_assert(qmp->cfg->num_nocsr_resets, qmp->nocsr_resets); + + clk_bulk_disable_unprepare(qmp->cfg->num_clks, qmp->clks); + regulator_bulk_disable(cfg->num_vregs, qmp->vregs); + qmp_pcie_pd_power_off(qmp); + + return 0; +} + +static int qmp_pcie_power_on(struct phy *phy) +{ + struct qmp_pcie *qmp =3D phy_get_drvdata(phy); + const struct qmp_phy_cfg *cfg =3D qmp->cfg; + const struct qmp_pcie_offsets *offs =3D cfg->offsets; + void __iomem *status; + unsigned int val; + int i, ret; + + ret =3D clk_bulk_prepare_enable(qmp->cfg->num_pipe_clks, qmp->pipe_clks); + if (ret) + return ret; + + ret =3D reset_control_bulk_deassert(qmp->cfg->num_nocsr_resets, qmp->nocs= r_resets); + if (ret) { + dev_err(qmp->dev, "no-csr reset deassert failed: %d\n", ret); + goto err_disable_pipe_clk; + } + + for (i =3D 0; i < cfg->num_regs; i++) { + status =3D qmp->base[i] + offs->pcs + cfg->regs[QPHY_PCS_STATUS]; + ret =3D readl_poll_timeout(status, val, !(val & cfg->phy_status), 200, + PHY_INIT_COMPLETE_TIMEOUT_US); + if (ret) { + dev_err(qmp->dev, "PHY power on timed-out (%s): %d\n", + cfg->reg_names[i], ret); + goto err_disable_pipe_clk; + } + } + + return 0; + +err_disable_pipe_clk: + clk_bulk_disable_unprepare(qmp->cfg->num_pipe_clks, qmp->pipe_clks); + + return ret; +} + +static int qmp_pcie_power_off(struct phy *phy) +{ + struct qmp_pcie *qmp =3D phy_get_drvdata(phy); + + clk_bulk_disable_unprepare(qmp->cfg->num_pipe_clks, qmp->pipe_clks); + + return 0; +} + +static int qmp_pcie_enable(struct phy *phy) +{ + int ret; + + ret =3D qmp_pcie_init(phy); + if (ret) + return ret; + + ret =3D qmp_pcie_power_on(phy); + if (ret) + qmp_pcie_exit(phy); + + return ret; +} + +static int qmp_pcie_disable(struct phy *phy) +{ + int ret; + + ret =3D qmp_pcie_power_off(phy); + if (ret) + return ret; + + return qmp_pcie_exit(phy); +} + +static const struct phy_ops qmp_pcie_phy_ops =3D { + .power_on =3D qmp_pcie_enable, + .power_off =3D qmp_pcie_disable, + .owner =3D THIS_MODULE, +}; + +static void qmp_pcie_pd_detach(void *data) +{ + struct qmp_pcie *qmp =3D data; + const struct qmp_phy_cfg *cfg =3D qmp->cfg; + int i; + + for (i =3D 0; i < cfg->num_pds; i++) { + if (!IS_ERR_OR_NULL(qmp->pd_devs[i])) + dev_pm_domain_detach(qmp->pd_devs[i], true); + } +} + +static int qmp_pcie_pd_init(struct qmp_pcie *qmp) +{ + const struct qmp_phy_cfg *cfg =3D qmp->cfg; + struct device *dev =3D qmp->dev; + int i, ret; + + if (!cfg->num_pds) + return 0; + + qmp->pd_devs =3D devm_kcalloc(dev, cfg->num_pds, sizeof(*qmp->pd_devs), + GFP_KERNEL); + if (!qmp->pd_devs) + return -ENOMEM; + + for (i =3D 0; i < cfg->num_pds; i++) { + qmp->pd_devs[i] =3D dev_pm_domain_attach_by_name(dev, + cfg->pd_names[i]); + if (IS_ERR_OR_NULL(qmp->pd_devs[i])) { + ret =3D PTR_ERR(qmp->pd_devs[i]) ? : -ENODATA; + goto err_detach; + } + } + + return devm_add_action_or_reset(dev, qmp_pcie_pd_detach, qmp); + +err_detach: + while (--i >=3D 0) + dev_pm_domain_detach(qmp->pd_devs[i], false); + + return ret; +} + +static int qmp_pcie_vreg_init(struct qmp_pcie *qmp) +{ + const struct qmp_phy_cfg *cfg =3D qmp->cfg; + struct device *dev =3D qmp->dev; + int i; + + qmp->vregs =3D devm_kcalloc(dev, cfg->num_vregs, sizeof(*qmp->vregs), + GFP_KERNEL); + if (!qmp->vregs) + return -ENOMEM; + + for (i =3D 0; i < cfg->num_vregs; i++) + qmp->vregs[i].supply =3D cfg->vreg_list[i]; + + return devm_regulator_bulk_get(dev, cfg->num_vregs, qmp->vregs); +} + +static int qmp_pcie_reset_init(struct qmp_pcie *qmp) +{ + const struct qmp_phy_cfg *cfg =3D qmp->cfg; + struct device *dev =3D qmp->dev; + int i, ret; + + qmp->nocsr_resets =3D devm_kcalloc(dev, cfg->num_nocsr_resets, + sizeof(*qmp->nocsr_resets), + GFP_KERNEL); + if (!qmp->nocsr_resets) + return -ENOMEM; + + for (i =3D 0; i < cfg->num_nocsr_resets; i++) + qmp->nocsr_resets[i].id =3D cfg->nocsr_reset_list[i]; + + ret =3D devm_reset_control_bulk_get_exclusive(dev, + cfg->num_nocsr_resets, + qmp->nocsr_resets); + if (ret) + return dev_err_probe(dev, ret, "failed to get no-csr resets\n"); + + return 0; +} + +static int qmp_pcie_clk_init(struct qmp_pcie *qmp) +{ + const struct qmp_phy_cfg *cfg =3D qmp->cfg; + struct device *dev =3D qmp->dev; + int i, ret; + + qmp->clks =3D devm_kcalloc(dev, cfg->num_clks, sizeof(*qmp->clks), + GFP_KERNEL); + if (!qmp->clks) + return -ENOMEM; + + for (i =3D 0; i < cfg->num_clks; i++) + qmp->clks[i].id =3D cfg->clk_list[i]; + + ret =3D devm_clk_bulk_get_optional(dev, cfg->num_clks, qmp->clks); + if (ret) + return ret; + + qmp->pipe_clks =3D devm_kcalloc(dev, cfg->num_pipe_clks, + sizeof(*qmp->pipe_clks), GFP_KERNEL); + if (!qmp->pipe_clks) + return -ENOMEM; + + for (i =3D 0; i < cfg->num_pipe_clks; i++) + qmp->pipe_clks[i].id =3D cfg->pipe_clk_list[i]; + + return devm_clk_bulk_get_optional(dev, cfg->num_pipe_clks, + qmp->pipe_clks); +} + +static int __phy_pipe_clk_register(struct device *dev, struct device_node = *np, + int idx, struct clk_fixed_rate *fixed) +{ + struct clk_init_data init =3D { }; + int ret; + + ret =3D of_property_read_string_index(np, "clock-output-names", idx, + &init.name); + if (ret) { + dev_err(dev, "%pOFn: No clock-output-names\n", np); + return ret; + } + + init.ops =3D &clk_fixed_rate_ops; + + fixed->fixed_rate =3D 125000000; + + fixed->hw.init =3D &init; + + return devm_clk_hw_register(dev, &fixed->hw); +} + +static struct clk_hw *qmp_pcie_multiphy_clk_hw_get(struct of_phandle_args = *clkspec, + void *data) +{ + struct qmp_pcie_multiphy *qmp_data =3D data; + unsigned int idx =3D 0; + + if (clkspec->args_count) + idx =3D clkspec->args[0]; + + if (idx < (unsigned int)qmp_data->num_pipe_outputs) + return &qmp_data->pipe_out_clks[idx].hw; + + return ERR_PTR(-EINVAL); +} + +static int qmp_pcie_multiphy_register_clocks(struct device *dev, + struct device_node *np, + struct qmp_pcie_multiphy *qmp_data) +{ + int num_pipe_outputs; + int i, ret; + + num_pipe_outputs =3D of_property_count_strings(np, "clock-output-names"); + + qmp_data->num_pipe_outputs =3D num_pipe_outputs; + qmp_data->pipe_out_clks =3D devm_kcalloc(dev, num_pipe_outputs, + sizeof(*qmp_data->pipe_out_clks), + GFP_KERNEL); + if (!qmp_data->pipe_out_clks) + return -ENOMEM; + + for (i =3D 0; i < num_pipe_outputs; i++) { + ret =3D __phy_pipe_clk_register(dev, np, i, + &qmp_data->pipe_out_clks[i]); + if (ret) + return ret; + } + + return devm_of_clk_add_hw_provider(dev, qmp_pcie_multiphy_clk_hw_get, qmp= _data); +} + +static int qmp_pcie_get_mmio(struct qmp_pcie *qmp) +{ + struct platform_device *pdev =3D to_platform_device(qmp->dev); + const struct qmp_phy_cfg *cfg =3D qmp->cfg; + struct device *dev =3D qmp->dev; + void __iomem *base; + int i; + + qmp->base =3D devm_kcalloc(dev, cfg->num_regs, sizeof(*qmp->base), + GFP_KERNEL); + if (!qmp->base) + return -ENOMEM; + + for (i =3D 0; i < cfg->num_regs; i++) { + base =3D devm_platform_ioremap_resource_byname(pdev, cfg->reg_names[i]); + if (IS_ERR(base)) + return PTR_ERR(base); + + qmp->base[i] =3D base; + } + + return 0; +} + +static int qmp_pcie_read_link_mode(struct device *dev, unsigned int *link_= mode) +{ + struct regmap *map; + unsigned int args[1]; + + map =3D syscon_regmap_lookup_by_phandle_args(dev->of_node, "qcom,link-mod= e", + ARRAY_SIZE(args), args); + if (IS_ERR(map)) + return PTR_ERR(map); + + return regmap_read(map, args[0], link_mode); +} + +static struct phy *qmp_pcie_multiphy_xlate(struct device *dev, + const struct of_phandle_args *args) +{ + struct qmp_pcie_multiphy *qmp_data =3D dev_get_drvdata(dev); + unsigned int idx; + + if (!qmp_data || args->args_count < 1) + return ERR_PTR(-EINVAL); + + idx =3D args->args[0]; + + if (idx < (unsigned int)qmp_data->mode_cfg->num_phys) + return qmp_data->phys[idx] ?: ERR_PTR(-EINVAL); + + return ERR_PTR(-EINVAL); +} + +static int qmp_pcie_probe_phy(struct qmp_pcie *qmp, struct device_node *np, + struct phy **out_phy) +{ + int ret; + + ret =3D qmp_pcie_get_mmio(qmp); + if (ret) + return ret; + + ret =3D qmp_pcie_clk_init(qmp); + if (ret) + return ret; + + ret =3D qmp_pcie_reset_init(qmp); + if (ret) + return ret; + + ret =3D qmp_pcie_vreg_init(qmp); + if (ret) + return ret; + + ret =3D qmp_pcie_pd_init(qmp); + if (ret) + return ret; + + *out_phy =3D devm_phy_create(qmp->dev, np, &qmp_pcie_phy_ops); + if (IS_ERR(*out_phy)) + return PTR_ERR(*out_phy); + + phy_set_drvdata(*out_phy, qmp); + + return 0; +} + + +static int qmp_pcie_multiphy_probe(struct platform_device *pdev) +{ + const struct qmp_pcie_match_data *match_data; + struct qmp_pcie_multiphy *qmp_data; + struct phy_provider *phy_provider; + struct device *dev =3D &pdev->dev; + unsigned int link_mode; + struct qmp_pcie *qmp; + struct phy **phys; + int phy_index; + int ret; + + qmp_data =3D devm_kzalloc(dev, sizeof(*qmp_data), GFP_KERNEL); + + match_data =3D of_device_get_match_data(dev); + if (!match_data) + return -EINVAL; + + if (!qmp_data) + return -ENOMEM; + + ret =3D qmp_pcie_read_link_mode(dev, &link_mode); + if (ret) + return dev_err_probe(dev, ret, "failed to read qcom,link-mode\n"); + + if (link_mode >=3D match_data->num_modes) + return dev_err_probe(dev, -EINVAL, "invalid qcom,link-mode: %u\n", + link_mode); + + qmp_data->mode_cfg =3D &match_data->mode_cfgs[link_mode]; + + qmp =3D devm_kcalloc(dev, qmp_data->mode_cfg->num_phys, sizeof(*qmp), GFP= _KERNEL); + if (!qmp) + return -ENOMEM; + + phys =3D devm_kcalloc(dev, qmp_data->mode_cfg->num_phys, sizeof(*phys), G= FP_KERNEL); + if (!phys) + return -ENOMEM; + + qmp_data->phys =3D phys; + dev_set_drvdata(dev, qmp_data); + + for (phy_index =3D 0; phy_index < qmp_data->mode_cfg->num_phys; phy_index= ++) { + qmp[phy_index].dev =3D dev; + qmp[phy_index].cfg =3D qmp_data->mode_cfg->cfgs[phy_index]; + ret =3D qmp_pcie_probe_phy(&qmp[phy_index], dev->of_node, &phys[phy_inde= x]); + if (ret) + return ret; + } + + ret =3D qmp_pcie_multiphy_register_clocks(dev, dev->of_node, qmp_data); + if (ret) + return ret; + + phy_provider =3D devm_of_phy_provider_register(dev, qmp_pcie_multiphy_xla= te); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static const struct of_device_id qmp_pcie_multiphy_of_match_table[] =3D { + { + .compatible =3D "qcom,glymur-qmp-gen5x8-pcie-phy", + .data =3D &glymur_qmp_gen5x8_match_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, qmp_pcie_multiphy_of_match_table); + +static struct platform_driver qmp_pcie_multiphy_driver =3D { + .probe =3D qmp_pcie_multiphy_probe, + .driver =3D { + .name =3D "qcom-qmp-pcie-multiphy", + .of_match_table =3D qmp_pcie_multiphy_of_match_table, + }, +}; +module_platform_driver(qmp_pcie_multiphy_driver); + +MODULE_AUTHOR("Qiang Yu "); +MODULE_DESCRIPTION("Qualcomm QMP PCIe Multi-PHY driver for Glymur"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Fri Oct 2 13:10:57 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 65BA435A93C for ; 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PCIe3a and PCIe3b share a single Gen5x8 QMP PHY that can be configured either as one x8 link or as two independent x4 links (bifurcated). The shared PHY is modelled as a single pcie3_phy provider; each controller selects its sub-PHY through &pcie3_phy (index 0 for PCIe3a, index 1 for PCIe3b). Update the GCC pipe clock parent array to reference the new PHY's clock outputs instead of the placeholders. Reviewed-by: Konrad Dybcio Signed-off-by: Qiang Yu Reviewed-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/glymur.dtsi | 336 +++++++++++++++++++++++++++++++= +++- 1 file changed, 334 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qco= m/glymur.dtsi index 4be7edf894b5..013d1dc9737b 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -801,8 +801,8 @@ gcc: clock-controller@100000 { <0>, /* USB 2 Phy PCIE PIPEGMUX */ <0>, /* USB 2 Phy PIPEGMUX */ <0>, /* USB 2 Phy SYS PCIE PIPEGMUX */ - <0>, /* PCIe 3a */ - <0>, /* PCIe 3b */ + <&pcie3_phy 0>, /* PCIe 3a pipe */ + <&pcie3_phy 1>, /* PCIe 3b pipe */ <&pcie4_phy>, /* PCIe 4 */ <&pcie5_phy>, /* PCIe 5 */ <&pcie6_phy>, /* PCIe 6 */ @@ -2374,6 +2374,62 @@ IPCC_MPROC_SIGNAL_GLINK_QMP }; }; =20 + pcie3_phy: phy@f00000 { + compatible =3D "qcom,glymur-qmp-gen5x8-pcie-phy"; + reg =3D <0x0 0x00f00000 0x0 0x10000>, + <0x0 0x00f10000 0x0 0x10000>; + reg-names =3D "port_a", + "port_b"; + + clocks =3D <&gcc GCC_PCIE_PHY_3A_AUX_CLK>, + <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_3_CLKREF_EN>, + <&gcc GCC_PCIE_3A_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_3A_PIPE_CLK>, + <&gcc GCC_PCIE_PHY_3B_AUX_CLK>, + <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, + <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_3B_PIPE_CLK>, + <&gcc GCC_PCIE_3B_PIPE_DIV2_CLK>; + clock-names =3D "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "phy_b_aux", + "cfg_ahb_b", + "rchng_b", + "pipe_b", + "pipediv2_b"; + + resets =3D <&gcc GCC_PCIE_3A_PHY_BCR>, + <&gcc GCC_PCIE_3A_NOCSR_COM_PHY_BCR>, + <&gcc GCC_PCIE_3B_PHY_BCR>, + <&gcc GCC_PCIE_3B_NOCSR_COM_PHY_BCR>; + reset-names =3D "port_a", + "port_a_nocsr", + "port_b", + "port_b_nocsr"; + + assigned-clocks =3D <&gcc GCC_PCIE_3A_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>; + assigned-clock-rates =3D <100000000>, <100000000>; + + power-domains =3D <&gcc GCC_PCIE_3A_PHY_GDSC>, + <&gcc GCC_PCIE_3B_PHY_GDSC>; + power-domain-names =3D "port_a", "port_b"; + + qcom,link-mode =3D <&tcsr 0x5000>; + + #clock-cells =3D <1>; + clock-output-names =3D "pcie3a_pipe_clk", + "pcie3b_pipe_clk"; + + #phy-cells =3D <1>; + + status =3D "disabled"; + }; + usb_hs_phy: phy@fa0000 { compatible =3D "qcom,glymur-m31-eusb2-phy", "qcom,sm8750-m31-eusb2-phy"; @@ -3755,6 +3811,8 @@ pcie3b_port0: pcie@0 { reg =3D <0x0 0x0 0x0 0x0 0x0>; bus-range =3D <0x01 0xff>; =20 + phys =3D <&pcie3_phy 1>; + #address-cells =3D <3>; #size-cells =3D <2>; ranges; @@ -3766,6 +3824,280 @@ pcie3b_port0_ep: endpoint { }; }; =20 + pcie3a: pcie@1c10000 { + device_type =3D "pci"; + compatible =3D "qcom,glymur-pcie", "qcom,pcie-x1e80100"; + reg =3D <0x0 0x01c10000 0x0 0x3000>, + <0x0 0x70000000 0x0 0xf20>, + <0x0 0x70000f40 0x0 0xa8>, + <0x0 0x70001000 0x0 0x4000>, + <0x0 0x70100000 0x0 0x100000>, + <0x0 0x01c13000 0x0 0x1000>; + reg-names =3D "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x100000>, + <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>, + <0x03000000 0x7 0x00000000 0x7 0x00000000 0x0 0x40000000>, + <0x43000000 0x70 0x00000000 0x70 0x00000000 0x10 0x00000000>; + + bus-range =3D <0x00 0xff>; + + dma-coherent; + + linux,pci-domain =3D <3>; + + operating-points-v2 =3D <&pcie3a_opp_table>; + + msi-map =3D <0x0 &gic_its 0xb0000 0x10000>; + iommu-map =3D <0x0 &pcie_smmu 0x30000 0x10000>; + + interrupts =3D , + , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 0 GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 851 IRQ_TYPE_LEVEL_HIGH>; + + clocks =3D <&gcc GCC_PCIE_3A_AUX_CLK>, + <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, + <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_3A_SLV_AXI_CLK>, + <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_3A_WEST_SF_AXI_CLK>; + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "noc_aggr"; + + assigned-clocks =3D <&gcc GCC_PCIE_3A_AUX_CLK>; + assigned-clock-rates =3D <19200000>; + + interconnects =3D <&pcie_west_anoc MASTER_PCIE_3A QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &pcie_west_slv_noc SLAVE_PCIE_3A QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "pcie-mem", + "cpu-pcie"; + + resets =3D <&gcc GCC_PCIE_3A_BCR>, + <&gcc GCC_PCIE_3A_LINK_DOWN_BCR>; + reset-names =3D "pci", + "link_down"; + + power-domains =3D <&gcc GCC_PCIE_3A_GDSC>; + + eq-presets-8gts =3D /bits/ 16 <0x5555 0x5555 0x5555 0x5555 + 0x5555 0x5555 0x5555 0x5555>; + eq-presets-16gts =3D /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>; + eq-presets-32gts =3D /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>; + + status =3D "disabled"; + + pcie3a_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000-1 { + opp-hz =3D /bits/ 64 <2500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <250000 1>; + opp-level =3D <1>; + }; + + /* GEN 1 x2 */ + opp-5000000-1 { + opp-hz =3D /bits/ 64 <5000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <500000 1>; + opp-level =3D <1>; + }; + + /* GEN 1 x4 */ + opp-10000000-1 { + opp-hz =3D /bits/ 64 <10000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1000000 1>; + opp-level =3D <1>; + }; + + /* GEN 1 x8 */ + opp-20000000-1 { + opp-hz =3D /bits/ 64 <20000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <2000000 1>; + opp-level =3D <1>; + }; + + /* GEN 2 x1 */ + opp-5000000-2 { + opp-hz =3D /bits/ 64 <5000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <500000 1>; + opp-level =3D <2>; + }; + + /* GEN 2 x2 */ + opp-10000000-2 { + opp-hz =3D /bits/ 64 <10000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1000000 1>; + opp-level =3D <2>; + }; + + /* GEN 2 x4 */ + opp-20000000-2 { + opp-hz =3D /bits/ 64 <20000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <2000000 1>; + opp-level =3D <2>; + }; + + /* GEN 2 x8 */ + opp-40000000-2 { + opp-hz =3D /bits/ 64 <40000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <4000000 1>; + opp-level =3D <2>; + }; + + /* GEN 3 x1 */ + opp-8000000-3 { + opp-hz =3D /bits/ 64 <8000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <984500 1>; + opp-level =3D <3>; + }; + + /* GEN 3 x2 */ + opp-16000000-3 { + opp-hz =3D /bits/ 64 <16000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1969000 1>; + opp-level =3D <3>; + }; + + /* GEN 3 x4 */ + opp-32000000-3 { + opp-hz =3D /bits/ 64 <32000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <3938000 1>; + opp-level =3D <3>; + }; + + /* GEN 3 x8 */ + opp-64000000-3 { + opp-hz =3D /bits/ 64 <64000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <7876000 1>; + opp-level =3D <3>; + }; + + /* GEN 4 x1 */ + opp-16000000-4 { + opp-hz =3D /bits/ 64 <16000000>; + required-opps =3D <&rpmhpd_opp_svs>; + opp-peak-kBps =3D <1969000 1>; + opp-level =3D <4>; + }; + + /* GEN 4 x2 */ + opp-32000000-4 { + opp-hz =3D /bits/ 64 <32000000>; + required-opps =3D <&rpmhpd_opp_svs>; + opp-peak-kBps =3D <3938000 1>; + opp-level =3D <4>; + }; + + /* GEN 4 x4 */ + opp-64000000-4 { + opp-hz =3D /bits/ 64 <64000000>; + required-opps =3D <&rpmhpd_opp_svs>; + opp-peak-kBps =3D <7876000 1>; + opp-level =3D <4>; + }; + + /* GEN 4 x8 */ + opp-128000000-4 { + opp-hz =3D /bits/ 64 <128000000>; + required-opps =3D <&rpmhpd_opp_svs>; + opp-peak-kBps =3D <15753000 1>; + opp-level =3D <4>; + }; + + /* GEN 5 x1 */ + opp-32000000-5 { + opp-hz =3D /bits/ 64 <32000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <3938000 1>; + opp-level =3D <5>; + }; + + /* GEN 5 x2 */ + opp-64000000-5 { + opp-hz =3D /bits/ 64 <64000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <7876000 1>; + opp-level =3D <5>; + }; + + /* GEN 5 x4 */ + opp-128000000-5 { + opp-hz =3D /bits/ 64 <128000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <15753000 1>; + opp-level =3D <5>; + }; + + /* GEN 5 x8 */ + opp-256000000-5 { + opp-hz =3D /bits/ 64 <256000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <31506000 1>; + opp-level =3D <5>; + }; + }; + + pcie3a_port0: pcie@0 { + device_type =3D "pci"; + compatible =3D "pciclass,0604"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + + phys =3D <&pcie3_phy 0>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; + }; + rng: rng@10c3000 { compatible =3D "qcom,glymur-trng", "qcom,trng"; reg =3D <0x0 0x010c3000 0x0 0x1000>; --=20 2.34.1 From nobody Fri Oct 2 13:10:57 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E735035AC16 for ; Fri, 31 Jul 2026 05:13:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3153e06f88fsm976435eec.20.2026.07.30.22.13.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jul 2026 22:13:56 -0700 (PDT) From: Qiang Yu Date: Thu, 30 Jul 2026 22:13:53 -0700 Subject: [PATCH v8 4/6] arm64: dts: qcom: glymur-crd: Add PHY supplies for pcie3_phy Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260730-glymur_linkmode_0731-v8-4-a455265ad8bf@oss.qualcomm.com> References: <20260730-glymur_linkmode_0731-v8-0-a455265ad8bf@oss.qualcomm.com> In-Reply-To: <20260730-glymur_linkmode_0731-v8-0-a455265ad8bf@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , Philipp Zabel , Bjorn Andersson , Konrad Dybcio Cc: Qiang Yu , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1785474832; l=1071; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=yFqbRmvKASE8ispuSnhnm/irGPiWYA6Psw6pyUHDm8M=; b=T/PpHPPG1SNWAOP4rQ8qbe9SpmWnhg8+GxiGQJf3+b2vhabGXPIUOnOm4hoAOcWwde1Jv2DNR qBJJQp2d/YCDPYk0pWbXuTH/CO7L3jLa27MdLJQBLUOXg1LnuQ5uM0w X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Proofpoint-GUID: NbmPkI3yccXqocX78I7VRv3r17JOG1xH X-Authority-Analysis: v=2.4 cv=FMsrAeos c=1 sm=1 tr=0 ts=6a6c2f16 cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=QdOup1CusybIpKGx1HsA:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzMxMDAzMiBTYWx0ZWRfX14aqOVEyg3XW JP+4tEHMk582H33P6BKOIfCm6VEjlfgnWyPbnzPI003Prlc+8KS+Ysmfk9dWr/ITlftW+gAeEf6 RIIJ5/vYY27AlbfFWNlAJ51GkhHO0rBFRNGeMf0jTn2wl9l94RF9h8zZ9NSszT404FjBVuICxRA 4wfZyM53S1lotS2wt4If9ogOtxGLwMQAtvBsyFLAMtu2IdzgvSDGnIIw6g37PEXse5WUTdepHku TYPNRvajc94VSGMa19GA+Dmp1AnQN4zGP0otdtTzyxp7hiLN1E4JwKNZkaU35XNH3ySJjors2wf XLyw/IlDjc6EDgEjOPeP96E9a7autR/6kE9/ntvkweLPu6d7akWnTjn6X/Nz9wfsdgcxOTGzqK5 vWrPwlyEa3Bf0R4LSFyDljNGF/kKBu61dD9OXbDzxvV5IVJBLh+4yMDS+HJq2E0QiEQa30gFIqU sALKXVRCFutNsZLVzXw== X-Proofpoint-ORIG-GUID: NbmPkI3yccXqocX78I7VRv3r17JOG1xH X-Proofpoint-Spam-Info: AW1haW4tMjYwNzMxMDAzMiBTYWx0ZWRfXyHK/Uiz1AGYW IsR+fYoT6iS7Xy2U2xQJorhHtPWFc18VpDdjPnYQJXPINW8571DsY1hPZKaGxLNiuOyMX53cNux e5QyF4i1FoG7IlXmuy2tPsNXYGJO+D8= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-31_02,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 phishscore=0 priorityscore=1501 clxscore=1015 bulkscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607310032 CRD wires the shared Gen5x8 PCIe PHY's regulator supplies through board-specific PMIC rails. Add the vdda-phy, vdda-pll, and vdda-refgen0p9/1p2 supplies for &pcie3_phy. Reviewed-by: Konrad Dybcio Signed-off-by: Qiang Yu Reviewed-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/glymur-crd.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/= qcom/glymur-crd.dts index 44766a73b0d1..b8e3fedcdea8 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -29,6 +29,14 @@ &mdss_dp1_out { link-frequencies =3D /bits/ 64 <1620000000 2700000000 5400000000 81000000= 00>; }; =20 +&pcie3_phy { + vdda-phy-supply =3D <&vreg_l3c_e1_0p89>; + vdda-pll-supply =3D <&vreg_l2c_e1_1p14>; + + vdda-refgen0p9-supply =3D <&vreg_l1c_e1_0p82>; + vdda-refgen1p2-supply =3D <&vreg_l4f_e1_1p08>; +}; + &tcsr { vdda-qrefrpt0-0p9-supply =3D <&vreg_l2f_e1_0p83>; vdda-qrefrpt1-0p9-supply =3D <&vreg_l2f_e1_0p83>; --=20 2.34.1 From nobody Fri Oct 2 13:10:57 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 75A57357D1E for ; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3153e06f88fsm976435eec.20.2026.07.30.22.13.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jul 2026 22:13:57 -0700 (PDT) From: Qiang Yu Date: Thu, 30 Jul 2026 22:13:54 -0700 Subject: [PATCH v8 5/6] arm64: dts: qcom: mahua: Replace pcie3a/pcie3_phy with dedicated pcie3b_phy Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260730-glymur_linkmode_0731-v8-5-a455265ad8bf@oss.qualcomm.com> References: <20260730-glymur_linkmode_0731-v8-0-a455265ad8bf@oss.qualcomm.com> In-Reply-To: <20260730-glymur_linkmode_0731-v8-0-a455265ad8bf@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , Philipp Zabel , Bjorn Andersson , Konrad Dybcio Cc: Qiang Yu , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1785474832; l=4363; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=MsC3j2tem4FZcoQZTIFpAAXfCmNseQgByW8DJZvce2A=; b=elcQLXDJpx/4Wqz0EbGv19rOxwV4hvmNq+Damu84rmhbxoX4pKEItXjYgmJ27pBs3Quid1vdL PDpWy8oSrSMA5XJjRHEiX05arz5exA7cfQCut/Ol9KwrDe/PfQkntnn X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Proofpoint-GUID: 7bkRkD0yDilu8PpOHs0Dvnx13toNYd09 X-Proofpoint-ORIG-GUID: 7bkRkD0yDilu8PpOHs0Dvnx13toNYd09 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzMxMDAzMiBTYWx0ZWRfX5ask8m/IAzus m0b9u/XWkXtzFo3dljRY/0Y/6zQgEzxjab4fkRdvERr4oe0fg9uWck9QVEoMTYgrhDzfMjo9X1J AsgeDF0WTU7FQ+vkIBEUvHrSXNMWpAs= X-Authority-Analysis: v=2.4 cv=WZQ8rUhX c=1 sm=1 tr=0 ts=6a6c2f17 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=ZTTPuMnDdfme7OPWMlMA:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzMxMDAzMiBTYWx0ZWRfX3EZwAdIZT/WD GtlECWB/GSRYg8YG8z1TQcqbv7g1NZ1Ei1vcQwqDwg6z+jspt2Tw6NsCovaj2PqzUIOKRGlLygh LYuKfiRsA70mu6rPi86hVnIt3Y2+sM3hEqiMRz2LMSRkplQcheX2n89pTURPu9N6GdnXW3qNV2P EqIOsTvS/pHxCxAxBuKcQQek6YnuPigAcHKNoRf1zJjawCok0tcdQPeSjyjMsC2uCSCOpys28S8 A6aXEoK8iY762R4Y3rEMDX713eUWeA7VXnR3BHbFUDjUuPgnIj3LGWBteSHlIHwllU2s5nnHStB n076ZMiB8pQLMDOt4G+khF6pQGemBdmYnWC7s1HQo1/RkCfXqM/yNCajl454yZWBWJt+WV4qPmv Xx3Jr7UAC55LUNiMD4n3A1RFRAKQvwD+WN4vnl82NUPILh+J0xJOV6GChGPcAUMQf9IGNTg2xWQ H8hQUp78RcJ0XgtzIWQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-31_02,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 phishscore=0 impostorscore=0 suspectscore=0 malwarescore=0 clxscore=1015 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607310032 Unlike Glymur, Mahua only has PCIe3b wired up; there is no PCIe3a controller and no shared Gen5x8 PHY block. Delete the inherited pcie3a and pcie3_phy nodes, and add a dedicated pcie3b_phy using the existing qcom,glymur-qmp-gen5x4-pcie-phy compatible. Point pcie3b_port0's phys and the GCC pipe clock parent array at &pcie3b_phy instead of the deleted &pcie3_phy. Reviewed-by: Konrad Dybcio Signed-off-by: Qiang Yu Reviewed-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/mahua.dtsi | 89 +++++++++++++++++++++++++++++++++= ++++ 1 file changed, 89 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/mahua.dtsi b/arch/arm64/boot/dts/qcom= /mahua.dtsi index e6c059708912..a59c5ed7b48e 100644 --- a/arch/arm64/boot/dts/qcom/mahua.dtsi +++ b/arch/arm64/boot/dts/qcom/mahua.dtsi @@ -22,6 +22,8 @@ /delete-node/ &cpu_pd16; /delete-node/ &cpu_pd17; /delete-node/ &cti_wpss; +/delete-node/ &pcie3_phy; +/delete-node/ &pcie3a; /delete-node/ &thermal_aoss_6; /delete-node/ &thermal_aoss_7; /delete-node/ &thermal_cpu_2_0_0; @@ -79,6 +81,52 @@ &config_noc { compatible =3D "qcom,mahua-cnoc-cfg"; }; =20 +&gcc { + clocks =3D <&rpmhcc RPMH_CXO_CLK>, /* Board XO source */ + <&rpmhcc RPMH_CXO_CLK_A>, /* Board XO_A source */ + <&sleep_clk>, /* Sleep */ + <0>, /* USB 0 Phy DP0 GMUX */ + <0>, /* USB 0 Phy DP1 GMUX */ + <0>, /* USB 0 Phy PCIE PIPEGMUX */ + <0>, /* USB 0 Phy PIPEGMUX */ + <0>, /* USB 0 Phy SYS PCIE PIPEGMUX */ + <0>, /* USB 1 Phy DP0 GMUX 2 */ + <0>, /* USB 1 Phy DP1 GMUX 2 */ + <0>, /* USB 1 Phy PCIE PIPEGMUX */ + <0>, /* USB 1 Phy PIPEGMUX */ + <0>, /* USB 1 Phy SYS PCIE PIPEGMUX */ + <0>, /* USB 2 Phy DP0 GMUX 2 */ + <0>, /* USB 2 Phy DP1 GMUX 2 */ + <0>, /* USB 2 Phy PCIE PIPEGMUX */ + <0>, /* USB 2 Phy PIPEGMUX */ + <0>, /* USB 2 Phy SYS PCIE PIPEGMUX */ + <0>, /* PCIe 3a pipe */ + <&pcie3b_phy>, /* PCIe 3b pipe */ + <&pcie4_phy>, /* PCIe 4 */ + <&pcie5_phy>, /* PCIe 5 */ + <&pcie6_phy>, /* PCIe 6 */ + <0>, /* QUSB4 0 PHY RX 0 */ + <0>, /* QUSB4 0 PHY RX 1 */ + <0>, /* QUSB4 1 PHY RX 0 */ + <0>, /* QUSB4 1 PHY RX 1 */ + <0>, /* QUSB4 2 PHY RX 0 */ + <0>, /* QUSB4 2 PHY RX 1 */ + <0>, /* UFS PHY RX Symbol 0 */ + <0>, /* UFS PHY RX Symbol 1 */ + <0>, /* UFS PHY TX Symbol 0 */ + <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, + <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, + <&usb_2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, + <&usb_mp_qmpphy0>, /* USB3 UNI PHY pipe 0 */ + <&usb_mp_qmpphy1>, /* USB3 UNI PHY pipe 1 */ + <0>, /* USB4 PHY 0 pcie pipe */ + <0>, /* USB4 PHY 0 Max pipe */ + <0>, /* USB4 PHY 1 pcie pipe */ + <0>, /* USB4 PHY 1 Max pipe */ + <0>, /* USB4 PHY 2 pcie */ + <0>; /* USB4 PHY 2 Max */ +}; + &hsc_noc { compatible =3D "qcom,mahua-hscnoc"; }; @@ -115,6 +163,10 @@ &oobm_ss_noc { compatible =3D "qcom,mahua-oobm-ss-noc", "qcom,glymur-oobm-ss-noc"; }; =20 +&pcie3b_port0 { + phys =3D <&pcie3b_phy>; +}; + &pcie5_phy { clocks =3D <&gcc GCC_PCIE_PHY_5_AUX_CLK>, <&gcc GCC_PCIE_5_CFG_AHB_CLK>, @@ -143,6 +195,43 @@ &pcie_west_slv_noc { compatible =3D "qcom,mahua-pcie-west-slv-noc"; }; =20 +&soc { + pcie3b_phy: phy@1b90000 { + compatible =3D "qcom,glymur-qmp-gen5x4-pcie-phy"; + reg =3D <0x0 0x01b90000 0x0 0x10000>; + + clocks =3D <&gcc GCC_PCIE_PHY_3B_AUX_CLK>, + <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_3_CLKREF_EN>, + <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_3B_PIPE_CLK>, + <&gcc GCC_PCIE_3B_PIPE_DIV2_CLK>; + clock-names =3D "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + resets =3D <&gcc GCC_PCIE_3B_PHY_BCR>, + <&gcc GCC_PCIE_3B_NOCSR_COM_PHY_BCR>; + reset-names =3D "phy", + "phy_nocsr"; + + assigned-clocks =3D <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>; 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Add the vdda-phy and vdda-pll supplies for &pcie3b_phy. Signed-off-by: Qiang Yu Reviewed-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/mahua-crd.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/mahua-crd.dts b/arch/arm64/boot/dts/q= com/mahua-crd.dts index fa5229064b10..17e40f2a6259 100644 --- a/arch/arm64/boot/dts/qcom/mahua-crd.dts +++ b/arch/arm64/boot/dts/qcom/mahua-crd.dts @@ -20,6 +20,11 @@ / { compatible =3D "qcom,mahua-crd", "qcom,mahua"; }; =20 +&pcie3b_phy { + vdda-phy-supply =3D <&vreg_l3c_e1_0p89>; + vdda-pll-supply =3D <&vreg_l2c_e1_1p14>; +}; + &tcsr { vdda-qrefrpt0-0p9-supply =3D <&vreg_l2f_e1_0p83>; vdda-qrefrpt1-0p9-supply =3D <&vreg_l2f_e1_0p83>; --=20 2.34.1