From nobody Sat Jul 25 23:41:46 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 23DB3385D6C for ; Sat, 25 Jul 2026 10:15:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784974532; cv=none; b=RlJzW7EjqRi1ne9ayI2w0soU5BryyCJKTMF9zCYJd4tYu52UgRYPjpmnI7KiLVwQneClFfAfEYJUDDEEjri2th5NPHqK8oCQLggmq7fHzKwmO2wBxGh0zIHLG5kjmtsG5nNMCmmO0C2k2elTeyNlgfVp0BrUwtRoI7PGNfanxjM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784974532; c=relaxed/simple; bh=aByVu9xDN/Hmxg3TIsdsXCvq+trny5YWc/enpmcfOQ0=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=raRLdlaEGVwilFvAV5raHaaq0SRMsgOfEOPDBGuMjcpSVYeIXN9PFyy4NpxDq0P+fRfMtVful7qkvEpvilMO0tTuXD7VVTQB1hkOE6T2cSsKYvAP7wQfZ4gXqKc1Pa6saWFi+Jc5eZcA03p4u7QkxEX2pAk0qbeSgkhsFe/gpAM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=gr3fvk6O; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="gr3fvk6O" Received: from mail01.layka.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id EB62285CB4; Sat, 25 Jul 2026 12:15:27 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id 5SZVBPukNLIW; Sat, 25 Jul 2026 12:15:27 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1784974527; bh=aByVu9xDN/Hmxg3TIsdsXCvq+trny5YWc/enpmcfOQ0=; h=From:To:Cc:Subject:Date; b=gr3fvk6OiI31UlM7WfRR8FirhoyVL5HGpw2/p/zXRbqBUt8PApmOI9lRlNNW4pfNH /lcodVac7lc6j8lJHZhG6vc3vvXDpgHSmFFDcMtgXajB3N5b0VcuSF0+ArwE4Z39Gf BJvIr+7wmJErrWtVmai+GFy528iiqP1Unen79P189Xi1r99w3AWnbkeOW9ARGVAFMA /VIY5iuBlhIviKV9R8t1wZgkahy9PKrHiwaBvQilhikub6/ZiGSD6mlzWwVtDP7gEC J1K11xKglqDAUf9dFiwAwgLLB/dOlD1eNNM2M/DCWvymOi81rSANHmAsmOlW6p3pnq zA0coTjJUVXYA== From: Rustam Adilov To: Thomas Gleixner , Birger Koblitz , Bert Vermeulen , John Crispin , linux-kernel@vger.kernel.org Cc: Rustam Adilov , Carlo Szelinsky Subject: [PATCH v2] irqchip/irq-realtek-rtl: change to __raw reads and writes Date: Sat, 25 Jul 2026 15:14:56 +0500 Message-ID: <20260725101456.31619-1-adilov@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When CONFIG_SWAP_IO_SPACE is enabled, readl() and writel() are changed to perform a byte swap to little endian type. This is incorrect because the devices that use the irq-realtek-rtl driver are all big endian MIPS chips. Fix this by converting the MMIO accesses to __raw_readl() and __raw_writel(), which do not byte swap the data. Tested-by: Carlo Szelinsky Signed-off-by: Rustam Adilov --- Changes in v2: - Make the commit message clearer. drivers/irqchip/irq-realtek-rtl.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/irqchip/irq-realtek-rtl.c b/drivers/irqchip/irq-realte= k-rtl.c index 4b59e0cd86bf..3077f4efb4e2 100644 --- a/drivers/irqchip/irq-realtek-rtl.c +++ b/drivers/irqchip/irq-realtek-rtl.c @@ -50,18 +50,18 @@ static inline void enable_gimr(unsigned int cpu, unsign= ed int hw_irq) { u32 gimr; =20 - gimr =3D readl(REG(cpu, RTL_ICTL_GIMR)); + gimr =3D __raw_readl(REG(cpu, RTL_ICTL_GIMR)); gimr |=3D BIT(hw_irq); - writel(gimr, REG(cpu, RTL_ICTL_GIMR)); + __raw_writel(gimr, REG(cpu, RTL_ICTL_GIMR)); } =20 static inline void disable_gimr(unsigned int cpu, unsigned int hw_irq) { u32 gimr; =20 - gimr =3D readl(REG(cpu, RTL_ICTL_GIMR)); + gimr =3D __raw_readl(REG(cpu, RTL_ICTL_GIMR)); gimr &=3D ~BIT(hw_irq); - writel(gimr, REG(cpu, RTL_ICTL_GIMR)); + __raw_writel(gimr, REG(cpu, RTL_ICTL_GIMR)); } =20 static void write_irr(unsigned int cpu, int hw_irq, u32 value) @@ -71,9 +71,9 @@ static void write_irr(unsigned int cpu, int hw_irq, u32 v= alue) unsigned int shift =3D IRR_SHIFT(hw_irq); u32 irr; =20 - irr =3D readl(irr0 + offset) & ~(0xf << shift); + irr =3D __raw_readl(irr0 + offset) & ~(0xf << shift); irr |=3D (value & 0xf) << shift; - writel(irr, irr0 + offset); + __raw_writel(irr, irr0 + offset); } =20 static void realtek_ictl_unmask_irq(struct irq_data *i) @@ -159,7 +159,8 @@ static void realtek_irq_dispatch(struct irq_desc *desc) unsigned int hw_irq; =20 chained_irq_enter(chip, desc); - pending =3D readl(REG(cpu, RTL_ICTL_GIMR)) & readl(REG(cpu, RTL_ICTL_GISR= )) & output->mask; + pending =3D __raw_readl(REG(cpu, RTL_ICTL_GIMR)) & + __raw_readl(REG(cpu, RTL_ICTL_GISR)) & output->mask; =20 if (unlikely(!pending)) { spurious_interrupt(); --=20 2.55.0